4 5 6 12 8 A7 B7 經濟部智慧財產局員工消赀合作；；？印_^ 五、發明說明（1 ) 發明領域 廣義而言，本發明與爐波有關’更明確地說，與使闬 實數到解析轉換執行頻域濾波的方法有關。 發明背景 很多數位信號處理（D s P )的應用，使用數位濾波 技術以過濾信號內不欲見的信號或雜訊頻率分量。實施此 等數位濾波，經常是使用有限脈衝響應（F I R )濾波， 它是一種使用捲積之眾所皆知的方法。此方法需要.對每一 個輸入做11次的乘與累加（MAC)運具’其中K是撼波 器中所實施的分接（taps)數量。該方法產生大約K/2 之樣本的固有延遲=如果輸入（及輸出）信號的取樣頻率 是F s，則每秒執行M A C的次數是F s * K。對較大的濾 波器或在較高的取樣率時*這會成爲計算機執行處理的負 擔。 ••月一種熟知的技術，即利用快速傅案轉換C F F 丁 )及逆抉速傅立葉轉換（I F F T )所做的快速捲積〔 F C )，可以克服這類密集的運算限制。雖然此種技術可 以大幅減少對處理器的運算要求，它需要集合與處理大小 爲N之區堤內的資料，其中N通常是以2爲基數的量。爲 大幅減少運算需求，N必須大於K ° 此方法主要的缺點是它引入了大小爲N的固有延遲’ 因此，相較於直接的F I R法’延遲大幅增加° 快速捲稂的跸闬很廣，已是眾所皆知。此技術最常用 ---------III ----I — ί 訂·---— 111* 妒- (請先閱請背面之注意事項再填寫本頁) 本紙5ίι尺度適用中困®家楳準（CNS)A4規格（210x297公釐） -4 - 456128 經濟部智慧財產局員工消货合作社印欠 A7 B7 五、發明說明（2 ) Μ因處埋所造成的固有延遲對應用而言並不重要，或是爲 Μ償系統中其它延遲而需要此等延遲。 使用快速捲積技術的例子可發現於音頻數據機的應用 ’如 I τ υ V 3 2 b i s 或 I 丁 U V . 3 4 。該技 # m來消除各種線路情況及損失所產生的回波信號。特別 胃用於消除接收自遠端側所產生之回波的遠端回波消除器 (FEEC)。回波往返延遲（RTD)的範圍從30毫 秒到2秒。爲適當補償此延遲，且爲不消耗大量的處理資 '源1 F E E C必須使用延遲暫存以延遲輸入信號，它的深 度要近乎等於往返延遲。 &於這些數據機需要固有延遲以補償經由物理情況所 引進的R 丁 D，它們可以很容易地結合快速捲積以減輕用 來模擬回波路徑之濾波器的運算負擔。 此外，如果是線路情況的損失，例如頻域多工器向上 轉換或向下轉換，引進頻率偏移，F E E C必須以相同的 頻率偏移扭轉〃模擬回波。頻率偏移可以使周鎖相迴路 (P L L ).電路追蹤。不過，必須事先儲存所傳送之信號 的正交分量，或從同相分量中導出。前者所需要的延遲暫 存加倍1後者需要使闱額外的Hubert濾波器’它使運算強 度增加。 現將描述典型習知數據機的設計。典型習知數據機實 施設計如圖1所示、包括一資料存取配置（D A A ) 4 2 '發射機3 2 '接收機3 4、数位到類比轉換器（D / A )3 8及類比到数位轉換器（A/D) 40 ^此外’全雙 H » I— i^i >^1 II ^^1 l^i i —i * 1 r- I 1 Ϊ— J 一 I Γ - I i . *4 I B1 (請先閱請貲面之注意事項再填寫本\貝> 本紙張尺度過用中® 0家棍準（CNS)A4規祐（210 X 297公犮） -5- 456128 經濟部智赵財產局员工消货合作枉印^ Α7 Β7 五、發明說明（3 ) 工音頻數據機也使用有限脈衝響應（F I R )調適漉波器 。此類F I R濾波器包括接收機3 4內的遠端回波消除器 4 1 F I R ’近端回波消除器3 3 F I R，以及等化 器F I R。操作期間，通訊系統實施數據機通常需要應付 極大量的不同通訊頻道，每一個都具有不同的頻道及回波 損失。 如前所討論’爲應付最差情況的損失需要各種較長的 濾波器’需要大量的處理器資源。爲減輕c P U處理濾波 器的負擔’在實行上述F I R濾波器方面，有數種習知的 DSP技術可供使用，諸如使用ffT及I FFT的·''重 疊與儲存〃及w重疊與相加〃。 在專用的D S P硬體中實行諸如*重疊與儲存〃及、、 重疊與相加〃等技術，將可節省大量的處理器資源，因爲 ϋ S P處理器具有專門用來執行信號處理功能的最佳化硬 體設計。 典型上’在硬體中最佳化及實施之信號處理功能的例 子包括位元反轉 '除數計數、乘與加功能'桶形移相器等 。這些硬體信號處理功可以做到高度最佳化，快速且有效 茧的F F 丁及I F F Τ操作= 發明槪述 因此’本發明發展一種頻域濾波的方法，以克服習知 技術的限制及缺點· 習知頻域快速捲積技術的限制包括，爲從同相中得到 ----------- --------訂----------綠 {請先閱讀背面之注意事項再填寫本頁) 本紐尺！顧中圈㈣樣準（CNS)A伐格（21〇χ 297公贫） -6 - 經！-部智--^產-具-消货合作社印焚 4 5 6 1 2 8 A7 —____si____ 五、發明說明（4 ) 正交分量並產生解析信號，在需要H丨1 bert總波轉換的情況. ，需要額外的c P U資源’即一複合信號中具有同相分量 ’也就是它的實部，以及一正交分量’也就是它的虛部— "實數對解析轉換"。此等信號具有正或負的頻率分量’ 且因此很容易經歷一頻移操作。 因此，本發明的目的是提供一種利用頻域捲積實行實 數對解析轉換的方法，且不需要使闬額外的c P U資源。 本發明的另一目的是提供一種利用 '' 重叠與儲存〃的 頻域捲積實行實數對解析轉換的方法，且不需要使用額外 的C P U資源。 如本發明提供一種方法，對一實輸入區塊及一組實有 限脈衝響應（F I R )係數執行實數對解析快速捲積，以 •產生一複合輸出向量，該方法的步驟包括對實輸入區塊執 行第一快速傅立葉轉換（F F T )，對一組F I R係數執 行第二F F T，對第二F F T所得到的元素逐一乘以理想 實數對解析轉換之頻率響應以形成第一乘積，對第一 F F T所得.到的元素逐一乘以該第一乘積以得到第二乘積 ，對第二乘積的結杲執行反怯速傅立葉轉換（I F F T ) 以產生複合輸出向量，並從輸出向量的實部形成第一實輸 • 1 · T > -t— 出蟲塊。 理想實數對解析轉換可包括正頻率實數對解析轉換或 負頻率實數對解析轉換。 本發明還提供一種方法，對一貨輸入區塊及一組實有 限脈衝饗應（F I R )係數執行寅数對解析怏速捲 以· 本紙張尺度過W中®囚家標準（CNS)A4規格（210 X 297公复） -fn 1^1 I- - - ...... ^^1 ΐ I ft— ^|> In In 訂---------絲 (請先閱靖背面之注意事項再填寫本頁) Α7 經濟部智慧財產局員工消货合竹社印欠 Β7_五、發明.說明（5 ) 產生一複合幟出向量，該方法的步驟包括對實輸入區塊執 行第一快速傅立葉轉換（F F T )，對一組F I R係數執 行第二F F T，對第一 F F T所得到的元素逐一乘以理想 實數對解析轉換之頻率響應以形成第一乘積·對第二 F F T所得到的元素逐一乘以該第一乘積以得到第二乘積 ，對第二乘積的結果執行反快速傅立葉轉換（I F F T ) 以產生複合輸出向量，並從輸出向量的實部形成第一實輸 出區塊。 此外1本發明還提供一種裝置，對實輸入信號.執行濾 波及頻移•該裝置輸出一實輸出信號|該裝置包括實數對 解析裝置，以對輸入信號執行實數對解析快速捲積，實數 對解析裝置操作輸出第一複合信號，頻率產生器裝置用以 產生第二複合信號，以e 表示，頻率產生器裝置操作 產生具有任何任意頻率ω之第二複合信號，一乘法器與實 數對解析裝置及頻率產生器裝置連接，乘法器將第一複合 信號與第二複合信號相乘得到第三複合信號，以及實裝置 與乘法器連.接，乘法器用以取出第三複合3言號的實分量以 得到實輸_出信號。 實數對解祈裝置包括對實輸入執行快速傅立葉轉換（ F F 丁）以得到第一 F F Τ的裝置，對一組實有限脈衝響 應（F I R )係數執行第二F F Τ以得到第二F F Τ輸出 的裝置·將第二F F Τ的_出元素逐一乘以理想實數對解 析轉換之頻率應以得到第一乘積的裝置，將第一 F F Τ 蝓岀的元素逐一乘以第一乘稂以得到第,二乘積的裝置|以 ' 1— I n ____ I . _ i__Γ— _ ] I - J I -JJ- I , , I I: ___— I c請先閱讀背面之注意事項再填寫本頁) 本紙讯尺度適用中®因家楳準（CNS)/V1規格（210 X 297公« ) 4 5 61 Α7 Β7 •5*、發明說明（6 ) 及對第二乘積執行反快速傅立葉轉換（I F F T )以產生 第~複合信號的裝置。 此外，本發明也提供一種方法，對一實輸入信號執行 '應波及頻移以便產生一實輸出信號，其方法的步驟包括對 輸入信號執行實數對解析的快速捲積，以得到第一複合信 號，.產生以e ιωι表示的第二複合信號，其中所產生的頻 率是任何任意的頻率ω，第一複合信號乘以第二複合信號 得到第三複合信號，取出第三複合信號中的實分量得到實 輸出信號。 執行實數對解析快速捲積的步驟包括’對實輸入信號 執行快速傅立葉轉換（F F Τ )，對一組實有限脈衝響應 (F I R )係數執行第二f F Τ'，所得到的第二F F Τ元 素逐一乘以理想實數對解析轉換之頻率響應以得到第一乘 積’所得到的第一F F Τ元素逐一乘以第一乘積以得到第 二乘積，對所得到的第二乘積執行反快速傅立葉轉換（ I F F Τ)以產生一複合輸出向量的步驟。 圖式簡單說明 本文經由實施例益參閱附圖描述本發明，其中： 圖1是說明習知全雙功音頻數據機之典型實施的高階 方堍圖； 圖2是說明第一種實施遠端回波消除器之習知技術的 詳絀方塊圖： 圖3是說明第二種質施遠端回波消除器之習知技術的 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂·--------^ν 本紙張尺度近用中®固家標準（CNS)A4規格（2]0 X 297公沒） -9- 45 61 . Α7 ______ Β7 五、發明說明（7 ) 詳細方塊圖； <請先閱磧背面之注意事項再填寫本頁) 圖4是說明習知技術之頻域捲積裝置的高階方塊圖； 圖5是按本發明之實施例使用實數對解析快速捲積架 構的遠端回波消除器詳細方塊圖； 圖6是說明本發明之實數對解析快速捲積設計之第一 種實施例的高階方塊圖； 圖7是說明本發明之實數對解析快速捲積設計之第二 種實施例的高階方塊圖； 圖8是說明習知技術之重疊與儲存〃頻域區.塊捲積 設計的高階方塊圖； 圖9是說明按本發明所架構之頻域爐波器結合實數Θ 解析轉換濾波器之實施例的高階方塊圖； 圖1 0是說明本發明之頻域濾波設計用於分頻多工（ F D Μ )之應用。 主要元件對照表 3 1 加總器 Ζ 2 . 發射機 33 近端回音消除器 經濟部智楚財產局员工消货合作社印,¾ 34 接收機 35 延遲線 3 6 回音消除塱元 3 7 加總器 3 8 數位到類比轉換器 4 0 類比到數位轉換器 4 1 遠端回音消除器 -10 - 本紙張尺度適ffl中國困冢楳準（CNS)A4規格（210 * 297公釐） 4 5 6 K A7 B7 經濟部智慧財產局員工消货合作杈印- 五、發明.說明（ 4 2 5 4 5 6 5 7 資料存取配置 有限脈衝響應濾波器 Hilbert 轉換 乘以'' 一 1 )功能 0 8 8 4 0 2 4 4 0 延遲暫存 實數對解析轉換 加總器 鎖相迴路（P L L )模組 乘法器 實分量擷取功能 發射機 延遲暫存 實數對解析快速捲積功能 乘法器 8 7 取實功能 90 先進先出 96 接收機 N - K個輸入樣本 K個樣本 玦速傅立葉轉換 長度爲K的濾波脈衝響應 緩衝器 快速傅立葉轉換 K個樣本 鎖相迴路功能 先進先出 先進先出 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家棵準（CNS)A4規格（210 X 297公^ ) -11 - 456128 A7 B7 五、發明說明（9 ) 2 4 0 N - K個輸入樣本 快速傅立葉轉換 長度爲K的濾波脈衝響應 緩衝器 快速傅立葉轉換 實數對解析轉換 乘法器 反快速傅立葉轉換4 5 6 12 8 A7 B7 The staff of the Intellectual Property Bureau of the Ministry of Economic Affairs eliminated cooperation;印 _ ^ V. Description of the invention (1) Field of the invention In a broad sense, the present invention relates to furnace waves', more specifically, it relates to a method for performing a frequency-domain filtering by converting a real number to an analytical conversion. BACKGROUND OF THE INVENTION Many digital signal processing (D s P) applications use digital filtering techniques to filter unwanted signals or noise frequency components within the signal. The implementation of such digital filtering is often performed using finite impulse response (F I R) filtering, which is a well-known method using convolution. This method requires 11 multiplication and accumulation (MAC) vehicles for each input, where K is the number of taps implemented in the shaker. This method produces an inherent delay of approximately K / 2 samples = If the sampling frequency of the input (and output) signal is F s, then the number of times M A C is performed per second is F s * K. For larger filters or at higher sample rates * this becomes a burden on the computer to perform the processing. •• A well-known technique, that is, fast convolution (F C) using fast Fourier transform (C F F D) and inverse fast Fourier transform (I F F T), can overcome this type of intensive computational limitation. Although this technique can greatly reduce the computational requirements on the processor, it needs to aggregate and process the data in the area bank of size N, where N is usually a base 2 quantity. In order to greatly reduce the computational requirements, N must be greater than K °. The main disadvantage of this method is that it introduces an inherent delay of size N. Therefore, compared to the direct FIR method, the delay is greatly increased. Is well known. This technology is most commonly used --------- III ---- I — ί Order · --- — 111 * Jealousy-(Please read the precautions on the back before filling this page) This paper is 5 liters in size Sleepy® furniture standard (CNS) A4 (210x297 mm) -4-456128 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs owe A7 B7 to the consumer goods cooperatives. 5. Description of the invention (2) The inherent delay caused by burial to the application It is not important, or it is needed for other delays in the M compensation system. Examples of the use of fast convolution techniques can be found in applications of audio modems such as I τ υ V 3 2 b i s or I ding U V. 3 4. This technique # m to eliminate echo signals generated by various line conditions and losses. In particular, the stomach uses a far-end echo canceller (FEEC) to cancel the echo generated from the far-end side. The echo round-trip delay (RTD) ranges from 30 milliseconds to 2 seconds. In order to properly compensate for this delay and not consume a large amount of processing resources, source 1 F E E C must use a delay buffer to delay the input signal, and its depth should be approximately equal to the round-trip delay. & As these modems require inherent delays to compensate for the R and D introduced through physical conditions, they can easily be combined with fast convolution to reduce the computational burden of filters used to simulate the echo path. In addition, if it is a loss of line conditions, such as frequency domain multiplexer up-conversion or down-conversion, the introduction of frequency offset, F E E C must be reversed with the same frequency offset 〃 analog echo. Frequency offset can track the phase-locked loop (P L L). However, the quadrature component of the transmitted signal must be stored in advance or derived from the in-phase component. The former requires twice the delay buffer. The latter requires an additional Hubert filter, which increases the computational intensity. The design of a typical conventional modem will now be described. A typical conventional modem implementation design is shown in Figure 1, including a data access configuration (DAA) 4 2 'transmitter 3 2' receiver 3 4, digital-to-analog converter (D / A) 38, and analog to Digital converter (A / D) 40 ^ In addition, 'all double H »I— i ^ i > ^ 1 II ^^ 1 l ^ ii —i * 1 r- I 1 Ϊ— J-I Γ-I i. * 4 I B1 (please read the precautions before filling out this book \ Shell > This paper is in the middle of standard use 0 0 sticks (CNS) A4 regulations (210 X 297 Gong) -5- 456128 Economy Employees of the Ministry of Intellectual Property and Property Management Co., Ltd. 消 Α7 Β7 V. Description of the Invention (3) The industrial audio modem also uses a finite impulse response (FIR) to adapt the wave filter. This type of FIR filter includes the receiver 3 4 Far-end echo canceller 4 1 FIR 'Near-end echo canceller 3 3 FIR, and equalizer FIR. During operation, the communication system implementation modem usually needs to cope with a very large number of different communication channels, each with a different Channel and echo loss. As discussed earlier, 'longer filters are needed to deal with worst-case losses' require a lot of processor resources. Reducing the burden of the cPU processing filter 'In implementing the above-mentioned FIR filter, there are several conventional DSP technologies available, such as "overlap and storage" and "w overlap and add" using fft and I FFT. Implementing technologies such as * overlap and storage, and, overlap and add in dedicated DSP hardware will save a lot of processor resources, because the SP processor has the best performance for signal processing functions. Examples of signal processing functions that are typically 'optimized and implemented in hardware include bit inversion' divisor counting, multiply and add functions' barrel phase shifters, etc. These hardware signal processing Work can be highly optimized, fast and effective FF operation and IFF T operation = invention description So 'the present invention develops a method of frequency domain filtering to overcome the limitations and shortcomings of the conventional technology. Limitations of the fast convolution technique include, for obtaining from the same phase ----------- -------- order ---------- green {Please read the back Please fill out this page again)) Gu Zhongquan Sample Standard (CNS) A Vage (21〇χ 297 public poverty) -6-Jing! -部 智-^ 产-具-消 消 合作社 印 印 4 5 6 1 2 8 A7 —____ si____ 5. Description of the invention (4) Orthogonal components and analytic signals are generated when H 丨 1 bert total wave conversion is required . Requires additional c PU resources 'that is, a composite signal has an in-phase component', that is, its real part, and a quadrature component, that is, its imaginary part-" Real Number Pair Analytic Conversion ". These signals have positive or negative frequency components ' and are therefore easily subjected to a frequency shift operation. Therefore, an object of the present invention is to provide a method for performing real-to-analytic conversion using frequency domain convolution, without requiring additional c P U resources. Another object of the present invention is to provide a method for performing real-to-analytic conversion using frequency domain convolution of overlap and storage chirps, without using additional CP resources. For example, the present invention provides a method for performing a real pair parsing fast convolution on a real input block and a set of real finite impulse response (FIR) coefficients to generate a composite output vector. The steps of the method include performing a real input block Perform a first fast Fourier transform (FFT), perform a second FFT on a set of FIR coefficients, multiply the elements obtained by the second FFT one by one with an ideal real number, and respond to the frequency response of the analytic conversion to form a first product. The obtained elements are multiplied by the first product one by one to obtain a second product. An inverse fast Fourier transform (IFFT) is performed on the result of the second product to generate a composite output vector, and a first real is formed from the real part of the output vector. Lose • 1 · T > -t— Infested. An ideal real-to-analytic conversion may include a positive-frequency real-to-analytic conversion or a negative-frequency real-to-analytic conversion. The present invention also provides a method for performing a number pair analysis on a cargo input block and a set of real finite impulse response (FIR) coefficients. The speed of this paper is over W ® ® Prisoner's Standard (CNS) A4. (210 X 297 public compound) -fn 1 ^ 1 I---...... ^^ 1 ΐ I ft— ^ | > In In Order --------- Silk (please read first Note on the back of Jing, please fill out this page again) Α7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs owe B7_5. Invention. Explanation (5) Generate a composite flag vector. The steps of this method include the actual input area. The block performs the first fast Fourier transform (FFT), performs a second FFT on a set of FIR coefficients, and multiplies the elements obtained by the first FFT by the ideal real number one by one to the frequency response of the analytic conversion to form the first product. The second FFT The obtained elements are multiplied by the first product one by one to obtain a second product, an inverse fast Fourier transform (IFFT) is performed on the result of the second product to generate a composite output vector, and a first real output region is formed from a real part of the output vector Piece. In addition, the present invention also provides a device that performs filtering and frequency shifting on a real input signal. The device outputs a real output signal. The device includes a real number pair parsing device to perform real pair parsing fast convolution on the input signal. The analysis device operates to output a first composite signal, and the frequency generator device is used to generate a second composite signal, denoted by e. The frequency generator device operates to generate a second composite signal having any arbitrary frequency ω. A multiplier and real number pair analysis device And the frequency generator device is connected, the multiplier multiplies the first composite signal and the second composite signal to obtain a third composite signal, and the real device is connected to the multiplier. The multiplier is used to extract the real component of the third composite 3 signal To get the actual output_output signal. The real number pair solution device includes means for performing a fast Fourier transform (FF Ding) on a real input to obtain a first FF T, and performing a second FF T on a set of real finite impulse response (FIR) coefficients to obtain a second FF T output. Device: The device that multiplies the _out elements of the second FF T by the ideal real number one by one to obtain the first product. The device multiplies the elements of the first FF TT by the first multiplier to obtain the first, Device of two products | Take '1— I n ____ I. _ I__Γ— _] I-JI -JJ- I,, II: ___— I c Please read the notes on the back before filling in this page) The dimensions of this paper apply Medium® due to the domestic standard (CNS) / V1 specifications (210 X 297 male «) 4 5 61 Α7 Β7 • 5 *, description of the invention (6), and inverse fast Fourier transform (IFFT) on the second product to produce the first ~ Composite signal device. In addition, the present invention also provides a method for performing a 'response frequency shift' on a real input signal so as to generate a real output signal. The steps of the method include performing a fast convolution of a real number pair analysis on the input signal to obtain a first composite signal. ,. Generate a second composite signal represented by e ιωι, where the generated frequency is any arbitrary frequency ω, multiply the first composite signal by the second composite signal to obtain a third composite signal, and take out the real component in the third composite signal. Get the real output signal. The steps of performing fast real-pair analytic fast convolution include 'performing a fast Fourier transform (FF T) on a real input signal, performing a second f F Τ' on a set of real finite impulse response (FIR) coefficients, and the resulting second FF Τ The elements are multiplied one by one by the ideal real number to the frequency response of the analytic transformation to obtain the first product. The first FF T element obtained is multiplied by the first product one by one to obtain the second product. The inverse fast Fourier transform is performed on the second product obtained. (IFT) to generate a composite output vector. Brief description of the drawings The present invention will be described briefly through the embodiments with reference to the accompanying drawings, in which: FIG. 1 is a high-order square diagram illustrating a typical implementation of a conventional full-duplex audio modem; FIG. 2 is a diagram illustrating the first implementation of far-end echo cancellation Detailed block diagram of the conventional technology of the device: Figure 3 is a description of the conventional technology of the second type of far-end echo canceller (please read the precautions on the back before filling this page) Installation ----- --- Order · -------- ^ ν The paper size is currently in use® Goods Standard (CNS) A4 specification (2) 0 X 297 public) -9- 45 61. Α7 ______ Β7 V. Description of the invention (7) Detailed block diagram; < Please read the notes on the back of the page before filling out this page) Figure 4 is a high-level block diagram illustrating the frequency domain convolution device of the conventional technology; Figure 5 is an implementation according to the present invention Example detailed block diagram of a remote echo canceller using real number pair analysis fast convolution architecture; FIG. 6 is a high-order block diagram illustrating a first embodiment of the real number pair analysis fast convolution design of the present invention; FIG. 7 is an illustration of the present A high-level block diagram of a second embodiment of the real number pair analytical fast convolution design of the invention; FIG. 8 is an explanatory diagram Figure 9 is a high-order block diagram illustrating an embodiment of a frequency-domain furnace waver combined with a real number θ analytical conversion filter constructed in accordance with the present invention; the overlap and storage of the frequency domain region. Block convolution design; FIG. 10 illustrates the application of the frequency domain filtering design of the present invention to frequency division multiplexing (FDM). Comparison table of main components 3 1 Totalizer Z 2. Transmitter 33 Near-end echo canceller Printed by employees of the Intellectual Property Bureau of the Intellectual Property Office of the Ministry of Economy, ¾ 34 Receiver 35 Delay line 3 6 Echo cancellation unit 3 7 Totalizer 3 8 Digital-to-Analog Converter 4 0 Analog-to-Digital Converter 4 1 Remote Echo Canceller -10-This paper is suitable for ffl Chinese Standard (CNS) A4 (210 * 297 mm) 4 5 6 K A7 B7 Consumer Goods Cooperation Agreement of the Intellectual Property Bureau of the Ministry of Economic Affairs-V. Invention. Explanation (4 2 5 4 5 6 5 7 Data Access Configuration Limited Impulse Response Filter Hilbert Transformation Multiplied by `` -1 1) Function 0 8 8 4 0 2 4 4 0 Delayed temporary real-number pair analytical conversion totalizer Phase-locked loop (PLL) module multiplier real component acquisition function Transmitter delayed temporary real-number pair analytical fast convolution function multiplier 8 7 Reality function 90 FIFO 96 receiver N-K input samples K samples 玦 fast Fourier transform filter impulse response buffer of length K fast Fourier transform K samples PLL function FIFO (please read the back first Note for refilling (This page) This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm ^) -11-456128 A7 B7 V. Description of the invention (9) 2 4 0 N-K input samples The fast Fourier transform length is K's Filtered Impulse Response Buffer Fast Fourier Transform Real Number Pair Analytical Conversion Multiplier Inverse Fast Fourier Transform
N K個有效樣本 (請先閉讀背面之注意事項再填寫本頁) 裝 4 2 4 2 2 4 經濟部智慧財產局員工消货合作社印災 9 9 4 K個無效樣本 第一快速傅立葉轉換功能 第二快速傅立葉轉換功能 乘法器 反快速傅立葉轉換功能 第一快速傅立葉轉換 第二快速傅立葉轉換 乘法器 乘法器 反快速傅立葉轉換功能 實數對解析快速捲積方塊 -ττ~- 、.一μ aD 乘法窃 複到實功能方塊 本地振盪器 濾波器及頻移模組NK valid samples (please close the precautions on the back before filling out this page) Pack 4 2 4 2 2 4 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Goods Cooperatives 9 9 4 K invalid samples The first fast Fourier transform function Two Fast Fourier Transform Function Multiplier Inverse Fast Fourier Transform Function First Fast Fourier Transform Second Fast Fourier Transform Multiplier Multiplier Inverse Fast Fourier Transform Function Real Pair Analytical Fast Convolution Block -ττ ~-、. One μ aD Multiplication Stealing To the real function block local oscillator filter and frequency shift module
! I J1T' S I f 本紙張尺度過用中國國家標準（CNS)；M規格（210 X 297公犮） -12 456128 A7 B7 五、發明說明（1〇) 發明詳細說明 使用之符號 本文件中使用以下的符號 經濟部智慧財產局員工消貨合作社印^ 符 號 定 義 C 〇 中 央 機 房 C Ρ u 中 央 處 理 Og 車 元 D A A 資 料 存 取 配 置 D S P 數 位 信 號 處 理 F C 快 速 捲 積 F D M 分 頻 多 工 F E E D 遠 端 回 波 消 除 F F T 快 速 傅 立 葉 轉 換 F I F 〇 先 進 先 出 F I R 有 限 脈 衝 響 應 I F F T 反 快 速 傅 立 葉 轉換 I S I 碼 間 干 擾 I T u. 國 際 電 信 聯 盟 Μ A c 乘 法 與 累 加 Ρ L L 鎖 相 迴 路 R F 射 頻 R Ύ D 往 返 延 遲 S s B 信 號 邊 ytib 帝 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中固國家標準（CNS)A4規格（210 X 297公« ) -13 - 45 61 28 A7 B7 經濟部智轻財產局工消货合作杜印- 五、發明說明（11 ) 一般描述 爲說明的目的，本發明所教導的方法以音頻全雙功通 訊系統中的遠端回波消除器濾波功能來展示，如最大資料 率 14，400bps 的 I 丁 U V.23bis，或最 大資料率12 ，80〇bps的ITU V. 34。遠端 回波消除濾波器可以使用快速捲積設計|如熟知的''重疊 與儲存〃設計。必須注意，熟悉此方面技術的人士可以將 本發明所教的設計應用於數據機中其它的濾波器，諸如執 行碼間干擾（I S I )消除的等化濾波器，近端回波消除 濾波器，以及應用於其它的信號處理用途|諸如射頻（ R F .)數據機及回波消除器。此外，熟悉此方面技術的人 士可將本發明的方法應用於其它快速捲積設計，諸如 ''重 疊與相加〃技術。 如前所述，圖1之習知技術的全雙功音頻數據機包括 發射機3 2、接收機3 4 '回波消除器單元3 6、加總器 37、D/ A轉換器38、A/D轉換器40及DAA或 混合4 2。回波消除器單元包括一近端回波消除濾波器 3 3、延遲線3 5、遠端回波消除濾波器4 1及加總器 3 1。發射機從T X資料輸入埠接收輸入的發射資料，並 將發射（T X )樣本輸出給回波消除器單元3 6及D / A 轉換器3 8 : D A A的功能是經甴將來自中央機房（C ◦ )之雙線對上的平衡類比電壓，轉換成一供給發射機’另 一烘給接攸機（反之亦然）之兩不平衡雙線對’以匹配電 話線及發射機與接收機間的阻抗。回波消除器單元3 6的 ------------* - 1 ----—丨訂 --------- 雜， (請先閱讀背面之注意事項再填寫本頁) 本紙5民尺度1®用中@囷家標準（CNS)A4規格（210 X 297公茇） -14 - 5 6128 A7 B7 五、發明說明（12 ) 功能是使用調適近端濾波器消除近端回波’以及使用調適 遠端濾波器消除遠端回波，以移除來自接收信號的回波。 輸入到遠端濾波器的信號被延遲線3 5延遲’以便匹配從 網路所引進的往返延遲（R T D )。遠端濾波器及近端濾 波器輸出的信號被加總器3 1加總1以產生回波消除器單 元的輸岀。接著，使用加總器3 7從所接收的信號中減去 回波消除器的輸出。接收器輸出一數位的接收R X資料輸 出信號。 圖2顯示說明實施帶通遠端回波消除器之習知技術的 詳細方瑰圖。遠端回波消除器4 1包括一調適F I R濾波 器5 4、Hilbert轉換5 6、延遲暫存5 8、乘以'' j 〃 ( )功能5 7、加總器6 0、鎖相迴路（P L L )模組. 、乘法器6 2、以及實分量擷取功能6 4。 發射機Τ X 3 2產生一模組化的通帶樣本流。樣本流 被延遲暫存3 5延遲，它的最小深度是從通信網路所引進 的最大往返延遲。信號接著通過調適F I R濾波益5 4， 它的功能是模擬回波損失路徑。在此點’信號是實信號’ 接著信號經過實數對解析轉換5 9，它包括Η11 ben轉換 5 6、延遲暫存5 8 '乘以V- 1、以及加總器6 0。信號 通過由F 1 R濾波器所實施的Hi丨b e r t轉換功能5 6 ’經歷 同相到正交轉換。實部被延遲暫存5 8延遲’其功能爲補 償因實施FI R Η Π b e τ t轉換功能所產生的延遲。延遲暫存 5 8的深度正好是用來實施Hilbert轉換功能之F I R濾波 器之分接數量之半。 1 -------1-------f » 1 I I----訂·--- ! ---- {請先Μ讀背面之注意事項再填寫本頁) 本紙張尺度適用中gg®家棵準（CNS)A4規格（210x 297公犮〉 -15 - 45 6 彳 28 A7 B7 經濟部智祛財產局員工消货合作社印" 五、發明說明（13 ) 信號的質部與虛部以加總器6 0結合，得到一解析信 號。經由乘法器6 2 ’實數對解析轉換5 9的複合輸出信 號乘以由P L L 6 1產生的調適相位旋轉修正因數。鎖相 迴路6 1的功能是模擬通信網路所累積的相位偏移e 1 «。 接著1經由加總器3 7，從A / D轉換器4 0的輸出中減 去乘法器6 2之輸出的實部及近端回波消除器3 3的輸出 °接著，加總器3 7所得到的輸出輸入到接收機R X 3 4 〇 習知技術之回波消除器設計的主要缺點是Hilbert轉換 需要消耗很大的CPU資源。 圖3顯示遠端回波消除器的第二種習知技術，嘗試克 服圖2之遠端回波消除器的問題。回波消除器4 1包括調 適FIR濾波器54、乘法器62、鎖相迴路61及取實 功能6 4。 發射機T X 3 2產生一複合解析信號。當在頻域中看 解析信號時，僅具有一側的頻率分量（正或負，在本實施 中爲正）。複合樣本流的實部被傳送並通過近端回波消除 器’同時，複合樣本流被延遲暫存器3 5延遲。被延遲的 複合信號被調適F I R濾波器5 4濾波，其功能是模擬回 波損失路徑。A F I R濾波器的複合輸出信號’經由乘法 器6 2乘以由P L L 6 1所產生的調適相位旋轉修正因數 e p。接著，經由加總器3 7，從A / D轉換器4 0的 輸出宁減去乘法器輸出的實部6 4及近端回波消除器3 3. 的輸出。接著 > 所得到的輸出輪入到接收機R x 3 4。 i—I n *^1 - ί 11 - - - -- ^^1 f^i I it— I- M 訂---------- {請先Mti背面之注意事項再填寫本頁) 本紙張尺度遇用中® S家標準（CNS)A4規格（210 x 297公；ίί ) -16- A7 B7 經濟部智慧財產局貝二消货合作社印.¾ 五、發明說明（14) 上述實施遠端回波消除器的第二種習知技術也有幾項 缺點=缺點之一是由於要儲存複合信號’因此延遲暫存器 所需要的記憶體加倍。另一個缺點是雖然去掉了消耗 c P U資源的FIR H i 1 b e r t轉換1但調適F I R所消耗的 C P U資源加倍，原因是調適濾波器是對複合信號操作’ 而非只對信號的實部操作。爲補償最惡劣的回波損失情況 ，因此A F I R 5 4通常是很長的濾波器，實施此也需要 很大的C P U資源。 圖4是說明習知技術之頻域捲積法的高階方塊圖。此 方法廣泛用於經由相乘雨時域信號之快速傅立葉轉換以捲 積兩時域信號。該方法包括取第一複合輸入並執行第一 F F T功能2 1 0，取第二複合輸入並執行第二F F 丁功 能2 1 2，接著，第一及第二FFT的結果以乘法器 2 1 4相乘，接著對乘積執行I F F T功能2 1 6，得到 一複合輸出。 本發明所提供的頻域濾波設計克服了習知技術的缺點 與限制。圖5顯示使用本發明之實數對解析快速捲積所架 構的遠端回波消除器實施例。實施本發明之方法的遠端回 波消除器1 7 0包括實數對解析快速捲積功能8 4 '乘法 器8 6、P L L功能8 7、實功能8 8及先進先出（ F I F ◦)(例如延遲暫存器）9 ◦。 發射機T X 8 0產生一通帶（即僅有實部）樣本輸出 流=使用延遲暫存（即F I F 〇 ) 8 2延遲樣本流。從發 射機輸出的每一個樣本被推入F I F08 2 *當 ---------------- ·丨 11 i 111 訂 ---------- (猜先閲背面之注意事項再填寫本頁) 本紙張尺度通用中囷囤家標準（CNS)A4規格（2】〇χ 297公釐） -17 - 五、發明說明（15) A7 B7 F I F 〇 8 2 被 塡 滿 1 長 度 爲 N — K 的 緩 衝 被 輸 入 到 本 發 明 的 實 數 對 解 析 快 速 捲 積 方 塊 8 4 它 執 行 調 適 瘋 波 及 實 數 對 解 析 的 轉 換 0 値 Ν 是 該 方 法 所 執 行 之 F F 丁 的 長 度 値 K a 疋 該 方 法 所 實 施 之 應 波 器 的 長 度 0 請 注 思 ! 實 數 對 解 析 快 速 捲 積 方 塊 8 4 > P L L 8 7 及 乘 法 器 8 6 的 輸 出 都 是 複 合 輸 出 f 因 此 以 雙 線 模 擬 表 示 0 實 數 對 解 析 快 速 捲 積 方 塊 8 4 輸 出 的 複 合 信 號 乘 以 P L L 8 7 所 產 生 之 調 適 相 位 旋 轉 修 正 因 數 e i t ? Q 接 ¥著， 乘 法 □ t=3 益 8 6 所 輸 出 之 信 Dr^ 的 實 部被 儲 存 到 F I F 〇 9 〇 0 從 A / D 轉 換 器 輸 出 的 接 收 信 號 被 儲 存 到 F I F 〇 9 8 〇 此. 外 J 來 白 近 端 回 波 消 除 器 9 4 的 信 號 也 被 儲 存 到 F I F 〇 9 6. 〇 輸 入 到 接 收 機 9 2 的 每 — 個 樣 本 j 都 是 從 取 白 F I F 0 9 8 之 樣 本 中 減 去 F I F 〇 9 0 中 之 個 樣 本 以 及 F I F 0 9 6 中 之 個 樣 本所得 到 的 樣 本 0 遠 端 回 波消 除 □□ 中 所使 用 之 每 —- 個 延 遲 暫 存 器 或 F I F 0 的 長 度 如 下 -------------裝·-- (請先閱讀背面之注意事項再填寫本頁) - --韓. 經"部智慧W產局員Η消货合作社印製 延遲暫存器或FIFO 長度 FIFO 8 2 max ( RTD, N-K ) FIFO 9 6, 9 8 max ( 0, N-K-RTD ) FIFO 90 N-K 其中RTD是估計的往返延遲，以取樣次敝的敝董度 本紙讯尺度適用中® ®家檁準（CNS)A4規格（210 X 297公釐） -18 - 經濟部智^財產局員工消貨合作社印*:< 5 61 28 A7 -------B7__五 '發明說明（16) 在區I 2及3所示的習知技術回波消除設計中，延遲暫 存器的大小與估計的往返延遲完全相同。不過，由於 F F T演算的應用，需要長度等於實數對解析快速捲積方 塊8 4之輸入緩衝長度N - K的全緩衝，因此 F I F 〇 8 2的大小需要大於或筹於N — K。實數對解析 快速捲積方塊8 4的輸出，在經過相位補償及取實部後， 必須儲存到另一個F I F0 9 0中。F I F09 0的大小 必須等於實數對解析快速捲積方塊爲每一個輸入緩衝輸出 之有效樣本的數量。此外，如果往返延遲小於N - K，則 F I F 0 8 2所引入的額外延遲必須以一對F I F ◦ 9 6 、9 8補償’每一個的長度爲n — K — RTD。 本發明的優點是緩和了前述記憶體及C P U資源的使 用問題。所需使闻的記憶體減少，因爲僅需將實樣本儲存 到延遲暫存（即F I F0)中，因此，不需要如第二種習 知設計需要雙倍記億體。 所使用的C P u資源也減少，·因爲本發明的實數對解 析快达捲積.法不需要時域Η1 i b e η轉換濾波’且能在絕大多 數的計算機上以更有效率的方法執行捲積。 圖6是本發明之實數對解析快速捲積第一種實施例的 高階方塊圖。該設計是以實係數捲積實輸入樣本的解析部 分。對實輸入樣本執行第一 F F T 2 2 0 '對實係數執行 第二F F T 2, 2 2 ^接著，頻域係數之元素逐一與理想實 數對解衍轉換之頻率響應相乘，以在頻域執行實數對解析 轉換t在本例中正频率解析信號的響應爲 1JH ^^1 n f— ^^1 - - ί - n ^^1 I 一d 1 I 1^1 Bit t— ^^1 n 一.· Λ ^^1 HJ Ϊ I— *n t^l n {請先M讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公龙） -19" 45 6 1 28 A7 _ B7 經濟部智慧財產局員工消货仓作··社印·" 五、發明說明（17 ) '2 0 < 1 <N/2 T p ( 1 )二 i =0> on = N / 2 [0 else 其中，T p ( i )是理想實數對解析（正頻率）轉換的 頻率響應，〇 S 1 < N及N是轉換的大小。 在負頻率解析信號的情況，響應爲 '2 Ν/2<ι<Ν T n ( ί ) = 1 1 i =0<?/i =Ν/2 〇 else 其中，T H ( i )是理想實數對解析（負頻率）轉換 的頻率響應，0名i < N及N是轉換的大小。須注意，當 使甩Tn ( 1 )時，即負頻率，頻移乘數e u必須是其共 軛。經由乘法器2 2 6，一半爲零的頻譜與前 所得到的第一 F F T元素逐一相乘。所得到的乘積接著輸 入I F F T.功能2 2 8，以得到複合輸出信號。 圖7是本發明之實數對解析快速捲積第二種實施例的 高階方塊圖。此設計與圖6之設計非常相似。差異處是以 實輸入樣本之F F T的元素，而非實係數，逐一與理想實 數對解析轉換之頻率響應經由乘法器2 2 4相乘。在兩種 設計中，所獲得的結果相同，即’兩種設計之乘法器 2 2 6的蝓出相同^ 圖8是說明習知技術之 '' 重®與儲存〃頻域區塊捲横 ! I--------- i . · -------f 訂·----! I ! ί ^ (請先閱讀背面之注意事項再填窝本頁) 本紙張尺度適用中固®家棵準（CNS)A4規格（210 X 297公发） -20 - 456128 Α7 Β7 經濟部智慧財產局員工消货合作杜印" 玉、發明說明（π) 設計的高階方塊圖。將κ個樣本1 〇 2置入緩衝器’並與 N _ K個輸入樣本1 0 0結合，構成一長度爲N的向量。 向量中的第一個K樣本是由內部記憶體提供’記憶體中儲 存前一個處理周期之輸入向量的最後一個κ樣本。 接著，大小爲N的向量歷經大小爲N之F F T轉換 1 0 4，得到輸出向量S ( i )。長度爲K的濾波脈衝響 應1 06，它是F IR係數，置入長度爲N的緩衝器。大 小爲N - K之緩衝器1 0 8的所剩部分以零塡充。經結合 構成一長度爲N的係數向量，接著歷經大小爲N的F FT 轉換1 1 0，得到大小爲N之頻域複合係數向量C ( i ) 。請注意，如杲濾波器不隨時間改變，則向量C ( 1 )可 以事先計算，或，向量C ( 1 )也可以隨時（on the fly ) 計算。 接著，以乘法器1 1 2將所得到之兩個頻域向量S ( i )及C ( i )的元素逐一·相乘。接著，大小爲N的乘法 器輸出經過反F F T轉換。所得到的向量包括N - K個有 效樣本及K,個無效樣本。產生無效樣本的原因是在快速捲 積設計（F F Τ'、乘、I F F T )中執行循環捲積的結果 。Ν _ Κ個有效輸出樣本被擷取，並爲次一個處理區塊儲 存來自輸入向量之最後的Κ樣本。因此，圖8所示之習知 技術的 ''重疊與儲存〃頻域區塊捲積設計，可以爲每一個 Ν — Κ個輸入樣本產·生Ν - Κ個輸出樣本。 區丨9顯不結合按照本發明所架構之實數對解析轉換之 频域爐波器的實施例。一緩衝器被實輸入樣本塡滿以構成 本紙張尺度通用中固國家標準（CNS)A4規格（210 x 297公釐） -21 - {請先閱？？背面之注意事項再填寫本頁). 裝 ---訂---------'^ 456128 A7 B7 五、發明說明（19 ) 一重疊窗口緩衝器，與圖8的設計相同。將κ個樣本 1 2 0置入緩衝器，並與ν ~ Κ個輸入樣本丨2丄結合， 構成—長度爲N的向量。向量中的第一個κ樣本是由內部 g己憶體提供’記憶體中儲存前一個處理周期之輸入向量的 最後一個K樣本。最後的K — N個樣本組成輸入向量是爲 N — K個樣冻；輸入到實數對解析快速捲積方塊8 4 (圖5 )。接著，輸入向量經過大小爲N的F FT轉換1 2 2得 iil S ( 1 )。 長度爲Κ的濾波脈衝響應1 2 4，它包括F I. R係數 ’置入長度爲Ν的緩衝器。大小爲Ν — Κ之緩衝器1 2 5 的所剩部分以零塡充。經結合構成一長度爲Ν的係數向量 ，接著經過大小爲Ν的F F Τ轉換1 2 6，得到大小爲Ν 之頻域複合係數向量C (:)。請注意，如果濾波器不隨 時間改變，則向量C 〔 1 )可以事先計算，或 > 向量C ( i )也可以隨時（on the fly )計算。 接著，頻域係數之元素逐一與理想實數對解析轉換之 頻率響應相.乘 > 在頻域對F F T 1 2 6的胃輸出執行實數對 解析轉換1 2 8。在本例中，正頻率解析信號的響應爲 '2 0 < 1 <Ν/2 τ p ( 1 ) = < 1 1 = 0 0/i = N/2 、0 else 其中，丁 P ( i )是理想實數對解析（正頻率）轉換的 頻率響應.〇 g 1 < N及N是轉換的大小。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國0家楳準（CNS)A4規格（210 X 297公ίί ) -22-I J1T 'SI f This paper has been used in China National Standards (CNS); M specifications (210 X 297 gong) -12 456128 A7 B7 V. Description of the invention (1〇) Symbols used in the detailed description of the invention Used in this document The following symbols are printed by the Consumer Goods Cooperatives of the Intellectual Property Bureau of the Ministry of Economy ^ Symbol definition C 〇Central computer room C pu Central processing Og Car element DAA Data access configuration DSP Digital signal processing FC Fast convolution FDM Frequency division multiplexing FEED Remote back Wave cancellation FFT fast Fourier transform FIF 〇 first-in-first-out FIR finite impulse response IFFT inverse fast Fourier transform ISI intersymbol interference IT u. International Telecommunication Union M A c multiplication and accumulation P LL phase-locked loop RF RF R Ύ D round-trip delay S s B signal side ytib emperor (please read the notes on the back before filling this page) This paper size is applicable to China Solid State Standard (CNS) A4 specification (210 X 297 male «) -13-45 61 28 A7 B7 property Du Yin, Co-operation of Consumer and Consumer Goods-V. Description of the Invention (11) General Description For the purpose of illustration, the method taught by the present invention is demonstrated by the far-end echo canceller filtering function in an audio full-duplex communication system, such as the maximum I. U. V.23bis with a data rate of 14,400 bps, or ITU V. 34 with a maximum data rate of 12,800 bps. The far-end echo cancellation filter can be designed using fast convolutions | such as the well-known `` overlap and storage '' design. It must be noted that those skilled in the art can apply the design taught by the present invention to other filters in a data machine, such as an equalization filter that performs inter-symbol interference (ISI) cancellation, and a near-end echo cancellation filter. And for other signal processing applications | such as radio frequency (RF.) Modems and echo cancellers. In addition, those skilled in the art can apply the method of the present invention to other fast convolution designs, such as '' overlap and add '' techniques. As mentioned above, the conventional full-duplex audio data machine of FIG. 1 includes a transmitter 3 2, a receiver 3 4 'echo canceller unit 36, a totalizer 37, a D / A converter 38, A / D converter 40 and DAA or hybrid 4 2. The echo canceller unit includes a near-end echo cancellation filter 3 3, a delay line 3 5, a far-end echo cancellation filter 41, and a totalizer 31. The transmitter receives the input transmission data from the TX data input port and outputs the transmission (TX) samples to the echo canceller unit 36 and the D / A converter 38. The function of the DAA is to send the data from the central computer room (C ◦) The balanced analog voltage on the two wire pairs is converted into two unbalanced two wire pairs that are supplied to the transmitter 'and another to the receiver (or vice versa)' to match the telephone line and the transmitter and receiver. impedance. Echo canceller unit 3 6 ------------ *-1 -------- 丨 order --------- Miscellaneous, (Please read the precautions on the back before (Fill in this page) This paper is used in 5 standard 1 @@@ 家家 标准 (CNS) A4 specification (210 X 297 public 茇) -14-5 6128 A7 B7 V. Description of the invention (12) Function is to use adaptive near-end filter 'Remove near-end echoes' and use far-end filters to remove far-end echoes to remove echoes from the received signal. The signal input to the far-end filter is delayed 'by the delay line 35 to match the round-trip delay (RTD) introduced from the network. The signals output by the far-end filter and the near-end filter are summed by a totalizer 3 1 to generate an input of the echo canceller unit. Next, the totalizer 37 is used to subtract the output of the echo canceller from the received signal. The receiver outputs a digital receive R X data output signal. Figure 2 shows a detailed block diagram illustrating a conventional technique for implementing a bandpass far-end echo canceller. The far-end echo canceller 41 includes an adaptive FIR filter 5 4. Hilbert conversion 5. 6. Delay temporary storage 5. 8. Multiply by '' j 〃 () function 5. 7. Totalizer 6. 0. Phase-locked loop ( PLL) module, multiplier 6 2, and real component acquisition function 64. The transmitter TX 3 2 generates a modular passband sample stream. The sample stream is temporarily delayed by 35 delays. Its minimum depth is the maximum round-trip delay introduced from the communication network. The signal then passes through the F I R filter to benefit 5 4 and its function is to simulate the return loss path. At this point the signal is a real signal. The signal then undergoes a real-to-analytic conversion 5 9 which includes Η11 ben conversion 5 6, a delay buffer 5 8 'multiplied by V-1, and a totalizer 6 0. The signal undergoes an in-phase to quadrature conversion by a Hi? Be r t conversion function 5 6 ′ implemented by an F 1 R filter. The real part is temporarily stored for 5 8 delays. Its function is to compensate for the delay caused by the implementation of the FI R Η Π b e τ t conversion function. The depth of the delay buffer 5 8 is exactly half the number of taps of the F I R filter used to implement the Hilbert conversion function. 1 ------- 1 ------- f »1 I I ---- Order · ---! ---- {Please read the notes on the back before filling this page) This Paper size is suitable for gg® CNS A4 size (210x 297 gong) -15-45 6 彳 28 A7 B7 Printed by the Consumer Goods Cooperative of the Intellectual Property Office of the Ministry of Economic Affairs " V. Description of Invention (13) Signal The prime part and the imaginary part are combined by the totalizer 60 to obtain an analytic signal. The multiplier 6 2 'real-to-analytic conversion 5 9 composite output signal is multiplied by the adaptive phase rotation correction factor generated by the PLL 6 1. Lock The function of the phase loop 6 1 is to accumulate the phase offset e 1 «accumulated in the communication network. Then 1 subtracts the output of the multiplier 6 2 from the output of the A / D converter 40 through the totalizer 37. The output of the real part and the near-end echo canceller 3 3 ° Then, the output obtained by the totalizer 37 is input to the receiver RX 3 4 〇 The main disadvantage of the echo canceller design of the conventional technology is that Hilbert conversion requires consumption Large CPU resources. Figure 3 shows the second conventional technique of the far-end echo canceller, trying to overcome the problem of the far-end echo canceller of Fig. 2. The echo canceller 41 includes FIR filter 54, multiplier 62, phase-locked loop 61, and fetch function 6 4. The transmitter TX 3 2 generates a composite analytical signal. When the analytical signal is viewed in the frequency domain, it has only one side of the frequency component ( (Positive or negative, positive in this implementation). The real part of the composite sample stream is transmitted and passed through the near-end echo canceller. At the same time, the composite sample stream is delayed by the delay register 35. The delayed composite signal is adapted FIR filter 54 filtering, its function is to simulate the return loss path. The composite output signal of the AFIR filter is multiplied by a multiplier 6 2 by the adaptive phase rotation correction factor ep generated by PLL 6 1. The converter 3 7 subtracts the output of the real part 6 4 of the multiplier output and the output of the near-end echo canceller 3 3. from the output of the A / D converter 4 0. Then the resulting output is rounded to the receiver R x 3 4. i—I n * ^ 1-ί 11----^^ 1 f ^ i I it— I- M Order ---------- {Please pay attention to the back of Mti first Please fill in this page for more information.) This paper size is in use® S Family Standard (CNS) A4 specification (210 x 297 public; ί) -16- A7 B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the China Consumer Goods Cooperative. ¾ 5. Description of the invention (14) The above-mentioned second conventional technique of implementing a remote echo canceller also has several disadvantages = one of the disadvantages is the delay of the register due to the need to store composite signals. The required memory is doubled. Another disadvantage is that although the FIR H i 1 b e r t conversion that consumes c P U resources is removed, the C P U resources consumed by adapting F I R are doubled, because the adaptation filter operates on the composite signal ’and not only the real part of the signal. In order to compensate for the worst case of return loss, A F I R 5 4 is usually a very long filter, and implementation of this also requires a large C P U resource. FIG. 4 is a high-order block diagram illustrating a frequency domain convolution method of the conventional technique. This method is widely used to convolve two time-domain signals via a fast Fourier transform of the multiplying rain-time domain signals. The method includes taking a first composite input and performing a first FFT function 2 1 0, taking a second composite input and performing a second FF Ding function 2 1 2, and then, the results of the first and second FFTs are multiplied by 2 1 4 Multiply, and then perform the IFFT function 2 1 6 on the product to get a composite output. The frequency domain filtering design provided by the present invention overcomes the disadvantages and limitations of the conventional technology. Fig. 5 shows an embodiment of a far-end echo canceller constructed using the real-pair analytical fast convolution of the present invention. The far-end echo canceller 170 implementing the method of the present invention includes a real-pair parsing fast convolution function 8 4 'multiplier 8 6, PLL function 8 7, real function 8 8 and first-in-first-out (FIF ◦) (eg Delay register) 9 ◦. The transmitter T X 8 0 generates a passband (that is, only the real part) sample output stream = using delayed temporary storage (that is, F I F 0) 8 2 delayed sample stream. Every sample output from the transmitter is pushed into FI F08 2 * When ---------------- · 11 i 111 Order ---------- (Guess Please read the notes on the back before filling in this page.) This paper is a universal standard (CNS) A4 specification (2) 〇χ 297 mm. -17-V. Description of the invention (15) A7 B7 FIF 〇 8 2 Fully buffered with a length of N — K is input to the fast pair of real number parsing in the present invention. 8 4 It performs the conversion of the adaptive wild wave and real number parsing. 0 値 N is the length of FF Ding performed by this method. K a 疋 The length of the echo wave implemented by this method is 0. Please note! The output of real pair parsing fast convolution block 8 4 > The output of PLL 8 7 and multiplier 8 6 are composite outputs f. 0 Real number pair analytic fast convolution block 8 4 Multiply the composite signal output by PLL 8 7 The adaptive phase rotation correction factor eit generated by Q? Q is followed by multiplication □ t = 3 益 8 6 The real part of the output letter Dr ^ is stored in the FIF 〇9 〇0 The received signal output from the A / D converter is stored in the FIF 〇9 8 〇 Here. The signal from the white near-end echo canceller 9 4 from J Also stored in FIF 〇9 6. 〇 Each sample j input to receiver 9 2 is subtracted from the sample taken FIF 0 9 8 FIF 〇 0 0 samples and FIF 0 9 6 The sample 0 obtained from each sample is used in the far-end echo cancellation □□ The length of each delay register or FIF 0 is as follows: (Please read the precautions on the back before filling out this page)---Han. The Ministry of Economics & Production Bureau, Consumer Goods Co., Ltd. printed delay register or FIFO length FIFO 8 2 max (RTD, NK) FIFO 9 6, 9 8 max (0, NK-RTD) FIFO 90 NK where RTD is the estimated round-trip delay and the sampling times are based on the paper standard applicable ® ® Home Standard (CNS) A4 (210 X 297 Mm) -18-Ministry of Economic Affairs ^ Printed by the staff of the Property Bureau, Consumer Goods Cooperatives *: < 5 61 28 A7 ------- B7__Five 'Invention Description (16) In the conventional technology echo cancellation design shown in districts I 2 and 3, delay The size of the scratchpad is exactly the same as the estimated round-trip latency. However, due to the application of F FT calculus, a full buffer with a length equal to the input buffer length N-K of the analytic fast convolution block 8 4 is required. Therefore, the size of F I F 〇 8 2 needs to be larger than or equal to N-K. The output of the fast convolution block 8 4 of real number pair analysis must be stored in another F I F 0 9 0 after phase compensation and real part taking. The size of F I F09 0 must be equal to the number of valid samples that the real-time parsing fast convolution block buffers for each input. In addition, if the round-trip delay is less than N-K, the extra delay introduced by F I F 0 8 2 must be compensated with a pair of F I F ◦ 9 6, 9 8 'each of which has a length of n — K — RTD. The advantage of the present invention is that it alleviates the aforementioned problems of using memory and CP resources. The required memory is reduced because only the real samples need to be stored in the deferred temporary storage (ie, F I F0), so there is no need to double the number of billions as in the second conventional design. The CP u resources used are also reduced, because the real number pair analysis of the present invention reaches fast convolution. The method does not require the time domain Η1 ibe η conversion filtering 'and can perform the volume in a more efficient way on most computers. product. Fig. 6 is a high-order block diagram of the first embodiment of real-pair analytical fast convolution of the present invention. The design convolves the analytic part of the real input samples with real coefficients. Perform the first FFT on the real input samples 2 2 0 'Perform the second FFT on the real coefficients 2, 2 2 ^ Then, the elements of the frequency domain coefficients are multiplied one by one with the frequency response of the ideal real number to the derivation conversion to perform in the frequency domain The response of the real number to the analytic conversion t in this example is 1JH ^^ 1 nf— ^^ 1--ί-n ^^ 1 I a d 1 I 1 ^ 1 Bit t— ^^ 1 n one ... Λ ^^ 1 HJ Ϊ I— * nt ^ ln {Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) A4 (210x 297 male dragon) -19 " 45 6 1 28 A7 _ B7 Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs made a storehouse sale ·· Institute of Seals " V. Invention Description (17) '2 0 < 1 < N / 2 T p (1) two i = 0 > on = N / 2 [0 else where T p (i) is the frequency response of the ideal real number to the analytic (positive frequency) conversion, and θ 1 < N and N are the sizes of the conversion. In the case of analysing signals at negative frequencies, the response is' 2 Ν / 2 < ι < Ν T n (ί) = 1 1 i = 0 <? / I = Ν / 2 〇else where TH (i) is the ideal real number pair Analyze (negative frequency) the frequency response of the transition, where 0 < N and N are the magnitude of the transition. It should be noted that when Tn (1) is caused, that is, a negative frequency, the frequency shift multiplier e u must be its conjugate. Via the multiplier 2 2 6, the half-zero spectrum is multiplied one by one with the first F F T element obtained previously. The resulting product is then input to I F F T. function 2 2 8 to obtain a composite output signal. Fig. 7 is a high-level block diagram of the second embodiment of the real-pair analytical fast convolution of the present invention. This design is very similar to the design of Figure 6. The difference is the element of F F T of the real input sample, not the real coefficient, and the frequency response of the analytic conversion of the ideal real number one by one is multiplied by a multiplier 2 2 4. In both designs, the obtained results are the same, that is, 'the multipliers 2 2 6 of the two designs have the same output ^ Figure 8 illustrates the conventional technique's 重 与 and storage 〃 frequency domain block curling! I --------- i. · ------- f Order · ----! I! Ί ^ (Please read the precautions on the back before filling in this page) This paper size applies High-level block diagram of the design of Zhonggu® Jiashuzhun (CNS) A4 (210 X 297) -20-456128 Α7 Β7 Consumer Goods Cooperation Dumpling " Jade and Invention Description (π) Design of Intellectual Property Bureau of the Ministry of Economic Affairs Κ samples 1 02 are placed in a buffer 'and combined with N_K input samples 1 0 0 to form a vector of length N. The first K sample in the vector is provided by the internal memory. The memory stores the last k sample of the input vector from the previous processing cycle. Next, a vector of size N undergoes F F T of size N to transform 1 0 4 to obtain an output vector S (i). The filter pulse of length K responds to 106, which is the FIR coefficient, and is placed in a buffer of length N. The remaining part of the buffer 108 of size N-K is filled with zero margin. After combining, a coefficient vector of length N is formed, and then F FT of size N is converted into 1 1 0 to obtain a frequency domain composite coefficient vector C (i) of size N. Note that if the (filter does not change over time, the vector C (1) can be calculated in advance, or the vector C (1) can be calculated on the fly. Then, the multipliers 1 1 2 multiply the elements of the two frequency domain vectors S (i) and C (i) obtained one by one. Next, the output of the multiplier of size N is inverse F F T converted. The resulting vector includes N-K valid samples and K, invalid samples. The cause of the invalid samples is the result of performing a circular convolution in a fast convolution design (F F T ′, multiplication, I F F T). N_K valid output samples are captured and the last K samples from the input vector are stored for the next processing block. Therefore, the “overlap and storage” frequency domain block convolution design of the conventional technique shown in FIG. 8 can generate N-K output samples for each N-K input sample. The embodiment 9 does not combine the embodiment of the real-time-to-analytic conversion frequency-domain furnace device constructed in accordance with the present invention. A buffer is filled with actual input samples to form the paper. This paper is a standard of the National Solid State Standard (CNS) A4 (210 x 297 mm). -21-{Please read first? ? Note on the back, please fill in this page again). Assemble --- Order --------- '^ 456128 A7 B7 V. Description of the invention (19) An overlapping window buffer, the same design as in Figure 8. Put κ samples 1 2 0 into the buffer and combine them with ν ~ K input samples 2 丨 to form a vector of length N. The first κ sample in the vector is provided by the internal g memory, and the last K sample in the memory stores the input vector of the previous processing cycle. The final K — N samples make up the input vector as N — K samples; the input is parsed into a fast convolution block 8 4 (Figure 5). Next, the input vector undergoes F FT conversion of size 1 2 to obtain iil S (1). The filter impulse response of length K is 1 2 4 which includes the F I. R coefficient ′ placed in a buffer of length N. The remaining part of the buffer 1 2 5 of size N-K is filled with zero. After combining, a coefficient vector of length N is formed, and then F F TT of size N is converted into 1 2 6 to obtain a frequency domain composite coefficient vector C (:) of size N. Note that if the filter does not change with time, the vector C [1] can be calculated in advance, or the vector C (i) can also be calculated on the fly. Next, the elements of the frequency-domain coefficients are one-by-one with the frequency response of the ideal real-to-analytic conversion. Multiply > Perform real-to-analytic conversion 1 2 8 on the gastric output of F F T 1 2 6 in the frequency domain. In this example, the response of the positive frequency resolved signal is' 2 0 < 1 < N / 2 τ p (1) = < 1 1 = 0 0 / i = N / 2, 0 else where 丁 P ( i) is the frequency response of an ideal real number to an analytical (positive frequency) conversion. og1 < N and N are the sizes of the conversion. (Please read the precautions on the back before filling out this page) This paper size applies to China's 0 Chinese standard (CNS) A4 specification (210 X 297 公 ί) -22-
45 61 2 Q 蛵滑部智慧財產局員工消&合作社印^ 頻 率 響 應 0 i < N 及 N 用 T N ( ί )時 ，即] 黃頻率 C e -j 1 Θ ) 〇 在 實 時 域 信 號 相 當 於 實 m :對 解 析 轉 換 〇 此 N / 2 + 1 的 有 效 大 小 0 此 改 變 j 則 向 丨量 C (: " 可 以 事 接 著 乘 χ.·™4- 広 DO 窃 1 3 0 將 與 F F 丁 方 -塊 1 2 2 輸 出 的 區 塊 的 逐 — .元 素 乘 法 只 需 N 乘 法 器 1 3 0 输 出 的 合 成 1品 I F F T 方 '塊 1 3 2 輸 出 的 本 1 3 6 > 以 及 K 個 姐 ^ 1 ' V 效 樣 因 曰 在 快 速 丨捲 積 三几 DX 計 f \ F F -^βϊ m X/iJ. 積 的 結 :杲 〇 因 此 J 實 數 5 ) 爲 每 ~1 .個 Ν — K 個 輸 入 使 本 :發 明 所 教 導 之 方 第 優 S占 曰 aE :節 省 記 憶 體 〇 它 波 消 除 器 ϊ 不 需 耍 加 倍 的 記 本紙汛尺度適用中困酉家棵準（CNS)A4规格（210 A7 B7 五、發明說明（2〇 ) 在負頻率解析信號的情況，響應爲45 61 2 Q Employees of the Intellectual Property Bureau of the Ministry of Economic Affairs & Cooperative Society ^ Frequency response 0 i < N and N when using TN (ί), that is] yellow frequency C e -j 1 Θ) 〇 equivalent signal in real-time domain Yu Shim: Analytical transformation. This effective size of N / 2 + 1 is 0. This change j will be the amount of C (: " can be multiplied by χ. · ™ 4- 広 DO theft 1 3 0 will be FF D Square-to-block 1 2 2 block-by-block output. Element multiplication requires only N multiplier 1 3 0 to output the synthesized 1 product IFFT square 'block 1 3 2 to output 1 1 6 > and K sisters ^ 1 The 'V' effect is that in the fast 丨 convolution of three DX DX calculations f \ FF-^ βϊ m X / iJ. The result of the product: 杲 〇 Therefore J real number 5) is every ~ 1. N — K inputs make this : The invention teaches the best formula S accounted for aE: saves memory 〇 wave wave eliminator ϊ do not need to play double-note notebook paper flood scale applicable to the difficult family standard (CNS) A4 specifications (210 A7 B7 V. invention Explanation (2〇) The case of analyzing a signal at a negative frequency Response to
2 N/2 < i <N Τ ν ( i ) = ί = 0 or i = N//2 else 其中，Τ κ ( i )是理想實數對解析（負頻率）轉換的 是轉換的大小β須注意，當使 ，頻移乘數e 必須是其共軛 的情況’將負頻率分量變爲零 減小了向量δ(ί)到 外’如果F I R係數不隨時間 先或隨時（onthefly)計算》 實數對解析轉換1 2 8的輸出 向量S ( i )相乘。須注意， / 2 + 1次複數乘法。接著對 塊執行反FFT132。從 合成向量包括N — K個有效樣 本1 3 4。產生無效樣本的原 丁、乘、I F F T )中執行循 對解析快速捲積方塊8 4 (圖 樣本產生Ντ - K個輸出樣本。 法執行頻域捲積有三大優點。 不像圇3之習知技術的遠端回 憶體。 -23 - - --- -I I fll· u n 1 1^1 r t f_i ^^1 1! ί ί - n 訂---------,^ (請先閱讀背面之注意事項再填寫本頁)， 經濟部智慧財產局員工消費合作杜印說 456128 A7 ___B7____ 五、發明說明（Μ ) 第二優點是減少使用c p u。在本發明的方法中1省 去了 Hilbert瀘波器5 6 (圖2 )。此外，比圖8所示的、' 重疊與儲存〃設計更有效率，因爲，在頻域中，只需要半 數的乘法。此外，熟悉此方面技術的人士可利用將 I F F T之第一階段中的負頻率分量變爲零以更進一步減 少使用C P U，且只需計算S ( i )中一半的點。 第三優點是，從每次輸出樣本需執行複數乘法之次數 的角度來看，圖5及9的快速捲積設計比圖2及3所實施 的習知技術更有效率，原因是在絕大部分的計算機上，與 F F T及I F F T相關之演算法比F I R濾波的計算複雜 度相對低了許多。 本發明之頻域濾波設計的另一種應用是分頻多工（ F D-Μ)系統。典型的F DM通訊系統可在一個輸出頻道 上多工複數個輸入頻道。每一個輸入頻道首先被濾波以產 生帶寬限制信號。濾波之後，信號之頻率被位移一對應於 指定給輸入頻道之特有頻_隙的特定量，亦即單邊帶（ S S B )調制。 圖1 0顯示本發明之頻域濾波設計用於分頻多工（ F D Μ )系統的高階方塊圖。以頻道# 1到頻道# N表示 的複數個輸入頻道信號，輸入到濾波器及頻移模組2 4 0 排。每一個濾波器及頻移模組2 4 0包括一實數對解析快 速捲積方塊2 3 0、乘法器2 3 2、本地振還器2 3 6、 以及複誔實功能方塊2 3 4。須注意1實數對解析快速捲 積方塊2 3 0、乘法器2 3 2 '本地振盪器2 3 6的蝓出 ------------* _ 裝·--------訂·--------¾ (請先Μ讀背面之泫意事項再填寫本頁) 本紙張尺度適用中® ®家棵準（CNS)A4規格（210 X 297公犮） -24 - Α7 Β7 五、發明說明（22 ) 是複合信號。實數對解析快速捲積方塊2 3 0、乘法器 2 3 2、以及複到實功能方塊2 3 4所執行的功能，分別 與實數對解析快速捲積方塊8 4、乘法器8 6及複到實功 能方塊8 8相同。對每一個的描述與前圖5相同。本地振 盪器是用來產生某指定頻率之正弦波形的電路。它可被相 移以產生9 0度相位差的信號，即正弦與餘弦。每一個濾 波器及頻移模組2 4 0的輸出經由加總器2 4 2相加，以 得到一合成的F D Μ輸出信號。 每一個頻道的頻移由複合信號e』ωι 1中的ω.ί決定， 它是由本地振盪器2 3 6產生及輸出。每一個頻道都有其 獨有的本地振盪器，其頻率爲ω,，其中i是頻道編號。 須注意，頻道的輸入信號被濾波及頻移，但並未使用 F I R濾波或Hilbert轉換。 .使周本發明之頻域濾波設計的優點是不需要Hllbert轉 換。除了不需要Hilbert轉換外，本發明的頻域濾波設計也 比對等的F I R濾波器快。本發明應用於f D Μ系統十分 適當，因爲每一個輸入頻道都包括一實信號，而非複合實 經浯部智慧財產局員工消費合作社印" ------------ ---- (請先閱讀背面之注意事項再填寫本頁) 及虛部的解析信號。 雖然本發明是以有限數量的實施例加以描述 > 但必須 瞭解，本發明還可做到很多變化及修改，以及其它的應用 本紙張尺度通用中囷®家棍準（CNS)A4規格（2i〇x 297公龙） -25-2 N / 2 < i < N Τ ν (i) = ί = 0 or i = N // 2 else where τ κ (i) is the ideal real number pair resolution (negative frequency) conversion is the size of the conversion β It must be noted that when the frequency shift multiplier e must be its conjugate case 'turning the negative frequency components to zero reduces the vector δ (ί) to the outside' if the FIR coefficients are not calculated first or on time (onthefly) over time 》 Real numbers are multiplied by the output vector S (i) of the analytic transformation 1 2 8. Note that / 2 + 1 complex multiplication. An inverse FFT 132 is then performed on the block. From the synthesized vector includes N — K valid samples 1 3 4. In the original sample, multiplication, and IFFT, which generate invalid samples, perform fast recursive analysis of convolution blocks 8 4 (picture samples generate Nτ-K output samples. There are three major advantages to performing frequency-domain convolution. Unlike the 囵 3 practice The remote memory of technology. -23----- -II fll · un 1 1 ^ 1 rt f_i ^^ 1 1! Ί ί-n Order ---------, ^ (Please read first Note on the back, please fill in this page again.) Du Yin, employee cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs said 456128 A7 ___B7____ 5. Description of the Invention (M) The second advantage is to reduce the use of CPUs. In the method of the present invention, 1 Hilbert is omitted. The waver 5 6 (Figure 2). In addition, it is more efficient than the 'overlap and storage' design shown in Figure 8, because in the frequency domain, only half of the multiplication is required. In addition, those familiar with this technology It can be used to reduce the negative frequency component in the first stage of the IFFT to zero to further reduce the use of the CPU, and only need to calculate half of the points in S (i). The third advantage is that complex multiplication needs to be performed from each output sample From the perspective of the number of times, the fast convolution design of Figs. 5 and 9 is better than the conventional implementation of Figs. 2 and 3. The technique is more efficient because the computational complexity of FFT and IFFT-related algorithms is much lower than that of FIR filtering on most computers. Another application of the frequency-domain filtering design of the present invention is multi-frequency division. (DM-M) system. A typical F-DM communication system can multiplex multiple input channels on an output channel. Each input channel is first filtered to generate a bandwidth-limited signal. After filtering, the frequency of the signal is shifted by one. Corresponds to the specific amount of the unique frequency_slot assigned to the input channel, that is, single sideband (SSB) modulation. Figure 10 shows the high-order block of the frequency domain filtering design of the present invention for a frequency division multiplexing (FD Μ) system. Figure. Multiple input channel signals represented by channel # 1 to channel # N are input to filter and frequency shift module row 2 40. Each filter and frequency shift module 2 4 0 includes a real number pair for fast analysis Convolution block 2 3 0, multiplier 2 3 2, local reducer 2 3 6, and complex real function block 2 3 4. Please note that 1 real number pair analysis fast convolution block 2 3 0, multiplier 2 3 2 'The emergence of the local oscillator 2 3 6- ---------- * _ Install · -------- Order · -------- ¾ (Please read the notice on the back before filling this page) This paper Standards applicable ® ® Family Tree Standard (CNS) A4 specification (210 X 297 gong) -24-Α7 Β7 V. Description of the invention (22) is a composite signal. Real number pair analysis fast convolution block 2 3 0, multiplier 2 The functions performed by 3 2, and the complex to real function block 2 3 4 are the same as the real number pair analysis fast convolution block 8 4, the multiplier 86, and the complex to real function block 8 8 respectively. The description of each is the same as the previous FIG. 5. A local oscillator is a circuit used to generate a sinusoidal waveform at a specified frequency. It can be phase shifted to produce a 90 degree phase difference signal, namely sine and cosine. The output of each filter and frequency shift module 240 is added via a totalizer 2 422 to obtain a composite F D M output signal. The frequency shift of each channel is determined by ω.ί in the composite signal e′ωι 1, which is generated and output by the local oscillator 2 3 6. Each channel has its own unique local oscillator with a frequency of ω, where i is the channel number. It should be noted that the input signal of the channel is filtered and frequency shifted, but F I R filtering or Hilbert conversion is not used. The advantage of the frequency domain filtering design of the present invention is that no Hllbert conversion is required. In addition to not requiring Hilbert conversion, the frequency domain filtering design of the present invention is also faster than equivalent FIR filters. The invention is very suitable to be applied to the f D Μ system, because each input channel includes a real signal, instead of being printed by the staff consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs & Quotation ------------ ---- (Please read the notes on the back before filling this page) and the analytic signal of the imaginary part. Although the present invention is described with a limited number of embodiments > it must be understood that the present invention can also make many variations and modifications, as well as other applications. This paper standard is Universal Chinese Standard (CNS) A4 Specification (2i 〇x 297 male dragon) -25-