TW456012B - Semiconductor wire bonding method preventing wire sweeping - Google Patents
Semiconductor wire bonding method preventing wire sweeping Download PDFInfo
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- TW456012B TW456012B TW089101449A TW89101449A TW456012B TW 456012 B TW456012 B TW 456012B TW 089101449 A TW089101449 A TW 089101449A TW 89101449 A TW89101449 A TW 89101449A TW 456012 B TW456012 B TW 456012B
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- solder joint
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
Description
^56012 五、發明說明（i) 【發明領域】 本發明係有關於一種防止沖線半導體，打線方法，特別是 有關於將導線在第一焊點及第二焊點之間往一側偏移，該 偏移增強該導線的側向強度以抵抗模流的沖力，及該偏移 形成該導線受模流時可變形的空間。 【先前技術】 習用半導體打線方法，請參照第一圖所示，將一半導體 元件100内以數條導線11()連接一第—焊墊〔位於晶片1〇1 上〕120及一第二焊墊〔位於内接腳上〕13〇形成一通路， 該導線1 1 0由該第一焊墊丨2 〇往上延伸後，再彎折該導線 110下降至該第二焊墊130，因而該導線110在該第一焊墊 120及第二焊塾130之間形成一凸起部，由於該導線11〇之 &起部祇以二銲點支撐，因此該凸起部容易受應力而產生 移位，當該半導體元件1〇〇進行灌膠時，該導線容易受液⑤ 態封膠物質衝擊而碰觸鄰近的另一導線，因而發生導線@〜 線〔wire sweep〕的問題，尤其是晶片角落及導線較不密 集之處。以晶片角落為例，請參照第二圖所示，由於在晶 月ιοί角落部分的焊塾間距過密，而導致位於該晶片角 落的兩料線110過於靠近’當該兩條導線110受到注腾所 產生的模流時’容易發生導線沖線。隨著晶片1〇1的表面 二間減^ ^可此以增大'焊墊間距的方法解決導線發生沖 線^ ^ ^ ° 再參照第三圖所示’當該半導體元件1 00進 行灌膠J生模流〔箭頭方向〕時，由於在晶片ι〇ι角落 分的焊墊間距過密，因而導致位於該角落的導線u〇受模^ 56012 V. Description of the Invention (i) [Field of the Invention] The present invention relates to a method for preventing punching a semiconductor and a wire bonding method, and in particular, it relates to shifting a wire to one side between a first solder joint and a second solder joint. The offset enhances the lateral strength of the wire to resist the impulse of the mold current, and the offset forms a space that the wire can deform when receiving the mold current. [Prior art] As a conventional method of semiconductor wiring, please refer to the first figure, and connect a first-pad [located on the wafer 101] 120 and a second solder with a plurality of wires 11 () in a semiconductor element 100 The pad [located on the inner pin] 13o forms a path, and the wire 110 extends upward from the first pad 1200, and then bends the wire 110 and descends to the second pad 130, so the The wire 110 forms a protrusion between the first pad 120 and the second welding pad 130. Since the & portion of the wire 11 is supported by only two solder joints, the protrusion is easily generated by stress. Displacement, when the semiconductor device 100 is filled with glue, the wire is easily affected by the liquid ⑤ state sealant material and touches another neighboring wire, so the problem of wire @ ~ wire [wire sweep] occurs, especially Chip corners and less dense wires. Taking the corner of the wafer as an example, please refer to the second figure. Because the solder pitch in the corner of the crystal is too close, the two material lines 110 located at the corner of the wafer are too close. When the two wires 110 are flooded The resulting mold flow is prone to lead punching. With the reduction of the two spaces between the surface of the wafer 101, ^, this can be solved by increasing the pad spacing. ^ ^ ^ ° Then refer to the third figure, when the semiconductor device 100 is potted. When the J mold flow [direction of the arrow], the pad pitch at the corner of the wafer is too dense, so that the wire u at the corner is subjected to the mold.
^560^2 五，發明說明（2) 流衝擊產生變形，當該導線11〇產生變形量大於二導線間 距時，該二導線1 1 0間接觸而發生沖線。 為了解決導線受模流發生沖線問題，於84年4月21曰公 告之我國專利公告第246245號「積體電路晶片之雙引線構 造」新型專利案，如第四及五圖所示，其係在積體電路晶 片2 0 0之搭接間距為4. 〇mi 1或以下，注模包封時，容易發 生短路接觸之引線，以雙引線21〇或二條以上引線210之並 聯結合方法，以克服在灌膠產生模流時產生引線變形，造 成引線短路故障之不良率。因此，該第246245號在積體電 路晶片200角落〔導線受最大模流處〕之第—焊墊220及第 二焊墊2 3 0之間連接並聯的雙導線21〇。 該第246245號主要藉以雙引線21 0或二條以上引線210之 並聯結合方法克服引線短路故障之不良率，其利用另一條 輔助引線阻擋模流〔箭頭方向〕，即使該輔助引線與主队 線間發生沖線時，該積體電路晶片本身不會發生短路β | 而’在積體電路晶片上多打一條輔助引線具有兩個主要& 點：第一缺點係輔助引線占用有限的晶片打線空間；第二 缺點係輔助引線增加積體電路的製造成本及製程時間。 有鑑於此’本發明之防止沖線半導體打線方法改良上述 之缺點，其將導線在第一焊點及第二焊點之間往一侧偏 移，使該導線的偏移具有增加導線抗應力、形成導線可變 形空間，因而減少產生導線沖線的問題。本發明主要以導 線往一側偏移方法替代習用第246245號之雙引線並聯結合 方法’該雙引線並聯結合方法需要額外打辅助引線。^ 560 ^ 2 Fifth, the description of the invention (2) The flow impact deforms. When the amount of deformation of the conductor 110 is greater than the distance between the two conductors, the two conductors are in contact with each other and the line is punched. In order to solve the problem that the wire is punched by the mold current, a new patent case of China Patent Bulletin No. 246245 "Dual Lead Structure of Integrated Circuit Chip" published on April 21, 84, as shown in Figures 4 and 5, It is based on the integrated circuit chip 2000 with a bonding pitch of 4.0 mm or less. When injection molding is used, the leads that are prone to short-circuit contact are connected in parallel by a two-lead 210 or two or more leads 210. In order to overcome the defective rate of the lead wire deformation caused by the mold flow caused by the pouring, which leads to the short circuit fault of the lead wire. Therefore, this No. 246245 connects the two parallel wires 21 between the first pad 220 and the second pad 230 at the corner of the integrated circuit wafer 200 (where the wire is subjected to the maximum mold current). This No. 246245 mainly overcomes the defect rate of the short circuit fault by the parallel combination method of two leads 210 or two leads 210. It uses another auxiliary lead to block the mold flow [arrow direction], even if the auxiliary lead and the home team line occur. When punching the wire, the integrated circuit chip itself does not have a short-circuit β | while 'making an additional auxiliary lead on the integrated circuit chip has two main & points: the first disadvantage is that the auxiliary lead occupies limited chip wiring space; The second disadvantage is that the auxiliary lead increases the manufacturing cost and processing time of the integrated circuit. In view of this, the method for preventing punched semiconductor wiring of the present invention improves the above-mentioned disadvantages, which shifts the wire to one side between the first solder joint and the second solder joint, so that the deviation of the wire has an increased stress resistance of the wire 2. Forming a deformable space of the wire, thereby reducing the problem of wire punching. The present invention mainly replaces the conventional two-lead parallel bonding method No. 246245 with the method of shifting the wires to one side. The two-lead parallel bonding method requires additional auxiliary leads.
C:\Program Files\Patent\PK7l49.ptd 第5頁 五、發明說明（3) 【發明概要】 it m要目的係提供一種防止沖線半導體打線方法， 焊點及第二焊點之間往-側偏移，該偏移增 =該導^的侧向強度以抵抗模流的沖力，該偏移形成該導 線受杈^時可變形的空間，因而本發明具有降低發生 沖線之功效》 根據本發明之半導體打線方法，該方法主要以一毛細管 嘴將一導線一端銲接至該第一焊墊，該第一焊墊相對廊於 另一第二焊墊，將該導線往上延伸一第一距離。該毛纟=管 嘴再將該導線往該第一焊墊及第二焊墊之一侧進行偏移一 第二距離，使該導線上形成一第一彎折及第二彎折，因而 該導線產生變形時’依該彎折處產生變形。該毛細管嘴再 將該導線往上延伸一第三距離。該毛細管嘴再將該導線往 該第二焊墊方向進行一第三彎折’使該導線上再形成一灣 折處，因而該導線產生變形時，依該彎折處產生變形。 毛細管嘴再將該導線往上傾斜延伸一第四距離，使該導^ 長度達預定距離’再將該導線末端移動至該第二焊墊上進 行銲接。因此，該導線連接該第一焊墊及第二焊墊且該導 線之第一距離、第二距離、第三距離及第四距離往該第— 焊墊及第二焊墊之一側偏移。 【實施例說明】 本發明導線的"偏移"係指在第一焊塾及第二焊塾之間進 行打線時，將毛細管嘴往該第一焊墊及第二焊墊一側移 位，使連接於該第一焊墊及第二焊墊的導線在該第一谭塾C: \ Program Files \ Patent \ PK7l49.ptd Page 5 V. Description of the Invention (3) [Summary of the Invention] The main purpose of the invention is to provide a method for preventing punched semiconductor wiring, between the solder joint and the second solder joint- Side offset, the offset increase = the lateral strength of the guide to resist the impulse of the mold flow, the offset forms a space that the wire can deform when it is branched, so the present invention has the effect of reducing the occurrence of the punch line. The semiconductor wire bonding method of the present invention mainly uses a capillary nozzle to solder one end of a wire to the first pad, the first pad is opposite to the other second pad, and the wire is extended upward by a first distance. The hairpin = nozzle shifts the wire to a side of the first pad and the second pad by a second distance, so that a first bend and a second bend are formed on the wire, so the When the wire is deformed, deformation occurs according to the bend. The capillary nozzle extends the wire upward a third distance. The capillary nozzle further bends the wire in the direction of the second bonding pad 'to form a bay fold on the wire. Therefore, when the wire is deformed, the wire is deformed according to the bend. The capillary nozzle then inclines the wire upward for a fourth distance, so that the length of the wire reaches a predetermined distance ', and then moves the end of the wire to the second pad for welding. Therefore, the wire is connected to the first pad and the second pad, and the first distance, the second distance, the third distance, and the fourth distance of the wire are offset to one side of the first pad and the second pad. . [Explanation of the embodiment] The "offset" of the wire of the present invention refers to moving the capillary nozzle to the side of the first welding pad and the second welding pad when wiring is performed between the first welding pad and the second welding pad. Position so that the wires connected to the first pad and the second pad are in the first
C:\Program Fiies\Patent\PK7149.ptd 第6頁 五、發明說明（4) 及第二焊墊一側傾斜，該導線之每一段距離所形成平面及 在該第—焊墊及第二焊墊上的垂直面之間形成—夾角。 本發明主要係將導線在第一焊點及第二焊點之間往一侧 偏移’該偏移方向與模流方向相反，因而該偏移增強該導 線的側向強度以抵抗模流的沖力，該偏移亦形成該導線受 模流時可變形的空間。本發明將前述的主要技術内容適^ 揭示於以下所列舉的較佳實施例内，並在該較佳實施例; 將本發明之主要技術内容與其他技術内容予以合併實施g 請參照第六圖所示，其揭示本發明較佳實施例之半導體 打線方法，該半導體打線方法之毛細管嘴路徑係將毛細管 嘴從第一焊點往上〔垂直方向〕移動一路徑A ;再將該毛® 細管嘴沿水平方向往第一焊點一側及遠離第二焊點方向移 動一路徑B，此時，該毛細管嘴已從第一焊點及第二焊點 上產生偏移，該第一焊點及第二焊點連接線與路徑B投氮 線〔平面〕之間形成一夾角0 i ，其較佳為135度（如J 七圖所示路徑B之上視圖，其水平夾開0 i約為135度；再 將該毛細管嘴往上〔垂直方向〕移動一路 細管嘴往上傾斜…靠近第二焊塾〕移動一路二： 第八圖所不路徑!）其與路徑B形成一夾角02，02之夹角以 180〇 — 6» 1較佳；最後將該毛細管嘴往第二焊點移動一路 徑E。該路徑a、B、c、D及e投影線往該第一焊點及第二焊 連接且線側偏移。本發明半導體打線方法較佳實施例係 路徑A長約等於路徑b長β 請再參照第九圖所示’本發明較佳實施例之半導體打線C: \ Program Fiies \ Patent \ PK7149.ptd Page 6 V. Description of the Invention (4) and one side of the second pad is inclined, and each section of the wire is a distance from the plane formed by the first pad and the second pad. An angle is formed between the vertical faces on the mat. The invention mainly shifts the wire to one side between the first solder joint and the second solder joint. The shift direction is opposite to the direction of the mold flow, so the shift enhances the lateral strength of the wire to resist the mold flow. The offset force also forms a space where the wire can be deformed when subjected to mold current. The present invention discloses the aforementioned main technical contents in the preferred embodiments listed below and in the preferred embodiments; combines the main technical contents of the present invention with other technical contents and implements them. Please refer to FIG. 6 As shown, it discloses the semiconductor wire bonding method of the preferred embodiment of the present invention. The capillary nozzle path of the semiconductor wire bonding method moves the capillary nozzle from the first solder joint upward (vertically) by a path A; The nozzle moves a path B along the horizontal direction to the side of the first solder joint and away from the second solder joint. At this time, the capillary nozzle has shifted from the first solder joint and the second solder joint. And the second solder joint connection line and the nitrogen injection line [plane] of path B form an included angle 0 i, which is preferably 135 degrees (as shown in the top view of path B shown in figure J.7, the horizontal angle is about 0 i It is 135 degrees; then move the capillary nozzle up [vertically] and tilt the thin nozzle upward ... near the second welding 塾] and move it all the way: the path shown in the eighth figure!) It forms an angle 02 with path B, The angle of 02 is preferably 1800—6 »1; the most Then move the capillary nozzle to path E by the second solder joint. The projection lines of the paths a, B, c, D, and e are connected to the first solder joint and the second solder joint and the line sides are offset. A preferred embodiment of the semiconductor wiring method of the present invention is that the length of path A is approximately equal to the length of path b. Please refer to FIG. 9 again.
C:\Program Files\Patent\PK7149,ptd 第7頁 五、發明說明（5) 方法以一毛細管嘴3〇〇將一導線31〇 一端銲接至在第一焊點 301之一第一焊墊320，將該導線31〇往上延伸一第一距離 31 此時，該毛細管嘴3〇〇沿第六圖所示的路徑a移動。 請再參照第十圖所示，該毛細管嘴30〇沿水平方向往該 第一焊塾320 —側及遠離一第二焊墊〔未繪示〕方向移動 延伸—第二距離313 ’該毛細管嘴30〇引導該導線3 1()進行 第 4折312及第一 ’曾折314，進而使該導線310上形 成一弯折處’因而該導線310產生變形時，依該彎折處產 生變形。此時，該毛細管嘴3〇〇沿第六圖所示的路徑b移 動而使該導線310從第一焊墊320及第二焊墊上產生偏 移。 ，清再參照第十一圖所示’該毛細管嘴3〇〇再將該導線31〇 往^延伸一第三距離31 5，此時，該毛細管嘴3 0 0沿第六圖 所不的路徑c移動’使得在該第二距離313及第三距離315 之間形成第二彎折314。因此，該導線31〇包含第—距& 311、第—彎折312、第二距離313、第二彎折314及第三距 離 315。C: \ Program Files \ Patent \ PK7149, ptd Page 7 V. Description of the Invention (5) Method A capillary 31 is used to solder one end of a wire 31 to a first pad 301 at a first solder joint 301. 320. Extend the wire 31 by a first distance 31. At this time, the capillary nozzle 300 moves along the path a shown in the sixth figure. Please refer to the tenth figure again, the capillary nozzle 30 is moved horizontally toward the first welding pad 320 —side and away from a second welding pad [not shown] — extending a second distance 313 'the capillary nozzle 30. Guide the wire 31 (1) to perform the fourth fold 312 and the first 'Zeng fold 314, so that a bend is formed on the wire 310'. Therefore, when the wire 310 is deformed, deformation occurs according to the bend. At this time, the capillary nozzle 300 moves along the path b shown in the sixth figure to cause the lead wire 310 to be offset from the first pad 320 and the second pad. Qing, referring to the eleventh figure, the capillary nozzle 300 is extended to a third distance 31 5 to the wire 31. At this time, the capillary nozzle 3 0 0 is along the path not shown in the sixth figure. c-movement 'causes a second bend 314 to be formed between the second distance 313 and the third distance 315. Therefore, the wire 31 includes the first distance & 311, the first bend 312, the second distance 313, the second bend 314, and the third distance 315.
，清再參照第十二圖所示，該毛細管嘴3〇〇再將該導線31〇 往該第二焊墊〔未繪示〕方向進行一第三彎折316，該導 線310上再形成一彎折處’因而該導線31〇產生變形時，依 該彎折處產生變形。該毛細管嘴3 〇 〇沿第六圖所示的路徑D 移動，將該導線31 0往上傾斜方向延伸—第四距離31 7 ,使 該導線310長度達預定距離，此時，在該第三距離315及第 四距離317之間形成第三，彎折316。因此，該導線31〇包含As shown in the twelfth figure, the capillary nozzle 300 performs a third bend 316 in the direction of the second solder pad [not shown], and a third bend 316 is formed on the lead 310. Bends' When the wire 31 is deformed, deformations occur according to the bends. The capillary nozzle 300 moves along the path D shown in the sixth figure, and extends the lead 31 0 in an upward tilt direction—a fourth distance 31 7, so that the length of the lead 310 reaches a predetermined distance. At this time, in the third A third, bent 316 is formed between the distance 315 and the fourth distance 317. Therefore, the wire 31〇 contains
C:\Program Files\Patent\PK7l49.ptdC: \ Program Files \ Patent \ PK7l49.ptd
456012 五、發明說明（6) ' ' 第一距離311、第一彎折312、第二距離313、第二彎折 314、第三距離315、第三彎折316及第四距離317。 請再參照第十三圖所示，該毛細管嘴3〇〇再將該導線31〇 末端移動至該第二焊點3〇2之第二焊墊33〇上進行銲接。該 毛細管嘴300沿第六圖所示的路徑E移動，此時，該導線 310連接該第一焊墊320及第二焊墊33〇。該毛細管嘴3〇〇從 執跡點W1經執跡點W2、W3、W4、W5及W6，最後至軌跡點 W7 β將該導線310進行銲線至該第二焊墊33〇上。 請再參照第十四圖所示，其揭示在第一焊墊32〇及第二 焊墊330之間連接的導線310之上視圖^將該第一焊墊3 2〇 及第一焊塾330連接定義為第一轴X〔虛線〕，此時，該導 線310之第一距離311、第二距離313、第三距離315及第四 距離317往第二轴Υ〔垂直於第一軸X〕方向偏移。該導線 31 0之每一點〔X i，Y i〕受沿第二軸γ的模流〔箭頭方&〕 衝擊時，該導線31 〇的結構本身沿第二軸γ在反模流方）^上 產生抵抗力，因此’該模流從第一焊點3〇 1或第二焊點3〇2 對導線3 1 0之每一點〔X i ’ Y i〕所產生的總和力矩減少， 本發明導線3 1 0的構造能抵抗較大的模流。此外，該導線 310之每一點〔Xi，Yi〕離開第一軸X具有Yi距離，使得該 導線31 0之每一點〔X i，Y i〕受模流沿第二軸γ可產生位移 的距離至少增加了 Yi距離’因此，該導線310往第一轴X — 側偏移對該第一轴X另一側的另一導線[未繪示〕而言， 本發明具有增加該導線受模流時可變形的空間及減少導線 間產生串音〔cross talk〕現象。456012 V. Description of the invention (6) '' The first distance 311, the first bend 312, the second distance 313, the second bend 314, the third distance 315, the third bend 316, and the fourth distance 317. Please refer to the thirteenth figure again. The capillary nozzle 300 is moved to the second pad 33 of the second solder joint 302 and soldered at the end of the wire 31. The capillary nozzle 300 moves along the path E shown in the sixth figure. At this time, the lead wire 310 is connected to the first pad 320 and the second pad 33. The capillary nozzle 300 passes from the track point W1 through the track points W2, W3, W4, W5, and W6, and finally to the track point W7 β to wire the wire 310 to the second pad 33. Please refer to FIG. 14 again, which shows a top view of the conductive wire 310 connected between the first pad 32 and the second pad 330 ^ the first pad 3 2 0 and the first pad 330 The connection is defined as the first axis X [dotted line]. At this time, the first distance 311, the second distance 313, the third distance 315, and the fourth distance 317 of the wire 310 are toward the second axis Υ [vertical to the first axis X]. Direction offset. When each point [X i, Y i] of the wire 31 0 is impacted by the mold flow [arrow side &] along the second axis γ, the structure of the wire 31 〇 is in the counter-mode flow side along the second axis γ) ^ Creates resistance, so 'the mold current from the first solder joint 301 or the second solder joint 302 to each point of the wire 3 10 [X i' Y i] reduces the moment, this The structure of the invention wire 3 1 0 can resist a large mold flow. In addition, each point [Xi, Yi] of the wire 310 has a Yi distance from the first axis X, so that each point [X i, Y i] of the wire 31 0 can be displaced by the model flow along the second axis γ. At least the Yi distance is increased. Therefore, the wire 310 is shifted toward the first axis X- side. As for another wire [not shown] on the other side of the first axis X, the present invention has an effect of increasing the mode flow of the wire. Deformable space and reduce cross talk between wires.
C:\Program FiIes\Patent\PK7149.ptd 第 9 頁 4 5 β(Μ 2 五、發明說明（7) 請再參照第一及十四圖所示’本發明較佳實施例之半導 體銲線方法應用於QFP型半導體元件100的晶片1〇1角落， 在該晶片101角落的導線110上形成三個弯折111，使該導 線110往第一谭整·120 —側偏移’因此，兩條導線之間 形成較大的空間，以避免該兩條導線110 —端之間產生串 音現象。尤其在該半導體元件100角落發生較大模流，因 而必須該導線11 0設有偏移以增強該導線的侧向強度供抵 抗模流的沖力’該偏移亦形成該導線受模流時可變形的空 間。本發明打線方法藉由該半導體元件1〇〇上的應用可界 定偏移量’該偏移量較佳大於或等於兩個焊墊間距的一 半。 请再參照第二及十四圖所示，本發明之導線1 1 Q較習用 之導線110具有較佳抵抗模流的沖力、較大的導線可變形 空間。因而本發明具有降低發生導線沖線及增加銲線 度之功效β 請再參f第十五、十六圖揭示未受模流〔虛線箭頭 向〕衝擊前，導線310連接於第一焊墊3 20及第二焊墊330 之，的情形’ & # ’靠近第—浑塾32G的導線310形成偏移 線段而其餘靠近第二焊墊33〇的導線31〇 ，及：二坪塾330的連線上。請再參照第十七丄= 二〔Λ線箭頭方向〕衝擊產生位移後該導線31 0各段所形 成：形狀’此時’導線31〇依所受的力矩大小，在遠離第 大及靠近第二焊塾33°的導議線段所產ί的： 乂 而在靠近第一焊墊32 0及遠離第二焊墊33〇的C: \ Program FiIes \ Patent \ PK7149.ptd Page 9 4 5 β (Μ 2 V. Description of the invention (7) Please refer to the first and the fourteenth drawings, 'Semiconductor bonding wire method of the preferred embodiment of the present invention' Applied to the corner of the wafer 101 of the QFP type semiconductor element 100, three bends 111 are formed on the wire 110 at the corner of the wafer 101, so that the wire 110 is shifted toward the first side and 120-side. Therefore, two A larger space is formed between the wires to avoid crosstalk between the ends of the two wires 110. In particular, a large mold current occurs at the corner of the semiconductor device 100, so the wires 110 must be offset to enhance The lateral strength of the wire is used to resist the impulse of the mold flow. 'The offset also forms a space where the wire is deformable when receiving the mold flow. The wire bonding method of the present invention can define the offset by the application on the semiconductor element 100' The offset is preferably greater than or equal to half of the distance between the two bonding pads. Please refer to the second and the fourteenth figures, the lead 1 1 Q of the present invention has better impulse resistance against die current than the conventional lead 110, Large wire can deform space. Therefore, the present invention has a reduced The effect of wire punching and increasing the welding wire degree β Please refer to f. 15 and 16 again to reveal that before being impacted by the mold flow (dotted arrow), the wire 310 is connected to the first welding pad 3 20 and the second welding The situation of the pad 330 '&#' The wire 310 near the first-hundred cymbal 32G forms an offset line segment and the rest of the wire 31 near the second pad 33o, and the connection of the Erping 塾 330. Please Refer to the seventeenth 丄 = two [direction of the Λ line arrow] after the impact displacement, the sections of the wire 31 0 are formed: the shape 'at this time' the wire 31 0 is away from the first and close to the second Producing from the lead line of 33 °: 乂 and close to the first pad 32 0 and away from the second pad 33 0
第10頁 4560^2 五、發明說明（8) 導線3】0線段所產生的位移相對較小。因此，該導線31 〇往 接近第一焊墊320及第二焊墊3 連線的方向位移，此時， 該導線310在靠近第一焊墊32〇的線段位於第一焊墊32Q及 第二焊墊330連線的一侧A，而該導線31〇在靠近第二焊墊 330的線段位於第一焊墊32〇及第二焊墊33〇連線的另一側 B，使得該導線310往平面〔第一焊墊32〇及第二焊墊33〇 所在平..面〕上投影時與第一焊墊32〇及第二焊墊33〇連線產 生一交點303。在受模流衝擊時該交點3〇3沿第一焊墊32〇 及第二焊墊330連線方向移動，當模流逐漸增大時，誃 點3 0 3從第二焊墊330往第一焊墊32〇的方向移動，^ 導線3 1 0受模流的位移不斷增大。 '' 雖然本發明已以前述較佳實施例揭示，然其並非 定本發明，任何熟習此技藝者，在不脫離本發明之二 範圍内：#可作各種之更動與修改，因此本發明之保2 圍當視後附之申請專利範圍所界定者為準。 、Page 10 4560 ^ 2 V. Description of the invention (8) Conductor 3] The displacement caused by the 0 line segment is relatively small. Therefore, the wire 31 is displaced toward the direction close to the connection line between the first pad 320 and the second pad 3, and at this time, the line 310 near the first pad 32o is located at the first pad 32Q and the second pad. One side A of the bonding pad 330 is connected, and the wire 31 is located on the other side B of the first bonding pad 32 and the second bonding pad 33 in a line segment close to the second bonding pad 330, so that the lead 310 When projecting onto a plane [the plane where the first pad 32o and the second pad 33o are located], a connection point 303 is generated by connecting the first pad 32o and the second pad 33o. When impacted by the mold current, the intersection point 303 moves along the connecting direction of the first pad 32 and the second pad 330. When the mold flow gradually increases, the point 3 0 3 from the second pad 330 to the first A pad 32o moves in the direction, and the displacement of the conductive wire 3 10 by the mold flow increases. '' Although the present invention has been disclosed with the aforementioned preferred embodiments, it is not a definition of the present invention. Any person skilled in the art will not depart from the scope of the present invention: # Various changes and modifications can be made, so the protection of the present invention 2 Wei Dang shall be determined as defined in the scope of the attached patent application. ,
闽式簡單說明 【圖式說明】 顯讓二：：：j和其他㈣、特徵、和優點能更明 作詳細說明i=舉本發明較佳實施例，並配合所附圖式， ^圖‘半導體元件内導線分佈之上視圖； 圖·第1圖半導體元件之局部放大圖； 圖.·習用半導體元件，發生沖線之局部放大圖； 繞Μ圖我國專利公告第246245號積體電路晶片之雙引 線構造之上視圖； 文 第5圖：第4圖積體電路晶片之雙引線構造之局部放大 第6圖： 路徑示意圖 第7圖： 第8圖： 第9圖： 圖； 本發明較佳實施例半導體打線方法之毛細管嘴 本發明路徑Β之上視圖。 本發明路徑D之上視圖。 本發明較佳實施例半導體打線方法路徑示g 第1 0圖：本發明較佳實施例半導體打線方法路徑示意 方法路徑示意 方法路徑示意 方法路徑示意 第1 1圖：本發明較佳實施例半導體打 ®· 第1 2圖：本發明較佳實施例半導體打 〇 ♦ 圖， 第1 3圖：本發明較佳實施例半導體打線Simple description of the Fujian style [Illustration of the diagram] Explicit second 2 ::: j and other features, features, and advantages can be more clearly explained in detail i = the preferred embodiment of the present invention, and with the accompanying drawings, ^ 图 ' Top view of the distribution of wires in a semiconductor element; Figure · Part 1 enlarged view of a semiconductor element; Figure. · A partial enlarged view of a conventional semiconductor element with a punched line; Top view of the double-lead structure; Figure 5: Figure 4 is a partial enlargement of the double-lead structure of the integrated circuit wafer. Figure 6: Schematic diagram of the route. Figure 7: Figure 8: Figure 9: Figure; Capillary Nozzle of the Example Semiconductor Bonding Method The top view of the path B of the present invention. Top view of path D of the present invention. FIG. 10 shows the path of the semiconductor bonding method according to the preferred embodiment of the present invention. FIG. 10 shows the path of the semiconductor bonding method according to the preferred embodiment of the present invention. ® · Fig. 12: Semiconductor wiring of the preferred embodiment of the present invention. ♦ Fig. 13: Semiconductor wiring of the preferred embodiment of the present invention.
C:\Prograra Files\Pateiu\PK7l49,ptd 第12頁 4 5 6 0 t 2 圖式簡單說明 圖； 第1 4 第1 5 導體元件 第1 6 上視圖； 第1 7 之上視圖。 【圖號說明 圖：本發 圖：本發 之上視圖 圖：本發 及 圖：本發 於半 100 半 導 體 元件 101 晶 片 110 導 線 111 彎 折 120 第 ΛΜ — 焊 墊 130 第 二 焊 墊 200 積 體 電 路晶 >1210 引 線 220 第 一 烊 墊 230 第 —- 焊 墊 300 毛 細 管 嘴 301 第 —一 焊 點 302 第 . _ 焊 點 303 交 點 310 導 線 311 第 , * 距 離 312 第 彎 折 313 第 二 距 離 314 第 —1 _ 彎 折 315 第 距 離 316 第 三 彎 折 317 第 四 距 離 320 第 —* 焊 墊 330 第 焊 墊 明較佳實施例導線構造之上視圖； 明較佳實施例半導體打線方法應用 明較佳實施例未受模流前的導線構造之 明較佳實施例在受到模流後的導線構造 ϋC: \ Prograra Files \ Pateiu \ PK7l49, ptd Page 12 4 5 6 0 t 2 Schematic illustration of the diagram; Page 1 4 No. 1 5 Conductor element No. 16 Top view; No. 17 top view. [Illustration of the drawing number: this hair map: this hair top view: this hair and diagram: this hair on half 100 semiconductor components 101 wafer 110 wire 111 bend 120th ΛM — pad 130 second pad 200 integrated body Circuit crystal> 1210 Lead 220 First pad 230 First —- Pad 300 Capillary nozzle 301 First — First solder joint 302 First. _ Solder joint 303 Intersection point 310 Lead 311 First, * Distance 312 First bend 313 Second distance 314 # 1 _ Bend 315 First distance 316 Third bend 317 Fourth distance 320 First — * Pad 330 First pad Top view of conductor structure of the preferred embodiment; Application of semiconductor wiring method of the preferred embodiment The wire structure of the preferred embodiment before being subjected to mold flow
C:\Program Files\Patent\ΡΚ7149.ptd 第13頁C: \ Program Files \ Patent \ ΡΚ7149.ptd Page 13
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Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089101449A TW456012B (en) | 2000-01-27 | 2000-01-27 | Semiconductor wire bonding method preventing wire sweeping |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089101449A TW456012B (en) | 2000-01-27 | 2000-01-27 | Semiconductor wire bonding method preventing wire sweeping |
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| TW456012B true TW456012B (en) | 2001-09-21 |
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| TW089101449A TW456012B (en) | 2000-01-27 | 2000-01-27 | Semiconductor wire bonding method preventing wire sweeping |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG143060A1 (en) * | 2005-05-10 | 2008-06-27 | Kaijo Kk | Wire loop, semiconductor device having same and wire bonding method |
| US8016182B2 (en) | 2005-05-10 | 2011-09-13 | Kaijo Corporation | Wire loop, semiconductor device having same and wire bonding method |
-
2000
- 2000-01-27 TW TW089101449A patent/TW456012B/en not_active IP Right Cessation
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG143060A1 (en) * | 2005-05-10 | 2008-06-27 | Kaijo Kk | Wire loop, semiconductor device having same and wire bonding method |
| US8016182B2 (en) | 2005-05-10 | 2011-09-13 | Kaijo Corporation | Wire loop, semiconductor device having same and wire bonding method |
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