TW455965B - Method for forming solder bumpers on IC package substrate and structure formed by the same - Google Patents

Method for forming solder bumpers on IC package substrate and structure formed by the same Download PDF

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Publication number
TW455965B
TW455965B TW89117431A TW89117431A TW455965B TW 455965 B TW455965 B TW 455965B TW 89117431 A TW89117431 A TW 89117431A TW 89117431 A TW89117431 A TW 89117431A TW 455965 B TW455965 B TW 455965B
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TW
Taiwan
Prior art keywords
layer
metal
substrate
bumps
opening
Prior art date
Application number
TW89117431A
Other languages
English (en)
Inventor
Ju-Ching Hu
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW89117431A priority Critical patent/TW455965B/zh
Priority to US09/796,268 priority patent/US6576541B2/en
Application granted granted Critical
Publication of TW455965B publication Critical patent/TW455965B/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/043—Reflowing of solder coated conductors, not during connection of components, e.g. reflowing solder paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0502—Patterning and lithography
    • H05K2203/054—Continuous temporary metal layer over resist, e.g. for selective electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof
    • H05K3/3473—Plating of solder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/26—Web or sheet containing structurally defined element or component, the element or component having a specified physical dimension
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/31504—Composite [nonstructural laminate]
    • Y10T428/31678—Of metal

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Description

59 6 5 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（f ) 發明領域： 本發明是關於-種在1C封裝基板上形成凸塊之方法及 結構’尤指適用於以覆晶式（Flip_chlp)方式進行封裝之 錫球陣列（Ball Grid Army ;簡稱BGA)基板，且於基板上 形成有凸塊（Solder Bumper)以供電性接合於一積體電路 晶片（ICChip)上之方法與裝置。 發明背景： 按，現今的半導體技術日新月異且競爭激烈，所有的半 導體製造與封裝業者無不竭心盡力企圖研發出體積更小、 效能更高、且成本更低的積體電路元件。除了積體電路晶 片（Integrated Circuit Chip;簡稱IC Chip)的生產技術已邁 入深次微米與十二对晶圓（Wafer)的製程之外，在晶片的 封裝技術上亦有長足的進步。從傳統的導線架封裝（Lead Frame Package)、錫球陣列封裝（BGAPackage)、到基板 自動接合錫球陣列封裝（Tape Automatic Bonding BGA ;簡 稱TAB BGA) ’目前的封裝技術已可使積體電路元件的元 件尺寸更小、更薄’且晶片執行效能與生產效率卻更高。 為了使積體電路元件的的尺寸更進一步縮小，現今更有 所謂「基板/晶片」尺寸比值低於1.2的晶片尺寸封裝（Chip Scale Package;簡稱CSP)技術、以及微型錫球陣歹封裝（Mini BGA)技術的產生。為了使「基板/晶片」尺寸比值能低於 1.2，這些CSP或是Mini BGA封裝有許多是使用覆晶式 (Flip-Chip)方式進行封裝。 2 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I ί.ϊι! --------^---------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 A6596r A7 _____B7 五、發明說明（ 如圖一所示，為一習用之覆晶式錫球陣列封裝 (FUp-DnpBGA)技術的示意圖。其主要是在一bga基板 11上依序形成有一金屬電路佈局層12 (Metal Layer)以及一 防焊層13 (Solder Mask)。該防焊層13之預定 若干?孔，使開孔處之金屬電路佈局層12可暴露於外二 不被蓋覆。開孔内所暴露的金屬電路佈局層12表面可電鍍 -層鎮、鐵、銅、金或是合金之金屬層’以作為鲜塾14: 用，或者，於開孔中亦可以網版印刷（ScreenPrim)的方式 印刷上一層錫錯合金的銲膏15。另外，於積體電路晶片 之作動面（Active Side)上除了積體電路佈局、外層之鋁金 屬電路層22、以及最外層之保護層23之外，目前習用的覆 晶式錫球陣列封裝技術，均是採用在積體電路晶片上形成 右干凸塊24 (Gold or Solder Bumper)其係電性連接於鋁 金屬電路層22。藉由將積體電路晶片之凸塊24加熱壓銲至 基板Η與其相對應的銲膏15 (或銲墊14)上，不僅可使積 體電路晶片21之電路與基板η電路耦合導通，且同時可完 成其兩者之結合動作。 惟，此種如圖一所示之習用覆晶式錫球陣列封裝技術仍 有下列缺點： (1)印刷形成凸塊接點之間距（pltch)較大。由於傳 統封裝基板上之銲膏是以網版印刷的方式塗附於基板、或 疋以獨立生產之小錫球體排列銲接於基板，因此其接點之 間距較大，其大多介於2〇〇〜250μηι左右，很難設計出接點間 距小於150μιη的產品。 3 本紙張尺度適财國國家標準(CNS)A4規格（210 X 297公爱） -------.-------褒--------訂----------^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印制衣 A7 ------B7 五、發明綱q ) · ~ (2)凸塊的製造成本較高。由於凸塊24是長在ic晶片 21上]因此需要在晶圓廠中藉由晶圓製程來進行製造，不 僅晶圓製程本來就成本較高，且更加上IC晶片（或晶圓）上 的積體电路岔集且複雜，且多是以耐熱度相對較低之捧雜 夕矽化合物或鋁金屬來構成該複雜的積體電路佈局，因 =在1C晶片上形成凸塊的製程條件更加複雜且技術較難，製 造成本不僅較高且產品良率反而可能降低。相對地，由於 基板的電路多是以对熱度較高的鋼金屬來製造，且電路複 雜度與密錢均較低許乡，偏若凸形成於基板上的 話’不僅所·術層讀低、且更將可大崎低製造成本。 發明概述： 、本發明之主要目的’即是在提供一種在IC封絲板上形 成凸塊之方法及結構，可將習用覆晶式BGA封裝技術中， 原本長在曰曰片上之凸塊（或稱為銲球），改成形成於封裝 基板上’然後再與晶片進行壓銲。如此，晶片上將不需要 長凸塊，而可降低製造成本。 本發明之3 -目的’ S在提供—種在版裝基板上形成 凸塊之方法及結構，齡在BGA縣基板找電錢的方式 形成凸塊，以取代習用印刷錫膏的技術，可大幅縮減凸塊 接點之間距至150μηι以下’而使封裝元件的尺寸得以進一步 縮小。 為達上述之目的，於本發明之較佳實施例中，該在IC 封裂基板上形成凸塊之方法’係包括有下列步驟： 4 本紙張尺度適用中關家標準（CNS)A4規格（210 X 297 * -1ΙΙΪΙ --------^---------線 (請先閱讀背面之注意事項再填寫本頁) 發明說明（L/ ) (A)準備-基板，於該基板之至少—側面上形成包括有一 金屬電路層以及-樹脂罩層蓋覆於金屬電路層上，該樹 脂罩層之適當位置處触若干_，賴减之金屬電 路層可暴露於外界而不被蓋覆； (A1)於樹脂罩層上形成—介質層，該介制於對應於開 孔位置處亦呈開孔狀態； ⑻以無電金屬化方式於基板之該側面形成—第一金屬 層，使該第一金屬層蓋覆於樹脂罩層及位於開孔位置處 之金屬電路層； (C) 於第-金屬層上形成—乾膜層，該乾膜層於對應於開 孔位置處亦呈開孔狀態，使開孔位置處之第一金屬層暴 露於外界而不被蓋覆； (D) 以禮方式於開孔娜成—預定厚度之金屬塾在第— 金屬層之上； (E) 於金屬塾上形成凸塊層； (F) 將開孔之外其他位置處之乾膜及第—金屬層均去除， 使凸塊層呈突出於基板之該側面上之狀態；以及， ⑹進行加溫回流（_⑽）及高度—致之製程，使凸塊 層表面具一致高度之凸塊結構。 由於該本發明之凸塊係突出於基板一側表面一預定高 度’因此可供直接壓銲於—IC晶狀金屬電路層上，於扣 晶片上不再需要形成凸塊。並且，本發縣由魏的方式 形成凸塊’可使凸塊接點之間距縮小至15〇师以下，達到 ⑽〜⑽哗左右的標準’以符合與晶片進行加熱壓鲜時所需 455965 A7 B7 五、發明說明) 規格，完全達到本發明之目的者。 本發明之在1C封裝基板上形成凸塊之結構，則包括有： 一樹脂基板； 一金屬電路層，形成於基板之一側面（上侧面）上； 一樹知罩層，蓋覆於該金屬電路層上，於樹脂罩層之適當 位置處設有若干開孔，使開孔處之金屬電路層可暴露於 外界而不被蓋覆； 第一金屬層，形成於各開孔内部之週緣表面，包括位於開 孔内之金屬電路層表面上； 金屬塾’形成於各開孔内部之第一金屬層上；以及， 凸塊，形成於各金屬墊上，且凸塊係突出於基板之該侧面 外一預定高度，以供銲接於一 1C晶片上。 當然，於基板的另一側面（下側面）亦設有若干錫球以 供焊接至外界電路板。然而，由於該基板下側面的錫球係 用於進行對外界電路板的銲接，所以其對於錫球尺寸以及 錫球接點之間距（Pitch)的尺寸均較大，一般均大於2〇〇pm 以上，故與本發明之以電鍍方式形成且係用於壓銲至仄晶 片上的凸塊無論於技術與功效上均不相同。 為使貴審查委員對於本發明能有更進一步的了解與 認同’兹配合圖式作一詳細說明如后。 圖式之簡單說明： 圖一係為習用之覆晶式錫球陣列封裝（FHp-Chip 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (諳先閱讀背面之注意事項再填寫本頁) I · I I ----I I 訂·------I I . 經濟部智慧財產局員工消费合作社印製 5 5 9 6 5 A7 ------ B7_ 五、發明說明（^) BGA)技術的示意圖。 圖二八至圖1係為本發明之在1(：封裳基板上形成凸 塊方法之-較佳實施例的實施步驟流 圖號說明： 11BGA基板 13防焊層 15銲膏 22鋁金屬電路層 24錫球 31基板 33 (第一）樹脂罩層 35介質層 37乾膜層 39凸塊層 52 (第二）電路層 54 (第二）開孔 56錫球 I2金屬電路佈局層 14銲墊 21積體電路晶片 23保護層 32 (第一）金屬電路層 34 (第一）開孔 36第一金屬層 38金屬墊 391凸塊 53 (第二）樹脂罩層 55導通孔 --------------裝--------訂- (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 發明之較佳實施例詳細說明： 本發明之在1C封裝基板上形成凸塊之方法及結構，主要 是藉由在BGA封裝基板之防焊層（SolderMask)外先附著一 層介質層，該介質層係選用與金屬及防焊層均有良好結合 能力的材質所構成’以克服金屬鋼不易附著在防焊層表面 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 4 5 59s 5 經濟部智慧財產局員工消費合作社印製 A7 B7 i、發明說明（2) 的問題。之後，再以薄薄一層化學銅覆蓋滿整個基板表面 以作為後續電鍍時之導電通路，之後再以乾膜覆蓋於化學 鋼上並定義出開孔位置。接著便進行電鍍而在開孔内先後 電錢上一定厚度的銅金屬與錫鉛合金。於是，當去除乾膜 後，該錫鉛合金便可突出於基板外一預定高度以作為與晶 片壓銲之凸塊了。以下將以一具體實施例詳細說明之。 請參閱圖二A至圖二H’為本發明之在1(；封裝基板上形成 凸塊方法之一較佳實施例的實施步驟流程圖，包括有下列 步驟： 步驟（1):如圖二A所示，準備一樹脂材質之BGA封裝 基板31。於該基板31之至少一側面上形成包括有一金屬電 路層32 (Metal Layer;通常為銅金屬或是金）以及一樹脂罩 層33 (又稱為綠漆或是防焊層；Solder Mask)蓋覆於金屬 電路層32 (亦即第一金屬電路層）上，該樹脂罩層33 (亦 即第一樹脂罩層）之適當位置處設有若干開孔34 (亦即第 開孔）’使開孔34處之金屬電路層32可暴露於外界而不 被蓋覆。由於圖二A所示之BGA封裝基板結構可以習知的基 板製裎技術製造，故不再贅述。 值得一提的是’ 一般的BGA封裝基板通常具有至少兩層 之電路層32、52其分別位於基板31之上下兩側面，該兩電 路層32、52之間以導通孔55做電性連接，且於基板31下側 面之電路層52 (亦即第二金屬電路層）上亦同樣設有樹脂 罩層53(亦即第二樹脂罩層）以及開孔54(亦即第二開孔）， 於開孔54内亦設有複數個錫球56 (SolderBall)以供焊接至 8 本紙張尺度4用中园國家標準（CNS)A4規格（21〇 χ 297公釐） --------------裝--------訂---------^ ί請先閱讀背面之注意事項再填寫本頁) ^ ϋ U D 〇 ^ ϋ U D 〇 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（γ) 一外界電路板（例如主機板Main Board，圖中未示）^由於 此所述之導通孔55以及位於基板31下侧面之電路層52、樹 脂罩層53、開孔54 '錫球56等元件係屬習知技術且並非本 發明所欲S斥求之技術特徵’也非為絕對必要之元件，因此 以下將不與贅述，且這些習知元件於圖式中亦僅僅是以虛 線方式表現於圖二A與圖二Η申，至於其他圖中則不再緣 入，合先敘明。 步驟（2):如圖二Β所示，於樹脂罩層33上形成一介質 層35，該介質層35於對應於開孔34位置處亦呈開孔狀態。 介質層35的材質係選用與金屬及樹脂罩層33均有相對較佳 結合能力（附著能力）的材質所構成，以克服在後續製程 中，金屬銅可能不易附著在樹脂罩層33表面的問題。於較 佳實施例中，介質層35的材質可為相對較易於附著於樹脂 上之金屬（例如鈦、或絡）、金屬化合物（例如氧化銅等）、 或是相對較易附著金屬之其他樹脂材料。該介質層邪可選 擇以化學氣相沈積（Chemical Vaporized Deposition;簡稱 ⑽）、真空濺鑛（Spu 11er i ng)、印刷、旋塗（Sp丨n c〇at丨ng， 僅適用於液狀樹脂.）' 或是貼合（可貼合薄膜狀之金屬箔 或樹脂膜）中的其中之一方式結合在樹脂罩層33上，必要 時並配合光阻、曝光、顯影、蝕刻等製程來定義介質層35 之開孔以使金屬電路層32可暴露在外界。 步驟（3):如圖二C所示，以無電金屬化方式於基板31 之该側面形成一第一金屬層36，使該第一金屬層36蓋覆於 介質層35表面（包括樹脂罩層33)、開孔34内部表面、及 9 本紙張尺度適Τ國國家標车（CNS)A4規格（21G X 297公f ) --1. : . 11 --------^---------A (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作衽印制衣
Q ^ K A7 ------^---- 五、發明說明（f ) 暴露於開孔k内之金屬電路層32表面上。第一金屬層邪的 材質於本較佳實施例中可為鈦（Tl)、錄㈤、金（Au)、 銅（〇0、鐵（Fe)、鉻（Cr)、或其合金。於較佳實施 例中，所述之無電金屬化方式係指真空錢鑛 (Sputtering)、或是-般習知的封驗板製造技術中， 用來進行導通孔表聽φ辦·之無電學銅（ρτΗ) 技術。由於此第-金屬層36僅僅如於在後續電鑛製程中 提供-導電通制而為-過渡軸的產物，#驗完成後 則將把此第-金屬層36去除，所以，此第—金屬層邪的厚 度不必很厚（厚度約在G_5至1蹲範圍即可），且第一金屬 層36與介質之__力（Ped s_gth ;或稱為抗剝 離強度）也不必太高。當然，吾人亦可選擇在形成第一金 屬層36後’另再额外進行電鍍以增加第一金屬層％的厚 度。然於此步驟中進行額外電鑛所增厚的金屬材質（一般 為銅金屬）則與第-金屬層36的材質並不—定相同。 步驟（4):如圖二D所示，於第一金屬層祁上形成一乾 膜層37 ’該乾膜層37於對應㈣孔％位置處亦呈開孔狀 態’使開孔34位置處之第-金屬層36暴露於外界而不被苔 覆:乾膜層37的材質可為樹月旨、光阻”戈其他高分子材料， 其係以網版印刷、旋塗、或是貼合中的其中之一方式垆入 在第-金屬層36上。於本較佳實施例中，乾膜層訂係選用 感光村备（例如光阻）以印刷或旋塗於第一金屬層％上。 然後’以-曝賴（财未示）透過—預定圖案之光罩⑽ 中未示）對乾膜層37進行曝光’該預定圖案係對應於開孔 適用中國國家標準（CNSM4規格⑵Ο X -------------
4 5 5965 經濟部智慧財產局員工消費合作社印製 A7 -------_______ 五、發明說明（/° ) 之形狀與位置。之後再對感光材質之乾膜層37進行顯影、 烘乾以及侧等触，以去除對應關德位置處之乾膜 材料，而暴露出第一金屬層％於開孔34内。 步驟（5):如圖二E所示，以電鍍方式於開孔内形成一 預疋厚度之金屬墊38在第一金屬層36之上。所述之金屬墊 38的材質可為銅 '金、錦、铭、路、或其合金。—般而言， 該金屬塾38的厚度應以略高於或齊平於樹脂罩層為較 佳。 步驟（6):如圖二f所示’繼續進行電鍍，於金屬墊38 上形成凸塊層39。凸塊層39的材質係為鋼、錫、鉛、或其 合金，一般以錫錯合金為較佳。於本實施例中，凸塊層39 與金屬墊38的位置與厚度係藉由同一乾膜層37來加以定 義。然而於另一較佳實施例中，吾人亦可選擇使用兩層乾 膜層來以兩階段製程分別形成（電鍍）該金屬墊38與凸塊 層39者。 步驟（7):如圖二G所示，將開孔之外其他位置處之乾 膜37、第一金屬層36、以及介質層35均去除，使凸塊層的 呈犬出於基板31之該側面上一預定高度之狀態。於本較佳 實施例中，可使用選擇性钱刻的方式來分別去除乾膜抑、 第一金屬層36、以及介質層35。於另一較佳實施例中，當 吾人於步驟（2)中所述之介質層35係採用將「薄膜」狀之 樹脂或金屬箔貼合在樹脂罩層33上時，吾人僅需直接將介 質層35連同其上所附著之乾膜37及第一金屬層36—起撕開 剝離，便能輕易將其去除。如前所述，由於本發明中之介 11 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — I----'11-----^ — I-----•麵 (請先閲讀背面之注意事項再填寫本頁) 45596 5 A7 _________B7_____ 五、發明說明（t|) (請先閱讀背面之注意事項再填寫本頁) 質層35、第:金屬層36、以及乾膜37均為製程中過渡時期 元件，並非最終產品時的結構，所以其附著力（抗剝離強 度）或貼合力不需太高且第一金屬層36的厚度很薄，即使 採直接剝離的方式，也不會傷害到金屬墊38與凸塊層39 (因 為以電鍵結合的強度相對較高許多）。 步驟（8):如圖二Η所示，進行加溫回流（Refl〇w)及 高度一致之製程，使凸塊層39表面成為具一致高度之凸塊 391。由於該凸塊391係突出於基板31—側表面一預定高 度’因此可供直接壓銲於一IC晶片（圖中未示）之金屬電 路層上，於1C晶片上不再需要形成凸塊。並且，本發明藉 由電鍍的方式形成凸塊’可使複數個凸塊（凸塊391)接點 之間距縮小至150μηι以下，達到80〜120μπι左右的標準，以 符合與晶片進行加熱壓銲時所需規格。當然，於基板31的 另一側面（下側面）亦設有若干錫球56以供焊接至外界電 路板。然而，由於該基板31下側面的錫球56係用於進行對 外界電路板的銲接’所以其對於錫球56尺寸以及錫球接點 之間距（Pitch)的尺寸均較大’一般均大於2〇〇μ1η以上，故 經濟部智慧財產局員工消費合作社印製 與本發明之以電鍍方式形成的凸塊3 9丨無論於技術與功效 上均不相同。 综上所述，本發明之在1(：封裝基板上形成凸塊之方法與 裝置至少有下列優點·· (1)凸塊接點之間距（Pitch)較小。本發明藉由電鍍 的方式形成凸塊’可使凸塊接點之間距縮小至15〇JLim以下， 達到80〜12〇μηι左右的標準，以符合與晶片進行加熱壓銲時 12 本紙張尺度翻”目家_ 雜咖χ 297公复） 55965 A7 B7 五、發明說明（广q 所需之規格，且更可幫錢縣元件的尺寸得⑽-步縮 /J、〇 ⑵凸塊的製造成本相職低。本伽之凸塊係以電 鍍方式形成於封裝基板上，相對於在晶圓（IC晶片）上形 成凸塊的技術’本發明不僅於製絲件控顺技術複雜度 均相對更低’產品良率相對增高，且製造成本也可大幅減 少0 以上所述係·-紐實酬詳細酬本伽，而非限 制本發明之範圍，而且熟知此類技藝人士皆能明瞭，適各 而作些_改變及前，仍將不失本發明之«所在，: 不脫離本發明之精神和範圍。 綜上所述，本發明實施之具體性，誠已符合專利法中 所規定之發明專利要件，謹請貴審查委員惠予審視，並 賜准專利為禱。 ---------——--------訂--------·% (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製

Claims (1)

  1. 經濟部智慧財產局員工消費合作社印製 Α8 68 C8 D8 六、申請專利範圍 1. 一種在1C封裝基板上形成凸塊之方法，包括有下列步驟： CA)準備一基板’於該基板之至少一側面上形成包括有— 金屬電路層以及一樹脂罩層蓋覆於金屬電路層上，該 樹脂罩層之適當位置處設有若干開孔，使開孔處之金 屬電路層可暴露於外界而不被蓋覆； (B) 以無電金屬化方式於基板之該側面形成一第一金屬 滑’使該第一金屬層蓋覆於樹脂罩層及位於開孔位置 處之金屬電路層； (C) 於第一金屬層上形成一乾膜層，該乾膜層於對應於開 孔位置處亦呈開孔狀態，使開孔位置處之第一金屬層 暴露於外界而不被蓋覆； (D) 以電鍍方式於開孔内形成一預定厚度之金屬墊在第一 金屬層之上； (E) 於金屬墊上形成凸塊層； (F) 將開孔之外其他位置處之乾膜及第一金屬層均去除， 使凸塊層呈突出於基板之該側面上之狀態。 2. 如申請專利範圍第丨項所述之在IC封裝基板上形成凸塊 之方法，其中，於步驟（A)與步驟之間更包括有 下列步驟： (A1)於樹脂罩層上形成一介質層，該介質層於對應於開 孔位置處亦呈開孔狀態。 3. 如申請專利朗第2項所述之在1C封裝基板上形成凸塊 之方法，其中，該介質層的材質可提供第一金屬層與基 ________14_ 本紙張尺度t S 國家縣· ( CNS ) ( 210X297^-t } '--—-- --------—裝—-----訂-----線 (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局S工消費合作社印製 45596S B8 C8 ~-------- 夂、申請專利範圍 板之間的良好結合介質，其玎為金屬、金屬化合物、或 是樹脂。 4.如申請專利範圍第2項所述之在1C封裝基板上形成凸塊 之方法’其中，該介質層係以化學氣相沈積（CVD)、濺 艘、電鍍、印刷、旋塗、或是貼合中的其中之一方式結 合在基板上。 5·如申請專利範圍第1項所述之在1c封裝基板上形成凸塊 之方法’其中’於步驟（B)與步驟（C)之間更包括有 下列步驟： (B1)進行電鍍’以增加第一金屬層的厚度。 6‘如申請專利範圍第5項所述之在1C封裝基板上形成凸塊 之方法’其中，於步驟（B1)中進行電鍍所增加的金屬 材質與第一金屬層的材質不一定相同。 7. 如申請專利範圍第丨項所述之在ic封裝基板上形成凸塊 之方法，其中，於步驟（B)中所述之無電金屬化方式係 指真空满:鍍（Sputtering)、或是無電解化學銅（pth)。 8. 如申請專利範圍第1項所述之在1C封裝基板上形成凸塊 之方法，其中，於步驟（C)中所述之乾膜層的材質可為 樹脂、光阻、或其他高分子材料。 9. 如申請專利範圍第丨項所述之在ic封裝基板上形成凸塊 之方法’其中’於步驟（C)中所述之乾膜層係以印刷、 旋塗、或是貼合中的其中之一方式結合在第—金屬層上。 10·如申請專利範圍第1項所述之在丨c封裝基板上形成凸塊 之方法，其中，於步驟（C)中係以下列步驟使該乾膜層 ____15_ 本紙張纽顧+ 轉CNS ) A4^( 210X297公釐} " 一 ----------裝------訂------線 (請先閡讀背面之注意事項再填寫本頁) _ 5 一-— 經濟部智慧財產局員工消費合作社印製 5 )S5 AS B8 ^^ C8 、 ^-------- κ、申請專利^ "' —-- 於對應於職位置結㈣孔狀態： )於第-金>1層上形成—乾膜層，該乾膜層感光 材質； (C2)以-曝光機透過1定圖案之鮮對乾膜層進行曝 光’该預定圖案係對應於開孔之形狀與位置； C3)對感光材質之乾膜層進行㈣錢侧製程，以去 除對應於開孔位置處之乾膜層，並暴露出第一金屬 層於開孔内。 11·如申請專利範圍第丨項所述之在IG封裝基板上形成凸塊 之方去，其中，於步驟⑺）中所述之金屬墊的材質係為 鋼金、錄、铭、絡、或其合金。 12.如申請專利範圍第1項所述之在1C封裝基板上形成凸塊 之方法，其中，於步驟（E)中所述之凸塊層的材質係為 鋼、錫、鉛、或其合金。 13_如申請專利範圍第1項所述之在1C封裝基板上形成凸境 之方法，其中，於步驟（F)之後更包括有一步驟： (G)進行加溫回流（Refl〇w)及凸塊高度一致之製程’使 凸塊層表面成為具一致高度之凸塊結構。 14· 一種1C封裝基板上具凸塊之結構，包括有： 一樹脂基板； 一金屬電路層，形成於基板之一側面上； 一樹脂罩層，蓋覆於該金屬電路層上，於樹脂罩層之適 當位置處設有若干開孔，使開孔處之金屬電路層可暴 露於外界而不被蓋覆； ______16___ 本紙張尺度適用中國國家榡準（CNS ) A4規格（210 X 297公釐） -- — - n ----I n n I ，1τI I : I I 線 - . c请先閲讀背面之注意事項再填寫本萸) 經濟部智慧財產局員工消費合作社印製 6 5 Λ8 B8 C8 ~ ___________D8 六'申請專利範圍 第-金屬層，形成於各開孔内部之週緣表面，包括位於 開孔内之金屬電路層表面上； 金屬塾’形成於各開孔内部之第-金騎上；以及， 凸塊，職於各金屬虹，且战係突出於基板之該側 面外一預定高度。 15. 如申請專利_第14項所述之在⑽裝基板上具凸塊 之結構’其中’該第一金屬層的材質係為鈦（Ti)、錄 ㈤、金（Au)、銅（Cu)、鐵（Fe)、鉻（〇)、 或其合金。 16. 如申請專概_14摘述之在_裝基板上具凸塊 之結構，其中，金屬塾的材質係為銅、金、鎳、紹、絡、 或其合金。 17. 如申請專利範圍以項所述之在1(：封裝基板上具凸塊之 結構，其中，凸塊的材質係為銅、錫、鉛、或其合金。 18. -種1C封躲板上具凸塊之結構，包括有： 一樹脂基板； 一第一金屬電路層’形成於基板之一側面上； -第-樹脂罩層’蓋覆於該第—金屬電路層上，於第一 樹脂罩層之適當位置處設有若干第一開孔，使第一開 孔處之第一金屬電路層可暴露於外界而不被蓋覆； 複數個凸塊，以電鑛之方式形成於第一開孔並搞合於第 - j電路層上’且凸塊係突出於基板之該側面外一 預定咼度，該複數個凸塊係可用於壓銲並電性連接於 一積體電路晶片； ^ ----------- 17 本紙張尺度適用中國國家標準（CNS ) A4见^Τ~210χ297公竣一^------ ---I.------- 裝------訂------^ (請先閲讀背面之注^Wl·-項再填寫本頁) 455965 A8 B8 I----- C8 . -------- D8 六、申請專利範圍' ' :-- 第電路層’开)成於基板之另_側面上且與第—金屬 電路層電性連接；以及， ’' 第-樹脂罩層蓋覆於該第二電路層上且設有若干第 二開孔，使第二開减之第二金屬電路層可暴露於外 界以供電性連接於一外界電路板。 (請先閱讀背面之注意事項再填寫本頁) —裝. 訂 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS )八4規潘（210X297公釐）
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