TW455957B - Manufacturing method and structure of mixed type wafer level package - Google Patents

Abstract

The present invention provides a manufacturing method and a structure of mixed type wafer level package. The structure is formed by first forming an elastomer on the bottom of solder bump; forming a metal supporter, being covered by polymer material such as polyimide; forming an UBM layer on a metal layer above the elastomer; forming a plurality of solder bumps on the UBM layer so that the tips of the solder bumps as exposed for increasing the height of the solder bump, thereby increasing the reliability of the solder bump and simultaneously packaging the plurality of dies on the wafer surface; and then dicing to have dies thereby completing the manufacture of semiconductor device.

Description

V. Description of the invention α) [Field of the invention] The present invention relates to a method and a structure for manufacturing a hybrid wafer scale structure, and particularly to a method for manufacturing at the bottom of a solder bump. An elastic body (Elsatomer), and then a metal support body is made, and then coated with a dielectric layer. [Background of the Invention] In recent years, Chip Scale Packages (CSP) have been regarded as a low-cost packaging technology and used to manufacture high-capacity integrated circuits. Proposed by Tessera Company 'They also call this technology a micro-BGA (Ball Grid Array) packaging method. This micr ο-BGA packaging method is used to simultaneously package a plurality of closely-regularly arranged packages to be packaged above a circuit board or substrate. At the same time, this micro-BGA packaging method is a high-density packaging method ', and it combines the advantages of flip-chip assembly and surface adhesion packaging. Therefore, using this wafer-scale packaging technology can perform advanced dispensing-like work on the entire wafer without the need to cut d i e before the traditional flip-chip packaging, and then perform the bonding process. The difference between this wafer-scale package and other packaging technologies is that it has an interposer layer. This interposer is made of a flexible and flexible material. This interposer can not only absorb The mechanical stress generated during the packaging step can further allow thermal expansion caused by different thermal expansion coefficients when the die is bonded to the substrate, that is, the role of the interposer here is a stress buffer layer and a thermal expansion buffer layer; in addition, Wafer-scale packages have other features, which are the same as micro-BGA packages

Page 5 4 5 59 5. '. V. Description of the invention (2) The moon dagger is capable of using Surface Mount Technology (SMT) process and circuit board for assembly work. In a typical nucro-BGA package, a flexible interposer (which may contain circuits) is used to bond the solder bumps on the surface of the integrated circuit chip and the solder bumps standing on the surface of the flexible circuit board. The thickness of the flexible circuit board is about 25. It is made by bonding a polymer material such as plyimide with an elastic layer (thickness: 150), which is an elastomer layer. It can provide the flexibility and flexibility in the triaxial direction to reduce the stress generated during the manufacturing process and the thermal expansion caused by different thermal expansion coefficients. Most integrated circuit wafers are designed to have I / O pads in a peripheral array. For today's high-density semiconductor components, the spacing between the I / O pads is shrinking. Therefore, in order to improve the distance between the I / 〇 pads, it is often necessary to use a 丨 / 〇 pad to re-start; 7 I / O pad Redistribution Process so that the I / 〇 pads are arranged by the peripheral matrix. Instead, it is arranged in an area matrix (Area Array). In the process of I / 〇 pad redistribution, I / 0 pads are often extended from the periphery of the die to the middle of the die by a metal wire. In order to determine the reliability of the wafer, a stress buffer layer must be formed under the metal line to buffer the stress generated during the manufacturing process. In the traditional wafer-scale fabrication method, an elastomer layer is used to reduce the damage of solder bumps by stress. However, the elastomer layer itself has a Coefficient of Thermal Expansion (CTE) that is too large to be related to the dielectric. When the layers are bonded, the dielectric layer is cracked and due to the elastomer material

4 5 5 9 5: ί 5. Description of the invention (3) is very soft, so when the I / 0 pad redistribution process is performed on the surface, the wire may break due to the deformation of the elastomer. In another conventional wafer-scale fabrication method, the height of solder bumps is increased to reduce stress. If you increase the height of the solder bumps to reduce stress, the effect of stress reduction is relatively limited because the height that can be increased is limited. [Summary and purpose of the invention] The present invention is a structure developed by combining the above two methods of reducing stress. The main structure is to first make an elastomer bump with a thickness of 10 to 150 / im at the bottom of the solder bump. (Elsatomer), and then make a metal support, and then cover it with an insulating material such as polyimide (PI; Nitride; Oxide: Ceramic ...) with a thickness of about 30 to 15 0 // m to complete the wafer scale. Of construction. The advantages of the present invention can avoid the problem of thermal expansion coefficient mismatch (CTE Mismatch) between the elastomer and the dielectric layer, and can further effectively reduce the stress. In order to achieve the above-mentioned object, the method for dimensionally fabricating a hybrid wafer disclosed in the present invention includes at least the following steps: providing a pre-processed semi-conductor wafer, wherein the wafer is built on a silicon substrate, and the silicon A plurality of bonding pads are formed on the top surface of the substrate, and the areas of the bonding pads except the top surface are exposed are buried in an insulating first protective layer; an elastomer is formed on the upper surface of the first protective layer. Depositing a first metal layer on the top surface of the first protective layer, the bonding pad and the elastomer;

4 5 5 9 5, V. Description of the invention (4) Define a photoresist layer (PR) as the cover and curtain to expose the top surface of the pad and the elastomer; deposit a second metal layer on the pad and Removing the photoresist layer from the top surface of the elastomer; and removing the excess first metal layer 40. Deposit a dielectric layer on the surface of the first protective layer and expose the top of the second metal layer to the outside; deposit a third metal layer on the top surfaces of the dielectric layer and the second metal layer to define Metal trace; depositing a second protective layer on the third metal layer, and exposing the third metal layer above the elastomer to form a contact hole; depositing a solder metallographic layer (Under Bump Metallurgy (UBM) on the contact hole; and solder bumps are implanted on the solder metallographic layer. The detailed content and technology of the present invention are described below in conjunction with the drawings: [Brief description of the drawings] Figure 1 is a cross-sectional view of a hybrid wafer scale structure of the present invention; and Figures 2A to 2H are shown Cross-sectional view of each step of the method for manufacturing the hybrid wafer scale structure of the invention. [Symbol description] 10 wafers 12 silicon substrates 20 pads 22 window openings

Page 8 455957 V. Description of the invention (5) 24 The first protective layer 30 The elastomer 40 The first metal layer 50 The light F and the layer 60 The opening T0 on the welding potential #The opening on the physical body 80 The second metal layer 90 Electrical layer 92, metal layer 100, Tan pigeon bump 110, second protective layer 112, contact hole 120 layer [Details of the invention, the invention is shown in detail. The structured wafer 10 is established on the surface to form a plurality of exposed areas and then the electrical connection between the first redeposited first metal path is defined to grow in the future. The construction method is to place a semi-conductive monolithic substrate 12 and a bond pad 20, and the domains are buried in an insulation-protective layer upper surface 24 layer 40 as a bottom electrode, and then use the lithography and surname welding The cross-sectional view of the pad and elastomer < _ structure is as shown in Figure 1 (Semi-conducting), and the surface of the sand substrate 12 is on the surface of the member. Form an elastic body 30, and then provide the pad 20 and the integrated electrical engraving technique to expand the photoresist in a photoresist, and then remove the photoresist layer 50 and connect the hole (60'70). A second metal layer 8 is formed above.

Page 9 45 5 9 V. Description of the invention (6) A second metal layer 80 is formed over the hole (60'70), the photoresist layer 50 is removed, and then the excess first metal layer 40 is etched. Remove. A second dielectric layer 90 'is deposited and the pad 20 and the second metal layer 80 above the elastomer 30 are exposed. Then a second metal layer 92 is deposited as a metal trace. This metal line can provide The electrical connection between the pad 2 〇 and the solder bump 丨 0 ′ 'and coated with a protective layer 1 1 0' and using lithography and etching technology to open the protective layer 1 10 above the elastomer 30 to be deposited In the opening of UBM, the third metal layer 92 is exposed, and finally a UM layer 120 ′ is formed on the third metal layer 92 above the elastomer 30, and a plurality of solder bumps 丨 〇〇 are formed on the ⑽ station layer 丨"On this occasion, a plurality of dies on the surface of the wafer 10 are packaged at the same time, and then the dies are cut to form a semiconductor element. The above-mentioned elastomer 30 is made of a flexible and flexible material. It is made. In the present invention, the role of this elastomer 30 is to act as a stress buffer layer and a thermal expansion relief layer. At the same time, the mechanical strength of the solder bumps formed subsequently is also improved by this elastomer 30. The reason is that this elastomer 3 can alleviate when the die is bonded to the substrate. Because the CTE difference between the two is too large (because the CTE of the silicon die = 2. D ~ 3ppm / t, and if the substrate is FR-4, its CTE = 17 ~ 18ppm / t), the stress is concentrated in the solder bump 100, and finally Causes solder bumps to crack or absorb mechanical stress generated when the die is bonded to the substrate; at the same time, the solder bumps 100 are formed above the elastic body 30 to make the solder bumps 100 The tip portion is exposed to increase the height of the solder bumps, thereby improving the reliability of the solder bumps 100. According to the above manufacturing method, the wafer-scale assembly method shown in "Figure 2" Sectional view to illustrate manufacturing of the present invention

Page 10 4 5 595 V. Description of the invention (7) Step. First, please refer to "Figure 2A", which is a semi-conducting wafer 10 of the present invention. This semi-conductive wafer 10 is built on a substrate 12 of a hair. First, a bond pad 20 is formed on the top surface of the silicon substrate 12 'for the electrical connection between the silicon substrate 12 and the outer substrate circuit' This solder pad 20 is made of a conductive metal material (such as Ming or Copper), and then use lithography technology to open the window opening 22 to be electrically connected on the pad 20, and simultaneously deposit a first protective layer 24 on the silicon substrate 12 to protect the pad 2. The first protective layer 24 is made of an insulating material, and the insulating material may be an oxide, a nitride, or an organic material. Please continue to refer to "Figure 2B". In this step, an elastomer 30 is deposited on the surface of the first protective layer 24. This elastomer 30 has flexibility and flexibility. It is made of an elastic material such as silicone rubber. (Si 1 ic〇ne Rubber) or Fluorosillcone Rubber, the elastomer 30 can be formed by printing or spin coating, where the elastomer 30 is deposited on the first-protective layer 24 After the top, the material of the elastomer 30 is cured by heating to improve its physical properties. The thickness of the elastomer 30 is between about 15 and 50 / zm. Please continue to refer to "Figure 2C". In this step, firstly, a first metal layer 4 of an appropriate thickness is deposited by sputtering (or physical vapor deposition (phyS ^ cai vap〇) r Deposition). The top surface of the first protective layer 24, the bonding pad 20 and the elastomer 30 is used as a bottom electrode, wherein the thickness of the first metal layer 40 is approximately 0.5 μ! Ϋ ~ 10 μm, and the first metal layer 40 can be made of copper, aluminum, steel alloy or aluminum alloy

Page 11 V. Description of the invention (8) Made of electric metal. Please continue to refer to "Figure 2D", define a photoresist layer (PR) 50 as a mask 'and use a lithography and etching technology to pattern the photoresist layer (pR) 50 to expose the pad 2 〇 and above the top surface of the elastomer 30, wherein the thickness of the photoresist layer 50 is between about 20 μm and 180 // m. Yan Qing continued to refer to "Figure 2E", and then used conventional techniques such as electroplating to form the second metal layer 80 in the defined openings 70), and removed the photoresist layer 50 'above. The thickness of the second metal layer 80 formed above the bonding pad 20 is approximately 20 mm, and the thickness of the second metal layer 80 formed above the elastomer ⑽ is equal to the thickness of the second metal layer above the bonding pad 20 80 thickness. Then, the excess first metal layer is removed by the last name. 0 Please continue to refer to "Figure 2F". In this step, a dielectric layer 90 is deposited on the surface of the first protective layer 24, and the second metal is The top of the layer 80 is exposed to the outside. The dielectric layer may be made of polyimide, benzocyclobutene (BCB), or other insulating materials. The method for depositing the dielectric layer 90 may be spin-coated. (Spin_c〇ating), screen or stencil printing (Screen or Stencil Printing) or laminating (Laminating) and other processes, where the thickness of the dielectric layer is about 30 μm ~ 1 5 0 # m between. Then please continue to refer to "Figure 2G". In this step, a third metal layer 92 of appropriate thickness is deposited on the top surface of the dielectric layer 90 and the second metal layer 80 to define a metal trace. , And this metal wire can be made of other metals such as copper, Shao, copper alloy or aluminum alloy, among which the metal wire

4 5 5 9; V. Description of the invention (9) The thickness is about 1 to 5 mm. This metal wire can provide the electrical connection between the solder pad 20 and the tin bump 100, while depositing the first Two protective layers 11 () are formed on the second metal layer 92, and the third metal layer 92 above the elastic body 30 is exposed to form a contact hole 112. The second protective layer nQ is made of an insulating material. Made, and the insulating material can be polyimide (mouth 〇 丨 y 丨 ① 丨 h), oxide, nitride or organic material.

Then please continue to refer to "Figure 2 η", in this step, first contact the metallographic layer (Unbump Metallurgy; UBM, UBM, which can also be called Ban Limiting Metallurgy; BLM) at the contact hole 112 / The UBM layer 120 is composed of an adhesion diffusion prevention layer (Adhesion Diffusion Barrier Layer), a wetting layer (Wet1; ing Uyer, also known as a tin dip layer), and a protective layer (not shown). The adhesion diffusion preventing layer may be made of titanium (Ti), titanium nitride (TiN), chromium (Cr), or other metal materials, and the wet layer may be made of materials such as copper (cu) or nickel (N 丨), and The protective layer may be selected from any one of a combination of gold (Au) and platinum (pt) materials. The UBM layer is mainly used to improve the adhesion relationship between the solder bump 100 to be formed and the top surface of the third metal layer 92. The UBM layer 1 20 can be formed by electroless plating or thin film deposition, and then a plurality of solder bumps 100 are formed in a defined manner by using traditional techniques such as ball implantation, screen printing, electroplating, electroplating, or steel printing. Inside the contact hole ιι2, and the above-mentioned manufacturing steps for forming the solder bump 100 using the conventional technique are known techniques, so it will not be described in detail here, where the thickness of the solder bump 100 is about 80 ~ 60 Between 0. So far, the crystals on the surface of the wafer 10 are cut, and then

4 5 5 9 ί 5. Description of the invention (i〇) The assembly work can be performed by using the electrical connection between a plurality of solder bumps 100 on the surface of the wafer 10 and the external circuit board. In this way, not only It can improve the individual dispensing problems caused by conventional die packaging, and can greatly reduce packaging costs. The solder bump 100 obtained by the above process is formed on the elastic body 30 so that the tip portion of the solder bump 100 is exposed to increase the height of the solder bump 100, thereby improving the solder bump 100. Reliability. Although the present invention is disclosed in the foregoing preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

Page M

Claims (1)

4 5 5 9 5 6. Scope of patent application 1. A method for manufacturing wafer-scale structures, the method includes at least the following steps: providing a pre-processed semi-conductor wafer, wherein the wafer is built on a silicon substrate Above, a top surface of the silicon substrate is formed with a plurality of bonding pads, and the remaining areas of the bonding pads are buried in an insulating first protective layer except the top surface is exposed; forming an elastic body on the first The upper surface of the protective layer; depositing a first metal layer on the top surface of the first protective layer, the pad and the elastomer; defining a photoresist layer as a cover to expose the top surface of the pad and the elastomer ; Depositing a second metal layer on the top surfaces of the bonding pad and the elastomer, removing the photoresist layer and removing the excess first metal layer; depositing a dielectric layer on the surface of the first protective layer, and The top of the second metal layer is exposed to the outside; a third metal layer is deposited on the top surface of the dielectric layer and the second metal layer to define a metal line; a second protective layer is deposited on the third metal layer And On the third metal layer of the elastic body exposed to the outside over a contact hole is formed; depositing a solder layer on the metallurgical contact hole; implantation and solder bumps on the solder layer microstructure. 2. The method for fabricating a wafer-scale structure as described in item 1 of the scope of the patent application, wherein the first protective layer may be selected from a combination of polyimide, oxide, nitride, and organic material. . Page 15 4 5 5 9 5 6. Application for Patent Fan Yuan 3. The manufacturing method of wafer-scale structure as described in item 1 of the scope of patent application, wherein the material of the aforementioned elastomer can be selected from silicone rubber and fluorosilicone Any of a combination of rubbers. 4. The manufacturing method of the wafer-scale structure as described in item 1 of the scope of patent application, wherein the thickness of the above-mentioned elastomer is between 10 μm and 150 / im. 5. The manufacturing method of the wafer-scale structure as described in item 1 of the scope of the patent application, wherein the thickness of the photoresist layer is between 30, and 180 / zm. 6. The manufacturing method of the wafer-scale structure as described in item 1 of the scope of patent application, wherein the thickness of the second metal layer is between 30 // m and 150. 7. The manufacturing method of the wafer-scale structure according to item 1 of the scope of patent application, wherein the thickness of the second metal layer formed above the elastic body is slightly equal to that of the second metal layer above the pad. thickness. 8. The manufacturing method of the wafer-scale structure as described in item 1 of the scope of patent application, wherein the thickness of the above-mentioned dielectric layer is between 30 and 150 μm. 9. The manufacturing method of the wafer-scale structure as described in item 1 of the scope of the patent application, wherein the material of the above-mentioned dielectric layer can be selected from any combination of polyimide, benzocyclobutene (BCB) and insulating material 0 1 0. The method for manufacturing a wafer-scale structure as described in item 1 of the scope of patent application, wherein the thickness of the third metal layer is between 1 / im and 5 / zm. 1 1. The manufacturing method of the wafer-scale structure as described in item 1 of the patent scope, wherein the material of the third metal layer can be selected from a combination of other metal materials such as copper, Shao, copper alloy and aluminum alloy. Any of them. 1 2. Manufacturing method of wafer scale structure as described in item 1 of the scope of patent application Page 16 4559 6. The scope of the patent application, wherein the above-mentioned second protective layer may be selected from any combination of polyimide, oxide, nitride and organic material. 13 3. The manufacturing method of the wafer-scale structure as described in item 1 of the scope of the patent application, wherein the solder metallographic layer further includes an adhesion prevention layer, a wetting layer, and a protective layer. 1 4. The manufacturing method of the wafer-scale structure as described in item 13 of the scope of the patent application, wherein the material of the adhesion prevention diffusion layer may be selected from titanium (Ti), titanium nitride (Ti), and chromium (Cr) Any combination of other metals. 1 5. The manufacturing method of the wafer-scale structure as described in Item 13 of the scope of the patent application, wherein the above-mentioned wet layer can be selected from any one of a combination order of copper (Cu) and nickel (N1) materials. 16. The manufacturing method of the wafer-scale structure as described in Item 13 of the scope of patent application, wherein the above protective layer may be selected from any combination of gold (Au) and platinum (Pt) materials. 1 7. The manufacturing method of the wafer-scale structure as described in item 1 of the scope of patent application, wherein the thickness of the above solder bump is between 80 // ni ~ 600 // m. 18. According to the wafer-scale fabrication method described in item 1 of the scope of patent application, wherein the solder bump can be formed by one of methods such as ball placement, screen printing, electrodeposition, electroplating, or steel printing. Implanted on the welded metallographic layer. 1 9, A wafer-scale structure, the structure includes at least: a pre-processed silicon wafer, wherein a top surface of the silicon wafer has a plurality of pads, and the pads are exposed except for the top surface The remaining areas are buried in an insulating first protective layer; Page 17 VI. Patent application scope An elastomer forms the upper surface of the first protective layer; a first metal layer is deposited on the first protective layer, the pads and the top surface of the elastomer; a photoresist layer Is used as a mask definition to expose the top surface of the pad and the elastomer; a second metal layer is deposited on the top surface of the pad and the elastomer; a dielectric layer is deposited on the first A top surface of a protective layer, and the top of the second metal layer is exposed to the outside; a third metal layer is deposited on the top surface of the dielectric layer and the second metal layer to define a metal line; a first Two protective layers are deposited on the third metal layer, and the third metal layer above the elastomer is exposed to form a contact hole; a solder metallographic layer is deposited on the contact hole; and a plurality of A solder bump is implanted on the solder metallographic layer. 20. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the first protective layer may be selected from any combination of polyimide, oxide, nitride, and organic material. One. 2 1. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the material of the aforementioned elastomer can be selected from any combination of silicone rubber and fluorosilicone rubber. 2 2. The wafer-scale structure described in item 19 of the scope of patent application, wherein the thickness of the aforementioned elastomer is between 10 // m and 150 " m. 2 3. The wafer-scale structure described in item 19 of the scope of patent application, Page 18 455 VI. Scope of patent application The thickness of the photoresist layer is between 30 and 180 // m. 2 4. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the thickness of the second metal layer is between 30 μm and 150. 25. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the thickness of the second metal layer formed above the elastomer is slightly equal to the thickness of the second metal layer above the pad. thickness of. 2 6. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the thickness of the dielectric layer is between 30 " m and 150 / zm. 2 7. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the material of the aforementioned dielectric layer may be selected from the group consisting of polyimide, be η ζ 〇cyc 丨 〇butene (BCB) and Any one of a combination of insulating materials. 8. The wafer-scale structure described in item 19 of the scope of patent application, wherein the thickness of the third metal layer is between 1 / MΠ and 5 / im. . 2 y. The wafer-scale structure described in item 19 of the scope of patent application, wherein the material of the third metal layer may be selected from a combination of other metal materials such as copper, aluminum, copper alloy and aluminum alloy Any of them. 30. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the second protective layer may be selected from any combination of polyimide, oxide, nitride, and organic material. One. 3 1. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the solder metallographic layer further includes an adhesion prevention layer, a wetting layer, and a protective layer. 32. The wafer-scale structure described in item 31 of the scope of patent application, Page 19 范围 Scope of patent application Wherein the material of the above-mentioned anti-adhesion diffusion layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), chromium (Cr) and other metal materials. 33. The wafer-scale structure described in item 31 of the scope of the patent application, wherein the wet layer can be selected from any combination of copper (Cu) and nickel (Ni) materials. 34. The wafer-scale structure described in item 31 of the scope of patent application, wherein the protective layer can be selected from any combination of gold (Au) and platinum (Pt) materials. 3 5. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the thickness of the above solder bump is between 80 // m ~ 600. 36. The wafer-scale structure described in item 19 of the scope of the patent application, wherein the solder bump can be formed by one of methods such as ball placement, screen printing, electrodeposition, electroplating, or steel printing. Implanted on the welded metallographic layer. Page 20