TW454144B - Method and apparatus for reducing the delay in generating saturation flags in an ALU - Google Patents

Abstract

A method and apparatus are disclosed for generating a preprocessed saturation flag in a multiplier. According to one aspect of the invention, the preprocessed saturation flag is produced at substantially the same time as the reduced products of the more significant side of an array of partial products are selected. A conventional multiplier generates an array of partial products. The partial products are reduced in the more significant side of the array assuming a carry-out from the less significant side of the array as taking on a first state to produce a first set of reduced products. The partial products are also reduced in the more significant side of the array assuming a carry-out from the less significant side of the array as taking on a second state to produce a second set of reduced products. Both sets of reduced partial products are generated in parallel with the carry-out from the least significant side. The first set of reduced products are selected as the reduced products of the more significant side of the array when the carry-out from the less significant side of the array takes on a first state. The second set of reduced products are selected as the reduced products of the more significant side of the array when the carry-out from the less significant side of the array takes on a second state. A number of the most significant bits of the first set of reduced products are combined to produce a first saturation flag and a number of the most significant bits of the second set of reduced products are combined to produce a second saturation flag. The appropriate saturation flag is selected based on the carry received from the least significant side of the array. The saturation flag is selected substantially simultaneously with the selection of the reduced products, based on the carry received from the least significant side of the array.

Description

454144 V. Description of the invention (i)

Igg field '. ≪ The present invention relates to data arithmetic units (DAU) of digital signal processors and other microprocessors, and more specifically, also to reducing the generation of advances in the data arithmetic units (DAU) of microprocessors. Method and device for processing delay of saturation flag. The background is two main units of digital signal processor (DSp) calculation. One of the operations supported by DAU is multiplication. The multiplier is a micro τ two = device or a digital signal processor used to obtain the multiplied number and the 'number multiplied by two' circuit. In a typical multiplier, the partial product is formed by a multiplicative representation, such as the number of the multiplicands of the binary, 2, and the complement = multiplied by the binary representation of the multiplier = = 2; the partial product. The partial product is simplified to obtain the second-hand partial product. The least significant bit (lsb) of any method and multiplier in most known methods is on the right, ^; to the left (considered as right-to-left or LSB). The first to do. 1 and 5 broadcast cards, μa, and carry is shift or eclipse iiL to; the calculation of the industrial product and carry spread is to simplify the top of the skin / knife product array and to the bottom of the array. The least significant part of the in product term is in binary form: 仃. The final part 1 is carried in the form of 1 and stored. The most significant ^ is generated ^ The most significant part is reached. The carry propagation adder is used to combine the most significant ϋ ϋ to t 孓Product term

4541 44 V. Description of the invention (2) The points are converted from the carry-storage form to two. After the multiplier cycle, the multiplication and system forms are used to complete the multiplication operation. Is the result product applied to the arithmetic logic two typically loaded into a register for processing in m first? Product based on the result: (ALU) or add before the adder, but it is usually pre-processed correctly and pre-processed as the supplier right or left. ^ = Contains saturation or the product is shifted to some i-significant bits for the result of the product ^ ^ ^ m to generate a pre-processing control signal. For example, if (the 3 most significant 'significant bits in a 32-bit π result product are logical'), the = and deuterium preprocessing operations will set the remaining 29 least significant bit values to 0 in a known manner, due to preprocessing The operation is completed in order by starting with selecting and obtaining the multiplier result and loading the multiplier result into the register, so the delay of the 3 or 4 stage is introduced. The delay of the import when calculating the pre-processing flag is considered the key of the dau Cotai 'RK Kolagotla et al. Custom in IEEE 1997

Integrated Circuits Conf., Pp. 469-72 (May 1997) " VLSI Implementation of 1 2000-MHz 16x16 Left-t〇-Right Carry-Free Multiplier in 0; 35 ^ m CMOS Technology for Next-Generation DSPs & quot The article, hereby incorporated in this article in the form of "1", reveals that the most significant bit is a multiplier that provides a partial product in a way that can be used earlier than the known multiplier, and _ 因 " This reduction is completed The time required for multiplication and multiplication. It is obvious from the above-mentioned disadvantages of obtaining the pre-processing flag by the conventional technology that it is necessary to evaluate the pre-processing flag as long as the most significant bit is usable. Summary of invention

5. Description of invention (3): and device. The multiplier generates a pre-processed saturation flag. It generates and partially multiplies the array fgu = two special 3, and pre-processes the saturation flag at the same time. The choice of the J-most effective side simplified product is essentially a traditional multiplier that produces a partial one-state array it /. The J-knife product is assumed to have the first reduction to produce the? -Th output and is the most efficient in the array. Array lowest right ^ f ,. Partial products can also be simplified by assuming that there is a side reduction to produce the second group] = bit output and carry out on the highest effective low effective side of the array. When the product is selected by the most effective side, the simplified S is selected. For the array maximum = 4, the second group is simplified ^ product selection; "=== the effective side simplified product. ~ The effective side is to generate pre-processed saturation Flag camphor, one: the effective bits are slaved to generate the second saturation flag and the most saturated flag based on receiving 2 $ private from the least significant side of the array. The choice of a suitable saturation flag is essentially a simplified product Select 4 = Select. According to the carry received by the least significant side of the array. 'Select as the same time, each according to the present invention allows the flags to be pre-processed early in the multiplication cycle,-the delay in generating the flags increases the cost of the area. When the multiplier is improved When the register is generated and selected for ALU pre-processing, the exposed product ^ saves 3 to 4 flags through the algorithm that calculates the saturation flag to generate 454144. 5. The description of the invention (4) paragraph. The invention is more complete Understanding and other aspects and advantages of the present invention will be obtained by referring to the following detailed description and drawings. Brief Description of the Drawings Figure 1 is a simplified diagram explaining the generation and addition of partial product terms and the calculation of multipliers and multiplicands Number product tradition Cardinality multiplier; Figure 2 is a simplified diagram to explain the adder of Figure 1, Figure 3 is a simplified diagram to explain the personality of Figure 1; Figure 4 is a simplified diagram to explain the grid of Figure 1; Figure 5 is a simplified diagram Figure 'explains the four basic radix multipliers used to generate and add partial product terms and (calculate multipliers and multiplied products); Figure 6 is a simplified diagram explaining the D grid of Figure 1; Figure 7 is a simplified diagram , Explain the traditional multiplier of FIG. 1 or FIG. 5 and the traditional pre-processing control block that generates different pre-processing operations; and FIG. 8 is a diagram explaining the -1 or the conventional multiplier of FIG. 5 and performing the pre-processing as the present invention. A pre-processing control block that handles saturation operations. Detailed description of the JI formula Figure 1 is a simplified diagram of an illustrative embodiment of a traditional multiplier 10. The multiplication 2 may be part of an integrated circuit (1C). The multiplier 1〇 It can be, for example, a signal processor (DSP), a microcontroller, an application-specific integrated circuit, or a data arithmetic unit part of the U channel. The multiplier 10 includes a carry as shown in Figure 2, α, \, geotechnical Converters 1, 4, 16 and adders 18 and 19. In the array 24 4 ^ phase million The mouth fish device 18 has a round-in 20 and a round-out 22, and the adder 18 is connected to each other in the array 24. The output of the adder 1 8 is + L ^

454144

V. Description of the invention (5) Force 2: Input of device 18. The multiplier 10 is explained in FIG. 1 as a multiplier that produces a sum and thus calculates the product of the n_bit multiplier and the η-bit multiplied to form a product with 20 bits: multiplier and bit multiplier adder 1 8 configurations are known for rows and columns. As shown in Figure 2-] 乂 and Ding are considered as full adders, as described in the same column (-Λ 丄 * 器 18 receives the following input 20⑴ from the upper carry wheel out of the field and c ..: the implement 18 and output; (ii ) The knowledge of the second lowest effective column. The product bits of each force part, such as the related arts, should be added to the addition of the adder 19 between the dashed lines 30 and 32: the knife product to the entry and the carry output signal Adder 18 ^. Γ < ^, carry output and partial product bits to produce the following output bits' The sum of the propagated bits and carry output of the array 2 4 of the adder 18, 19 is shown on the side. Adder The most significant bit side of the array 24 of 18 and 19 is the side 2 6 Α ί, and the least significant side of the array 24 of the adder 18 and 19 is on the right side of the figure. The complete simplified array is not shown. Carry propagation adder 12 The partial sum and the carry output signal are received by the adder 18 on the bottom row on the least significant side 26 of the array 24. The carry propagation addition 12 produces a multi-bit output 40 and at least one carry output bit. In the example, the multi-bit output 40 includes (η + 1) bits and a carry output Bit 42 is a single bit. Carry output bit 42 provides a selection input to the multiplexer 14 to control the output of the multiplexer 4 and will be further discussed below. Between the virtual lines 30 and 32 The adder 19 interfaces the adder 丨 8 of the array 24 with the converter 16. The adder 19 does not increase a part of the product bits. The adder

Page 12 4 5 4 彳 44 V. Description of the Invention (6) 1 9 Add the 3 bits generated by the array 24 together and generate 2 outputs to the converter 16. < Converter 16 includes two types of plows, designated a and b. Figure 3 is a simplified diagram of grid a 'showing the logical combination of outputs s (and) and C (carry), and outputs A, G, Z0, and 00 as inputs. A formula indicating how the inputs are logically combined to form an output is shown on the right side of FIG. . As shown in Fig. 1, each A cell is composed of a peer adder 19 between dotted lines 30 and 32, which is rounded in place. Each grid is summed by the same i adder 18 between 虡 and 30. The simplification of the most significant bit is done in the octets and squares, so that the input of the multiplexer 14 can be used before the carry output 42 of the carry propagation adder 12 or the carry of the carry adder 12 Output 42 is available at the same time. In this manner, a multiplexer delay after the carry output 42 of the adder 12 can be used, and 44 can be used as the output of the multiplexer 14. Figures ^ and ΐ ^ show the inputs Z1 and 〇 1 (received by the eighth output of the queue Z0 and 00) and the age and ^ received by the peer A. Each 6 cells pass inputs A and G to adjacent b cells (presented there) and produce outputs and ⑻. Loss = zo and oq are logical combinations of B-box turns. Indicating how the round-in is logically grouped s to form the Chen style of round-out in each B cell is shown on the right side of FIG. 4. A and B cells, according to the relationship between input and output, and calculate and maintain the __ 々 々 Xi Xijie County > Shidi pendulum between the East and the West, and then the character of the product of the form with the innermost significant bit sum Yixian zinc, s green curve energy, the carry output 42 generated by the propagation adder is the first — logical state ^ such as 0, converter 16, calculates the most significant bit and the state of the series, such as 1, conversion crossbow] R 介 二 + Guanxian Yishi & Out 4 2 is the second logically narrow Is 1 6 Also count the most significant bit and simplify

Page 13 45 4 1 4 4 V. Description of the Invention (7) '' — Product. The A and B outputs of the bottom row provide two sums as inputs to the multiplexer i 4. One of the sums is represented by the Z0 output, and the second sum is represented by the 00 output. ′ When the carry video adder 12 has completed the calculation and the carry out 42 is available ’The correct one of the two sums calculated by the converter 16 or the simplified product is selected by the multiplexer 14. When the carry output 42 produced by the carry propagation adder 12 has a first state, the first sum calculated by the converter 16 is selected as the output of the multiplexer 14. When the carry output 42 produced by the carry propagation adder 12 has the second state, the second sum calculated by the converter 6 is selected as the multiplexer 14 and the output is also lost. For example, the first sum represented by the Z0 input may be the input to the multiplexer, whereas the second sum represented, for example, by the 0 input may be the input to the multiplexer Η. " ^ In an illustrative embodiment, the multiplexer 14 provides (ni) output 44 and the carry propagation adder 12 provides (η + 1) round out 40, focusing on multiplying by bits ^ 4 multiplexer The output 44 generated by 14 is the most significant bit of the product, and the output 42 generated by the carry propagation adder 12 is the least significant bit of the product. One digit is simplified between dashed lines 30 and 32 in FIG. For this reason, the number of bits out by the round of the carry propagation adder 40 is greater than the number of bits out by the round 14 of the multiplexer 1. Digits are lag2 bases. . The product difference line between the lowest charge-effect side of the array 2 6 and the most significant side of the array 26 may vary depending on the number of bits in the multiplier and the multiplicand. Fig. 5 shows a schematic diagram of a base-to-number multiplier converter multiplier 10. Figure 5: The components provide similar functions to those in the embodiment of radix_2 in Figure 1 and are shown with the same reference numerals and apostrophes. In the radix_4 converter, a one-bit comparison with the personality of the radix_2 converter in FIG.

Page 454 144

5. Description of the invention (8) Generates two bits. Due to the conversion between the dotted lines 30, and 32, the carry propagates the adder 12, and the two digits between the output bits are rounded out by the simplifyer 14 '. 4G is output by the D grid ^, which is greater than many. Since the operand is the base-4, so Figure 1bis = logic is shown in Figure 6. To replace. Although the present invention is a person with a cardinality of 2 3 A and a type of D in FIG. 5, the present invention is not limited to this specific embodiment. … Tsukiji · Multiplier of Figure 1 and Figure 5! 0, i 〇, OK. It is manufactured by a well-known VLSI process. This application is used in the integrated circuit of Tian Shaoyi. Therefore, Lei ίΛ, s ~ u l is particularly advantageous in the use of refined technology including this technology. The communication system: installation force to complete the advantages of signal processing. Multipliers ㈠, ^:: due to α Ϊ Ϊ f can be used as the most significant bit to provide part of the product ’s reason: 匕 reduces the time required to complete the multiplication. The invention is advantageous with many simplified designs, types of multipliers, and cardinalities. This method can be used with any radix_2 array multiplier, such as 2's complement multiplier, Booth-MacSorley multiplier, or any higher radix multiplier. Pre-processing flag detection In FIG. 7, the multipliers 10, ι0 of FIGS. 1 and 5 are divided into a multiplier array 24, a converter 16, a final multiplexer stage 14, and a carry propagation adder 12. (The elements in FIG. 7 provide functions similar to the elements in the illustrative embodiment of the radix-2 in FIG. 1 or in the illustrative embodiment of the radix-4 in FIG. 5, and are shown with the same reference numerals. As shown in FIG. 7, The product multiplied by the result of the multiplier 丨 〇 is placed in the load register 70. The pre-processing control is performed. Block 72 is provided by the register 70

Page 15

454144

V. Description of the invention (9) The result product receives the most significant number of pre-defined bits and generates a timing control signal for performing different pre-processing operations such as saturation or left / right shift k-bit operations. The present invention relates to a saturation preprocessing operation. As previously indicated, the 'saturation pre-processing will multiply the result of the evaluation-some of the most significant bits', and if saturation is present, the saturation pre-processing will saturate the result product. For example, a saturation situation may require that the 3 most significant bit values have a logic one. If saturation is present, the saturation-first processing, for example, will saturate the result product by setting the remaining least significant bit to zero. The key delay paths of the multiplication-painting cycle of Fig. 7 are as follows: selection of the selection signal generated by the carry propagation adder 1, 2, the final multiplexer stage 14, loading of the multiplier f, and final loading into the loading register 7, 0, and evaluation of the advance Processes the MSB of control block 72. Therefore, when the multiplier product is selected to be pre-processed by the ALU via the load register, the key delay path is the flag generation logic 3 to (late stage.) As in the present invention, as long as the most significant bit is available When used, the pre-processing operation is performed. As previously indicated, the conversion of the most significant bits is completed by the converters u and 16 in the A and B cells, so that the multiplexed / input is carried in the carry propagation adder 丨The 2 carry output 42 can be used before or at the same time as the carry propagation adder 1 2 '. The carry output 42 can be used at the same time. In this way, the multiplexer delay after the carry output 4 2 of the adder 12 can be used, And 44 can be used as the output of the multiplexer η. Figure 8 illustrates a multiplier with a pre-processing stage such as the present invention Q. The pre-processing stage 100 introduces a pair of blocks 80 and 82 for Preprocessing multiplier multiplication

454144 V. Description of the invention (ίο) ": ---- Product of MSB. Basically, blocks 80 and 82 determine whether the predetermined most significant bit το is all equal to 1. The first block 80 preprocesses the msb related to the first sum (Z (ι)) calculated by the converter 16, and the second block 82 preprocesses the second sum (0 (丨)) calculated by the converter 16 MSB. In a production, each of the blocks 80, 82 AND's a predetermined number of MSBs together to determine whether all MSBs have a value of logical i. The multiplexer 14 operates in the same way as the multiplexer in the figure] and the multiplexer 14 'in FIG. 5, and the same selection signal carry propagation adder 12 is generated to select one of two logical states. Each of the pre-processed M3β bits generated by blocks 80, 82. When the carry carry adder 12 has completed the calculation and the carry output value 42 is available, the correct one of the two sums calculated by the converter 16 is summed or simplified, and is selected by the multiplexer 14 plus g. In addition, the correct one of the predicted values generated by the blocks 80 and 82 is selected. When the carry-propagation adder 12 generates a state of ί: Ϊ: 4 = ϊ, the converter 16 calculates the first-and-by-pass ij4 output and the first pre-processed saturation value is selected. When the carry round out 42 generated by the two-pass propagator 12 has the second state, the conversion is saturated: the first sum is selected as the output of the multiplexer u and the second pre-processing option is selected. For example, the first sum represented by the ζ0 input may be a maximum of ^^ input, however, the second sum represented by the 00 input may be an input of 14. In the present invention, the msb output count of the multiplier product of the multiplexer u is used to calculate the preprocessing bit of the multiplier product (saturation flag). After the preflag is generated by the preprocessing stage 100,标 应用 处理 控制 平面 7 2。 Standard application processing control block 7 2. If the saturation flag has been set to 0,

4 5 4 14 4 V. Explanation of the invention (11) The pre-processing block 72 saturates the multiplier product by the above formula. However, this saturation is earlier than the traditional technique: what is to be interpreted is the ^^ change shown and explained here. Only i and various changes can be made by those who are familiar with the related technology without departing from the spirit and spirit of the present invention.

Page 18

Claims (1)

6. Scope of Patent Application 1. A method for multiplication includes the following steps: generating a partial product matrix, assuming that the array is the lowest, sometimes the simplified array has the highest product; assuming that the array is the lowest, sometimes, the simplified array has the highest product; The first 纰 simplified product is the array with the least effective side product. The second set of simplified products is the combination of the first set of sum flags and the combination of the second and second saturation flags; and When in the second state, ^ if the scope of patent application is • substantially the same as the choice 3. If the scope of patent application 'ΐί No this policy — & or the pigeons and flags of 1 which generate a pre-processed saturated flag Method, column; the carry output produced by the effect side has a partial product of the first state effect side to produce a first set of carry outputs produced by the dare side has a partial product of the second state effect side to produce a second group g When the carry output generated on the side has the first state, it is the simplified product of the most significant side of the array, and when the bit output has the second state, the column with the highest status is selected. The simplified product of the effective side; the product of the most significant bit number of the product to produce the first saturation "and the simplified product of the most significant bit number to produce the carry from the first side When the wheel has the first state, t and when the least significant side of the array produces Carry the loser to select the second saturation flag. Method 1 1 ^ where the step 2 of the selection flag is performed concurrently. A method 'where the combination step produces the H-th and simplified product. The most significant bit I Page 19 4 5 4 1 4 4 6. The scope of patent application 4. If the patent application covers the method of the first group or item, the step of the combination still includes the steps to determine the highest significant bit AND 5 of the simplified product of a = — * group For example, if you apply for a patent] and the most significant digit is 1. The method of item 1 of the effective bit side also includes simplifying the minimum array. 6. For example, the method of applying item 1 generated on the bit side of the output step I of applying for the production of anger, where the array has the highest The product of the simplified part of the effect: = The product is generated on the least significant bit side of the array. 7. If a patent application is applied, the method uses the simple 2 CU generated on the bit side, where the simplification generated by the array 歹 JL is the most efficient. The partial raid product is essentially the side with the least significant bit of the array 8.-Species are used in ΐϊίΠΓ. The method includes the following steps: a method for generating a pre-processed saturation flag, and generating a product array of partial parts; simplifying the hierarchical carry-in and burying 1, soil gg A, and the product to generate the first and last;: Π ::: The sum of the partial multiplications is based on the carry received by the least significant side of the train. The simplified partial product is combined to combine the first most significant bit of the simplified product with the sum flag and the second-saturated second-saturated flag is combined. ; And the number of the most significant bits of the product is saturated with the carry received by the least significant side of the array based on the production-generation basis. 9. If the method of the patent application for the fresh item% selects the saturation, the step of simplifying the product with the selection is essentially: At the same time: Choose. Steps of knowing 454144 VI. Application scope of patents _ I 0. If the application is applied to _ indicate whether the method of the 8th item is' in which the combination step produces a saturation flag of all 1 or the second set of simplified products The Most Significant Bit II · If applying for a true brake includes the method of the Λ or the perimeter, where the combination step is still and, the second most simplified bit of the most significant bit 12 is such as My sister * 疋 Should all the most significant bits be 1. Effective bit side? The method of the eighth round of the eighth part of the method also includes the step of simplifying the array-column minimum i3 such as _ towards the knife to produce a round of carry. The bit-side method of generating the 8th item, in which the product of the fraction of the product of the simplified part of the array with the highest i is generated as the least significant bit of the array < 刖 can be used. 1 4. If the simplified partial product 2b produced by the patent application is substantially the same as the least significant bit of the array _ side, the product of r .. 丨 knife 1 can be used at the same time. 15. —A kind of multiplier, including: The first circuit is used to simplify the most productive array of partial products. The product is clever: the _ carry state is related to: = The product is used to reduce the number of parts used to simplify the most significant side of the partial product array. A selector for selecting the first set of simplified products as the array 彳 when the recognition produced on the least significant side of the array has the first carry state, and the simplified product on the output side; and When there is a second carry state, the second set of simplified multiplications is selected as the simplified product of the effective side of the carry wheel; 21st poor 6. The scope of the patent claims that the processor 'is used to combine the first set of simplified fees. ^ There is a neodymium saturation flag and the second set of simplified registration counties: Valid: Yuan to generate the second saturation Flag; and the gated product has the two most: ^ Li: the carry round produced on the least effective side of the Γ train line out of the least effective side production 1: advance: a saturated flag; Saturation flag. When the wheel enters and exits with the second level, the multiplier of item 15 of the patent scope is selected, and the second selection ^ saturation flag is essentially a simplified product of the first selector selection. It is the multiplier of item 15 of the same device, wherein the pre-processing effect bit is entered into Qiu & the first or second group of simplified products has the highest saturation flag with a king of 1. The device asks for the multiplication steaming of item 17 of the patent scope, where the pre-processed product I 2 2 AN1) gate is used to combine the first or second group of simplified multiplication i. U 冋 significant bits to determine whether the most significant bits are all 19. A multiplier includes: multiplying #i less one circuit for simplifying a part of the hierarchical carry selection adder ΐ t ί 2 of the most significant side Part "product to produce the first and second-group" ί “ί", which is used to select the sum of the simplified partial products according to the carry received by the least significant side of the array; a pre-processor is used to combine the most significant bits of the first group of simplified products 454 彳 44 VI. Application for Patent Scope _ Yuan to generate 坌 effective number of digits to produce 7 main soil 饱和 saturation flag; and ^ §? Gp saturation flag product 'based on the carry selection received by the least significant side of the array The multiplier of item 19 of the patent scope 'wherein the second alternative time. The sum flag is essentially a simplified multiplication product of the first selector selection and the multiplier of item 19 of the patent scope of the same patent application, wherein the preprocessing ° _: Does not mean that the most significant bit of the simplified product of the first group or the second group is a saturation flag which is all 1. 2 2. As in the multiplier of the 21st scope of the patent application, the preprocessingThe device includes an f-AND gate for combining the most significant bits of the first group or the second group of simplified products to determine whether the most significant bits are all 1 ° 23. A kind of integrated electric bee, including: A multiplier, the multiplier further comprising: a first circuit for simplifying a partial product of the most significant side of the partial product array side to generate a first set of simplified products related to a first carry state; a second circuit 'for simplifying the partial product Product of the most significant side part of the array side to generate a second set of simplified products related to the second carry state; a first selector for selecting the first when the carry output produced by the least significant side of the array has the first carry state The set of simplified products is the simplified product of the most effective side of the array; and when the carry output produced by the least significant side of the array has the second carry state, it is used to select the second group of simplified products- 4 5 4 1 4 4 Patent application scope High effective side simplified product pre-processor 'used to combine _ 篦 a group _ _ + number of bits to produce the first full deduction 旒 擗 0x' 4 The product has the most significant effective number of significant digits to produce the second Saturation flag; and-the system product is issued in the most round. 选择: Selector 'is used to select the "full house" carry when the lowest effective side of the array is produced. ^ Quasi-flag, and when the carry output used to select the second full saturation has the second carry state: Yu I! Miru integrated circuit of item 23 of the scope of patent application, of which the Dengxixi flag is Xiao Zhi supposes that the saturation of the choice has = Mu 2 5 as the arithmetic logic unit of the f-saturation arithmetic logic unit pre-processor. The way is to count the product circuit of the 23rd item, where the product is two digits. No. processor (DSP), where the integrated circuit is included in the integrated circuit, and the integrated circuit is included in the integrated circuit 2 6 · If the integrated circuit circuit of item 23 of the patent application is a microprocessor. 27, if applied The integrated circuit of item 23 of the patent scope is a micro control 2. 8. The product of patent application range of the second three-way circuits is electrically integrated a particular application ^ jC).