JP2000222172A - Method and device for reducing delay in generation of saturation flag of alu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve delay as to the generation of a flag as a substitute for an increasing area by selecting a specific saturation flag according to a carrier received from a lower-order side of an array. SOLUTION: Preprocessing saturating operation is carried out once high-order bits are obtained. Blocks 80 and 82 of a preprocessing means 100 decide whether or not a predetermined number of high-order bits all equal '1'. The 1st block 80 preprocesses the MSB relating to a 1st sum (Z(i)) which has been calculated by a converter 16 and the 2nd block 82 preprocesses the MSB relating to a 2nd sum (0(i)) which has been calculated by the converter 16. At the time of execution, the blocks 80 and 82 AND a predetermined number of the MSBs to decide whether all the MSBs have a value of logic 1. A multiplexer 14" selects one of two logical states for each preprocessed MSB bit which is generated by the blocks 80 and 82 as a select signal 42 is generated by a carry transmission adder 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data arithmetic unit (DAU) of a digital signal processor or another microprocessor, and more particularly to a digital arithmetic processor (DAU) for generating a saturation flag which is preprocessed in a data arithmetic unit (DAU) of a microprocessor. Method and apparatus for reducing delay.

[0002]

2. Description of the Related Art A data operation unit (DAU) is a main calculation execution unit of a digital signal processor (DSP). One of the tasks supported by the DAU is multiplication. A multiplier is a dedicated circuit in a microprocessor or digital signal processor used to obtain the product of a multiplicand and a multiplier.
In a typical multiplier, the partial product multiplies the binary representation of the multiplicand, eg, the binary number, two's complement or one's complement form, by a binary representation of the multiplier to form a two-dimensional array of partial products. It is formed by this. This partial product is reduced to obtain a binary representation of the product.

[0003] Partial products can be reduced in any of several known ways. For the least significant bit (LSB) of the multiplicand and multiplier on the right, the product LS
B is also on the right. The traditional method of converting partial products is
Start from the right and proceed to the left (right to left,
Or LSB first), and the carry is shifted or transmitted to the left. The operation of converting the partial product and the carry transmission are repeated.

In a typical right-to-left carry-save multiplier, the partial products are scaled starting from the top of the array of partial products and proceeding toward the bottom of the array. The least significant part of the last partial product term occurs in binary form, while the most significant part occurs in carry-save form.
The most significant bits arrive at the same time. The carry transfer adder is used to convert the most significant part of the last partial product term to a binary form and terminate the multiplication operation.

After the multiplication cycle, the products are typically loaded into registers and pre-processed before the resulting products are provided to an arithmetic unit (ALU) or adder.
The net pre-processing performed on the resulting product is vendor specific, but in general, the pre-processing work involves saturating or shifting the product by k bits to the right or left. Including. During the preprocessing stage, some of the most significant bits of the resulting product are used to generate a preprocessing control signal. For example, if the three most significant bits in the resulting product of 32 bits are all logical ones, the saturating preprocessing operation sets the value of the 29 least significant bits to zero in a known manner.
The pre-processing operation starts and ends after the multiplication result is selected and obtained and loaded into the load register.
Alternatively, a four-stage delay is introduced. The delay introduced in calculating the pre-processing flag is said to be on the DAU's critical path.

[0006] RK Kolagotla, incorporated herein by reference.
et al., “VLSI Implementation ofa 2000-MHz 16x16 L
eft-to-Right Carry-Free Multiplier in 0.35 μm CMO
S Technology for Next-Generation DSP, "IEEE 1997 Cu
stom Integrated Circuits Conf., 469-72 (May 1997) provides partial products in a way that the upper bits are available earlier than known multipliers, thereby reducing the time required to complete the multiplication A multiplier is disclosed.
As is evident from the above-mentioned disadvantages of the conventional method for obtaining the preprocessing flag, as soon as the upper bits are available,
The preprocessing flag needs to be evaluated.

[0007]

SUMMARY OF THE INVENTION Generally, a method and apparatus for generating a preprocessed saturation flag in a multiplier is disclosed. According to one aspect of the invention, the pre-processed saturation flag occurs substantially simultaneously with the selection of a reduced product of the upper side of the array of partial products.

[0008] Conventional multipliers generate arrays of partial products. The partial products are scaled on the upper side of the array assuming carry-out from the lower side of the array to take a first state to generate a first set of scaled products. Also, the partial products are scaled on the upper side of the array assuming carry-out from the lower side of the array to take a second state to generate a second set of scaled products. Both sets of reduced partial products occur in parallel with carry-out from the bottom side. The first set of reduced products is selected as the reduced product of the upper side of the array when the carry out from the lower side of the array assumes the first state. The second set of scaled products is selected as the scaled product of the upper side of the array when the carry out from the lower side of the array assumes a second state.

To generate a preprocessed saturation flag, some of the most significant bits of the first set of scaled products are combined to generate a first saturation flag and generate the scaled product. Some of the most significant bits of the second set are combined to generate a second saturation flag. The particular saturation flag is selected based on the carry received from the lower side of the array. The saturation flag is effectively
Selected at the same time as the reduced product selection, each based on the carry received from the lower side of the array.

The present invention allows the flags to be preprocessed early in the multiplication cycle, thereby improving the delay in generating the flags at the expense of increasing area. The disclosed algorithm for precomputing the saturation flag reduces the three to four delay stages of the flag generation logic when the multiplier product is selected for ALU preprocessing by the load register.

A more complete understanding of the present invention, as well as other features and advantages of the present invention, will be obtained by reference to the following detailed description and drawings.

[0012]

FIG. 1 is a schematic diagram of one embodiment of a conventional multiplier 10 that can be part of an integrated circuit (IC). The multiplier 10 includes, for example, a digital signal processor (DSP), a microcontroller, a microprocessor, an application-specified integrated circuit (ASI).
C) or may be part of a data processing unit in another integrated circuit. The multiplier 10 includes a carry transfer adder 12, a multiplexer 14, a converter 16,
It comprises adders 18 and 19. As shown in FIG. 2, adder 18 has inputs 20 and outputs 22 and is interconnected in an array 24. Here, an output from one adder 18 is an input to another adder 18. The multiplier 10 generates a partial product term in FIG.
It is shown to add, thus calculating the product of the n-bit multiplier and the n-bit multiplicand. As is known in the art, the product of an n-bit multiplier and an n-bit multiplicand is a product having 2n bits.

The adders 18 are arranged in a matrix and can be full adders, as is known in the art. As shown in FIG. 2, adder 18 may, as is known in the art, provide the next output 20, namely, (i) the sum output from adder 18 (if present) on the same row. When,
(Ii) receive the carry output of the next lower row and (iii) the underlying partial product bit. Each adder 18 has a dashed line 3
Except for adder 19 between 0 and 32, it adds the partial product to the incoming sum and carry-out signal. Adder 18
Adds the sum output, the carry output, and the partial product bit to form the following output: the sum bit and the carry out bit transmitted through the array 24 of adders 18, 19, as shown in FIG. Occurs. Adder 18,
The upper bit side 28 of the array 24 of 19 is on the left side of FIG. 1, while the lower bit side 26 of the array 24 of adders 18 and 19 is on the right side of FIG. The entire conversion array is not shown.

Carry transfer adder 12 receives the partial sum and carry out signals from the bottom row of adder 18 on lower side 26 of array 24. Carry transmission adder 12
Produces a multi-bit output 40 and one or more carry-out bits 42. In this embodiment, the multi-bit 40 includes (n + 1) bits, and the carry-out bit 42 is one bit. Carry-out 42 provides a selection signal to multiplexer 14 to control the selection of the multiplexer 14 output, as described further below.

The adder 19 between the dashed lines 30 and 32 interfaces the converter 16 with the adder 18 in the array 24. The adder 19 does not add the partial product bits. Adder 19 adds the three bits from array 24 together and generates two outputs to converter 16.

The converter 16 is composed of two types of cells designated by A and B. FIG. 3 is a schematic diagram of an A cell, showing inputs S (sum) and C (carry), and outputs A, G, ZO, and OO as a logical combination of inputs. An expression showing how the inputs are logically combined to form the output is shown on the right side of FIG.

As shown in FIG. 1, each A cell has:
The carry input is received from the adder 19 between the broken lines 30 and 32 in the same column. Each A cell has a dashed line 30 in the same row.
And 32 from the adder 18. The conversion of the upper bits is such that A and B are such that the input to multiplexer 14 is available either prior to or simultaneously with carry out 42 of carry transfer adder 12.
Is achieved in Thus, sum 44 is available as an output from multiplexer 14 after one multiplexer delay when carry-out 42 from carry transfer adder 12 is available.

FIG. 4 is a schematic diagram of the B cell of FIG. 1 showing inputs Z1 and O1 (received from the outputs ZO and OO of the A cell in the same row) and A and G received from the A cell in the same column. Show. A representation showing how the inputs are logically combined to form the output at each B cell is shown on the side of FIG.

The A and B cells calculate and maintain two forms of the sum of the most significant bits of the product, ie, the reduced product, based on the logical relationship between the inputs and outputs and the interconnect architecture. Converter 16 calculates the sum or reduced product of the most significant bits assuming that carry out 42 from carry transfer adder 12 is in a first logic state, eg, zero. Converter 16 also calculates the sum or reduced product of the most significant bits assuming that carry out 42 from carry transfer adder 12 is at a second logic state, eg, one. The outputs of the bottom columns of A and B cells provide the two sums as inputs to multiplexer 14. One of the sums is represented by the ZO output, and the second sum is represented by the OO output.

Carry transfer adder 12 finishes the calculation,
When the carry-out 42 is available, the correct one of the two sums calculated by converter 16, or the converted seat, is selected by multiplexer 14. If the carry out 42 from carry transfer adder 12 assumes the first state, the first sum calculated by converter 16 is selected as the output of multiplexer 14. Carry out 42 from carry transfer adder 12
In the case of the state of
Is selected as the output of the multiplexer 14.
The first sum is represented, for example, by the OO input to multiplexer 14.

In this embodiment, the multiplexer 14 is
(N-1) The output 44 is supplied and the carry transfer adder 12
Become 2n bits of the product together (n + 1)
An output 40 is provided. Output 4 from multiplexer 14
4 is the most significant bit of the product, carry transfer adder 1
The output 42 from 2 is the least significant bit of the product. 1 is
It is converted between the broken lines 30 and 32 in FIG. Thus, the number of bit outputs from carry transfer adder 12 is one greater than the number of bit outputs from multiplexer 14. The number A is the log ₂ of the radix.

The exact boundary between the lower side of array 26 and the upper side of array 26 may vary depending on the number of bits in the multiplier and the multiplicand.

FIG. 5 shows a schematic diagram of a converter multiplier 10 'for a radix-4 multiplier. The five components in the figure that provide the same functions as the components in the radix-2 embodiment of FIG.
The same reference numerals and primes are used. In a radix-4 converter, two bits occur in each D cell when compared to one bit that occurs in the A cell for the radix-2 multiplier of FIG. Output 4 from carry transfer adder 12 '
The number of bit outputs as 0's is indicated by dashed lines 30 'and 32'
Multiplexer 1 due to the two bits being converted between
It is two larger than the number of bits from 4 '. The logic performed on the D cells is shown in FIG. Type A of FIG.
The cell is replaced by the type D cell of FIG. 5 due to the radix-4 radix. Although the present invention is illustrated in FIG. 1 with a radix-2 embodiment and in FIG. 5 with a radix-4 embodiment, the invention is not so limited, as will be apparent to those skilled in the art.

The multipliers 10, 10 'in FIGS. 1 and 5
It can be manufactured using well-known VLSI processing on one or more integrated circuits. The present invention is particularly useful in communication systems and equipment using integrated circuits that include this technology. Such communication systems and equipment include:
This has the advantage that the speed of performing signal processing is increased. Multipliers 10, 10 'provide partial products so that the high order bits are available earlier than known multipliers, thereby reducing the time required to complete the multiplication. The present invention is useful with many reduction schemes, multiplier types, and radixes. Any radix-2 multiplier, such as a Baugh-Wooley-Blankenship coded two's complement multiplier, or a Booth-MacSorley multiplier, or higher radix multiplication Can be used with any of the vessels.

Detection of preprocessing flag In FIG. 7, the multipliers 10 and 10 'of FIGS. 1 and 5 are used.
Is decomposed into a multiplier array 24, a converter 16, a final multiplexer stage 14, and a carry transfer adder 12. The components in FIG. 7 that provide the same functions as the components in the radix-2 embodiment of FIG. 1 or the radix-4 embodiment of FIG.
Indicated by the same reference numerals. As shown in FIG.
The resulting product generated by multiplier 10 is input to load register 70. Next, the pre-processing control block 72
Receives a predetermined number of the most significant bits from the resulting product from the register 70 and performs clocked selection to perform different preprocessing operations such as saturating or shifting left / right by k bits only. Generate a signal. The present invention relates to a saturating pretreatment operation.

As previously indicated, saturating preprocessing evaluates some of the most significant bits of the resulting product and, if a saturating condition exists, causes the resulting product to saturate. For example, a saturating state may require the most significant bit to have a logic one value. If a saturating condition exists, saturating pre-processing saturates the resulting product, for example, by setting the remaining lower bits to logic zero. The important delay paths of the multiplication cycle in FIG. 7 are as follows. That is, carry transfer adder 1
Loading the select signal generated at 2, the final multiplexer stage 14, the multiplier final product into the load register 70, and evaluating the MSB for the pre-processing control block 72. Thus, the important delay path is the three to four delay stages of the flag generation logic when the multiplier product is selected for ALU preprocessing via the load register 70.

According to a feature of the present invention, the preprocessing saturating operation is performed as soon as the upper bits are available. As indicated earlier, the conversion of the upper bits is performed by the converters 16 and 17 in the A and B cells such that the input of the multiplexer 14 is available either prior to or simultaneously with the carry out 42 of the carry transfer adder 12. Achieved at 16 '. Thus, sum 44
Is the carry out 42 from carry transfer adder 12
Are available as an output from multiplexer 14 after one available multiplexer delay.

FIG. 8 shows a multiplier 10 with a pre-processing stage 100 according to the invention. The preprocessing stage 100 calculates the multiplier product M
A pair of blocks 80 and 8 for preprocessing the SB bit
2 inclusive. In essence, blocks 80 and 82 determine whether a predetermined number of upper bits are all equal to one. A first block 80 pre-processes the MSB associated with the first sum (Z (i)) calculated by converter 16;
The second block 82 pre-processes the MSB associated with the second sum (O (i)) calculated by the converter 16. At run time, each block 80, 82 has a predetermined number of M
An AND of SB is determined to determine whether all MSBs have a logical 1 value. Multiplexer 14 "operates in the same manner as multiplexer 14 of FIG. 1 and multiplexer 14 'of FIG. 5, with the same select signal 42 being generated by carry transfer adder 12 and of the pre-processed MSB bits generated at blocks 80 and 82. Select one of two logic states for each.

When the carry-out adder 12 has finished the calculation and the carry-out value 42 is available, the correct one of the two sums, ie, the reduced product, calculated by the converter 16 is passed to the multiplexer 14. Selected. In addition, the correct one of the preprocessed values occurring in blocks 80 and 82 is selected. Carry transmission adder 1
2 takes the first state, the first sum calculated by converter 16 is applied to multiplexer 1
4 and the first preprocessed saturate value is selected. If the carry out from carry transfer adder 12 assumes the second state, converter 16
Is selected as the output of the multiplexer 14, and a second preprocessed saturating value is selected. The first sum can be represented, for example, by the input ZO to the multiplexer 14, and the sum of the large two can be represented, for example, by the input OO to the multiplexer 14.

Therefore, the present invention provides a multiplexer 1
4 is used to calculate the preprocessed MSB bits of the multiplier product in parallel with the calculation of the output of the MSB bits of the multiplier product. After the saturating flag is generated in the preprocessing stage 100, the flag is provided to the preprocessing control block 72. If the saturating flag is set to 0, the pre-processing control block 72 saturates the multiplier product like magic. However, the saturating flag occurs three or four delay stages earlier than in the prior art.

It is understood that the embodiments and variations shown and described herein are merely illustrative of the present invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention. It should be.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a conventional radix-2 multiplier for generating and adding partial product terms and calculating a product of a multiplier and a multiplicand.

FIG. 2 is a schematic diagram illustrating the adder of FIG. 1;

FIG. 3 is a schematic diagram showing an A cell of FIG. 1;

FIG. 4 is a schematic diagram showing a B cell of FIG. 1;

FIG. 5 is a schematic diagram illustrating a conventional radix-4 multiplier for generating and adding partial product terms and calculating a product of a multiplier and a multiplicand.

FIG. 6 is a schematic diagram showing the D cell of FIG. 1;

FIG. 7 is a schematic diagram showing the conventional multiplier of FIG. 1 or 5 and a conventional preprocessing control block that generates different preprocessing operations.

FIG. 8 is a schematic diagram showing the conventional multiplier of FIG. 1 or 5 and a pre-processing control block for performing pre-processing saturation work in accordance with the present invention.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Alexander Goldbusky United States 19115 Pennsylvania, Philadelphia, Jamison Avenue 9346 A

Claims (28)

[Claims] 1. A method for generating a pre-processed saturation flag in a multiplier, the method comprising: generating an array of partial products; and generating a first set of reduced products. Converting the partial product on the upper side of the array assuming a carry-out from the bottom side of the array as taking a state; and generating a second set of converted products by: Converting the partial product on the upper side of the array assuming a carry-out from the bottom side of the array as taking the state of 2; If the carry-out from the least significant side of the array takes the first state, select the first set of converted products and Selecting the second set of reduced products if the carry-out assumes a second state; and combining some most significant bits of the first set of reduced products to a first Generating a second saturation flag and combining the most significant bits of the second set of reduced products to generate a second saturation flag; and carrying from the least significant side of the array. When the out takes the first state, the first saturation flag is selected, and when the carry out from the least significant side of the array takes the second state, the second saturation flag is selected. A method consisting of steps. 2. The method of claim 1, wherein the step of selecting a saturation flag is performed substantially simultaneously with the step of selecting the reduced product. 3. The method of claim 1, wherein the combining step generates a saturation flag indicating whether the most significant bits of the first or second set of reduced products are all ones. Method. 4. The method of claim 3, wherein the step of combining further comprises: ANDing the most significant bit of the first or second set of reduced products;
Determining whether the most significant bits are all ones. 5. The method of claim 1, further comprising:
Converting a partial product on the lower side of the array to produce a carry-out. 6. The method of claim 1, wherein the reduced partial product from the upper side of the array is available prior to the reduced product from the lower side of the array. 7. The method of claim 1, wherein the reduced partial product from the upper side of the array is obtained substantially simultaneously with the reduced partial product from the lower side of the array. 8. A method for generating a preprocessed saturation flag in a multiplier, comprising: generating an array of partial products; and converting a partial product on the upper side of the array in a hierarchical carry select adder. And the first and second
Generating a set of reduced products; selecting a sum of reduced partial products based on the carry received from the least significant side of the array; and selecting some of the tops of the first set of reduced products. Combining the bits to generate a first saturation flag and combining some of the most significant bits of the second set of reduced products to generate a second saturation flag; Selecting a saturation flag based on the carry received from the bottom side of the array. 9. The method of claim 8, wherein the step of selecting the saturation flag is performed substantially simultaneously with the step of selecting the converted product. 10. The method of claim 8, wherein the step of combining comprises the first or second of the reduced products.
Generating a saturation flag indicating whether the most significant bits of the set are all ones. 11. The method according to claim 10, wherein said combining step further comprises the step of:
Or, ANDing the most significant bits of a second set to determine if the most significant bits are all ones. 12. The method of claim 8, further comprising: converting a partial product on a lower side of the array to:
A method comprising the step of generating a carry-out. 13. The method of claim 8, wherein the reduced partial product from the upper side of the array is obtained prior to the reduced partial product from the lower side of the array. 14. The method of claim 8, wherein the reduced partial product from the upper side of the array is obtained substantially simultaneously with the reduced partial product from the lower side of the array. 15. A first circuit for converting a partial product on an upper side of the partial product array to generate a first set of reduced products associated with a first carry state; A second circuit for converting the partial product on the upper side to generate a second set of converted products associated with a second carry state; and as a converted product on the upper side of the array, When the carry-out from the bottom side of the array takes the first carry state, the converted first set is selected, and the carry-out from the bottom side of the array takes the second carry state. If so, a first selector for selecting the converted second set, and some most significant bits of the first set of the converted product are combined to generate a first saturation flag. , A preprocessor for combining some of the most significant bits of the second set of computed products to generate a second saturation flag; and a carry-out from the least significant side of the array taking a first state. And a second selector for selecting the first saturation flag if the carry-out from the least significant side of the array takes the second state. . 16. The multiplier according to claim 15, wherein said second selector selects a saturation flag at substantially the same time as said first selector selects said converted seat. vessel. 17. The multiplier according to claim 15, wherein the preprocessing unit generates a saturation flag indicating whether all the most significant bits of the first or second set of the converted products are all 1s. Multiplier. 18. The multiplier of claim 17, wherein the pre-processing unit combines the most significant bits of a first or second set of the converted products so that the most significant bits are all ones. A multiplier including one or more AND gates for determining whether 19. At least one circuit for converting a partial product on the upper side of the partial product array in the hierarchical carry select adder to generate first and second sets of the converted products; Combining a number of the most significant bits of the first set of converted products based on the carry received from the least significant side and selecting a sum of the converted products; A pre-processor for generating a flag, combining some of the most significant bits of the second set of reduced products to generate a second saturation flag, and a carry received from the least significant side of the array. And a selector for selecting a saturation flag based on the multiplier. 20. The multiplier according to claim 19, wherein said second selector selects a saturation flag substantially simultaneously with said first selector selecting a converted product. . 21. The multiplier according to claim 19, wherein said preprocessing unit generates a saturation flag indicating whether all of said first or second set of converted products are all ones. 22. The multiplier of claim 21, wherein the pre-processing unit combines the most significant bits of a first or second set of prescaled products so that the most significant bits are all A multiplier that includes one or more AND gates that determine whether they are 1 or not. 23. An integrated circuit including a multiplier, the multiplier further converting a partial product on an upper side of a partial product array to generate a reduced product of a reduced product associated with a first carry state. A first circuit for generating a set of ones, and a second circuit for converting a partial product on an upper side of the partial product array to generate a second set of reduced products associated with a second carry state. And if the carry-out from the bottom side of the array takes the first carry state, as the converted product of the upper side of the array, select a first set of the converted products; A first selector for selecting a second set of the converted products, wherein the carry-out from the least significant side of the array assumes the second carry state; Some of the top of the set A pre-processor for combining the bits to generate a first saturation flag and for combining some most significant bits of the second set of the reduced products to generate a second saturation flag; When the carry-out from the bottom side of the array takes the first state, the first saturation flag is selected. When the carry-out from the bottom side of the array takes the second state, An integrated circuit comprising: a second selection unit that selects the second saturation flag. 24. The integrated circuit according to claim 23,
An integrated circuit, wherein the selected saturation flag is supplied to a pre-operation processing unit, and the pre-operation processing unit saturates an output of the multiplier when the selected saturation flag has a predetermined value. 25. The integrated circuit according to claim 23,
An integrated circuit that is a digital signal processor (DSP). 26. The integrated circuit according to claim 23, wherein
An integrated circuit that is a microprocessor. 27. The integrated circuit according to claim 23,
An integrated circuit that is a microcontroller. 28. The integrated circuit according to claim 23, wherein
An integrated circuit that is an application specified integrated circuit.