4 53 04 經濟部令央標準局員工消費合作杜印製 Λ7 B7 五、發明説明(I ) 本發明係有關一種多位元逐次比較型類比數位轉換器, 用以將類比k號轉換成Β(Β=ΜχΝ)位元的數位輸出碼,其 頻率範圍的使用大大提高,可提高到數MHz以上,可利用 到視訊(Video)之領域中,使傳統的逐次比較型類比數位轉 換器無法達成之頻率範圍能夠改善,使其應用範圍擴大於 更多領域。 以往,在傳统的逖次比較型類比數位轉換器,其係 單位元(Bit) ’依每個位元,逐次單一去比較,因此其 轉換速度受到限制,轉換速度僅能敗到數十KHZ至數百 KHZ之内·應用在(AUDIO)領域,若要應用在(VIDEO )領域•則無法達成,因其利用單位无比較轉換之忮街 使得轉換速率無法提高。 有錨於習見之類比數位轉換器有上迷块點,發明人 乃研究改進之道,终於完成本發明。 因此,本發明之主要目的在提供一種可提髙轉換速 牟*尤其在视訊領域之應用之多位无逐次比較型類比數 位轉換器。 本發明之另一目的在提供一種多用途及提高轉換速 牟*捋應用程度提升至VIDEO之應用絶困•而且解析度_ 並不會因而降低。4 53 04 Consumption cooperation by the staff of the Central Standards Bureau of the Ministry of Economic Affairs, printed by Λ7 B7 V. Description of the invention (I) The present invention relates to a multi-bit successive comparison analog digital converter, which is used to convert the analog k number into Β ( Β = ΜχΝ) bit digital output code, the use of its frequency range has been greatly improved, can be increased to more than a few MHz, can be used in the field of video (Video), making the traditional successive comparison analog digital converter unable to achieve The frequency range can be improved to expand its application range to more fields. In the past, in the traditional digital comparison type analog digital converter, the unit bit (Bit) is compared one by one according to each bit, so its conversion speed is limited, and the conversion speed can only be defeated to tens of KHZ to Within hundreds of KHZ, it is applied in the (AUDIO) field. If it is applied in the (VIDEO) field, it cannot be achieved. Because it uses a unit without comparison conversion, the conversion rate cannot be increased. The analog digital converter anchored in the conventional analogy has some fascinating points. The inventor studied the improvement and finally completed the present invention. Therefore, the main object of the present invention is to provide a multi-bit non-successive comparison type analog-to-digital converter which can improve the conversion speed, especially in the video field application. Another object of the present invention is to provide a multi-purpose and improve the conversion speed. The application level is improved to VIDEO. The resolution is not reduced.
爲達上迷之目的,主要利用數個比較器使得該多位 元逐次比較型類比數位轉換器在單一時脈可產生數個位 无(Bit),降低其轉換所需的時腺遇期(clock cycle ),則可改變其轉换速度,使得轉換的頻率提高到數MHZ -2 - 本紙張尺度適用中國國家標準(CNS ) Λ4規洛(297公釐) ----1丨^---裝-------訂------A. (諳先閱讀背面之注意事項再填寫本頁) 4 53 0 A7 B7 五、發明説明(>) *其比較器仍保有逐次比較的架構,包括:輸入取樣裝 置(I/P sample) *数位頦比轉換預夏狀慜(DA predict )及數位類比轉換決定装置(DA decision)三種不同狀 Λ,以反映輸入机號(V IN)的數位瑪,同時比較器利用 電容耦合技巧可將該多位无迻次比較型類比數位轉換器 的解析度延伸。另外,在副數位類比轉換器(SUB-DAC) 與比較器輸入端電容的棑列,可透過利用其不同比例, 使剎數位類比轉換器(SIIB-DAC)與另外之主DAC所使用 之参考t壓不至相差欠大。 至於本發明之_細構速、應Λ原理、作用與功效, 則参照下列藺式及所作之説明即能了解。 圖式: 第一圇爲本發明之方塊圖。 (請先閱讀背面之注意事項再填寫本I) ,裝. 經濟部中央標準局負工消費合作社印製 11 數位類比轉換器1, 提供参考電壓机號 -,DACli(i=l,2,..2 -1)及DAC1X 12 數位類比轉換器2 * 提供参考電壓机號 * DAC2i(i=l,2,..2 -1)及DAC2X 13 數位類比轉換器j, 浞供本考電壓机號 ,DACji(i=l,2,·.2 -1)及DACjX 1 4 數位類比轉換器N, 提供本考電壓紙號 ,DACNi (i = l,2,·.2 -1)及DACNX 15 比較器 16 溫度尺瑪解碟器 17 輸出瑪資料纪綠装置 -3 - 本纸浓尺度適用中國國家.樣毕(CNS ) Λ4規格(2丨0Χ297公釐) 經濟部中央標準局工消资合作社印製 4 5 3 1; A7 B7 五、發明説明(>) 第二I爲本發明之時序®。 弟三®爲本發明9位元(Bits)试號處理之實施例 0 第四®爲本發明9位无(Bits)實施之時序圖。 第五豳爲本發明9位无(Bits)賞施例勤作時之期 係躕。 第六豳爲本發明實施例之電路躕之5-1。 第七圖爲本發明實施例之笼路圈之5-2。 第八躕爲本發明實施例之電勞圉之。 第九®爲本發明實施例之電路®之5-4。 第十I爲本發明實施例之電路圈之5-5。 請秦閲第一躕所示,其係爲本發明之方瑰® *其扒 號由不同之類比钒號由數位類比轉換器1(11)、数 位颠比轉換器2 ( 1 2)、..、數位類比轉換器j ( 1 3)、..、數位類比轉換器N (14) ·將此類比机號 送至比較器之一端,籍著數锢比較器(15),捋比較 器(15)之钒號輸出送到溫度尺瑪解瑪器(16),經 該解瑪器解瑪後送出Μ位无(Bits)之位址讯號•提供 給輸出資料纪錄装置(17),待所有轉換完成後,將 完成钒號資料送出。 春閲第二圖所示爲本發明之時序與各電客取樣電赓 之相對鼷,包括各電容取樣電壓(VI *V2 * · * , Vj ,·. *VN)及時脈產生器,及資料輸出記綠裝 置之拭號波形•首先,在時脈(CLOCK) 之紙號第一個 -4 - 本紙張尺度適用中國國家榇準(CNS > Μ規格(210X 297公釐) ΙΊ-^-- (請先閲讀背面之注意事項再填寫本頁) 、-5In order to achieve the goal of obsession, several comparators are mainly used to make the multi-bit successive comparison type analog digital converter can generate several bits in a single clock, reducing the time required for conversion ( clock cycle), the conversion speed can be changed so that the frequency of conversion can be increased to several MHZ -2-This paper size applies the Chinese National Standard (CNS) Λ4 gauge Luo (297 mm) ---- 1 丨 ^ --- Install ------- Order ------ A. (谙 Please read the notes on the back before filling in this page) 4 53 0 A7 B7 V. Description of the invention (>) * The comparator is still kept one by one The comparison architecture includes: input sampling device (I / P sample) * digital prediction conversion (DA predict) and digital analog conversion decision device (DA decision) three different shapes Λ to reflect the input machine number (V In), the comparator uses the capacitive coupling technique to extend the resolution of the multi-bit non-shifting comparison analog digital converter. In addition, in the queue of the sub-digital analog converter (SUB-DAC) and the input capacitance of the comparator, it can use the different ratios to make the reference of the digital-to-brake analog converter (SIIB-DAC) and the other main DAC. t pressure is not too large. As for the fine structure speed, the principle of application, the function and the effect of the present invention, it can be understood by referring to the following formula and the description made. Schematic: The first block diagram is a block diagram of the present invention. (Please read the precautions on the back before filling in this I), and install. Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives, 11 Digital Analog Converter 1, providing the reference voltage machine number-, DACli (i = l, 2 ,. .2 -1) and DAC1X 12 digital analog converter 2 * Provide reference voltage machine number * DAC2i (i = l, 2, .. 2 -1) and DAC2X 13 digital analog converter j, , DACji (i = l, 2, · .2 -1) and DACjX 1 4 digital analog converter N, provide the paper number for this test, DACNi (i = 1,2, · .2 -1) and DACNX 15 comparison Device 16 temperature ruler and disc solver 17 output device information green device-3-The paper is thick and scale applicable to China. Sample complete (CNS) Λ4 specification (2 丨 0 × 297 mm) Printed by the Industrial Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs System 4 5 3 1; A7 B7 V. Explanation of the invention (>) The second I is the time sequence of the invention. Di San® is an example of the 9-bits test number processing of the present invention. 0 Fourth is a timing diagram of the 9-bits-free implementation of the present invention. Fifth stage is the period when the 9-bit rewards example of the present invention is performed. The sixth embodiment is the circuit 5-1 of the embodiment of the present invention. The seventh figure is 5-2 of the cage circuit of the embodiment of the present invention. The eighth aspect is the electrical labor of the embodiment of the present invention. The ninth ® is 5-4 of the circuit ® of the embodiment of the present invention. The tenth I is 5-5 of the circuit circle of the embodiment of the present invention. Please refer to Qin Yi's first note, which is the square rose of the present invention. * The number of the vanadium is different from the analog. The vanadium number is changed by the digital analog converter 1 (11), the digital inversion converter 2 (1 2),. ., Digital analog converter j (1 3), .., digital analog converter N (14) · Send the analog machine number to one end of the comparator, with the digital comparator (15), the comparator (15 The output of the vanadium number is sent to the temperature ruler and demagnetizer (16). After the demagnetizer demagnetizes, it sends out the M bit address signal. • Provide it to the output data recording device (17). After the conversion is complete, the completed vanadium data will be sent out. The second diagram of Spring Reading shows the relative timing of the present invention and the sampling voltage of each electric guest, including the sampling voltage of each capacitor (VI * V2 * · *, Vj, ·. * VN) and clock generator, and data Output the swipe waveform of the green recording device. • First, the paper number of the clock (CLOCK) is the first -4-This paper size applies to China National Standards (CNS > Μ specifications (210X 297 mm) ΙΊ-^- -(Please read the notes on the back before filling this page), -5
4 5 3 C 經濟部t央標準局員工消费合作社印製 A7 B7 五、發明説明(4 ). 遇期時之前半週時(即®中的A時段)*各個比較器的 VI均在取樣狀態,V2爲一直流秦考電壓(Vr-) * Vj及VH亦同,在後半逋時(即®中的B時段)*V1 在預置狀態(predict),此時各比較器的预置電壓各 爲DACli(i=1..2M-l),當钒號第二個遥期時(即囿中 的C時段),各比較器的VI電壓剷均爲DAC1X ,V2 在报置狀態其各別電壓分別爲DAC2i(i=1..2M-l ) *而輸 出資料纪錄装置(17 )此時捋第一组MSB資料送出, 在前半遇送出資料1 (C時徙)_,後半遇返出資料2 ( D時段),依次類推,至第(N+2)/2個週期送出第N組資料 *共计K個位元組資料完成轉換。 参閲第三圖、第四躕爲本發明9位无(Bits) 訊號 處理之實施例及時序圖。 参閲第五躕,爲本發明勤作時之關係®,例如每次 比出三個位元,共循環三次,該ADC總位元數爲9位元, 使用7個比較器時,即M=3*比較器的數目舆位元數有下 列的關係:比較器數目為2M-1 (M:位元數),若使用2M-1個 比較器(3 1)’而每個比較器使用n個電容所組成的排列, 則本發明之總位元數為MxN ’而所需要的時脈數目為限 (N+2)/2 ’因此若使用時脈數之執行週期數降低,使用較多 之比較器’而較少的電容排列,即可達成本發明之目的, 而提兩使用之頻率範圍達到數MHz以上,可完全應用在 視頻(VIDEO)之領域裡。 ; 裝-------訂--------線 (請先閱讀背面之注意事項再填寫本頁〕 4 53 0 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明(5) 在第五躕之中,钇栝相位1 (phase 1 ),相位2 (phase 2),相位 3 (phase 3),相位4 (phase 4) 及相位5 (phase 5)之運作情形》 相位1時,比較器於ΑϋΤΟ-ZERO狀態》因此*其輸 入®電壓爲VCH。 在相位2上之節黠VXli之訊號電鏖與輸入之钒號電 壓關係如下: VXli = VIN - DACli + VCM 其中VCM爲相位1上之VCM期之電麼 在相位3之中* 其 VX2i = VCM+VlN-DAClX-(C2/Cl) * DAC2i 在相位4之中, 其 VX3i = VlN + VCM-DAClX-(C2/Cl) * DAC2X-(C3/C1) . DAC3i 在相位5乏中, 其乂乂4! = 乂1科 + \7 0»4-〇八(:1乂-(02/(:1).〇久。2父-〇:3/(:1)*0八03乂 其中 Cl = 2C2 = 4C3 DAC1X = (4D8 + 2D7 + D6) VREF/8 DAC2X = (4D5 + 2D4 + 4D3) VREF/32 DAC3X = (4D2 + 2D1 + DO) VREF/128 比較器乃使用全差勛式(fully-differential)方 式訊號,殫僅爲單邊钒號,若一端均接到共模電壓,使 其仍能以全差勤式方式動作。 春閲第六、第七、第八、第九、第十軀,爲本發明 實施例之電路皤。 -6 一 (請先閱讀背面之注意事項再填寫本頁) -裝_4 5 3 C Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (4). Half a week before the expiration date (ie, A period in ®) * The VI of each comparator is in the sampling state , V2 is the direct current Qin Kao voltage (Vr-) * Same for Vj and VH, in the second half of the time (ie, period B in ®) * V1 is in the preset state (predict), at this time the preset voltage of each comparator Each is DACli (i = 1..2M-l). When the vanadium is in the second remote period (that is, period C in 囿), the VI voltage shovel of each comparator is DAC1X, and V2 is in its reported state. The voltages are DAC2i (i = 1..2M-l) * and the output data recording device (17) now sends the first set of MSB data, and sends the data 1 in the first half (C time migration) _, and returns in the second half Output data 2 (D period), and so on, and send the Nth set of data * to the (N + 2) / 2 cycle. A total of K bytes of data is completed for conversion. Refer to the third figure and the fourth figure for the embodiment and timing diagram of 9-bit signal processing in the present invention. Refer to Chapter 5 for the relationship when working hard in the present invention®. For example, compare three bits at a time and cycle three times. The total number of ADC bits is 9 bits. When 7 comparators are used, it is M = 3 * The number of comparators and the number of bits have the following relationship: the number of comparators is 2M-1 (M: number of bits), if 2M-1 comparators (3 1) 'are used and each comparator is used In the arrangement of n capacitors, the total number of bits of the present invention is MxN 'and the number of required clocks is limited to (N + 2) / 2'. Therefore, if the number of execution cycles using the number of clocks is reduced, the use is more More comparators and less capacitor arrangement can achieve the purpose of the invention, and the frequency range of the two uses can reach more than several MHz, which can be completely applied in the field of video (VIDEO). ; Install ------- Order -------- line (please read the notes on the back before filling in this page) 4 53 0 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Explanation (5) In the fifth scandium, the operation of yttrium scandium phase 1 (phase 1), phase 2 (phase 2), phase 3 (phase 3), phase 4 (phase 4) and phase 5 (phase 5) 》 When Phase 1, the comparator is in ΑΟΤΟ-ZERO state. Therefore * its input® voltage is VCH. The relationship between the signal voltage of VXli and the input vanadium voltage in phase 2 is as follows: VXli = VIN-DACli + VCM Where VCM is the electricity in the VCM period on phase 1 is in phase 3 * its VX2i = VCM + VlN-DAClX- (C2 / Cl) * DAC2i is in phase 4 and its VX3i = VlN + VCM-DAClX- ( C2 / Cl) * DAC2X- (C3 / C1). DAC3i is in phase 5 and its 乂 乂 4! = 乂 1 Section + \ 7 0 »4-〇 八 (: 1 乂-(02 / (: 1) .〇 久. 2 fathers-0: 3 / (: 1) * 0 eight 03, where Cl = 2C2 = 4C3 DAC1X = (4D8 + 2D7 + D6) VREF / 8 DAC2X = (4D5 + 2D4 + 4D3) VREF / 32 DAC3X = (4D2 + 2D1 + DO) The VREF / 128 comparator uses a fully-differential signal. For a single vanadium, if one end is connected to the common mode voltage, it can still operate in a full-duty mode. The sixth, seventh, eighth, ninth, and tenth bodies of the spring reading are examples of the present invention. Circuit 皤. -6 I (Please read the precautions on the back before filling in this page) -Installation_
.1T —線 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) 4530 Λ7 B7 五、發明説明(6 ) 對於傳Μ故#之使用方式,其爲以單位元作逅次比 較•若位无數爲Ν·則所須之時脈數nr至少須Ν,因此其 有效之處理速度限制了可使用的晃園,其铯園僅能敗到 數十KHZ ’或數瓦KHZ,本發明利用數锢比較器使得該多 位元逐次比較型額比數位轉換器在單一時脈可產生數個 位元,用以降低其轉換所需的時脈週期數目,可完全改善 習用技術之缺點,而且可將該轉換器,利用其電容耦合技 巧將解析度延伸。 從上所迷可知,本發明之多位无逖次比較型類比數 位轉換器’確實具有達到提高麵率葩团及提高解析度之 功效*而該功效確實可以改進f旯之弊,且其並未見諸 於公開使用•合於專利法之规定*懇諳踢准專利。 惟以上所迷僅爲本發明之較佳可行實施例,非因此 即拘限本發明之專利範囲,故舉凡運用本發明説明書及 蘭式内容爲之等负结構變化,均同理皆包含於本發明之 範囲内,合予陳明。 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央橾準局貝工消費合作社印製 本紙張尺度適用中國國家橾擎(CNS ) A4規格(210X297公釐).1T — The paper size of the paper is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 4530 Λ7 B7 V. Description of the invention (6) For the use of Chuan M 故 #, it is compared with the unit yuan. If the number of bits is N ·, the required clock number nr must be at least N, so its effective processing speed limits the usable garden, and its cesium garden can only lose to tens of KHZ 'or several watts of KHZ. The invention uses a digital comparator to enable the multi-bit sequential comparison type ratio digital converter to generate several bits in a single clock to reduce the number of clock cycles required for its conversion and can completely improve the shortcomings of conventional technology. And, the converter can use its capacitive coupling technique to extend the resolution. It can be known from the above that the multi-dimensional non-comparison analog digital converter of the present invention does have the effect of improving the surface area and the resolution *, and the effect can indeed improve the disadvantages of f and furthermore Not seen in public use • Compliance with Patent Law However, the above is only a preferred and feasible embodiment of the present invention, which does not limit the patent scope of the present invention. Therefore, any negative structural changes using the description and blue content of the present invention are included in the same reason. Within the scope of the present invention, Chen Ming is incorporated. (Please read the precautions on the back before filling out this page) Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs This paper is sized for China National Standard Engine (CNS) A4 (210X297 mm)