4 經濟部中央標率局員工消費合作杜印製 5296 9 at •442；uu 1' doc/OOK 37 五、發明説明（/ ) 發明頜域 本發明是有關於一種製造動態隨機存取記憶體（DRAM) 的方法，且特別是有關於一種製造堆疊式電容器的方法。 發明背景 減小記憶胞的尺寸大小以增加積集度與動態隨機存取 記憶體晶片的記憶容量已經成爲一種趨勢。隨著動態隨機 存取記憶體的尺寸縮小，用於動態隨機存取記憶體之電容 器的容量也相對地減小。 動態隨機存取記憶體的記憶胞通常是由一個儲存電極 與一個存取電晶體所組成。伴隨著大型積體動態隨機存取 記憶體元件的進步，元件的尺寸變得愈來愈小，因此單一 記憶胞所能佔有的面積也變得非常小。 ―種增加電容面積的方法包括在非晶矽上形成半球狀 晶粒複晶矽並且增加電容器的高度。然而，要增加電容器 高度就需要增加非晶矽層的高度，而這需要增加非晶矽層 的沉積時間。較長的沉積時間會導致非晶矽的結晶化。非 晶矽的結晶化抑制了矽的遷移，使得在非晶矽上之半球形 晶粒的形成情形較差，因此減少了面積的增加。 另外，傳統堆疊式電容器的階梯高度差，在平坦化時 會造成困難。傳統堆疊式電容器的下儲存電極具有大約 6000埃至9000埃的高度，而複晶矽上電極則具有500埃 至1500埃的厚度。在記憶胞與週邊各層之間的高度差增 加了平坦化的困難度。 ‘ 因此需要·種減少非晶矽之結晶化，並可以有較好之 本紙張尺度適用中國&樣準（CNS ) Λ4規格（2!0Χ 297公釐 II--.-----f------訂------線· I (請先閱讀背面之注意事項再填寫本頁) 452969 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（i) 平坦化製程，較好的製造堆疊式電容器的方法。 發明槪述 本發明揭露的是一種在基底上形成電容器之儲存下電 極的方法。此方法包括的步驟有：於基底上方形成第一絕 緣層；圖案化並蝕刻穿過第一絕緣層直到到達基底，以形 成一個位元線接觸窗開口：沉積一層導電層於位元線接觸 窗開口中與第一絕緣層上方；圖寒化並蝕刻導電層以形成 位元線；沉積第二絕緣層於位元線與第一絕緣層上方，沉 積氮化物層於第二絕緣層上方；沉積第三絕緣層於氮化物 層上方；圖案化並蝕刻第三絕緣層，氮化物層，第二絕緣 層與第一絕緣層，並終止於基底，以形成第一儲存電極接 觸窗開口；沉積非晶矽層於第一儲存電極接觸窗開口中與 第三絕緣層上方；圖案化並蝕刻非晶矽層與第三絕緣層， 並終止於氮化物層，以形成開口；沿著開口的側壁形成非 晶矽側壁間隙壁；並且沉積半球狀晶粒（HSG)複晶矽於非 晶矽層與非晶矽側壁間隙壁上。 圖示之簡單說明 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，T文特配合所附圖式做一詳細說明，其中： 第1圖至第7圖繪示依照本發明之形成堆疊式亀容器 的步驟之半導體基底的剖面圖。 圖示之標號說明 1〇〇 :基底 102 :第一氧化層 (請先閲讀背面之注項再填寫本頁) .妒.1 訂 線 本紙張尺度適用中國國家標準（CNS ) A4規格（2iOX297公釐） 452969 A7 B7 經濟部中央標準局員工消費合作社印裝 五、發明説明（A ) 104 :位元線接觸窗開口 106 :複晶矽層 108 :矽化鎢層 11 〇 :複合結構 112 :第二氧化層 Π4 :氮化物I# Π6:第二氧化層 - 118 :光阻層 120 :第…儲存電極接觸窗開口 122 :非晶矽層 124 :開口 125 :非晶矽間隙壁 126 :半球形晶粒複晶矽 12S :薄介電層 1 3 0 :上複晶砂層 · 較佳實施例之詳細描沭 本發明將配合所附之圖式作詳細說明。本發明提供一 種形成堆疊式電容器的方法。 請參照第丨圖，繪示-個半導體基底100。此基底可 以包含有一個半導電性晶圓，形成於晶圓中的主動與被動 元件以及形成於晶圓表面的各層。基底的意義則是包含了 形成於半導體品圓中的元件與覆蓋於晶圓上的各層。 在第1國中，形成第一絕緣層或是氧化層102於基底 100上方。此絕緣層可以是由氧化矽，硼磷矽玻璃（BPSG) II--：-----擎.------訂------線· (請先閱讀背面之注項再填寫本頁) 本紙浪尺度適用中國國家標準（CNS > A4規格（210X297公釐） A7 B7 5296 9 44-->iw r.tioc/aos 五、發明説明（iX ) 或是其組合所形成。利用傳統的微影與触刻技術形成位兀 線接觸窗開口 104。控制蝕刻至到達基底100時終止。利 用任何的傳統技術在位元線接觸窗開口 104中與第一氧化 層104上方沉積複晶砂層106。舉例來說，可以使用以磷 化氫與矽烷作爲反應氣體的化學氣相沉積（CVD)製程。複 晶矽層106具有大約500埃至1000埃的厚度爲較佳。形 成一層矽化鎢層〗08於複晶矽層106上方。矽化鎢層108 的厚度以大約1000埃爲較佳。利用傳統圖案化與蝕刻的 技術，蝕刻複晶矽層106與矽化鎢層108直到到達第一氧 化層1〇2。在位元線開口 104上形成了由複晶矽層]·06與 矽化鎢層108所組成的複合結構110。複晶矽層106與矽 化鎢層108形成了動態隨機存取記憶體記憶胞的位元線連 結。 請參照第2圖，沉積厚度以大約2000埃至4000埃爲 較佳的第二氧化矽層112於複合結構110與第一氧化層102 上方。接著，於第二氧化層1丨2上方沉積厚度以大約150 埃至5〇〇埃爲較佳的氮化矽層114。於氮化物層114上沉 積一層厚度以大約6000埃至9000埃爲較佳的第三氧化矽 層Η6。沉積第三氧化層的較佳方法爲傳統的電漿增強四 乙基正矽酸鹽或是電漿增強矽烷。這種技術提供了低成本 高沉積速率的優點。 請參照第3圖，於第三氧化層116上沉積光阻層1丨8 並加以圖案化與顯影。以光阻層Π8爲罩幕，蝕刻第三氧 化層116、氮化物層114、第二氧化層112與第一氧化層 1 I J- n ^^,.1 I ^ I 線 (讀先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） d529S9 44230 (Mi 8 A7 B7 經濟部中央橾準局負工消費合作社印装 五、發明説明（6) i 〇2，以形成第一儲存電極接觸窗開口 120。如同第3圖中 所顯示的，複合結構110會被蝕刻穿過，由於複合結構1 10 實際上就是動態隨機存取記憶體記憶胞的位元線，儲存電 極開口需形戎於複合結構的前方或是後方以避免與位元線 接觸。控制註刻於基底100終止。之後，以任何的傳統技 術移除光阻晉1 1 8。 請參照第4圖，於接觸窗開口 120中與第三氧化層1 16 上方沉積一罾臨場摻雜的非晶矽層122。非晶矽層122得 較佳厚度約_ 5〇0埃至1500埃。沉積非晶矽層可以用任 何已知的傳統技術來進行，比如以矽烷作爲反應氣體。非 晶矽的沉積溫度則以介於攝氏500至530度之間爲較佳。 請參照第5圖，蝕刻非晶矽層122與第三氧化層116， 形成開口 124。控制蝕刻至氮化物層114終止。使用傳統 的微影技術蝕刻非晶矽層122與第三氧化層116。 請參照第6圖，於第5圖之結構的上表面上沉積一層 第二臨場摻雜非晶性層，至厚度約爲400埃至750埃。之 後’非等向性地蝕刻此非晶矽層（比如爲反應性離子蝕刻）， 沿著第三氧化層116的側壁形成非晶矽間隙壁125。形成 間隙壁約需要進行臣分之三十至五十的過度蝕刻=當非等 向性蝕刻形戎間隙壁時，在蝕刻的過程中移除較佳厚度約 爲200埃至400埃的非晶矽層122。如第6圖所示，.非晶 矽層1二與非晶矽間隙壁125都在接觸窗中，以形成下儲 存電極= 請參照第7圖，在非晶矽層122與非晶矽間矽壁125 I ~! . I i —if —訂— 線 l (諳先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS > A4規格（2! 0 X 2们公釐） 452969 A7 經濟部中央標準局員工消費合作社印袋 •44：3t\\ I doc/OOS 五、發明説明) 上形成半球形晶粒（H S G)複晶砂1 2 6。以高真空回火形成 半球形晶粒複晶矽126。高真空的回火溫度較佳約爲攝氏 560度至660度。形成半球形晶粒複晶矽126以播種與高 真空技術進行爲較佳。總而言之，矽烷或是二矽烷被用來 種植於非晶矽的表面。接著，於高真空中形成半球形晶粒 複晶矽。用這個方法形成下接觸電極。 最後，進行一般的薄介電層128與上複晶矽層130的 沉積，以完成電容器。薄介電層較佳爲厚度小於80埃的 氧化物/氮化物/氧化物（ΟΝΟ)複合層。爲了完成動態隨機 存取記憶體的電容器，應用傳統的微影圖案化與蝕刻移除 在週邊電路的上複晶政層1 3 0，薄介電層1 2 8，半球形晶 粒複晶矽126與非晶矽層122。 因此，最後的階梯高度差小於2000埃。與傳統的堆 疊式電容器所用的厚非晶矽層不同，沉積且不移除週邊之 厚第三氧化層116減小了階梯高度差。階梯高度差的減小 改善了平坦化製程。此外，與傳統的堆疊式電容器所使用 之6000埃至9000埃厚的非晶矽層相比，全部的非晶矽氧 化層的厚度約爲900埃至2250埃。較小的非晶砂高度所 需要的沉積時間較短，因此減少了會抑制半球形晶粒形成 的非晶矽的不預期微結晶。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當π丨作各種之更動與潤飾。 (請先閲讀背面之注意事項再填寫本頁) 本纸張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐）4 Consumption Cooperation of Employees of the Central Standards Bureau of the Ministry of Economic Affairs 5296 9 at • 442; uu 1 'doc / OOK 37 V. Description of the Invention (/) Invention of the Jaw Field The present invention relates to a method for manufacturing dynamic random access memory ( DRAM) method, and in particular, a method for manufacturing a stacked capacitor. BACKGROUND OF THE INVENTION It has become a trend to reduce the size of memory cells to increase the degree of accumulation and the memory capacity of dynamic random access memory chips. As the size of the dynamic random access memory is reduced, the capacity of the capacitor used for the dynamic random access memory is also relatively reduced. The memory cell of a dynamic random access memory is usually composed of a storage electrode and an access transistor. With the advancement of large-scale integrated dynamic random access memory devices, the size of the devices has become smaller and smaller, so the area occupied by a single memory cell has also become very small. ―A method for increasing the capacitance area includes forming a hemispherical grain polycrystalline silicon on amorphous silicon and increasing the height of the capacitor. However, increasing the height of the capacitor requires increasing the height of the amorphous silicon layer, and this requires increasing the deposition time of the amorphous silicon layer. Longer deposition times result in crystallization of amorphous silicon. The crystallization of amorphous silicon inhibits the migration of silicon, making the formation of hemispherical grains on amorphous silicon worse, thus reducing the increase in area. In addition, the step height difference of conventional stacked capacitors can cause difficulties during planarization. The lower storage electrodes of conventional stacked capacitors have a height of about 6000 Angstroms to 9,000 Angstroms, while the polycrystalline silicon upper electrodes have a thickness of 500 Angstroms to 1500 Angstroms. The height difference between the memory cells and the surrounding layers increases the difficulty of flattening. 'Therefore, there is a need to reduce the crystallization of amorphous silicon, and to have a better paper size suitable for China & Sample Standard (CNS) Λ4 specification (2! 0 × 297 mm II --.----- f ------ Order ------ Line · I (Please read the notes on the back before filling in this page) 452969 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (i) Flat Process, a better method for manufacturing stacked capacitors. SUMMARY OF THE INVENTION The present invention discloses a method for forming a storage lower electrode of a capacitor on a substrate. The method includes the steps of: forming a first insulating layer over the substrate; Pattern and etch through the first insulating layer until reaching the substrate to form a bit line contact window opening: deposit a conductive layer in the bit line contact window opening above the first insulating layer; map cold and etch the conductive layer To form a bit line; deposit a second insulating layer over the bit line and the first insulating layer, deposit a nitride layer over the second insulating layer; deposit a third insulating layer over the nitride layer; pattern and etch a third Insulation layer, nitride layer, second insulation Layer and first insulating layer, and terminated on the substrate to form a first storage electrode contact window opening; depositing an amorphous silicon layer in the first storage electrode contact window opening and above the third insulating layer; patterning and etching the amorphous silicon Layer and a third insulating layer, and terminate in a nitride layer to form an opening; an amorphous silicon sidewall spacer is formed along the side wall of the opening; and hemispherical grain (HSG) polycrystalline silicon is deposited on the amorphous silicon layer and the non-crystalline silicon layer Crystal silicon on the side wall. The brief description of the figure is to make the above and other objects, features, and advantages of the present invention more comprehensible, T Wente will make a detailed description in conjunction with the drawings, where: Figure 1 Fig. 7 to Fig. 7 are cross-sectional views of a semiconductor substrate in accordance with the steps of forming a stacked plutonium container according to the present invention. The reference numerals in the illustration 100: substrate 102: first oxide layer (please read the notes on the back before filling (This page) .Envy.1 The size of the paper is applicable to the Chinese National Standard (CNS) A4 (2iOX297 mm) 452969 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of Invention (A) 104: Bit Line contact window Port 106: polycrystalline silicon layer 108: tungsten silicide layer 11 〇: composite structure 112: second oxide layer Π4: nitride I # Π6: second oxide layer-118: photoresist layer 120: storage electrode contact window opening 122: Amorphous silicon layer 124: Opening 125: Amorphous silicon spacer 126: Hemispherical grained polycrystalline silicon 12S: Thin dielectric layer 1 30: Upper polycrystalline sand layer · Detailed description of the preferred embodiment of the present invention The accompanying drawings will be described in detail. The present invention provides a method for forming a stacked capacitor. Referring to FIG. 丨, a semiconductor substrate 100 is shown. The substrate may include a semi-conductive wafer, active and passive components formed in the wafer, and layers formed on the surface of the wafer. The meaning of the substrate is to include the elements formed in the semiconductor circle and the layers covered on the wafer. In the first country, a first insulating layer or an oxide layer 102 is formed over the substrate 100. This insulating layer can be made of silicon oxide, borophosphosilicate glass (BPSG) II ----------- engine .------ order ------ line · (Please read the note on the back first (Fill in this page again) This paper applies the Chinese national standard (CNS > A4 specification (210X297 mm) A7 B7 5296 9 44-> iw r.tioc / aos 5. Description of invention (iX) or its combination Forming. The bit line contact window opening 104 is formed using conventional lithography and touch-engraving techniques. The controlled etching is terminated until reaching the substrate 100. The bit line contact window opening 104 is formed above the first oxide layer 104 using any conventional technique. A polycrystalline sand layer 106 is deposited. For example, a chemical vapor deposition (CVD) process using phosphine and silane as a reactive gas can be used. The polycrystalline silicon layer 106 preferably has a thickness of about 500 to 1000 angstroms. Formation A layer of tungsten silicide layer 08 is above the polycrystalline silicon layer 106. The thickness of the tungsten silicide layer 108 is preferably about 1000 angstroms. Using conventional patterning and etching techniques, the polycrystalline silicon layer 106 and the tungsten silicide layer 108 are etched until reaching First oxide layer 102. A polycrystalline silicon layer is formed on the bit line opening 104]. 06 and silicidation A composite structure 110 composed of a tungsten layer 108. The polycrystalline silicon layer 106 and the tungsten silicide layer 108 form a bit line connection of a dynamic random access memory memory cell. Referring to FIG. 2, the deposition thickness ranges from about 2000 Angstroms to 4000 Angstroms. The preferred second silicon oxide layer 112 is above the composite structure 110 and the first oxide layer 102. Next, a thickness of about 150 angstroms to 5,000 angstroms is a preferred nitrogen layer over the second oxide layer 1-2. Siliconized layer 114. A third silicon oxide layer is preferably deposited on the nitride layer 114 with a thickness of about 6000 angstroms to 9,000 angstroms. 6. The preferred method of depositing the third oxide layer is conventional plasma-enhanced tetraethyl Orthosilicate or plasma-enhanced silane. This technology provides the advantage of low cost and high deposition rate. Please refer to Figure 3, deposit a photoresist layer 1 on the third oxide layer 116 and pattern and develop it. Using the photoresist layer Π8 as a mask, the third oxide layer 116, the nitride layer 114, the second oxide layer 112, and the first oxide layer 1 I J- n ^^ ,. 1 I ^ I line (read first read (Notes on the back, please fill in this page) Standards are applicable to Chinese National Standard (CNS) A4 specifications (210 × 297 mm) d529S9 44230 (Mi 8 A7 B7) Printed by the Consumers ’Cooperative of the Central Standards and Quarantine Bureau of the Ministry of Economic Affairs 5. Description of invention (6) i 〇2 to form the first storage The electrode contacts the window opening 120. As shown in FIG. 3, the composite structure 110 will be etched through. Since the composite structure 1 10 is actually a bit line of the dynamic random access memory memory cell, the storage electrode opening needs to be shaped Stand in front of or behind the composite structure to avoid contact with the bit lines. The control injection is terminated on the substrate 100. After that, the photoresist is removed by any conventional technique. Referring to FIG. 4, a field-doped amorphous silicon layer 122 is deposited in the contact window opening 120 and above the third oxide layer 116. The amorphous silicon layer 122 preferably has a thickness of about -500 Angstroms to 1500 Angstroms. Deposition of the amorphous silicon layer can be performed by any known conventional technique, such as using silane as a reactive gas. The deposition temperature of amorphous silicon is preferably between 500 and 530 degrees Celsius. Referring to FIG. 5, the amorphous silicon layer 122 and the third oxide layer 116 are etched to form an opening 124. The controlled etch is terminated until the nitride layer 114 is terminated. The amorphous silicon layer 122 and the third oxide layer 116 are etched using a conventional lithography technique. Referring to FIG. 6, a second field-doped amorphous layer is deposited on the upper surface of the structure in FIG. 5 to a thickness of about 400 to 750 angstroms. Thereafter, the amorphous silicon layer is anisotropically etched (for example, reactive ion etching), and an amorphous silicon spacer wall 125 is formed along the sidewall of the third oxide layer 116. The formation of the gap wall requires about 30 to 50 minutes of over-etching = when the gap wall is anisotropically etched, the amorphous layer with a preferred thickness of about 200 Angstroms to 400 Angstroms is removed during the etching process. Silicon layer 122. As shown in FIG. 6, the amorphous silicon layer 12 and the amorphous silicon spacers 125 are both in the contact window to form a lower storage electrode. Please refer to FIG. 7, between the amorphous silicon layer 122 and the amorphous silicon. Silicon wall 125 I ~!. I i —if — order — line l (谙 Please read the precautions on the back before filling this page) This paper size applies to Chinese national standards (CNS > A4 size (2! 0 X 2men public) (Centi) 452969 A7 Printed bags of consumer cooperatives of employees of the Central Standards Bureau of the Ministry of Economic Affairs • 44: 3t \\ I doc / OOS 5. Description of the invention) Hemispherical grains (HSG) complex crystal sands 1 2 6 were formed. Hemispherical grain polycrystalline silicon 126 was formed by high vacuum tempering. The high vacuum tempering temperature is preferably about 560 ° C to 660 ° C. The formation of hemispherical grained polycrystalline silicon 126 is preferably performed by seeding and high vacuum technology. In summary, silane or disilane is used to grow on the surface of amorphous silicon. Next, hemispherical grains of polycrystalline silicon are formed in a high vacuum. In this way, a lower contact electrode is formed. Finally, a general thin dielectric layer 128 and an upper polycrystalline silicon layer 130 are deposited to complete the capacitor. The thin dielectric layer is preferably an oxide / nitride / oxide (ONO) composite layer having a thickness of less than 80 angstroms. In order to complete the capacitor of the dynamic random access memory, the conventional lithographic patterning and etching are used to remove the upper polycrystalline silicon layer 1 3 0, the thin dielectric layer 1 2 8 and the hemispherical grain polycrystalline silicon. 126 和 122。 Amorphous silicon layer 122. Therefore, the final step height difference is less than 2000 Angstroms. Unlike the thick amorphous silicon layer used in conventional stacked capacitors, the thick third oxide layer 116 deposited without removing the periphery reduces the step height difference. The reduced step height difference improves the planarization process. In addition, the thickness of the entire amorphous silicon oxide layer is about 900 Angstroms to 2250 Angstroms compared to the 6,000 Angstroms to 9,000 Angstroms thick amorphous silicon layers used in conventional stacked capacitors. Smaller amorphous sand heights require shorter deposition times, thereby reducing unexpected microcrystals of amorphous silicon that inhibit hemispherical grain formation. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. (Please read the precautions on the back before filling this page) This paper size applies to China National Standard (CNS) Α4 specification (210X297 mm)