五、發明說明（1) 本發明疋有關於—種半導體（semiconductor)積體電 路（integrated circuits ;ICs)製程技術’特別是有關於 種利用化學乱相沈積法（chemicai vap〇r deposition ; CVD)^/成低介電常數材料（i〇w k material)的方法，藉由 k供夕1¾ #又間歇性射幅電源（ra{j i 〇 f requenCy p〇wer )， 以提昇低介電常數材料的機械性質並且降低漏電流現象。 不論何種電子元件均少不了用來傳輸電訊的金屬導 線’半導體積體電路元件亦然，各個元件必藉由適當的内 連線¥作電性連接’方得以發揮所欲達成之功能。在今曰 多層内連線製程中，除了製作各層導線圖案之外，更須藉 助接觸孔（contact via)構成，以作為元件接觸區與導線 之間或疋多層導線之間的聯繫通道。再者，隨著積體電路 積集度不斷地提昇，電路設計尺寸逐漸縮小為〇18//111或 以下’一種能夠同時在介電材料蝕刻形成溝槽（trench)與 接觸孔’而後填入銅金屬材料的鑲嵌式銅導線製程 (damascene Cu process)正是目前的主流。 其次，為了有效地降低導線間寄生電容（parasitic capacitance)和元件的RC延遲，内連線之製程逐漸使用具 有低介電常數（例如k = 2. 5〜3. 〇)之有機介電材料等，來取 代傳統的二氧化矽以及氮化矽等材料（k例如為4以上），上 述有機介電材料例如為，伸芳香基醚類聚合物 (polyUryiene ether) P〇lymer)。另外，近來aer〇gel、 xerogel 'naiioglass 等含有微細多孔隙（tiny p〇r〇sity) 的玻璃（二氧化石夕）材料’例如在二氧化矽之中摻入碳與V. Description of the invention (1) The present invention is related to a semiconductor integrated circuit (ICs) process technology, and particularly to a method using a chemical vapour deposition method (CVD). ^ / The method of forming a low dielectric constant material (i〇wk material), by using a k supply evening 1¾ # and intermittent radiation power supply (ra {ji 〇f requenCy p〇wer), to improve the low dielectric constant material. Mechanical properties and reduce leakage current. No matter what kind of electronic component is indispensable, the metal wire used for transmitting telecommunications is also a semiconductor integrated circuit component, and each component must perform its desired function through proper interconnections for electrical connection. In today's multi-layer interconnect process, in addition to making each layer of wire pattern, it is also necessary to use contact vias to form the contact channel between the contact area of the component and the wire or between the multi-layer wire. Furthermore, as the integration degree of integrated circuits continues to increase, the circuit design size is gradually reduced to 〇18 // 111 or below. 'A trench and contact hole can be simultaneously etched in a dielectric material' and then filled The damascene Cu process of copper metal materials is the current mainstream. Secondly, in order to effectively reduce the parasitic capacitance between the wires and the RC delay of the device, the process of interconnects gradually uses organic dielectric materials with low dielectric constants (such as k = 2.5 to 3. 3). To replace conventional materials such as silicon dioxide and silicon nitride (k is 4 or more, for example), and the organic dielectric material is, for example, polyUryiene ether (Polymer). In addition, recently, aerogel, xerogel 'naiioglass, and other glass materials containing fine porosity (silica dioxide)' are doped with carbon and silicon dioxide, for example.
4i29 2 Ο 五、發明說明（2) 氫’亦被當作低介電常數材料使用，其能夠降低金屬内連 線之間的寄生電容與RC延遲，進而提昇元件之間的傳輸效 率 〇 以下利用第1 Α圖〜第1 Β圖所示的製程剖面圖，以舉例 說明習知在低介電常數材料層嵌入銅金屬之製程剖面示意 圖。 首先，請參照第1A圖’該圖之符號10表示半導體基 底，上述半導體基底1〇已形成有若干半導體元件與若干層 的銅金屬内連線（圖皆未顯示）。將上述形成有若干半導體 元件的基底10移至電聚加強型化學氣相沈積（plasma e n h a n c e d c h e m i c a 1 v a ρ 〇 r d e ρ 〇 s i t i ο η ; P E C V D )反應室 (chamber)之中，接著供給一氧化二氮（n2〇) '矽甲烷 (SilU、三曱基矽烷（（CH3)3SiH))於上述化學氣相沈積反 應室’在大約17。〇400 DC的溫度下提供大約75W，30〜60秒 的射頻電源於化學氣相沈積反應室，以在上述半導體基底 10表面形成一摻有碳（C)與氫（η)的多孔質二氧化矽構成之 低介電常數材料層12。 接著，請參照第1 B圖’利用傳統微影製程與蝕刻步驟 以選擇性蝕穿低介電常數材料層12以形成鑲嵌溝槽14，然 後利用電化學沈積形成銅金屬再以化學機械研磨法進行銅 金屬的平坦化以形成鑲嵌式鋼導線〗6。 然而，由於多重内連線的製程，係由鑲嵌銅導線的多 層$電材料構成’此多層堆疊的結果容易導致多孔隙低介 電常數材料的龜裂（如第u或第1β圖所示之符號CK)，再4i29 2 〇 5. Description of the invention (2) Hydrogen 'is also used as a low dielectric constant material, which can reduce the parasitic capacitance and RC delay between metal interconnects, thereby improving the transmission efficiency between components. The cross-sectional views of the process shown in FIG. 1A to FIG. 1B are used to illustrate the cross-sectional schematic diagrams of the conventional process of embedding copper metal in a low dielectric constant material layer. First, please refer to FIG. 1A. The reference numeral 10 in the figure indicates a semiconductor substrate. The above-mentioned semiconductor substrate 10 has formed a plurality of semiconductor elements and a plurality of layers of copper metal interconnects (all of which are not shown in the figure). The substrate 10 on which the several semiconductor elements are formed is moved to a plasma enhanced chemical vapor deposition (plasma enhanced chemica 1 va ρ 〇 rd ρ 〇 siti ο η; PECVD) reaction chamber (chamber), followed by supply of nitrous oxide (N2O) 'Silmethane (SilU, trimethylsilyl ((CH3) 3SiH)) in the above-mentioned chemical vapor deposition reaction chamber' is about 17. 〇400 DC temperature of about 75W, RF power for 30 ~ 60 seconds in the chemical vapor deposition reaction chamber to form a porous dioxide doped with carbon (C) and hydrogen (η) on the surface of the semiconductor substrate 10 Low dielectric constant material layer 12 made of silicon. Next, please refer to FIG. 1B. FIG. The copper metal is planarized to form a damascene steel wire. 6 However, due to the multiple interconnecting process, it is composed of multiple layers of electrical materials inlaid with copper wires. The result of this multilayer stack can easily lead to cracks in porous low dielectric constant materials (as shown in Figure u or Figure 1β) Symbol CK), then
4 5 29 2 g_ 五、發明*---- 者，谷易產生電荷效應（Charging effect)而導致漏電 流’此現象由C-V分析儀測出之平帶電壓（f lat band voltage)偏高（例如-76v)得到證實。此係由於提供連續性 射頻電源，使得低介電常數材料的微細孔洞大都為連續 性。 有鑑於此，本發明的目的在於提供一種低介電常數材 料的方法，能夠藉由使微細孔洞轉變為非連續性’以降低 應力（stress)與耐衝擊特性，進而防止多層介電材料堆義 產生的龜裂。 ι 本發明的另一目的在於提供一種低介電常數材料的方 法’能夠大幅降低電荷效應’以防止漏電流。 根據上述目的，本發明提供一種形成低介電常數材 的方法，包括下列步驟：提供一半導體基底，該基底形成 有若干半導體元件；將上述半導基底置於一電漿加強型化 學氣相沈積反應室；供給一氧化二氮（N2 〇)'甲基石夕燒 ((C )4_n S i Hn)於該化學氣相沈積反應室，並且提供一多 段間歇性射頻電源’以在上述半導體基底表面形成一 電常數材料層；上述n =卜3。 ~ 1 再者’上述形成低介電常數材料的方法，其中該多 段間歇性射頻電源至少包括：施以第1階段功率；與第2 段功率，其中第1階段功率小於第2階段功率，且該第i與％ 第2階段功率介於〇〜2 0 〇 W之間，例如7 0 W，0〜1 〇秒； 、 140W，11 〜20 秒兩階段；70W，〇〜1〇 秒；140W，1 卜 20 秒；7〇w 21〜3 0秒三階段。 ’4 5 29 2 g_ V. Invention * ---- In the case of Gu Yi, the charge effect (Charging effect) results in leakage current. This phenomenon is that the flat band voltage (f lat band voltage) measured by the CV analyzer is too high ( For example -76v) is confirmed. Because this series provides continuous RF power, the fine pores of low dielectric constant materials are mostly continuous. In view of this, an object of the present invention is to provide a method for a low-dielectric-constant material, which can reduce the stress and impact resistance characteristics by transforming micro-voids into discontinuities, thereby preventing the stacking of multilayer dielectric materials. The resulting cracks. ι Another object of the present invention is to provide a method of a low-dielectric-constant material, which can greatly reduce the charge effect, to prevent leakage current. According to the above object, the present invention provides a method for forming a low dielectric constant material, which includes the following steps: providing a semiconductor substrate having a plurality of semiconductor elements formed thereon; and placing the semiconductor substrate in a plasma enhanced chemical vapor deposition Reaction chamber; supply dinitrogen monoxide (N2 0) 'methyl stone sinter ((C) 4_n SiHn) to the chemical vapor deposition reaction chamber, and provide a multi-stage intermittent radio frequency power supply' to the above semiconductor An electric constant material layer is formed on the surface of the substrate; the above n = Bu3. ~ 1 Furthermore, the above-mentioned method for forming a low dielectric constant material, wherein the multi-stage intermittent radio frequency power supply includes at least: applying a first stage power; and a second stage power, wherein the first stage power is less than the second stage power, and The power of the i-th and second-stages is between 0 ~ 2 00W, such as 70 W, 0 ~ 10 seconds; 140W, 11 ~ 20 seconds; 70W, 0 ~ 10 seconds; 140W 1 Bu 20 seconds; 70w 21 ~ 30 seconds in three stages. ’
第6頁 452920Page 452 920
五、發明說明（4) 然而，本發明不限於低-高功率兩階段或低、 率三階段’例如施以高-低-高-低-高〜低功率多階段= 實現本發明，而每一階段的沈積時間則可視需要地 整’例如每一階段進行數秒~數十秒。本發明在每階p改 變射頻電源的功率’可使沈積而得的低介電常數材料又 細孔隙變得不連續，藉以降低材料的應力與耐衝^ 進而防止多層介電材料堆疊產生的龜裂現象。纟且：大幅 地降低電荷效應，以防止漏電流 再者，上述形成低介電常數材料的方法，其中低介電 常數材料可以是摻有碳與氫的多孔皙_ ' 再者，上述形成低介電常數材料;;方法，可以更包括 導入氧氣於該化學氣相沈積室的步驟。並且’最好至少在 沈積的第1階段與最後階段導入氧氣，藉此提昇低介—電常 數材料的黏著性質。 為了讓本發明之上述目的、特徵、和優點能更明顯易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1 A圖〜第1B圖係根據習知例在低介電常數材料層嵌 入銅金屬之製程剖面示意圖。 第2 A圖〜第2B圖係根據本發明實施例在低介電常數材 料層嵌入銅金屬之製程剖面示意圖。 符號之說明 一 1 0、1 0 0〜半導體基底；V. Description of the invention (4) However, the present invention is not limited to low-high power two-stage or low-rate three-stage 'for example, high-low-high-low-high ~ low-power multi-stage = implement the present invention, and each The deposition time of one stage can be adjusted as needed, for example, each stage is performed for several seconds to several tens of seconds. According to the present invention, the power of the RF power source is changed at each step p to make the deposited low-dielectric-constant material fine pores become discontinuous, thereby reducing the stress and impact resistance of the material ^, and thereby preventing the turtles produced by the multilayer dielectric material stacking. Cracking phenomenon. Furthermore, the charge effect is greatly reduced to prevent leakage current. Furthermore, the above-mentioned method for forming a low-dielectric-constant material, wherein the low-dielectric-constant material may be porous doped with carbon and hydrogen. The dielectric constant material; the method may further include the step of introducing oxygen into the chemical vapor deposition chamber. And 'it is preferable to introduce oxygen at least in the first and last stages of the deposition, thereby improving the adhesion properties of the low-dielectric constant material. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: Figure 1A ~ FIG. 1B is a schematic cross-sectional view of a manufacturing process of embedding copper metal in a low dielectric constant material layer according to a conventional example. FIG. 2A to FIG. 2B are schematic cross-sectional views of a process for embedding copper metal in a low-dielectric-constant material layer according to an embodiment of the present invention. Explanation of symbols-1 0, 1 0 0 ~ semiconductor substrate;
4S29 2 Ο4S29 2 Ο
五、發明說明（5) 12、120〜低介電常數材料層； 14、140〜用來填入飼金屬的溝槽 16、160〜嵌入式銅導線。 CK〜龜裂。 實施例 以下利用第2Α圖〜第2Β圖所示的製程剖面圖，以說明 本發明較佳實施例在低介電常數材料層嵌入銅金屬之製程 剖面示意圖 首先’請參照第2Α圖，該圖之符號1 〇〇表示例如單晶 石夕構成的半導體基底，上述半導體基底1〇〇已形成有若干 半導體元件與若干層的銅金屬内連線（圖皆未顯示）。將上 述形成有若干半導體元件的基底10〇移至電漿加強型化學 氣相沈積反應室之中，接著供給一氧化二氮（化〇)、矽甲 烧（SiM、三甲基矽烷於上述化學氣相沈積 反應室，在大約400 °C的溫度下，提供例如（a)70ff，〇〜1() 秒；（b)140ff， 1卜20秒；（c) 7〇w，2卜3〇秒的多階段間歇 性射頻電源（radio frequency p〇wer ;RF p〇wer)，以在 上述半導體基底100表面形成一摻有碳與氫的多孔質二氧 化矽構成之低介電常數材料層12〇。當然，可視厚度需要 在上述（c)之後繼續提供（d)14〇w，3卜4〇秒； (e)70W，4卜50秒，與（f)i4〇w，51~60秒的射頻電源。另 1卜1最在上述多階段間歇性射頻電源之第1階段及/或最 '雷：氧氣(02)於上述化學沈積反應室，以提昇低介 吊數材料與鄰接材料之間的黏著性質（adhesion)。V. Description of the invention (5) 12, 120 ~ low dielectric constant material layer; 14,140 ~ for filling trenches for feeding metal 16,160 ~ embedded copper wires. CK ~ cracked. EXAMPLES The following is a cross-sectional view of the process shown in FIG. 2A to FIG. 2B to illustrate the cross-sectional schematic diagram of the process of embedding copper metal in a low dielectric constant material layer according to a preferred embodiment of the present invention. First, please refer to FIG. 2A, which The symbol 100 indicates a semiconductor substrate composed of, for example, a single crystal stone. The semiconductor substrate 100 has formed a plurality of semiconductor elements and a plurality of layers of copper metal interconnects (all are not shown in the figure). The above-mentioned substrate with a plurality of semiconductor elements 100 was moved into a plasma enhanced chemical vapor deposition reaction chamber, and then nitrous oxide (Chemical), silicon silicate (SiM, trimethylsilane) were supplied to the above chemical The vapor deposition reaction chamber, at a temperature of about 400 ° C, provides, for example, (a) 70 ff, 0 ~ 1 () seconds; (b) 140 ff, 1 bu 20 seconds; (c) 70 watts, 2 bu 3. A multi-stage intermittent radio frequency power source (RF power) in seconds to form a low dielectric constant material layer 12 made of porous silicon dioxide doped with carbon and hydrogen on the surface of the semiconductor substrate 100. 〇 Of course, the visible thickness needs to continue to provide (d) 1440w, 3b 40 seconds after (c) above; (e) 70W, 4b 50 seconds, and (f) i4 0w, 51-60 seconds The other is the first stage of the above-mentioned multi-stage intermittent radio frequency power supply and / or the most thunder: oxygen (02) in the above chemical deposition reaction chamber to enhance the low-medium-hanging number of materials and adjacent materials. Adhesion.
第8頁 452920 五、發明說明（6) 接著，請參照第2B圖’利用傳統微影製程 (photo 1 i thography)與蝕刻步驟（etching)以選擇性蝕穿 低介電常數材料層1 2 0以形成鑲嵌溝槽1 4 〇，然後利用電化 學沈積法（electrochemical deposition ;ECD)形成銅金 屬再以化學機械研磨法進行銅金屬的平坦化以形成鑲鼓式 銅導線1 6 0。 發明特 本 過程中 功率， 的沈積 不連續 層介電 效應， 壓接近 雖 限定本 神和範 當視後 徵與功效 發明提供一種形成低介電常數材料的方法，在沈積 提供多階段間歇性射頻電源，亦即改變射頻電源的 以進行高-低-高-低功率的沈積或低_高_低_高功率 ，此能夠使沈積的低介電常數材料的微細孔隙變得 ，藉以降低材料的應力與耐衝擊特性，進而防止 2堆疊產生的龜裂現象。並且，大幅地降低電荷 :防止漏電流，此現象由㈠分析儀 零（例如-2V)得到證實。 卞f电 然本發明已以較佳實施例揭露如上，麸 發明，任何熟習此項技藝者，在不胺：f並非用以 圍内’當可作更動與潤飾，因此本本發明之精 附之申請專利範圍所界定者為準本發明之保護範圍Page 8 452920 V. Description of the invention (6) Next, please refer to FIG. 2B 'Using the traditional photolithography process (photo 1 i thography) and etching step (etching) to selectively etch the low dielectric constant material layer 1 2 0 To form a damascene trench 140, then use electrochemical deposition (ECD) to form copper metal, and then use chemical mechanical polishing to planarize the copper metal to form a drum-shaped copper wire 160. In the process of the invention, the dielectric effect of the deposited discontinuous layer in the process of power and pressure is close to the limit of the intrinsic and vantage. The invention provides a method for forming a low dielectric constant material and provides a multi-phase intermittent RF power source in Shenji. That is, change the RF power supply for high-low-high-low power deposition or low_high_low_high power, which can make the fine pores of the deposited low dielectric constant material become smaller, thereby reducing the stress of the material And impact resistance, and further prevent the cracking phenomenon generated by 2 stacks. Moreover, the charge is drastically reduced: leakage current is prevented, and this phenomenon is confirmed by the tritium analyzer zero (for example, -2V).电 f The present invention has been disclosed in the preferred embodiment as above. The bran invention, anyone skilled in this art, does not amine: f is not used to surround it. It can be modified and retouched. Therefore, the essence of the present invention is The scope of protection of the present invention shall be defined by the scope of the patent application