A7 B7 五、發明説明（ ~~__丨 10 15 經 濟 部 智 慧 財 產 局 消費 合 作 杜 印 製 20 本發明係有關於一種具有自我校準之時序產生裝置， 特別是指一種能夠根據外部的參考時脈以產生時序處理 之具有自我校準之時序產生裝置。 按’時序產生裝置（Timing generator)通常使用在積 體電路（Integrated Circuit : 1C)測試機中，主要的功能 是提供一準確的時序脈波（Timing Pulses)，使其他測試機 之模組可在準確的時序操作，由於Ic測試機需要測視各 種不同的積體電路產品，因此時序產生器需要具有高準確 度的時序才能符合所有產品的要求，近來越來越多測試機 系統採用CMOS作為時序產生器的主要元件，然而CM〇s於 溫度變化時，時序則有很大的變動趨勢，因此需要一補償 (compensation)與校準（calibration)的電路，本發明係提 供一校準的方法，於操作時可以達到時間的準確度。 請參考第一圖所示係為一般時序產生模組之原理方塊 圖，主要有兩個時序產生模組，係包括有一主時序模組 l〇(master timing module)與一次時序模組 u(suve module)，該主時序模組1〇係根據外部的參考時脈 (Reference Ciock)而產生一粗調時序（⑶虹^ timin幻，該 次時序模組係與該主時序產生模组1()成電氣連接用以產 生-微調時序（fine timing),該主時序模組1()產生之粗調 時序係產生例如：2.〇、3.G.㈣。傭Gnd等週期的 時序‘而㈣組U线料序㈣粗調時序微調後 再送出，產生例如0.05、M〇，〇丨5撕〇等 更小週期的時序調整.若要產生週期為6,!2 narG,..second 請 先 閲 讀 背 意 事 項 再 填 本 頁 裝 訂 度趟用士國國家樓準‘ 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（2 ) 的時序訊號，則其中6.0nar〇_sec〇nd由該主時序模組 產生，而0.12 naro-second則由該次時序模n組進行調 整產生。 請參考第二圖所示係為習知之第一種時序產生裝置方 5塊圊，主時序模組10係為一鎖住相位循環震盪器100(phase locked ring oscillator)，該次時序模組u係由一可程式延 遲單元110(programmable delay unit)組成，其中該主時序 模組為一閉迴路系統（close l〇〇p system)，由於是回授控制 ，而能夠獲得非常高的準確度，然而該次時序模組u係為 10 一開迴路系統’為維持其時序的準確度’校準的動作格外 重要’然而，校準又是一個費時且需要相當勞力與技術的 工作，非為一般人員所能完成，因此需要大筆經費培育人 才。 第三圖係為習知之第二種時序產生裝置方塊圖，與習 15知第一種時序產生裝置的不同處在於，由於積體電路技術 的發展’次時序模組11可為一鎖住相位延遲線u〇(Phase locked delay line) ’將主時序模組i 〇所產生之粗調時序作 進一步處理而成為微調時序，由相位選擇多工器U1(phase selection multiplexer)選擇出精準時序（refine timing)，然 20而’雖然可以從該次時序模組11得到準確的微調時序，由 於相位選擇多工器111位於鎖住相位循環震盪器100之外， 因此時序的準確度大大受到固態裝置（s〇Hd state devices)的 高溫度係數（high temperature coefficient)影響，在不同的溫 度影響下很難維持一定的準確度，因此需要一溫度補償機 本紙張尺度適用中國國家揉準（CNS ) A4規格（2丨0><297公羞） (請先聞讀背面之注項再填窝本頁)A7 B7 V. Description of the invention (~~ __ 丨 10 15 Duo printed by the Intellectual Property Bureau of the Ministry of Economy 20 This invention relates to a timing generating device with self-calibration, especially a device that can be based on an external reference clock Timing generator with self-calibration to generate timing processing. According to the 'Timing generator' is usually used in integrated circuit (1C) testing machine, the main function is to provide an accurate timing pulse wave ( Timing Pulses), so that the modules of other testing machines can operate at accurate timing. Because the Ic testing machine needs to inspect various different integrated circuit products, the timing generator needs high accuracy timing to meet the requirements of all products. Recently, more and more tester systems use CMOS as the main component of the timing generator. However, when CM0s changes in temperature, the timing has a large tendency to change. Therefore, compensation and calibration are needed. Circuit, the present invention provides a calibration method, which can achieve time accuracy during operation Please refer to the first figure for a schematic block diagram of a general timing generation module. There are mainly two timing generation modules, including a master timing module 10 (master timing module) and a timing module u (suve module), the main timing module 10 is based on an external reference clock (Reference Ciock) to generate a coarse timing (CD rainbow ^ timin), the secondary timing module and the main timing module 1 () The electrical connection is used to generate -fine timing. The coarse timing generated by the main timing module 1 () is generated for example: 2.0, 3.G. Group U line material is finely adjusted and then sent out after the coarse adjustment timing, resulting in timing adjustments of smaller cycles, such as 0.05, M0, 〇5, 5 tearing, and so on. To generate a cycle of 6, 2 narG, .. second, please first Read the remarks and fill in this page for binding. Use the National Property Standard of the National Government of the People's Republic of China to print A7 B7 printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The timing signal of the description of the invention (2), of which 6.0nar〇_sec〇nd Generated by the primary timing module, and 0.12 naro-second is generated by the n sequential timing modules Please refer to the second figure. It is a conventional first timing generating device. The main timing module 10 is a phase locked ring oscillator 100. This time, The timing module u is composed of a programmable delay unit 110 (programmable delay unit), in which the main timing module is a closed loop system (close loop system), because it is feedback control, it can obtain very high However, the timing module u is 10, an open-loop system. 'To maintain the accuracy of its timing,' the calibration action is particularly important '. However, calibration is a time-consuming and requires considerable labor and technical work. It can be done by ordinary people, so it needs a lot of money to cultivate talents. The third diagram is a block diagram of the second type of timing generating device that is known. The difference from the first type of timing generating device that is known in FIG. 15 is that due to the development of integrated circuit technology, the secondary timing module 11 can be a locked phase. Delay line u〇 (Phase locked delay line) 'The coarse timing adjusted by the main timing module i 〇 is further processed to become a fine timing. The phase selection multiplexer U1 (phase selection multiplexer) selects the precise timing (refine timing), while 20 and 'Although accurate timing can be obtained from the timing module 11, the phase selection multiplexer 111 is located outside the locked phase cycle oscillator 100, so the timing accuracy is greatly affected by the solid state device ( high temperature coefficient of s〇Hd state devices), it is difficult to maintain a certain accuracy under the influence of different temperatures, so a temperature compensation machine is required. The paper size is suitable for China National Standard (CNS) A4. (2 丨 0 > < 297 public shame) (please read the note on the back before filling in this page)
五、發明説明（ 構且必須量測溫度 睹旦古此，t 乂决疋要補仏I ’再者’設計一個同 ' 、速且穩定的延遲單元是很困難的。 極鑑t斯’本發日月人累積多年從事該行業之經驗，積 攸研九如何增進時序的準確度，減小時序校準的成本 '去不只疋依賴快速的元件來製造快速的時序，而可容易的 '到相對的穩定度之具有自我校準能力的時序產生裝置。 本七月之主要目的係提供—種具有自我校準之時序產 生裝置，增進時序準確度，減小時序校準的成本，不只是 10 依賴快速的電子元件來產生快逮的時序，而可容易的達到 相對的穩定度。 15 本發明係根據外部的參考時脈進行產生時序的處理 其特徵在於係包含一主時序模組、一次時序模組及一校準 =组；其中該主時序模組，係根據該參考時脈輸出一粗調 時序；該次時序模組係包括有一延遲控制單元（De丨叮| Control Unit : DCU)及電壓控制延遲單元（v〇ltage| Controi led Delay Unit ·· VCDU)，並與該主時序模組成電 經 濟 部 智 慧 財 產 局 員 X 消 費 ΐ 社 印 製 20 氧連接，用以將该主時序模組所產生之粗調時序製作為 微調時序，再者，該電壓控制延遲單元（VCDU)係與該延遲 控制單元（DC10成電氣連接，並接收該延遲控制單元（DCU)| 之延遲控制訊號而調整該微調時序的相位；該校準模組係 包括有一相位偵測單元（Phase Detect Unit : PDU)、一相 位量測單元（Phase Measure Uni t : PMU)以及一相位補償單 元〔Phase Compensate Umt : PCU)，且與上述之主時序模 組的輸出及次時序模組的輸出成電氣連接，並比較該主時 ____ _______ 一―__ 本紙译尺度適用中國國家標率；CXS) Λ4規格（：U)x_ ?.97公釐） ---------- 45265 4 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（4 ) 序產生器輸出之粗調時序與該次時序模組輸出之微調時彳 而輸出一數位的相位補償訊號（phase compensatio. single)至該次時序模組之延遲控制單元，藉此，控制該4 時序模組調整時序，以達到所要求的相位差。 5 爰是，為達到上述之目的，本發明係包含一主時序术 組、一次時序模組及一校準模組；其_該主時序模組係术 據外部之參考時脈而輸出一粗調時序：該次時序模組係岁 該主時序模組成電氣連接，係包括有一延遲控制單元及一 電壓控制延遲單元，該電壓控制延遲單元係與該延遲控幸 10單元成電氣連接；該校準模組係包括有一相位彳貞測單元、 一相位量測單元以及一相位補償單元，且與.上述之主時片 模組的輸出及次時序模組的輸出成電氣連接，並比較該主 時序產生器輸出之粗調時序與該次時序模組輸出之微調畤 序’而輸出一數位的相位補償訊號至該次時序模組之延過 控制單元。 有關本發明為達上述目的、特徵所採用的技術手段及 其功效，茲例舉較佳實施例並配合圖式說明如下：第一圖係為習知之模組方塊圊。 第一圖係為第一種習知之方塊圖。 第二圖係為第二種習知之方塊圖。 第四圖係為本發明之模組方塊圖。 第五圖係為本發明之校準模組與次時序模組方塊圖。 第六圖係為本發明之相位偵測單元（pDU)電路圖。 第七圖係為本發明之相位差訊號波形圖。 15 20 本紙⑽適用中國涵準(CNS ) (請先聞讀背面之注意Ϋ項再填寫本頁) • nn. · 裝 -訂一 A7 A7 經濟部智慧財產局員工消費合作社印製 21 次時序模組 23參考時脈（CLKref) 2 5微調時序 31互斥或閘（x〇r) 34參考時序（TMrei) 36相位差訊號 371責任週期（Dr) 41取樣時脈輸入端 43相位差訊號输入端 50減法器 52相位差數值輸入端 6 2相位補償訊號輸入端 61電容器 73控制電壓輸入端 7i固定之電容器負載（Q) 五、發明説明（） V 5 ' 第八圖係為本發明之相位量測單元（PM(J)電路圖。 第九圖係為本發明之相位差訊號與取樣時脈波形圖。 第十圖係為本發明之相位補償單元（PCU)方塊圖。 第十一圖係為本發明之延遲控制單元（DCU)電路圖。 5 第十二圖係本發明之電壓控制延遲單元（VCDU)電路圖 圖號對照表： 20主時序模組 22校準模組 24粗調時序 26 相位補償訊號 3 相位偵測單元（PDU) 32、33多工器 35校準時序（TMcal) 37相位差訊號 4相位量測單元（PMU) 42相位差數值輪出端 410取樣時脈 5相位補償單元（pcu) 51暫存器 5 3相位補償訊號輸出端 6延遲控制單元（DCu) 6 0充電幫浦電路 63控制電壓（匕） 7電壓控制延遲單元（VCDU) 7 0電壓控制緩衝器 72固定輸出緩衝器 首先凊參閱第四圖所示，本發明係包括一主時序模 2 0、一次時序模組21以及一校準模組2 2 : 該主時序模組20係根據據參考時脈23(CLKref)輪 1〇 一粗調時序24 ; 該次時序模組21係與該主時序模組20成電氣連接 I I i t j 線 (請先閣讀背面之注意事項再填寫本頁) 本紙 m种 _ I:鱗 處 ；D 4 A7 ----------------B7 五、發明説明（） 6 用以將上述主時序模組20所產生之粗調時序24製作為一 微調時序25 ;V. Description of the invention (Construction and measurement of temperature is necessary. In order to solve this problem, it is very difficult to design the same, fast and stable delay unit. Furthermore, it is very difficult to design the same. The sun and moon people have accumulated many years of experience in the industry, and they have learned how to improve the accuracy of timing and reduce the cost of timing calibration. 'Go not only rely on fast components to make fast timing, but can easily' to relative Timing generator with self-calibration capability. The main purpose of this July is to provide a timing generator with self-calibration to improve timing accuracy and reduce the cost of timing calibration. It is not just 10 relying on fast electronics Components to generate fast timing, and can easily achieve relative stability. 15 The present invention is based on an external reference clock to generate timing processing. It is characterized by including a main timing module, a timing module and a Calibration = group; where the main timing module outputs a coarse adjustment timing according to the reference clock; the timing module includes a delay control unit (De 丨 ding | Contr ol Unit: DCU) and voltage control delay unit (V〇ltage | Controi led Delay Unit ··· VCDU), and the main timing module forms the Intellectual Property Bureau of the Ministry of Electricity and Economics X Consumer Electronics Co., Ltd. printed 20 oxygen connection for The coarse timing sequence generated by the main timing module is made into a fine timing sequence. Furthermore, the voltage control delay unit (VCDU) is electrically connected to the delay control unit (DC10) and receives the delay control unit (DCU) | The delay control signal adjusts the phase of the fine-tuning timing; the calibration module includes a phase detection unit (Phase Detect Unit: PDU), a phase measurement unit (Phase Measure Uni t: PMU), and a phase compensation unit [ Phase Compensate Umt: PCU), and is electrically connected to the output of the primary timing module and the output of the secondary timing module, and compare the main time ____ _______ one __ This paper translation standard applies to China's national standard; CXS) Λ4 specification (： U) x_? .97 mm) ---------- 45265 4 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (4) The rough output of the sequence generator Timing When a fine adjustment with the output of the timing module is performed, a digital phase compensation signal (phase compensatio. Single) is output to the delay control unit of the timing module, thereby controlling the 4 timing module to adjust the timing to achieve The required phase difference. 5 Yes, in order to achieve the above purpose, the present invention includes a master timing group, a timing module and a calibration module; its _ the master timing module is based on an external reference clock to output a coarse adjustment Timing: The timing module is electrically connected to the main timing module, and includes a delay control unit and a voltage control delay unit. The voltage control delay unit is electrically connected to the delay control unit 10; the calibration The module system includes a phase measurement unit, a phase measurement unit, and a phase compensation unit, and is electrically connected to the output of the above-mentioned main time module and the output of the time-sequence module, and compares the main timing The coarse adjustment timing of the generator output and the fine adjustment sequence of the output of the timing module are output, and a digital phase compensation signal is output to the delay control unit of the timing module. Regarding the technical means adopted by the present invention to achieve the above-mentioned objects and features, and their effects, the preferred embodiments are illustrated together with the drawings as follows: The first figure is a conventional module block 圊. The first picture is a block diagram of the first kind. The second diagram is a second conventional block diagram. The fourth figure is a block diagram of the module of the present invention. The fifth figure is a block diagram of the calibration module and the sub-sequence module of the present invention. The sixth figure is a circuit diagram of a phase detection unit (pDU) of the present invention. The seventh diagram is a phase difference signal waveform diagram of the present invention. 15 20 This paper is applicable to China Standards (CNS) (please read the notes on the back before filling in this page) • nn. · Binding-A7 A7 Printed 21 times by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Group 23 reference clock (CLKref) 2 5 fine-tuning timing 31 mutually exclusive OR gate (x〇r) 34 reference timing (TMrei) 36 phase difference signal 371 duty cycle (Dr) 41 sampling clock input terminal 43 phase difference signal input terminal 50 subtracter 52 phase difference value input terminal 6 2 phase compensation signal input terminal 61 capacitor 73 control voltage input terminal 7i fixed capacitor load (Q) 5. Description of the invention () V 5 'The eighth figure is the phase quantity of the invention Measurement unit (PM (J) circuit diagram. The ninth diagram is a phase difference signal and sampling clock waveform diagram of the present invention. The tenth diagram is a block diagram of the phase compensation unit (PCU) of the present invention. The eleventh diagram is The circuit diagram of the delay control unit (DCU) of the present invention. 5 The twelfth diagram is the comparison chart of the circuit diagram of the voltage control delay unit (VCDU) of the present invention: 20 main timing module 22 calibration module 24 coarse adjustment timing 26 phase compensation signal 3 Phase Detection Unit (PDU) 32 33 Multiplexer 35 Calibration timing (TMcal) 37 Phase difference signal 4 Phase measurement unit (PMU) 42 Phase difference value wheel output 410 Sampling clock 5 Phase compensation unit (PCU) 51 Register 5 3 Phase compensation signal Output 6 Delay Control Unit (DCu) 6 0 Charge Pump Circuit 63 Control Voltage (Dagger) 7 Voltage Control Delay Unit (VCDU) 7 0 Voltage Control Buffer 72 Fixed Output Buffer First, refer to the fourth figure, this The invention includes a main timing module 20, a primary timing module 21, and a calibration module 22: the main timing module 20 is based on the reference clock 23 (CLKref) wheel 10 and a coarse adjustment timing 24; the time The timing module 21 is electrically connected to the main timing module 20 by the II itj cable (please read the precautions on the back before filling out this page). Type m of this paper _ I: scale; D 4 A7 ------ ---------- B7 V. Description of the invention () 6 is used to make the coarse timing sequence 24 generated by the above main timing module 20 into a fine timing sequence 25;
(請先閱讀背面之注項再填寫本頁J 該校準模組22係與該主時序模組2〇的輸出及次時序 模組21的輸出成電氣連接，並比較該主時序產生模組 5輸出之粗調時序24與該次時序模組21輸出之微調時序25 ’而輸出一數位的相位補償訊號26至該次時序模組21， 藉此，控制該次時序模組21調整時序，以達到所要求的相 位差。 請參閱第五圖所示，校準模組22係包括有一相位偵測 1〇單元3(PDU)、一相位量測單元4(PMU)以及一相位補償單元 5(PCU)； 次時序模組21係包括有一延遲控制單元6(DCU)及一 電壓控制延遲單元7(VCDU); 經濟部智慧財產局貝工消費合作社印製 请參閱第五、六圖所示，在本例中，相位偵測單元3 15係具有一互斥或閘（X〇R)3卜多工器32、33以及一相位差 訊號輸出端36，該多工器32、33分別與XOR 31成電器連 接，該多工器32係選擇主時序模組2〇所產生的粗調時序 24之其中一個時序為參考時序34( reference TMref: ’該多工器33係選擇次時序模組21所產生的微調時序25 20之其中一個時序為校準時序35(calibration timing: TMcai) ’該TMref 34訊號與TMcal 35訊號輸入該XOR 31並產 生如第七圖所示之相位差訊號36(phase difference)且輸 出至如第八圖所示之相位量測單元（PMU)4之相位差訊號輸 入端43。 制 2H)X2；^--- 五、發明説明 10 15 A7 B7 經濟部智慧財產局員工消費合作杜印製 20 請參閱第八圖所示，相位量測單元4(PMU)，在本例中 ’係為一數位之計數器結構（digital counter)且具有一相 位差訊號輸入端43、一取樣時脈輸入端41以及一相位差 數值輸出端42，係將第七圖之相位差訊號36輸入至該相 位差sfl號輸入端43，並由該相位差數值輸出端42輸出轉 換為數位的相位差數值。 請參閱第八、九圖所示，相位差訊號37係具有一週期 370(了）與一責任週期371( a)，該取樣時脈410係於該週 期370(Τ)中具有κ次脈波之時脈，該相位量測單元4(pmu) 係藉由該取樣時脈410決定取樣與計數之作動，且根據該 取樣時脈410之脈波對該相位差訊號37進行取樣，當該取 樣時脈410為正值且該相位差訊號3 7為正值則該相位量測 單元（PMU) 4之相位差數值加一 ’因此，κ值越大則該相位 量測單元（PMU)4之相位差數值越接近該責任週期371(q) 之實際值’且由該相位差數值輸出端42輸出相位差數值至 如第十圖所示之相位補償單元（PCU)5。 請參閱第八、十圖所示’該相位補償單元5(PCU)，名 本例中係可為一減法器50 ’其係具有一暫存器51、相位I 數值輸入端52以及一相位補償訊號輸出端53，該相位J 數值輸入端52係與係與相位量測單元4(PMU)之相位差窦 值輸出端42成電氣連接’並將該相位差數值輸出端42軺 出之相位差數值輸入該相位補償單元5(PCU)，根據存放方 暫存器51.内之统計平均值與該相位差數值比較 < 並產生-數位之相彳立補償訊號、d 1 g i ta 1 phase compen_sa 1： 1 on s i gna 1 ^------IT------0 (請先聞讀背面之注意事項再填寫本頁) 本紙mut晒家標举. ，C'NS ) Λ4規格；2ΐ0 x 297公釐— 五、發明説明（ 10 15 A7 B7 經濟部智慧財產局貝工消費合作社印製 20 ，由該相位補償訊號輸出端53輸出至如第五圖所示之次時 序模組21的延遲控制單元6 〇 請參閱第十、十一圖所示，延遲控制單元6(DCU)，在 本例中其係具有一相位補償訊號輸入端62、一充電幫浦電 路60(charge pump circuit)、一電容器61以及一控制電 壓63(〇，係用以將相位補償單元5(PCU)所輸出的數位之 相位補償訊號轉換為類比之控制電壓63(匕），該充電幫浦 電路60係充電與放電該電容器61(C)至期望之控制電壓 63(乙），由相位補償訊號輸入端62將該相位補償單元5(PCU: 輸出的相位補償訊號輸入該充電幫浦電路60，以控制對該 電容器61充電量與放電量的大小，並將該控制電壓63(匕〕 輸出至第十二圖之電壓控制延遲單元7(VCDU)的控制電壓 輸入端73。 請參閱第十一、十二圖所示，電壓控制延遲單元7(VCDU: 係包括有一控制電壓輸入端73、一電壓控制緩衝器 TOCvoltage controlled variable gain buffer ： VCB) ' 一固定之電容器負載71(Ct)及一固定輸出緩衝器72(f ixed output buffer : Buf)，該控制電壓輸入端73係與第十— 圖之控制電壓63(R)成電氣連接，該電壓控制延遲單元 7(VCDU)係根據该控制電壓63(匕）控制參考時序34(TMref) 的延遲時間，並輸出校準時序35(TMcal)。 綜上所述，本發明之『具有自我校準之時序產生裝置 』具備以下之優點： 1.由於本發明係為一閉迴路系統，且於時序的輸出端做 n· 1^— - «m -- I— n^i nn ^^1 I - - - ....... 1^1 i請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用中國固家標準（CNS ) Μ規格（210Χ297公釐） 經濟部智慧財產局員工消費合作钍印製 A7 ----------B7 五、發明説明（) 一^" ~~~~—-〜 9 相位的檢查’因此可確保時序輸出點之準破度。 2, 本發明係直接量測相位，換句話說是自我校準，因此 不再需要校準的程序。 3. 係直接使用數位的平均數值，因此不需要類比與數位 5 間的轉換，即可達到更高的準確度與節省成本。 4·使用統計平均值，因此可根據系統的需求彈性的調整 ’需要尚準確度或高速度的系統響應’可使用相同的結 構達成。 ~ 5. 選擇最適當的粗調時序作為延遲的起始時序，因此不 需要非常快速的延遲單元，而可以設計來提供高準確度 與高穩定度。 & 6. 選擇最適合的粗調時序提供相位偵測，因此可穩定的 改進相位量測的準確度。 本案於申請之前並未有相同之構造之具有自我校準之 時序產生裝置公開或使用在先，爰依法提請新型專利之申 請，並祈旱賜新型專利權，惟前述有關本發明之内容，僅 係本發明之較佳可行實施例而已，任何基於本發明如下申 請專利範圍所作之適當修正，均應包含於本發明之專利矿 疇！ η 先 閱 背 1¾ 意 事 項 再 寫 本 頁 裝 10 訂 線 本故張义度適用中國國家標糸.；CNS ΐ Α4規格；公釐(Please read the note on the back before filling in this page. J The calibration module 22 is electrically connected to the output of the primary timing module 20 and the output of the secondary timing module 21, and the primary timing generation module 5 is compared. The coarse adjustment timing 24 of the output and the fine adjustment timing 25 'of the secondary timing module 21 are output, and a digital phase compensation signal 26 is output to the secondary timing module 21, thereby controlling the secondary timing module 21 to adjust the timing to The required phase difference is achieved. As shown in the fifth figure, the calibration module 22 includes a phase detection unit 10 (PDU), a phase measurement unit 4 (PMU), and a phase compensation unit 5 (PCU). ); The sub-sequence module 21 series includes a delay control unit 6 (DCU) and a voltage control delay unit 7 (VCDU); printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, please refer to the fifth and sixth figures. In this example, the phase detection unit 315 has a mutually exclusive OR gate (XOR) 3 multiplexer 32, 33 and a phase difference signal output terminal 36, the multiplexer 32, 33 and XOR 31 respectively It becomes an electrical connection. The multiplexer 32 selects one of the coarse timings 24 generated by the main timing module 20. One timing is reference timing 34 (reference TMref: 'The multiplexer 33 selects the fine-tuning timing 25 generated by the secondary timing module 21 and one of the timings is the calibration timing 35 (calibration timing: TMcai)' The TMref 34 signal And TMcal 35 signals are input to the XOR 31 and a phase difference signal 36 (phase difference) shown in the seventh figure is generated and output to the phase difference signal input terminal 43 of the phase measurement unit (PMU) 4 shown in the eighth figure 2H) X2; ^ --- V. Description of the invention 10 15 A7 B7 Employee consumption cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed 20 Please refer to the eighth figure, phase measurement unit 4 (PMU), in this example “Zhong” is a digital counter structure with a phase difference signal input terminal 43, a sampling clock input terminal 41 and a phase difference value output terminal 42. The phase difference signal 36 of the seventh figure is input. To the phase difference sfl input terminal 43 and output from the phase difference value output terminal 42 into a digital phase difference value. Please refer to the eighth and ninth diagrams, the phase difference signal 37 has a period of 370 (L) With a duty cycle of 371 (a), the The sample clock 410 is the clock with the κ sub-pulse in the period 370 (T). The phase measurement unit 4 (pmu) determines the sampling and counting action by the sampling clock 410, and according to the sampling The pulse wave of the clock 410 samples the phase difference signal 37. When the sampling clock 410 is positive and the phase difference signal 37 is positive, the phase difference value of the phase measurement unit (PMU) 4 is increased by one. 'Therefore, the larger the κ value, the closer the phase difference value of the phase measurement unit (PMU) 4 is to the actual value of the duty cycle 371 (q)' and the phase difference value is output from the phase difference value output terminal 42 to the first Phase compensation unit (PCU) 5 shown in Figure 10. Please refer to the eighth and tenth illustrations, 'The phase compensation unit 5 (PCU), which is a subtractor 50 in this example', has a register 51, a phase I value input terminal 52, and a phase compensation. Signal output terminal 53, the phase J value input terminal 52 is electrically connected to the phase difference sinus value output terminal 42 of the phase measurement unit 4 (PMU), and the phase difference is output from the phase difference value output terminal 42. The value is input to the phase compensation unit 5 (PCU), and the phase difference value is compared with the statistical average value in the register 51. of the depositor < and a digital-phase-independent compensation signal, d 1 gi ta 1 phase compen_sa is generated. 1: 1 on si gna 1 ^ ------ IT ------ 0 (Please read the precautions on the back before filling in this page) This paper is marked by mut .., C'NS) 4 specifications 2ΐ0 x 297 mm — V. Description of the invention (10 15 A7 B7 Printed by Shelley Consumer Cooperative of Intellectual Property Bureau, Ministry of Economic Affairs, 20, and output from phase compensation signal output terminal 53 to the secondary timing module as shown in the fifth figure 21 delay control unit 6 〇 Please refer to the tenth and eleventh diagrams, the delay control unit 6 (DCU), in this example, its attachment There is a phase compensation signal input terminal 62, a charge pump circuit 60, a capacitor 61, and a control voltage 63 (0), which are used to phase-compensate the digital output signals from the phase compensation unit 5 (PCU). Converted to an analog control voltage 63 (dagger), the charging pump circuit 60 charges and discharges the capacitor 61 (C) to the desired control voltage 63 (B), and the phase compensation unit 5 is input by the phase compensation signal input terminal 62 (PCU: The output phase compensation signal is input to the charging pump circuit 60 to control the amount of charge and discharge of the capacitor 61, and the control voltage 63 (dagger) is output to the voltage control delay unit of the twelfth figure 7 (VCDU) control voltage input terminal 73. Please refer to the eleventh and twelfth figures. The voltage control delay unit 7 (VCDU: includes a control voltage input terminal 73 and a TOC voltage controlled variable gain buffer : VCB) 'A fixed capacitor load 71 (Ct) and a fixed output buffer 72 (fixed output buffer: Buf), the control voltage input terminal 73 is electrically connected to the tenth-control voltage 63 (R) Connection, the voltage control delay unit 7 (VCDU) controls the delay time of the reference timing 34 (TMref) according to the control voltage 63 (dagger), and outputs the calibration timing 35 (TMcal). In summary, the present invention " The timing generating device with self-calibration has the following advantages: 1. Since the present invention is a closed loop system, and n · 1 ^ —-«m-I— n ^ i nn ^^ 1 I---....... 1 ^ 1 i Please read the precautions on the back before filling out this page) This paper size is applicable to China Good Standards (CNS) M specifications (210 × 297 mm) Wisdom of the Ministry of Economic Affairs A7 ---------- B7 printed by the staff of the property bureau for consumer cooperation V. Description of the invention () a ^ " ~~~~ --- ~ 9 Phase check 'so it can ensure the accuracy of timing output points Break degree. 2. The present invention measures the phase directly, in other words self-calibration, so the calibration procedure is no longer needed. 3. The digital average value is directly used, so no conversion between analog and digital 5 is needed to achieve higher accuracy and cost savings. 4. The statistical average value is used, so it can be adjusted elastically according to the needs of the system. ‘A system response that still requires accuracy or high speed’ can be achieved using the same structure. ~ 5. Select the most appropriate coarse timing as the start of the delay, so there is no need for a very fast delay unit, but it can be designed to provide high accuracy and stability. & 6. Select the most suitable coarse timing to provide phase detection, so the accuracy of phase measurement can be improved steadily. Before this application, the self-calibrating timing generating device with the same structure was not disclosed or used before. It applied for a new patent in accordance with the law, and prayed for the grant of a new patent. However, the foregoing content of the present invention is only for Only the best feasible embodiment of the present invention, any appropriate amendment based on the scope of the following patent application of the present invention should be included in the patent domain of the present invention! η Read and memorize 1¾ the items of interest first, and then write this page with 10 stitches. Therefore, Zhang Yidu applies Chinese National Standards; CNS ΐ Α4 specifications; mm