4 51213 A7 B7 五、發明說明（丄） 發明領域 {請先閱讀背面之注意事項再填寫本頁) 本發明係關於一種週邊記憶體連接線路之測試裝置及其 方法，特別是關於一種可自動測試一週邊記憶體連接線路 之位址匯流排及資料匯流排之裝置及其方法。 發明背景 經濟部智慧財產局員工消費合作社印製 圖1係習知之一影像處理系統，包含一影像輸入機構 11、一影像處理單元12、一顯示機構13、一微控制器18及 一週邊記憶體14。該影像輸入機構11，例如為一類比數位 轉換器（analog to digital converter)或一影像解碼器（video decoder)，連接至該影像處理單元12。該影像處理單元12 可為一數位控制器，用於執行影像處理之動作，例如作影 像解析度的轉換、畫面更新頻率轉換（frame rate conversion) 或自動調整（auto tune)等。該週邊記憶體14、該微控制器18 及該顯示機構13連接至該影像處理單元12，該顯示機構13 可為一平面顯示器（flat panel display)。該微控制器18用於設 定影像處理之參數。該影像處理系統之動作如下，首先該 影像處理單元12擷取該影像輸入機構11之圖素（texel)，並 透過一位址匯流排15及一資料匯流排16將該圖素存入該週 邊記憶體14，然後該影像處理單元12依據輸入與顯示解析 度之比例將該圖素轉換為對應的像素（pixel)並輸出於該顯 示機構13。 習知之影像處理系統之資料傳輸路徑（data transmission path)完全由位於該影像處理單元12及謓週邊記憶體14之間 之位址匯流排15及資料匯流排16控制，若該位址匯流排15 -4 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 451213 A7 ----------- B7 五、發明說明（2 ) (請先閱讀背面之注意事項再填寫本頁) 或該資料匯流排16有任何錯誤，例如一固定錯誤（Mud at 細It)、短路（short)或斷路（〇pen)，則將導致該影像處理系 統在顯示上出現錯誤。目前業界用於量測該位址匯流排Μ 或資料匯流排16錯誤之方式係使用一邏輯分析儀（1〇gic analyzer)或示波器（〇sciU〇sc〇pe) ’且由該影像處理系統之外 部加入複數組測試樣本’但上述測試方式須由系統人員花 費許多精神和時間才得以完成，往往造成研發時程的延 遲° 由以上的敘述可知’現行應用於影像處理系統之週邊記 憶體連接線路之測試方式並不能符合市場的需要。 發明之簡要説明 --線· 本發明之目的係為解決習知之週邊記憶體連接線路之測 試方式須花費許多猜神和時間才得以完成之缺點。為了達 到上述目的，本發明提供一種週邊記憶體連接線路之自我 測試裝置及其方法，並提出—套測試流程之演算法及複數 組測試樣本，可自動測試連接於該週邊記憶體之位址匯流 排及資料匯流排之正確性。+ 經濟部智慧財產局員工消費合作社印製 本發明在裝置方面包含一測試樣本產生器25、一記憶體 控制模组24、一比較器23及一輸出模組22。該測試樣本產 生器25用於產生一測試該位址匯流排15及該資料匯流排16 内之未相鄰線路是否有錯誤之第一測試樣本，及測試該資 料匯流排I6之相鄰線路是否有錯誤之第二測試樣本和第三 測試樣本。該記憶體控制模組24連接於該測試樣本產生器 25 ’用於產生測試該週邊記憶體14之位址及控制信號。該 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚） 經濟部智慧財產局員工消費合作社印製 4 β J 2 1 3 Α7 ' --------------- 五、發明說明（3 ) 比車父器23用於比較該測試樣本產生器25之第一至第三測試 樣本及m資料匯流排16之值是否相同。該輸出模組22連接 於孩比較器23 ’用於記錄測試結果，當該比較器23之比較 '结果為錯誤時，則再記錄測試樣本及該測試樣本位於該週 邊死憶體I4之位址。 本發明在方法方面包含步騾51〜59。步驟51為進入本發 明 < 自我測試程序。步驟52為將第一測試樣本依序窝入該 週邊記憶體14内。步驟53為由該週邊記憶體14依序讀出資 料並與第—測試樣本比較。若比較之結果不同則進入步驟 59 ’即停止自我測試並報告測試結果、錯誤發生之位址及 β錯誤之測試樣本號碼。若比較之結果相同則進入步騾 54 ’即將第二及第三測試樣本依序交替窝入該週邊記憶體 14 °步騾55為由該週邊記憶體14讀出資料並與第二及第三 4試樣本交替比較D若比較之結果不同則進入步騾59，即 停止自我測試並報告測試結果、錯誤位址及測試樣本號 碼°若比較之結果相同則進入步驟56，即將第三及第二測 4樣本依序交替窝入該週邊記憶體14，和步驟54不同的 是’步驟56係先寫入第三測試樣本再窝入第二測試樣本。 步驟57為由該週邊記憶體14讀出資料並與第三及第二測試 樣本交替比較。若比較之結果不同則進入步驟59，即停止 自我測試並報告測試結果、錯誤發生之位址及該錯誤之測 試樣本號碼。若比較之結果相同則進入步騾58，即結束自 我測試’並報告測試結果，亦表示測試後的週邊記憶體連 接線路是正確的。 ___ ~ 6 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公复] -----------!'、--------，訂---------線 (請先閱讀背面之沒意事項再填寫本頁}4 51213 A7 B7 V. Description of the invention (丄) Field of invention {Please read the precautions on the back before filling this page) The invention relates to a test device and method for peripheral memory connection lines, and more particularly to an automatic test Device and method for address bus and data bus of peripheral memory connection line. BACKGROUND OF THE INVENTION An image processing system printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics is one of the conventional image processing systems, which includes an image input mechanism 11, an image processing unit 12, a display mechanism 13, a microcontroller 18, and a peripheral memory. 14. The image input mechanism 11 is, for example, an analog to digital converter or a video decoder, and is connected to the image processing unit 12. The image processing unit 12 may be a digital controller for performing image processing operations, such as converting image resolution, frame rate conversion, or auto tune. The peripheral memory 14, the microcontroller 18 and the display mechanism 13 are connected to the image processing unit 12. The display mechanism 13 may be a flat panel display. The microcontroller 18 is used to set parameters for image processing. The operation of the image processing system is as follows. First, the image processing unit 12 captures the texel of the image input mechanism 11 and stores the pixel into the periphery through an address bus 15 and a data bus 16. The memory 14, and then the image processing unit 12 converts the pixels into corresponding pixels according to a ratio of input and display resolution and outputs the pixels to the display mechanism 13. The data transmission path of the conventional image processing system is completely controlled by the address bus 15 and the data bus 16 located between the image processing unit 12 and the peripheral memory 14. If the address bus 15 -4-This paper size is in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 451213 A7 ----------- B7 V. Description of the invention (2) (Please read the note on the back first Please fill in this page again) or if there is any error in the data bus 16, such as a fixed error (Mud at fine It), short circuit (short) or open circuit (〇pen), it will cause the image processing system to display errors. . The current method used by the industry to measure the address bus M or the data bus 16 error is to use a logic analyzer (10gic analyzer) or an oscilloscope (〇sciU〇sc〇pe) and the image processing system. Externally added a complex array of test samples', but the above test method must be completed by system staff with a lot of effort and time, often causing a delay in the R & D time course. From the above description, we can see that the current peripheral memory connection lines used in image processing systems The test method does not meet the needs of the market. Brief Description of the Invention-Lines · The purpose of the present invention is to solve the shortcomings of the conventional testing method of peripheral memory connection lines that require a lot of guesswork and time to complete. In order to achieve the above object, the present invention provides a self-testing device and method for a peripheral memory connection line, and proposes a set of algorithm and test samples for a test process, which can automatically test the address confluence connected to the peripheral memory. The correctness of the bus and data bus. + Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economics The present invention includes a test sample generator 25, a memory control module 24, a comparator 23, and an output module 22 in terms of equipment. The test sample generator 25 is used to generate a first test sample for testing whether there is an error between non-adjacent lines in the address bus 15 and the data bus 16, and whether the adjacent lines of the data bus I6 are There are errors in the second and third test samples. The memory control module 24 is connected to the test sample generator 25 'for generating addresses and control signals for testing the peripheral memory 14. The size of this paper is in accordance with Chinese National Standard (CNS) A4 (210 X 297). Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4 β J 2 1 3 Α7 '------------ --- V. Description of the invention (3) The car master device 23 is used to compare whether the values of the first to third test samples and the m data bus 16 of the test sample generator 25 are the same. The output module 22 is connected to the child comparator 23 'for recording the test result. When the comparison result of the comparator 23 is an error, then the test sample and the test sample are located at the address of the peripheral memory body I4. . The method includes steps 51 to 59 in terms of methods. Step 51 is to enter the present invention < self-test procedure. Step 52 is to sequentially nest the first test sample into the peripheral memory 14. Step 53 is to sequentially read out data from the peripheral memory 14 and compare it with the first test sample. If the results of the comparison are different, then proceed to step 59 ', that is, stop the self-test and report the test result, the address where the error occurred, and the test sample number of the β error. If the result of the comparison is the same, proceed to step 54 ', that is, the second and third test samples are sequentially nested in the peripheral memory 14 °. Step 55 is to read data from the peripheral memory 14 and compare it with the second and third. 4 Samples are compared alternately. D If the results of the comparison are different, go to step 59, that is, stop the self-test and report the test results, error address and test sample number. The second test 4 samples alternately nested into the peripheral memory 14 in sequence. The difference from step 54 is that 'step 56 is first written into the third test sample and then nested into the second test sample. Step 57 is to read data from the peripheral memory 14 and compare it with the third and second test samples alternately. If the comparison results are different, then proceed to step 59, that is, stop the self-test and report the test result, the address where the error occurred, and the test sample number of the error. If the results of the comparison are the same, proceed to step 58, which ends the self-test 'and reports the test results, which also indicates that the peripheral memory connection lines after the test are correct. ___ ~ 6-This paper size is applicable to China National Standard (CNS) A4 (210 χ 297 public reply) -----------! ', --------, order --- ------ line (Please read the unintentional matter on the back before filling in this page)
五、發明說明（ 本發明將配合後附圖式來說明，其中， 圖1係習知之影像處理系統圖； 圖2係本發明之一實施例之系統圖； 圖3係本發明之週邊記憶體之儲存 '之一實施例 圖4係本發明之測試樣本之一實施例. 圖5係本發明之測試流程圖。 jt件符號說明 經濟部智慧財產局員工消費合作社印製 11影像輸入機構 13顯示機構 15 位址匯流排 17控制匯流排 20自我測試裝置 22輸出模組 24記憶體控制模組 3 1第一儲存區塊 41第一測試樣本 43第三測試樣本 較佳實施例說明 圖2係本發明之一實施例之系統圖，包含一影像輸入機 構11、一影像處理單元12、一自我測試裝置20、—週邊記 憶體14、一微控制器is及一顯示機構π。和圖i之钟構不 同的是圖2之結構加入一自我測試裝置20，在影像處理 統初次完成並開始除錯時，利用微控制器啟動影像處理 一 7 一 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 12衫像處理單元 14週埯記憶體 16資科隨流排 18微检制器 23比較器 25測試樣本產生器 32第二儲存區塊 42第二測試樣本 (請先閱讀背面之注意事項再填寫本頁) · 丨線· 451213 A7 B7 五、發明說明（5 > 經濟部智慧財產局員工消費合作社印製 單元内之自我測試裝置20，該自我測試裝置20即自行產生 複數個測試樣本，並儲存至該週邊記憶體14。之後，再由 該週邊記憶體14讀出測試樣本，並與原先該自我測試裳置 20所產生的測試樣本比較，若兩者不同則視為有錯誤發 生’並經由該微控制器18顯示該錯誤樣本之編號及該錯誤 樣本位於該週邊記憶體14的位址。該自我測試裝置2〇包含 一記憶體控制模組24、一測試樣本產生器25 ' —比較器23 及一輸出模組22。該記憶體控制模組24為該自我測試裝置 20之控制中心，其負責產生存取該週邊記憶體14之位址及 控制信號。該自我測試裝置2〇相對於該週邊記憶體Μ有兩 個週期’分別為寫入週期及讀取週期。在寫入週期時，該 記憶體控制模組24通知該測試樣本產生器25產生相對應之 測試樣本’並依序（例如由最低的記憶體位置至最高的記 憶體位置）窝入該週邊記憶體14。在讀取週期時，該記憶 體控制模組24產生位址及控制信號並讀取該週邊記憶體14 在該位址信號之資料，該比較器23以該週邊記憶體14讀出 的資料及該測試樣本產生器25之測試樣本進行比對。若發 現比對的結果為不相等時，則视為有錯誤發生，並將該錯 »吳之測式樣本編號及該測試樣本位於該週邊記憶體14之位 址傳至一輸出模組22。該輸出模组22可包含複數個用於儲 存錯誤測試樣本之編號及該測試樣本位於該週邊記憶體丄4 之位址之暫存器及一微控制器輸出介面等功能，亦可用於 將該記憶體控制模组24所產生之一個二維位址轉換為一個 一維位址，以方便該微控制器18顯示該微控制器Μ連接 _ 一 8 _ 本紙張尺度適^中國國家標準（CNS)A4規格（210 X 297公爱)------ 4*121 3 A7 B7 五、發明說明（6 ) 於該輸出模組22 ’系統人員可程式化該微控制器18而讀取 測試樣本比較的結果，並分析所顯示之錯誤測試樣本編號 及該測試樣本位於該週邊記憶體14之位址，而可快速找出 發生錯誤之原因。 圖3係本發明之週邊記憶體之儲存方式之一實施例。在 本實施例中係將該週邊記憶體14以三顆容量各為1M* 16位 元（bit)之同步動態隨機存取記憶體（SDRAM)组成1M*48位 元之記憶體結構。該記憶體結構分為兩個儲存區塊 (bank)，分別為第一儲存區塊（βα=0)及第二儲存區塊 (BA=1)。該第一儲存區塊31及第二儲存區塊32各包含256 個行位址及2048個列位址，每個行位址與列位址的二維組 合可定址出一記憶單元（memory cell)，其寬度為48位元。 該週邊記憶體14亦可以二顆容量各為1M* 16位元之動態隨 機存取記憶體组成1M*48位元之記憶體結構，而僅將位元 16〜23及40〜47空著不使用。以上之記憶體結構僅表示為 一可行之實施例，並非用於限制本發明之用途。 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) -線- 圖4係本發明之測試樣本之一實施例，包含第一至第三 測試樣本41〜43。第一測試樣本41記錄該週邊記憶體14之 二維位址信號，其中符號C〇l[7:0]為二進位之行位址之位 元7至位元0，/(：〇1[7:0]為<：〇1[7:0]取補數；11〇界[7:〇] 為二進位之列位址之位元7至位元〇，/ r〇w[7:〇]為 Row [ 7 : 0 ]取補數；R0W [ 10 : s ]為二進位之列位址之位元 10至位元8，/ R〇w[l〇:8]為Row[10:8]取補數；BA指出 為第一或第二儲存區塊，/ BA為BA之二進位值取補數； 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公楚) ----- Α7 Β7 451 2 1 五、發明說明（ 1 [ 7 . Ο ]㊉BA為Col [ 7 : Ο ]之位元7至ο與BA經互斥或 (EXOR)邏輯運算後再組合而成共8位元之二進位數。第一 4試樣本41將一進位之該週邊記憶體14位址之列位址及其 補數、行位址及其補數和儲存區塊之編號及其補數和行地 址與儲存區塊編號之互斥或邏辑運算值互相交錯儲存，以 檢測位址匯流排15與資料匯流排16之未相鄰線路的錯誤。 原則上，若孩位址匯流排15及該資料匯流排16没有發生錯 '•吳，則該第一測試樣本W應該相等於由該週邊記憶體14讀 出的資料。而若該週邊記憶體14之„個列位址線、行位址 線或儲存區塊位址線發生錯誤，例如匯流排之兩個相鄰線 路發生短路，則該第一測試樣本41將被儲存於該週邊記憶 體14内之一錯誤位址，因此藉由讀取該週邊記憶體之資 料和第一測試樣本41比較，若發現不相等，即代表有錯誤 發生。第二測試樣本42及第三測試樣本U各儲存一固定 值’分別為十穴進位的55及AA ’其相對的二進位值為 01010101及1〇1〇1〇1(^因為第二測試樣本42及第三測試樣 本43之二進位表示法之相鄰位元係處於互補之狀態（即由1 變成〇，或由0變成1 )，因此可作為測試該資料匯流排16 之相鄰連接線路之正確性。和第一測試樣本41相同之方 去’可以藉由先窝入該週邊記憶體14再讀出，而與該第二 測試樣本42及第三測試樣本43比較。若比較之結果為不相 等’即代表資料匯流排16有錯誤發生。 圖5係本發明之測試流程圖。步驟51為進入本發明之自 我測試程序。步驟52為將第一測試樣本依序窝入該週邊記 本紙張尺度適用中國國家標準（CNS)A4規格（210 χ 297公釐） (請先閱讀背面之注意事項再填寫本頁) 訂： --線 經濟部智慧財產局員工消費合作杜印製V. Description of the invention (The present invention will be described in conjunction with the following drawings. Among them, FIG. 1 is a conventional image processing system diagram; FIG. 2 is a system diagram of an embodiment of the present invention; and FIG. 3 is a peripheral memory of the present invention. Figure 4 is an example of a test sample of the present invention. Figure 5 is a flowchart of the test of the present invention. The jt symbol indicates the printing by the Intellectual Property Bureau employee consumer cooperative of the Ministry of Economic Affairs 11 image input agency 13 display Institution 15 address bus 17 control bus 20 self test device 22 output module 24 memory control module 3 1 first storage block 41 first test sample 43 third test sample illustration of preferred embodiment The system diagram of an embodiment of the invention includes an image input mechanism 11, an image processing unit 12, a self-test device 20, a peripheral memory 14, a microcontroller is, and a display mechanism π. The difference is that a self-testing device 20 is added to the structure of FIG. 2. When the image processing system is first completed and debugging is started, the microcontroller is used to start the image processing. Standard (CNS) A4 (210 X 297 mm) 12-shirt image processing unit 14 weeks 埯 memory 16 asset stream 18 micro-controller 23 comparator 25 test sample generator 32 second storage block 42 Two test samples (please read the precautions on the back before filling this page) · 丨 line · 451213 A7 B7 V. Description of the invention (5 > Self-testing device 20 in the printing unit of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economy The self-test device 20 generates a plurality of test samples by itself and stores them in the peripheral memory 14. After that, the peripheral memory 14 reads out the test samples and compares them with the original test samples generated by the self-test dress 20 If the two are different, it is deemed that an error has occurred ', and the microcontroller 18 displays the number of the error sample and the address of the error sample in the peripheral memory 14. The self-test device 20 includes a memory control Module 24, a test sample generator 25'-comparator 23, and an output module 22. The memory control module 24 is the control center of the self-test device 20, which is responsible for generating access to the peripheral memory Address and control signal of 14. The self-test device 20 has two cycles with respect to the peripheral memory M, which are a write cycle and a read cycle. During the write cycle, the memory control module 24 notifies The test sample generator 25 generates corresponding test samples and sequentially inserts them into the peripheral memory 14 (for example, from the lowest memory position to the highest memory position). During the reading cycle, the memory control module The group 24 generates an address and a control signal and reads the data of the peripheral memory 14 at the address signal. The comparator 23 compares the data read by the peripheral memory 14 with the test sample of the test sample generator 25. Correct. If it is found that the comparison result is not equal, it is regarded as an error, and the error »Wu's test sample number and the address of the test sample in the peripheral memory 14 are transmitted to an output module 22. The output module 22 may include a plurality of functions for storing the number of the erroneous test sample and a temporary register of the test sample located at the address of the peripheral memory 丄 4 and a microcontroller output interface. A two-dimensional address generated by the memory control module 24 is converted into a one-dimensional address, so that the microcontroller 18 can display the microcontroller M connection. _ 8 _ This paper is suitable for China National Standard (CNS ) A4 specification (210 X 297 public love) ------ 4 * 121 3 A7 B7 V. Description of the invention (6) In the output module 22 'System personnel can program the microcontroller 18 to read and test The result of the sample comparison, and analysis of the displayed error test sample number and the location of the test sample in the peripheral memory 14 can quickly find the cause of the error. FIG. 3 is an embodiment of a storage method of a peripheral memory according to the present invention. In this embodiment, the peripheral memory 14 is composed of three synchronous dynamic random access memories (SDRAMs) each having a capacity of 1M * 16 bits (SDRAM) to form a memory structure of 1M * 48 bits. The memory structure is divided into two storage blocks (bank), which are a first storage block (βα = 0) and a second storage block (BA = 1). The first storage block 31 and the second storage block 32 each include 256 row addresses and 2048 column addresses. A two-dimensional combination of each row address and column address can address a memory cell. ), Which is 48 bits wide. The peripheral memory 14 can also be composed of two dynamic random access memories with a capacity of 1M * 16 bits each to form a memory structure of 1M * 48 bits, and only the bits 16 ~ 23 and 40 ~ 47 are left empty. use. The above memory structure is only shown as a feasible embodiment, and is not intended to limit the application of the present invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) -line-Figure 4 is an embodiment of the test sample of the present invention, including the first to third test samples 41 ~ 43 . The first test sample 41 records the two-dimensional address signal of the peripheral memory 14, in which the symbol C0 [7: 0] is the bit 7 to the bit 0 of the binary row address, / (: 〇1 [ 7: 0] is <: 01 [7: 0] complement; 11o boundary [7: 〇] is bit 7 to bit 0 of the binary column address, / r0w [7: 〇] is the complement of Row [7: 0]; R0W [10: s] is the bits 10 to 8 of the binary column address, / R0w [10: 8] is Row [10: 8] Complement number; BA indicates the first or second storage block, / BA is the complement number of the binary value of BA; This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 cm)- ---- Α7 Β7 451 2 1 V. Description of the invention (1 [7. 〇] ㊉BA is Col [7: 〇] Bits 7 to ο and BA are formed by mutual exclusion or (EXOR) logical operation and then combined There are 8 binary digits in total. The first 4 sample book 41 will carry a rounded row address and its complement of the 14 address of the peripheral memory, a row address and its complement, and the number of the storage block and The complement or row address and the storage block number are mutually exclusive or the logical operation values are interleaved and stored to detect the address bus 15 and the data bus 16 There is no error in the adjacent line. In principle, if the address bus 15 and the data bus 16 are not wrong, in principle, the first test sample W should be equal to the data read from the peripheral memory 14 If the column address line, the row address line or the storage block address line of the peripheral memory 14 is in error, for example, two adjacent lines of the bus are short-circuited, the first test sample 41 will An incorrect address is stored in the peripheral memory 14, so by reading the data in the peripheral memory and comparing it with the first test sample 41, if it is found to be different, it means that an error has occurred. The second test sample 42 And the third test sample U each store a fixed value of '55 and AA of the ten-point carry, respectively 'and their relative binary values are 01010101 and 1010101 (^ because the second test sample 42 and the third test The adjacent bits of the binary representation of sample 43 are in a complementary state (that is, from 1 to 0, or from 0 to 1), so they can be used to test the correctness of the adjacent connection lines of the data bus 16. and The first test sample 41 goes the same way 'can be borrowed The peripheral memory 14 is first nested and then read out, and compared with the second test sample 42 and the third test sample 43. If the comparison result is not equal ', it means that the data bus 16 has an error. Figure 5 is this The test flow chart of the invention. Step 51 is to enter the self-testing procedure of the present invention. Step 52 is to sequentially embed the first test sample into the peripheral notebook. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 x 297 mm). ) (Please read the notes on the back before filling out this page) Order:-Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs
經濟部智慧財產局員工消費合作社印製 五、發明說明（8 ) 憶體14内。步驟53為由該週邊記憶體14依序讀出資料並與 第—測試樣本41比較。若比較之結果不同則視為有錯誤發 生’並進入步驟59，即停止自我測試並報告測試結果、錯 誤發生之位址及測試樣本號碼。若比較之結果相同則進入 步騾54，即將第二測試樣本42及第三測試樣本43交替寫入 該週邊記憶體14。步驟55為由該週邊記憶體14讀出資料並 與第二測試樣本42及第三測試樣本43交替比較。若比較之 結果不同則视為有錯誤發生，並進入步驟59，即停止自我 測試並報告測試結果、錯誤發生之位址及測試樣本號碼。 若比較之結果相同則進入步驟56，即將第三測試樣本43及 第二測試樣本42交替寫入該週邊記憶體14，和步驟54不同 的是，步騾50係先窝入第三測試樣本43再寫入第二測試樣 本42。步騾w為由該週邊記憶體14讀出資料並與第三測試 樣本4·3及弟二測試樣本42交替比較。若比較之結果不同則 進入步驟59，即停止自我測試並報告測試結果、錯誤發生 之位址及測試樣本號碼❶若比較之結果相同則進入步驟 8即結束自我測式’並報告測試結果’此步驟亦表示測 試後的週邊記憶體連接線路是正確的。 本發明之技術内容及技術特點巳揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾；因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 (請先閱讀背面之注意事項再填寫本頁) 1&· -線- 11Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (8) In memory 14. Step 53 is to sequentially read data from the peripheral memory 14 and compare it with the first test sample 41. If the results of the comparison are different, it is considered that an error has occurred 'and the process proceeds to step 59, that is, the self-test is stopped and the test result, the address where the error occurred, and the test sample number are stopped. If the comparison result is the same, step 54 is executed, that is, the second test sample 42 and the third test sample 43 are alternately written into the peripheral memory 14. Step 55 is to read data from the peripheral memory 14 and compare it with the second test sample 42 and the third test sample 43 alternately. If the comparison results are different, it is deemed that an error has occurred, and it proceeds to step 59, that is, it stops the self-test and reports the test result, the address where the error occurred, and the test sample number. If the results of the comparison are the same, proceed to step 56, that is, the third test sample 43 and the second test sample 42 are alternately written into the peripheral memory 14. Unlike step 54, the step 50 is first nested into the third test sample 43 Write the second test sample 42 again. Step 骡 w reads out the data from the peripheral memory 14 and compares it with the third test sample 4.3 and the second test sample 42 alternately. If the comparison results are different, then proceed to step 59, that is, stop the self-test and report the test result, the address where the error occurred, and the test sample number. If the comparison results are the same, then enter step 8 to end the self-test formula and report the test result. The steps also indicate that the peripheral memory connection lines after the test are correct. The technical content and technical features of the present invention are disclosed as above. However, those familiar with the technology may still make various substitutions and modifications without departing from the spirit of the present invention based on the teaching and disclosure of the present invention; therefore, the scope of protection of the present invention should not be changed. It is limited to those disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and are covered by the following patent application scope. (Please read the notes on the back before filling this page) 1 & · -line-11