TW451115B - Method and apparatus for digital voltage regulation - Google Patents
Method and apparatus for digital voltage regulation Download PDFInfo
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- TW451115B TW451115B TW088119930A TW88119930A TW451115B TW 451115 B TW451115 B TW 451115B TW 088119930 A TW088119930 A TW 088119930A TW 88119930 A TW88119930 A TW 88119930A TW 451115 B TW451115 B TW 451115B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/157—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators with digital control
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Radar, Positioning & Navigation (AREA)
- Automation & Control Theory (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
4 51115 A7 ^ _ B7_ 五、發明說明(/ ) 務明背晉 本發明大體上俗關於電壓調整器,更持別地,傜關於 切換電壓調整器用之控制糸統。電壓諏整器,如DC對DC (直流對直流)轉換器,傺用於提供電子糸統上之穩定電 源。有效率之DC對DC轉換器對低功率裝置,如膝上筆記 型電腦(laptop netobooks)及行動電話(cellular phones) ,上蓄電池之操控尤其需要。切換電壓調整器(或簡稱 為”切換調整器")熟知傜為效率型DC對DC轉換器。切換 調整器僳將輸入DC電壓轉換成高頻罨壓,及將高頻電腱 濾波成DC輸出電壓。典型地,切換諏整器包含一開閼, 用於交替地聯結未調整之輸入DC電源,如蓄電池,與負 載,如積體電路。典型地含有電感器和電容器之濾波器 葆聯結在輸入電源與負載之間以濾波開關之輸出俾提供 輸出DC電壓。控制器測定電路之電氣持性,例如通過負 載之電壓或電流,及設定開關之貴務週期(duty cycle) 俾維持輸出DC電壓於實質均勻之位準〇 微處理器用之電壓調整器之性能要求更為鹾苛。一種 趨勢係在高電流,例如,352 5G安培下動作。另一趨勢 導通或截斷微處理器之不同部份俾節省電力。此需要電 (請先閱讀背面之注意事項再填寫本頁)4 51115 A7 ^ _ B7_ V. Description of the invention (/) The present invention is generally about voltage regulators, and more specifically, about the control system for switching voltage regulators. Voltage regulators, such as DC-to-DC (direct-current to direct-current) converters, are used to provide a stable power supply for electronic systems. Efficient DC-to-DC converters are especially needed for low-power devices such as laptop netobooks and cellular phones. Switching voltage regulators (or "switching regulators" for short) are well known as efficient DC-to-DC converters. Switching regulators convert the input DC voltage to high-frequency voltage and filter high-frequency electric tendons into DC Output voltage. Typically, switching regulators include an switch for alternately connecting an unregulated input DC power source, such as a battery, and a load, such as a integrated circuit. A filter typically includes an inductor and a capacitor The output DC voltage is provided by the filter switch output between the input power and the load. The controller measures the electrical persistence of the circuit, such as the voltage or current of the load, and the duty cycle of the set switch. 俾 Maintains the output DC The voltage is at a substantially uniform level. The performance requirements of voltage regulators for microprocessors are more stringent. One trend is to operate at high currents, such as 352 5G amps. Another trend is to turn on or cut off different parts of the microprocessor Shares save electricity. This requires electricity (please read the precautions on the back before filling this page)
'裝--------訂----^ I 線/ 經濟部智慧財產局員工消費合作社印製 從勢寄是器 内趨之但整 W 之上。調 9f外線耗壓 09另接損電 (1再連之 . 秒。少流近 奈應減電附 個反俾免之 幾速置避器 在快設而理 如出器進處 例作理-微 ,載處感在 變負微電設 改大近或器 之最靠 \ 整 載到器及調 負化整阻歷 對變調電電 器載壓,將 整負電容了 調小將電為 壓最傺生 , 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 五、發明說明(>) 需小及具有方便之形式因數(form factor)。 (請先閱讀背面之注意事項再填寫本頁) 除了這些特殊趨勢之外,一般需要高效率俥避免在高 負載時産生過熱,進而增加手提式条統之蓄電池壽命, 另外期望之特歡傺電壓調整器應提供在低負載時消耗電 力小之_'待機模式__。 傳統之控制器像由諸如電阻器,電容器及蓮算放大器 之類比電路所構成。具體言之,類tb電路偽昂貴及/或 難於製成積體電路另外,類比信號會因噪音而劣化, 導致資訊漏失^ 鑑於前述,電壓調整器及其之控制条統有尚待改善之 空間。 發昍概沭 大體上,本發明之一型態係闊於蓮轉電壓調整器之方 法,此電壓調整器具有聯結輸入電源之輸入端子,聯結 負載之輸出端子及用於交替地聯結及解聯輸入端子與輸 出端子之複數切換電路。前逑方法計算毎個切換電路之 預估電流;每個預估電流俗代表通過與切換電路有關聯 之電感器之電流;及計算為維持輸出端子上之輸出電壓 於實質恒常所需通過電感器之總電流。切換電路傜根據 預估電流及需要之總輸出電流而控制俥使通過電感器之 總電流約等於需要之總輸出電流》 本發明之另外型態傜關於具有聯結輸入電源之輸入端 子及聯結負載之輸出端子之電壓調整器。複數之切換電 路镨應數位控制信號而間斷地聯結輸入端子及輸出端子 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) B7 五、發明說明(彡) <請先閱讀背面之注意事項再填寫本頁) »複數之濾波器,各含有電感器,在輸出端子上提供大 體為DC之輸出電壓。複數之電流偵测器産生自通過切換 電路之電流導出之回授信號》數位控制器接收及使用複 數之回授信號以計算每掴切換電路之預估電流;毎個預 估電流傜,代表通過與切換電路有關聯之電感器之電流 及計算為維持在輸出端子上之輸出電壓於簧質恒常所需 通過電感器之總輸出電流。數位控制信號僳根據預估之 電流及所需之總輸出電流而産生,俾使通過電感器之總 電流約等於所需之總輸出電流。 經濟部智慧財產局員工消費合作杜印製 本發明之3外型態僳關於決定流過電睡調整器之切換 電路之所裔總電流,俾維持在輸出端子上之输出電壓於 實質恆常。切換電路間斷地聯結輸入端子與輸出端子, 輸入端子fe聯結輸入電源,而输出端子則聯結負載β電 壓調整器含有至少一個聯結至輸出端子之電容器。第1 在输出端子上测定第1輸出電壓,第2次在輸出端子上 測定第2輸出電壓。計算代表流過電感器之電流之預估 電流,根據第1輸出電壓與第2输出電壓之差計算代表 流進,流出前逑至少一個電容器之電流,及根據所要之 電壓與第1及第2輸出電壓之一之差計算校正電流β電 壓調整器之所需總p流傜從預估電流及校正電流之總和 與電容器電流間之差計算出。 本發明之另外型態偽關於電壓調整器。調整器具有聯 結輸入電歷之輸入端子和聯结負載之輸出端子。切換電 路逛應數位控制信號間斷地聯結輸入端子與輸出端子。 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) A7 451115 B7_ 五、發明說明(0 ) (請先閱讀背面之注意事項再填寫本頁) 濾波器提供輸出端子大體上為DC之输出電懕^電流偵測 器産生代表流過切換電路之電流之第1數位回授倍號。 電壓偵測器産生代表輸出電壓之第2數位回授信號。數 位控制器接收及利用數位回授信號産生數位控制信號。 數位控制器係構成能維持輸出端子上之输出電®於實質 恒常之位準。 本發明之S外型態係關於具有聯結輸入電源之輸入端 子及聯結負載之輸出端子。電壓調整器具有複數之附屬 切換電路(Slave)毎値附屬切換電路具有逛應數位控制 倍號間软地聯結输入端子與輪出端子之切換電路,提供 輸出端子大體為DC之輸出電壓之濾波器,産生代表通過 切換電路之電流之數位回授佶號及接收並利用來自複數 之附靥切換電路之數位回授信號以産生複數之數位控制 信號之R位控制器。數位控制器偽構成能維持輸出端子 上之輸出電壓於實質恆常之位準。 經濟部智慧財產局員工消费合作社印製 本發明之另外型態係關於運轉具有聯結輸入電源之輸 入端子及聯結負載之输出端子之電壓調整器之方法。輸 入端子及輸出端子偽藉切換電路蜜應數位控制倍號而間 歇地聯結。切換霄路之输出濾波俾提供大體上為DC之输 出電壓給輸出端子》代表通過切換電路之電流之數位回 授信號偽·籍電流偵測器而産生。數位控制器接收並利用 來自附屬切換電路之數位回授信號以産生數位控制信號 。數位控制器構成能維持輸出端子上之輸出電壓於寅質 恒常位準β -6 - 本紙張尺度適用中國囷家棵準(CNS)A4規格(210 * 297公釐) 451115 A7 __B7___ 五、發明說明(r) 本發明之另外型態偽拥於具有输出輸入電源之輸入端 子及聯結負載之輸出端子之電壓調整器。切換電路逛應 控制信號間歇地聯結輸入端子與輸出端子。濾波器提供 輸出端子大體為DC之輸出電壓。數位控制器傜在遠高於 切換電路之所要切換頻率fswitCh 之時脈頻率fcl(JCk 數 位控制器接收從輸出端子上之輸出電壓毐出之第1數位 回授信號及從逋過切換電路之電流導出之第2數位回授 信號,藉以産生控制切換電路之控制信號俾維持輸出電 壓於實質恆常位準。 本發明之另外型態傜關於蓮轉具有聯结輸入電流之輸 入端子及聯結負載之输出端子之電歷調整器之方法。输 人端子及輸出端子傜藉切換電路迆應數位控制信號而間 歇地聯結。切換電路之輸出經濾波後提供大體為DC之輸 出電壓至输出端子。數位控制器係在遠高於切換電路之 所要切換頻率fswiteh 之時脈頻率fclock 下蓮轉。數位 控制器毎一時脈週期接收從輸出端子上之輸出電壓導出 之第1數位回授信號及從通過電感器之電流導出之第2 (請先閱讀背面之注意事項再填寫本頁) ----訂---------線. 經濟部智慧財產局員工消費合作社印製 信 感子之雷 制電端流估 控之入電預 之器輸之之 路 整結器期 電 諏聯烕初 換 壓地電整 切 C 電歇過調 制準過間流態 控位通有表狀 生之估含代之 産常預器存路 器恆於整貯電 -制質關調。換 。7 控實偽壓路切流 -位於態電電據電 數 Ε 型,換根估 。電外法切-預 號出另方之流的 佶輸之之子電新 授持明流端估生 回雒發電出預産 位俥本之輸期而 數號 器與初流 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 451115 A7 B7 五、發明說明(; 經濟部智慧財產局員工消費合作社印製 輸端DC表狀維之出輸 感子電流初 端含切,貯狀維-之出為代之為器輸總 電端過電從 入器之器器之為流 源輸質存路定感總之 之出流量則 輸整子波制路定電 電至實貯電決電之需 器输表增時 之諝端濾控電決出 入子生。換。過需所 整結代時地 源壓出之位換,輸 輸端産法切流通所於 調聯僳子接 電電输壓數切流缌 结入上方據電简及等 壓地流端子 入。與電。據電之 聯輸子之根估所流約 電歇電入端 輸器子出器根估器 有結端器,預常電流 過間估輸出 結整端輸感,預威 具聯出整流的恆估電 通有預至輸 聯調入之電流的電 轉.,輸調電新質預總 估含之結果 c有壓输DC有電新過 浬子在壓估生實據之 預器期聯如流具電結為含估生逋 於端於電預産於根器 於整初子而電於之聯體器預産需 關出用之期而壓俗感 關調。端,之關子地大波期而所 係輸有器初流電路電 俗壓路出流量係端歇子濾初流常 態之含波之電出電過 態 '電電輸電減態出間端述之電恒 塑載及濾流估輸換通 型,換果估去型輸而出前器估質 外負;之電預之切使 外法切如預減外之號輸,感預實 S結路器之之上。俥S方之。之流另載信供器電之於 之聯電is器期子流制 之之子流期電之負制提制過期壓 明·,換電感初端電控 〇明流端電初估明結控,控流初電 發子切之電整出出而流發電入之於預發聯應路位表整出 本端之壓過調輸輸流電本之輸器加之本及锻電數代調輸 入子電流態持總電出 器至感則期 子有換及存態持 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中困0家標準<CNS)A4規格(210 X 297公釐) 451115 A7 _B7_ 五、發明說明(7 ) 及根據諏整過之預估電流及所需之緦輸出電流産生控制 切換電路之控制信號,俥維持輸出電壓於實質恆常之位 準。 本發明之另外型態偽關於蓮轉具有聯結輸入電源之輸 入端子;聯結負載之輸出端子:及用於間歇地聯結輸入 端子與輸出端子之至少一個切換電路;之電壓調整器之 方法。對每嫡前述切換電路計算預估電流,每個預估之 電流係代表通過與切換電路有關聯結之電感器之電流β 計算為維持輸出端子上之輸出電壓於實質恆常位準所需 通過電鉞器之總電流,及計算電流之上及下限值。電流 之上及下限值之平均傺等於各個電感器所需之輸出電流 。對於一個或多値切換電路,當預估電流降到低於電流 之下限值時切換電路則動作以聯結輸入端子至輸出端子 ,而當預估電流超過電流之上限值時切換電路則將輸出 端子接地。 本發明之S外型態偽關於蓮轉具有聯結輸入電源之輸 入端子;聯結負載之輸出端子;及至少一値間歇地聯結 (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---- 經濟部智慧財產局員工消費合作社印製 法表輸之需換 。 方代持器所切流 之係維感個使電 器流為電各以之 整電算過算流要 調估計通計電所 壓預。需,之於 電個流所流霈等 之每電準電所約 ;-之位換個流 路流器常切各電 電電感恆個與之 換估電質多流路 切預之實或電電 之之聯於個之換 > 路關壓一估切 端電有電於預過 出換路出對較通 輸切電輸。比使 與嫡換之流及俥 子每切上、電,換 端定與子出流切 入決過端輸電路 輸。通出總之電 本紙張尺度適用中國國家標準(CNS)A4梘格(210 X 297公釐) 451115 A7 ' _ B7_ 五、發明說明(2 ) 本發明之另外型態偽關於運轉:具有聯結至輸入電源 之輸入端子;聯結至負載之輸出端子;及用於間歇地聯 結輸入端子與輸出端子之複數切換電路;之m壓調整器 之方法。選定複數切換電路中之一値做為參考電路,而 對剩餘之切換電路決定所需之相位偏移。計算每値切換 電路之預估電流,每個預估電流俗代表通過與此切換電 路有關聯之電戲器之電流。計算為維持輸出端子上之輸 出電壓於實質恒常位準所需通過電感器之總輸出電流, 切換電路被促成將輸出端子接至輸入端子或接地俾賁質 地逹到所要之相位偏移及所要之總輸出電流〇 本發明之優點可包括下述:電壓調整器應付相當大之 電流及對負載之變化能快速反應。電壓調整器可使用具 有便利之形狀因數之小型電容器;電壓調整器能包含複 數不同相位運轉俾減少電流建波之附靥切換電路;藉控制 器將類比測定轉換成數位信號以減少類比電路之使用至 最少;控制器幾乎全部使用數位電路執行控制動作及藉 熟知之流程利用傳統之互補金氣半導體(CMOS)製造技術 製成,進而減少控制器内離晶片(off-chip)構件之數目 ------------裝--- (請#--閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 參算對號 轉蓮許佶 運制容位 之控俾數 器位,以 制數作能 控;蓮器 ,更下整 作變率調 。 蓮而頻壓性 則器脈電靠 法整時從可 算諝之及訊 蓮壓率主通 制電頻.,之 控之換應良' 位用切反改 數應於速供明 藉同高快提説 係不遠化此蜚 器合在變藉簡 制配能之,之 控可則載訊式 ;數法負通購 本紙張尺度適用中國國家標準(CNS)A4規格(210x 297公釐) 451115 A7 B7 五、發明說明(彳 第第第 。電 意 塊示 方之 之器 。例測 圔實偵 塊外流 方另電 之之之 器器器 整整整 調調調 換換換 切切 之之 3J 33 發發 本本 傺僳 圖圖 切 之 圖 1 第 僳 圖 _ 塊 方 之 器 制 控 之 器 整 諏 換 切 之 圖 第 係 圖 〇 3 圖第 路 圖 塊 方 之 器 制行 控執 之器 器制 整控 調之 換圖 切 3 之第 圖藉 1Α出 第示 傲你 圖圖 A 3 4 第第 切 靥 附 過 通 與 流 電 估 預 較 比 偽 圖 5 第 。流 圖電 程際 流實 之之 法路 方電 之換 圄 序 時 之 正 修 之 流 估 預 明 說 偽 圖 D 0 6 圃? 序 6 時第 之 有 電 正 出 修 輸 之 際 流 實 電 之 估 器 預。整 之圖調 圖序換 6D時切 ~ 之與 6A號壓 第信電 與出之 出輸需 示器所 傺測較 圖偵bh 7D流傺 ; 電圖 7 之 8 第聯第 闢 圖 序 時 之 壓 驟 步 Ο 之 圖路 路電 電換 意切 示制 化控 簡上 之法 流方 電之 需圃 所 4 定第 決在 於出 用示 係係 圖圖 ο 9 1 第第 電 換 切 觴 附 考 參 器 整 爾 換 切 之 圃 1 第 制 控 出 示 〇 係 囿圖 程11 流第 之 (請先閱讀背面之注意事項再填寫本頁) ----訂---------線' 經濟部智慧財產局員工消費合作社印製 換 切 屬 附 考 參 過 通 之 生 産 法 方 之 _ 1± 。第 圖藉 程出 流示 之俗 法圔 , 2 方1 之第 路 之 號 信 制 控 之 路 S 換 切 屬 附 者 參 之 。圖 圖11 序第 時出 之示 流像 電圃 之13 路第 i i AN 換 切 靥 附 考 參 上 器 整 0 換 切 之 圖 A IX 第 出 示 傜 圖 0 A I 3 圖 1 序第 時 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐〉 451115 AA7 BB7 五、發明說明(π ) 路之控制信號之時序圖。 (請先閱讀背面之注意事碩再填寫本頁) 第1 4圖俗示出控制附屬切換電路間之相位關係之方法之 流程圖,其中一値電晶體在參考附屬切換電路切換達事先 設定之時間後切換,其它之電晶體則根據預估電流對電 流之限制值之比較結果而切換。 第15圖僳示出藉第14圖之方法所産生之通過參考從切 換電路及非參考附靥切換電路之電流之時序圖〇 第1 6圖傜示出控制附靥切換電路間之相位關俗之方法之 流程匯,其中諏整非參考附靥切換電踣之電流限制值。 第17圖僳示出藉第16圔之方法所産生之通過參考從切 換電路及非參考附屬切換電路之電流之時序圔〇 第18国傺示出産生非參考附屬切換電路之虛影電流 (g h 〇 s t c u r r e n t)之方法之流程圖。 第1 9 _係示出控制附屬切換電路間之相位關條之方法之 流程圖,其中預估之附靥切換電路之電流偽與虛影電流比 較。 第2fl_係示出在執行第18及第19圖之方法期間通過參 考附屣切換電路之電流之時序圖。 第21圖偽示出第20圔之參考附靥切換電路電流所産生之 非參考附屬切換電路之一之虛影導通狀態之時序圖。 第22圖偽示出第18圖之方法所産生之虛影電流及第21 圖之虛影導通狀態之時序圖。 第23圖傜示出藉第19圔之方法所産生之參考附屬切換電 路性能及第22圖之虛影電流之時序圖^ *12" 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 451 1 1 5 ΑΆ7 BB7 五、發明說明() 第24圖偽示出控制附屬切換電路間之相位關傺之方& $ 流程圖,其中産生參考和非參考附屬切換電路之影電 及預估之附屬切換電路電流與附靥切換電路之虛影胃 俥控制附靥切換電路。 第25圖傜示出時脈信號所産生之非參考附靥切換電@ = 一之虛影導通狀態之時序圖。 第26圔傜示出藉第18圖之方法所産生之虛影锺流及第 25圖之虛影導通狀態之時序圖β 第27_僳示出藉第24圖之方法所産生之附靥切換電路之 性能及第26圖之虛影電流時序圖* 鈕瞄諾细說明 參照第1圖,切換調整器10藉輸入端子20連接至未調 整之DC輸入電流,如替電池。切換諏整器10S緒輸出端 子22接至負載14,如積體電路β負載14典型地具有期望 之標稱電壓vnran及零壓容許度 ΔνηΜΠ。微處理器晶>1之 典型標稱電壓Vn<an約為1 . 0至5 . 0伏,例如約為1 . 2至1 8 伏,而典型之電壓容許度ΛνηΜη像為標稱電壓Vnmn 2 + /-6%,亦即,1.2伏標稱電壓時約為80n\f。切換調整 器10傺做為輸入端子20與輸出端子22間之DC對DC轉換器 。切換調整器10包含一値或多値用於將輸入端子上之賴1 入電壓轉換為輸出端子22上之输出電壓VDUt ;此輸 出電壓Vwt係在標稱電壓Vn<)m之容許度範圍内; 及用於控制附屬切換電路16之動作之主控制器18。主控制· 器18可由電源12(如圖示)或其它電源供電。 -13- 本紙張尺度適用_國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) / 裝-------訂----i 1 I 線' 451115 A7 B7 五、發明說明( 簡言之,主控制器18使用以數位電流為主之控制蓮算 法則。根據輸出電壓附屬切換電路之回授,主控 制器1 8之控制運算法則決定為維持輸出電壓V。^於實質 恆常位準,亦卽在容許度範圍内,各値附屬切換電路之 狀態。主控制器18産生控制各附靥切換電路並將之設定於 適宜狀態之一組控制信號。更具體言之,主控制器18確 保流出切換諏整器10之電流匹配流入負載14之電流,藉 此維持輸出電壓於實質恆常之位準例如,如果電流負 載(或簡稱為"負載”)增加時通過動作之附靥切換電路之電 流量則増加《這則容許電流H遞昇”到所要之負載為止。 相反地,如果負載減少時通過勤作之附靥切換電路之電流 量卽減少《這則容許電流__遞降”到所要之負載為止。 每個附屬切換電路16含有切換電路24,此切換電路24條 做為交替地將輸入端2 0與中間端子2 6聯結及解聯之電力 開關。切換電路24S含有將中間端子26接地之整流器, 經濟部智慧財產局員工消費合作社印製 ------------1-裝--- . , (請先閱讀背面之注意事項再填寫本頁)'Installation -------- Order ---- ^ I line / Printed by the Consumers' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Adjust the 9f outside line power consumption 09 and connect the power loss (1 and then connect. Seconds. Shao Liu Jin Nai should reduce the power and attach a few speed avoidance avoidance device in the fast setting, just as the machine enters the example- Micro, the load sense is near the negative micro-electric device is changed recently or the device is the most close \ The whole load to the device and the negative adjustment of the whole resistance to the voltage of the variable electrical appliances, reduce the negative capacitor to reduce the voltage The size of this paper applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm). 5. The description of the invention (>) should be small and have a convenient form factor. (Please read the precautions on the back before reading) (Fill in this page) In addition to these special trends, high efficiency is generally required to avoid overheating at high loads, thereby increasing the battery life of portable systems. In addition, it is expected that the voltage regulator should provide consumption at low loads. Low power _'standby mode__. Traditional controllers are like analog circuits such as resistors, capacitors, and amplifiers. Specifically, tb-like circuits are pseudo-expensive and / or difficult to make integrated circuits. The analog signal will be degraded by noise. Missing information ^ In view of the foregoing, there is room for improvement in the voltage regulator and its control bar. Generally speaking, one form of the present invention is broader than the lotus-to-voltage regulator method. This voltage adjustment The device has input terminals for connecting input power, output terminals for connecting loads, and a plurality of switching circuits for alternately connecting and disconnecting input terminals and output terminals. The previous method calculates the estimated current of each switching circuit; each estimate The current custom represents the current through the inductor associated with the switching circuit; and the total current through the inductor calculated to maintain the output voltage at the output terminal at a substantially constant level. The switching circuit is based on the estimated current and the total output current required And control so that the total current through the inductor is approximately equal to the total required output current. Another aspect of the present invention is a voltage regulator having an input terminal connected to an input power source and an output terminal connected to a load. A plurality of switching circuits should be used. Digital control signals are used to intermittently connect input terminals and output terminals. This paper size applies to China National Standard (CNS) A 4 specifications (210 X 297 mm) B7 V. Description of the invention (彡) < Please read the notes on the back before filling out this page) »Plural filters, each of which contains an inductor, are provided in the output terminals as DC Output voltage. The plurality of current detectors generate feedback signals derived from the current through the switching circuit. "The digital controller receives and uses the plurality of feedback signals to calculate the estimated current for each switch circuit; an estimated current 傜 represents the pass The current of the inductor associated with the switching circuit and the total output current calculated through the inductor required to maintain the output voltage on the output terminal at the constant quality of the spring. The digital control signal is generated based on the estimated current and the required total output current, so that the total current through the inductor is approximately equal to the required total output current. Printed by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs on consumer cooperation. The third aspect of the present invention is to determine the total current flowing through the switching circuit of the sleep regulator, and to maintain the output voltage on the output terminal at a substantially constant level. The switching circuit intermittently connects the input terminal and the output terminal, the input terminal fe is connected to the input power source, and the output terminal is connected to the load β voltage regulator including at least one capacitor connected to the output terminal. The first output voltage is measured on the output terminal for the first time, and the second output voltage is measured on the output terminal for the second time. Calculate the estimated current that represents the current flowing through the inductor, and calculate the current that flows in and out of at least one capacitor before the current based on the difference between the first output voltage and the second output voltage, and according to the desired voltage and the first and second The difference between one of the output voltages is used to calculate the required total p current of the correction current β voltage regulator, which is calculated from the difference between the sum of the estimated current and the correction current and the capacitor current. Another aspect of the present invention relates to a voltage regulator. The regulator has an input terminal connected to the input calendar and an output terminal connected to the load. The switching circuit should intermittently connect the input terminal and the output terminal with a digital control signal. This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 451115 B7_ V. Description of invention (0) (Please read the precautions on the back before filling this page) The output terminals provided by the filter are generally The output voltage of the DC current detector generates the first digital feedback multiple representing the current flowing through the switching circuit. The voltage detector generates a second digital feedback signal representing the output voltage. The digital controller receives and uses digital feedback signals to generate digital control signals. The digital controller is configured to maintain the output power at the output terminals at a substantially constant level. The S appearance of the present invention relates to an input terminal having a connected input power source and an output terminal connected to a load. The voltage regulator has a plurality of slave switching circuits. The slave switching circuit has a switching circuit that softly connects the input terminal and the wheel output terminal between digital control multiples, and provides a filter whose output terminal is generally DC output voltage. An R-bit controller that generates a digital feedback signal representing a current through a switching circuit and receives and uses a digital feedback signal from a plurality of attached switching circuits to generate a plurality of digital control signals. The digital controller pseudo-structure can maintain the output voltage on the output terminal at a substantially constant level. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Another aspect of the present invention is a method for operating a voltage regulator having an input terminal connected to an input power source and an output terminal connected to a load. The input terminals and output terminals are intermittently connected by digitally controlling the number by means of a switching circuit. The output filter of the switching road: It provides the DC output voltage to the output terminal. It represents the digital feedback signal of the current passing through the switching circuit. It is generated by the current detector. The digital controller receives and uses the digital feedback signal from the auxiliary switching circuit to generate a digital control signal. The digital controller structure can maintain the output voltage on the output terminal at a constant level of β-6.-This paper size is applicable to the Chinese standard (CNS) A4 (210 * 297 mm) 451115 A7 __B7___ 5. Description of the invention (R) Another type of the present invention is a voltage regulator having an input terminal with an output power source and an output terminal connected to a load. The switching circuit should intermittently connect the input and output terminals with the control signal. The filter provides an output voltage that is roughly DC. Digital controller: The clock frequency fcl (JCk digital controller receives the first digital feedback signal from the output voltage on the output terminal and the current through the switching circuit is much higher than the desired switching frequency fswitCh of the switching circuit The derived second digital feedback signal is used to generate the control signal of the control switching circuit, which maintains the output voltage at a substantially constant level. Another aspect of the present invention is related to the input terminal and connection load of the Lianzhuan that have a connected input current. Method for adjusting the calendar of the output terminal. The input terminal and the output terminal are intermittently connected by a digital control signal through a switching circuit. The output of the switching circuit is filtered to provide a substantially DC output voltage to the output terminal. Digital control The device rotates at a clock frequency fclock that is much higher than the desired switching frequency fswiteh of the switching circuit. The digital controller receives the first digital feedback signal derived from the output voltage on the output terminal in one clock cycle and from the inductor through the inductor. The second part of the current export (please read the precautions on the back before filling this page) ---- Order --------- line. Ministry of Economic Affairs wisdom The production bureau employee consumer cooperatives printed the letter sensor, the lightning system, the current flow of the electric terminal, the control of the electric power, the road of the power output, and the road of the integrator. The flow control position has the appearance of the normal production, the pre-preserver, the reserver, and the constant storage power-quality control. Change. 7 Control the real pseudo-pressure circuit to cut the flow-located in the state of electricity and electricity data E Type, change the root estimate. Electricity outside the cut-pre-numbered out of the son of the loser of the new generation of electricity Dian Xinming to hold Mingliu end-of-life assessment and return to the production date of the pre-production position, and the number device and the beginning The size of the current paper is applicable to China National Standard (CNS) A4 (210 X 297 mm) 451115 A7 B7 V. Description of the invention The initial end of the current includes the cut, and the storage-dimensional output is replaced by the power transmission terminal. The device that passes the electricity from the device to the device is the flow source. The mass storage circuit is set. The end-of-line filtering and control of the power demand when the electricity demand from the fixed power to the actual storage power is increased. The position is changed, and the transmission and output terminal cuts the current at the power transmission line. The power transmission voltage is cut into the upper part. According to the power line and the isostatic ground current terminal, it is connected to the power. According to the root of the power transmission line, It is estimated that the current input and output terminals of the electric power interruption device have a terminal device. The pre-constant current is used to estimate the output terminal's entire terminal inductance. The electric conversion of the transferred current. The result of the total pre-assessment of the new quality of the transmission and adjustment. C There is a voltage transmission. The DC has electricity. Yu Duan Yudian pre-produced in the root organ in the first stage and electric Yu's pre-production of the conjoined device need to be closed and used to suppress the sense of vulgarity. The output flow of the electric circuit is the electric discharge over-state of the wave-breaking normal state at the end of the filter, and the electric constant plastic load and the filter flow rate described in the electric power transmission reduction state are described below. The former loses its quality and loses its value when the model loses; the electric pre-cut makes the foreign method cut like the pre-reduction of the foreign sign, and it feels that it is above the S circuit breaker.俥 S party. The current also contains the letter of the power supply, the power of the UMC, the current of the sub-current system, the negative current of the sub-current system, and the overdue voltage of the system. The current-controlling electric power generator cuts out the electricity and outputs it, while the current electricity generation enters the pre-synchronization circuit table to rectify the local voltage over-regulation, the transmission device, the transmission device, and the generator and the forging electricity number. The sub-current state holds the total electric generator to the sense period, and there is a change and storage state (please read the precautions on the back before filling this page) This paper is applicable to 0 standards < CNS) A4 specifications (210 X 297 mm) 451115 A7 _B7_ V. Description of the invention (7) and the control signal of the control switching circuit is generated based on the estimated current and the required output current to maintain the output voltage at a substantially constant level. Another aspect of the present invention is pseudo-relevant to the input terminal of the Lianzhuan that has a connected input power source; an output terminal connected to the load: and at least one switching circuit for intermittently connecting the input terminal and the output terminal; a voltage regulator method. The estimated current is calculated for each of the aforementioned switching circuits. Each estimated current represents the current through the inductor associated with the switching circuit. Β is calculated as the current required to maintain the output voltage on the output terminal at a substantially constant level. Total current of the instrument, and calculate the upper and lower limits of the current. The average of the upper and lower current limits is equal to the output current required by each inductor. For one or more switching circuits, the switching circuit operates to connect the input terminal to the output terminal when the estimated current falls below the lower limit of the current, and the switching circuit will switch when the estimated current exceeds the upper limit of the current. The output terminal is grounded. The S appearance of the present invention is about the input terminal of the lotus turn with a connected input power supply; an output terminal connected to the load; and at least one intermittent connection (please read the precautions on the back before filling this page). ---- Order ---- Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to exchange the printed form. The flow cut by the Fang Dai holder is to make the current flow of the electric power to be calculated separately. The calculated current must be adjusted and estimated by the metering station. It is necessary to make a reservation for each electricity quasi-electricity, such as the flow of electricity; to change the current flow, the current inductor is always cut, and the constant current is changed. The connection to the individual exchanges> The road closing pressure estimates that there is electricity in the cut-off terminal and that the pre-transmission circuit is switched to the out-of-circuit circuit. Each time the switch and the switch are switched on and off, the switch is switched and the switch is switched on and off. In short, the paper size is applicable to the Chinese National Standard (CNS) A4 grid (210 X 297 mm) 451115 A7 '_ B7_ V. Description of the invention (2) Another type of the invention is pseudo-operational: it has a connection to the input The input terminal of the power supply; the output terminal connected to the load; and a plurality of switching circuits for intermittently connecting the input terminal and the output terminal; the method of m voltage regulator. One of the plurality of switching circuits is selected as a reference circuit, and the required phase shift is determined for the remaining switching circuits. Calculate the estimated current of each switching circuit, and each estimated current represents the current through the theater device associated with this switching circuit. Calculate the total output current through the inductor required to maintain the output voltage on the output terminal at a substantially constant level. The switching circuit is urged to connect the output terminal to the input terminal or ground, texture, to the desired phase offset and the desired Total output current. The advantages of the present invention can include the following: the voltage regulator can handle a relatively large current and can respond quickly to changes in load. The voltage regulator can use a small capacitor with a convenient form factor; the voltage regulator can include complex different phase operation, and a switching circuit that reduces the current build-up; the controller converts the analog measurement into a digital signal to reduce the use of the analog circuit To a minimum; almost all controllers use digital circuits to perform control actions and use well-known processes to use traditional complementary metal-gas semiconductor (CMOS) manufacturing technology to reduce the number of off-chip components in the controller- ---------- Installation --- (Please #-Read the notes on the back and fill out this page) Control the number of digital devices, the system can be used to control the number; The pulse frequency of the device is based on the pulse frequency, which can be calculated from the calculated frequency and the signal pressure ratio. The control frequency should be good. The change should be reversed and changed at the same time. Quick mention is that this device is not far away from the simple power distribution, the control can be carried by information; the number method negative through the purchase of this paper size applies Chinese National Standard (CNS) A4 specifications (210x 297 mm ) 451115 A7 B7 V. Description of the invention (彳 第 第 .Electrical block shows the device of the square. For example, test the outflow side of the real detection block and the device of the other device. The first version of the book is shown in Figure 1. Figure _ Diagram of the block-side device control and control of the device. Figure 3. Control the change of the map and cut the 3rd picture by 1A to show you the best picture A 3 4 The 3rd piece is attached to the pass and the current estimation is compared with the false figure 5. The flow path is the way to be realistic The current estimate of Fang Dian's change in the sequence is predictive of the false picture D 0 6? When there is electricity being repaired and delivered, the estimate of the actual electricity is forecasted. The whole picture adjustment sequence is changed to 6D when the time is cut ~ and the No. 6A voltage signal and the output and output demand indicator are compared with the picture detection bh 7D flow; electric map 7-8 The first step in the sequence of the first picture of the first step of the map road electricity and electricity change intention display system control and control of the traditional method of electricity demand Use the diagram to show the diagram ο 9 1 The first electric switch and the attached reference device to change and cut the garden 1 The system control is presented 〇 System diagram 11 Flow chart (Please read the precautions on the back before filling this page ) ---- Order --------- Line 'Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, which is a production method with a test pass and passed _ 1 ±. The customary method shown in the figure, the 2 way 1 of the road No. 1 of the letter system control road S is switched by the attached party. Figure 11 shows the current image of the electric garden No. 13 road ii AN Attach the tester to complete the 0-cut drawing A IX, shown in Figure 0 AI 3 Figure 1 In the preface, the paper size is applicable National Standard (CNS) A4 size (210 X 297 mm> 451115 AA7 BB7 V. Description of the Invention timing chart of control ([pi]) of the channel signals. (Please read the cautions on the back before filling this page.) Figure 14 shows a flow chart showing the method of controlling the phase relationship between the auxiliary switching circuits. One of the transistors is switched by referring to the auxiliary switching circuit to the preset value. After the time, the other transistors are switched according to the comparison result of the estimated current to current limit. Fig. 15 shows the timing diagram of the current generated by the method of Fig. 14 by referring to the switching circuit and the non-reference attached switching circuit. Fig. 16 shows the customs of controlling the phase between the attached switching circuits. The process flow of the method is to adjust the current limit value of the non-reference attached switching switch. Figure 17 (shown in Figure 16) shows the timing of the current from the reference switching circuit and the non-reference auxiliary switching circuit generated by the method in (16). (18) shows the generation of the ghost current of the non-reference auxiliary switching circuit (gh 〇stcurrent) method flowchart. Section 19_ is a flowchart showing a method for controlling the phase bar between the auxiliary switching circuits, in which the estimated current pseudo and ghost currents of the auxiliary switching circuits are compared. Figure 2fl_ is a timing chart showing the current through the reference attached switching circuit during the execution of the method of Figures 18 and 19. FIG. 21 is a timing chart of the ghost conduction state of one of the non-reference auxiliary switching circuits generated by the current of the 20th reference switching circuit. FIG. 22 is a timing chart of the ghost current generated by the method of FIG. 18 and the ghost conduction state of FIG. 21. Figure 23 傜 shows the performance of the reference auxiliary switching circuit generated by the method in Figure 19 圔 and the timing chart of the ghost current in Figure 22 ^ * 12 " This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 451 1 1 5 ΑΆ7 BB7 V. Description of the invention () Figure 24 shows a schematic diagram of the method of controlling the phase relationship between the auxiliary switching circuits & $ flow chart, which generates the shadows of the reference and non-reference auxiliary switching circuits. The current of the auxiliary switching circuit and the estimated switching current of the auxiliary switching circuit control the auxiliary switching circuit. Figure 25 shows the timing diagram of the non-referenced switching power @ = one generated by the clock signal. Figure 26 shows the timing diagram of the ghost flow generated by the method of Figure 18 and the conduction state of the ghost shadow of Figure 25. Figure 27_ 僳 shows the additional switching generated by the method of Figure 24. Circuit performance and timing diagram of phantom current in Figure 26. * Detailed description of the button. Referring to Figure 1, the switching regulator 10 is connected to the unadjusted DC input current through the input terminal 20, such as for a battery. The output terminal 22 of the switching conditioner 10 is connected to the load 14. For example, the integrated circuit β load 14 typically has a desired nominal voltage vnran and a zero-voltage tolerance ΔνηΜΠ. The typical nominal voltage Vn of the microprocessor crystal > 1 is about 1.0 to 5.0 volts, such as about 1.2 to 18 volts, and the typical voltage tolerance ΛνηΜη is like the nominal voltage Vnmn 2 + / -6%, that is, about 80n \ f at a nominal voltage of 1.2 volts. The switching regulator 10 傺 serves as a DC-to-DC converter between the input terminal 20 and the output terminal 22. The switching regulator 10 includes one or more switches for converting the input voltage on the input terminal to the output voltage VDUt on the output terminal 22; this output voltage Vwt is within the allowable range of the nominal voltage Vn <)m; And a main controller 18 for controlling the operation of the auxiliary switching circuit 16. The main controller 18 may be powered by a power source 12 (as shown) or another power source. -13- The size of this paper applies _ National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling this page) i 1 I line '451115 A7 B7 V. Description of the invention (In short, the main controller 18 uses a digital current-based control algorithm. According to the feedback of the output voltage attached switching circuit, the main controller 18 controls The algorithm is determined to maintain the output voltage V. ^ At the substantially constant level, and within the tolerance range, the state of each auxiliary switching circuit. The main controller 18 generates and controls each auxiliary switching circuit and sets it to an appropriate level. A group of control signals. More specifically, the main controller 18 ensures that the current flowing out of the switching regulator 10 matches the current flowing into the load 14, thereby maintaining the output voltage at a substantially constant level. For example, if the current load ( Or "load" for short) When the amount of current passing through the attached switching circuit is increased, "this allows the current H to step up" to the desired load. Conversely, if the load is reduced, it is switched by the auxiliary operation. Circuit current Reduce the "this allowable current __decrease" to the desired load. Each auxiliary switching circuit 16 contains a switching circuit 24, and this switching circuit 24 alternately connects and disconnects the input terminal 20 and the intermediate terminal 26. The power switch. The switching circuit 24S contains a rectifier that grounds the intermediate terminal 26. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------ 1-install ---., (Please read first (Notes on the back then fill out this page)
如開關或二極體。每锢附屬切換電路藉輸出濾波器2B而 連接至輸出端子22。切換電路24之開及關在中間端子26 上産生具有長方波形之中間電瞪Vilvt。輸出濾波器28在 输出端子22上將長方波彤轉換成實質為DC之輸出電壓。 雖然下面將示出及敘述之切換調整器係用為大的轉換器 形態(bupk converter topolgy),但是本發明亦可應用 於其它之電壓調整器、形態,如增強轉換器(boost converter)或大的-增強轉換器(buck-boost converter) 拓撲。 -1 4 - 本紙張尺度適用中國國家標準(CNS〉A4規格(210 X 297公釐) 4S1 1 1 5 A7 B7 五、發明說明(θ) 如所示,切換電路24及輸出滴波器28偽構成為大的轉 換器形態β具體言之,每値附靥切換電路16之切換電路 24包含開關,如具有連接至輸入端子20之源極及連接至 中間端子26之汲極之第1電晶體3〇。切換電路24另包含 整流器,如具有連接地之源極及建接至中間端子26之汲 極之第2電晶體32。第1電晶體30可為Ρ型HOS(PMOS) 裝置,至於第2電晶體32可為N型MOS(NHOS)裝置。替 選地,第2電晶體32可用二極體取代或加設二捶體俥提 供整流作用。第1及第2,電晶體3[)及32可被控制線44a 及44 b上之切換倍號驅動。輸出墟波器28含有接在中間 端子2 6與輸出端子22間之電感器3 4及與負載14並聯連接 之電容器36。另外,每掴附屬切換電路16可加設連接至 電感器3 4之共通線之一锢或刀値電容器或藉以取代電容 器36〇 當第1電晶體30關閉及第2電晶體32打開(PH0S導通 狀態)時中間端子26即連接至電源12,而電源12則經第 1電晶體30供給能量主負載14。相反地,如果第1電晶 體打開及第2電晶體32闘閉(NM0S導通狀態)時中間端子 26即接地t能量則藉電感器34供給至負載14β 經濟部Λ°慧財產局員工消費合作社印製 毎値附藤切換踅路另含有用於测定流過第1及第2電 晶體30及32之電流之第1及第2電流偵測器40及42»主 控制器18在以電流為主之控制運算法則下偽使用來自電 流偵測器40及42之資訊。每値電流偵測器在一或多條輸 出線上産生數位輸出信號。對單一位元倍號言’輸出線 -1 5 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 45丨1丨5 A7 B7 五、發明說明(沖) (請先閒讀背面之注$項再填寫本頁) 上之數位輸出當通過附屬切換電路之電流下降到低於觸發 電流時可從高切換為低(或反之亦是具體言之,第1 電流偵測器40輸出在第1输出線44 C上之倍號當通過第 1電晶體之電流超過第1觸發電流IPeroSS # III # fg to 換為高。相似地,第2電流偵測器42輸出在第2輸出線 44d上之輸出信號當通過第2電晶體32之電流下降到低 於第2觸發電流ItIenjss 時則從高切換為低。 如第1圖所示,毎條輸出線44c及44 d可直接連接至主 控制器18。種選地,如第1A圖中所示,第1及第2輸出 線可結合在一起以形成單一之輸出線44ge這種情形, 主控制器18根據附屬切換電路是否PM0S(第1罨晶體或 P Μ 0 S (第2電晶體之導通狀態判別在輸出線4 4 g上之信號 gi ,g2,...gn是杏代表通過第1或笫2電晶體之電流。 參照第2圖,毎値電流偵測器,如第1電流偵測器40 ,含有參考電晶體52,電流源54,及比較器56。相似之 電流偵測器偽敘述於由同時申諳,美國專利申請序號第 0 9/ 1 83 , 4 1 7 ,名稱為電流測定技術,快遞號碼(ExpressSuch as switches or diodes. Each auxiliary switching circuit is connected to the output terminal 22 through an output filter 2B. The switching circuit 24 is turned on and off on the intermediate terminal 26 to generate an intermediate electroscope Vilvt with a rectangular waveform. The output filter 28 converts the rectangular wave to an output voltage substantially DC at the output terminal 22. Although the switching regulator shown and described below is used as a large converter form (bupk converter topolgy), the present invention can also be applied to other voltage regulators and forms, such as boost converters or large converters. -Buck-boost converter topology. -1 4-This paper size applies Chinese national standard (CNS> A4 size (210 X 297 mm) 4S1 1 1 5 A7 B7 V. Description of the invention (θ) As shown, the switching circuit 24 and the output dropper 28 are false In the form of a large converter β, specifically, each of the switching circuits 24 of the switching circuit 16 includes a switch, such as a first transistor having a source connected to the input terminal 20 and a drain connected to the intermediate terminal 26. 30. The switching circuit 24 further includes a rectifier, such as a second transistor 32 having a source connected to ground and a drain connected to the intermediate terminal 26. The first transistor 30 may be a P-type HOS (PMOS) device, as for The second transistor 32 may be an N-type MOS (NHOS) device. Alternatively, the second transistor 32 may be replaced by a diode or a dimorphium may be provided to provide rectification. The first and second transistors 3 [ ) And 32 can be driven by switching multiples on control lines 44a and 44b. The output amplifier 28 includes an inductor 34 connected between the intermediate terminal 26 and the output terminal 22, and a capacitor 36 connected in parallel with the load 14. In addition, each auxiliary switching circuit 16 may be provided with a common line connected to the inductor 34 or a capacitor or replace the capacitor 36. When the first transistor 30 is turned off and the second transistor 32 is turned on (PH0S is turned on) State), the intermediate terminal 26 is connected to the power source 12, and the power source 12 supplies energy to the main load 14 through the first transistor 30. Conversely, if the first transistor is turned on and the second transistor 32 is turned off (NM0S is on), the intermediate terminal 26 is grounded, and t energy is supplied to the load 14 through the inductor 34. Ministry of Economic Affairs The control circuit of the Fujitsu switching circuit additionally includes the first and second current detectors 40 and 42 for measuring the current flowing through the first and second transistors 30 and 32. The main controller 18 is mainly based on the current. The control algorithm uses information from the current detectors 40 and 42 in a pseudo manner. Each current detector generates digital output signals on one or more output lines. For single digit times, 'output line-1 5-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 45 丨 1 丨 5 A7 B7 V. Description of the invention (punch) (please first Read the “$” on the back of the idle reading and then fill in this page) The digital output on the above can be switched from high to low when the current through the auxiliary switching circuit drops below the trigger current (or vice versa, specifically, the first current detection When the current passing through the first transistor exceeds the first trigger current IPeroSS # III # fg to high, similarly, the output of the second current detector 42 is output at the first The output signal on the 2 output line 44d is switched from high to low when the current passing through the second transistor 32 drops below the second trigger current ItIenjss. As shown in the first figure, the single output lines 44c and 44d can Directly connected to the main controller 18. Alternatively, as shown in Figure 1A, the first and second output lines can be combined to form a single output line 44ge. In this case, the main controller 18 is based on an auxiliary switching circuit Whether the PM0S (1st crystal or P M 0 S (conduction state of the second transistor is on the output line) The signals gi, g2, ... gn on 4 4 g are the currents that the apricot represents through the first or 笫 2 transistor. Referring to the figure 2, the 毎 値 current detector, such as the first current detector 40, contains Reference is made to transistor 52, current source 54, and comparator 56. Similar current detectors are pseudo-described in the simultaneous application, US Patent Application No. 0 9/1 83, 4 1 7, the name is current measurement technology, express Number (Express
Mail Label)EM 202 542 906 US,並已譲渡给本發明之 經濟部智慧財產局員工消費合作社印製 受譲人,之專利申請案裡,該專利申諳案所掲示之金部 内容由本文採做為參考。參考電晶體52具有連接至由測 定之電晶體,亦即第1電晶體30,之源極之源極,建接 至電流源54之汲搔,及連接至控制線44e之閘棰。參考 電晶體52僳匹配功率電晶體30,亦即電晶體元件偽在相 同之晶片上及相同之尺寸利用相同之流程製造俾這些電 -1 6 - 本紙張尺度適用中國國家標準(CNS>A4規格(210 X 297公釐) 4 51115 A7 1 _B7_ 五、發明說明(纩) 晶體具有實質相等之電氣特性》既知之電流I 流過電 流源54。比較器56之正輸入俱接至參考電晶體52之汲極 (請^-閱讀背面之注意事項再填寫本頁) 與電流源54間之節點58,比較器56之負輸入傜連接至中 間端子26。比較器56之输出偽連接至參考線44ce第2電 流偵測器4 2之構成像與第1電流偵測器4 0者相同,但極 性則依HOS電晶體之需要而定。 在運轉中,假設功率電晶體3 0及參考電晶體5 2皆關閉 時,則附靥切換電路之電流 Islave 則流過功率電晶體3 0 ,而參考電流 Irei流過參考電晶體52。節點58上之電壓 (V_ )係依 Vnode = % - U R X Irei )得出,其中 R R 係 1 電晶體5 2之等效電阻,至於在中間端子2 6上之電壓Vint 刖依Vm = - ( R p X Islave )得出,其中R p傑功率電晶 體30之等效電阻。因·參考電晶體52僳用單電晶體元件製 造,功率電晶體用N電晶體元件製造,故功率電晶體之 電阻RP實質等於1/fi之參考電晶體52之電阻,是以節點 電壓VMde = - ( E f X N X Irap )若附屬切換電路電流Mail Label) EM 202 542 906 US, and has been transferred to the Intellectual Property Bureau of the Ministry of Economic Affairs of the Intellectual Property Bureau employee consumer cooperative to print the trustee. In the patent application, the content of the gold department shown in this patent application is collected by this article. As a reference. The reference transistor 52 has a source connected to the source of the measured transistor, that is, the first transistor 30, a drain connected to the current source 54, and a gate connected to the control line 44e. Reference transistor 52. Matching power transistor 30, that is, the transistor components are fabricated on the same wafer and the same size using the same process. These transistors are -1 6-This paper size applies to Chinese national standards (CNS > A4 specifications). (210 X 297 mm) 4 51115 A7 1 _B7_ V. Description of the invention (纩) The crystal has substantially equal electrical characteristics. The known current I flows through the current source 54. The positive input of the comparator 56 is connected to the reference transistor 52. The drain (please ^-read the notes on the back and fill in this page) node 58 between the current source 54 and the negative input 比较 of the comparator 56 is connected to the intermediate terminal 26. The output of the comparator 56 is pseudo-connected to the reference line 44ce The composition of the second current detector 42 is the same as that of the first current detector 40, but the polarity depends on the needs of the HOS transistor. In operation, it is assumed that the power transistor 30 and the reference transistor 5 When both 2 are closed, the current Islave of the attached switching circuit flows through the power transistor 3 0 and the reference current Irei flows through the reference transistor 52. The voltage (V_) at node 58 is based on Vnode =%-URX Irei) It can be concluded that RR series 1 transistor The equivalent resistance 52, as the intermediate terminal 26 of voltage Vint on INTRODUCTION by Vm = - (R p X Islave) obtained, wherein the equivalent resistance R p 30 Jie power transistor. Because the reference transistor 52 僳 is made of a single transistor element and the power transistor is made of an N transistor element, the resistance RP of the power transistor is substantially equal to the resistance of the reference transistor 52 of 1 / fi, which is based on the node voltage VMde = -(E f XNX Irap)
Isiave 大於N X Ircf 時則大於中間電壓Vk . 〇因此,電 流偵測器4 Q若附屬切換電路電流Islave ( I _ )大於臨 經濟部智慧財產局員工消費合作社印製 界電流N X .時則在輸出線4 4 c上輸出髙信號,而若從 切換電路電流Islave 小於臨界電流N X ^ 時則在參考 線4 4 c上輸、出低信號。 、 兩電流偵測器4 0及4 2可構成不同之參考電流Iref以提 供不同之臨界電流 IPercss 及INe_ 。第1輸出偵測器 40之第1臨界電流 IPeross 可大於第2電流偵測器42之 -17" 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 45llig 經濟部智«財產局員工消費合作社印製 A7 B7 五、發明說明(4) 第2臨界電流INcross 。因此,電流偵測器4tm附·藤切換 電路電流Isiave大於臨界電流Ipm>ss時則在第1輸出 線44c上輸出高倍號,反之則輸出低信號。相同地,電 流偵測器4 2苕附屬切換電路電流Is^ve大於臨界電流INcn)SS 時則在輸出線4 4 d上输出高信號*反之則輸出低信號。 這些提供主控制器18有關流過附屬切換電路之電流之資訊 之簡單臨界輸出電流比類比信號較不受曝音之干擾,消 耗較少功率及省去金面類比對數位之電流轉換所需之大 量互聯。 選定電流臨界值INe_ 及1使附屬切換電路電流 Is]ave在毎個切換週期,亦即毎個PMOS及NMOS導通狀態 期間,至少越過一個臨界值。臨界電流1p〇ross應大於臨 界電流 INc_俥增加附靥切換電路電流Is^在hb較 器使能(enabled)後越過臨界電流Ipcross 之機率。於一 實例上,第1臨界電流IPcn)SS 可約為8安培,而第2臨 界電流INe_ 可約為2安培。 電流偵測器能構成輸出多値數位信號。例如,電流偵 測器若附座切換電路電流ISlav« 超過第1臨界電流IPcross 時能産生第1數位信號,若附屣切換電路電流〖slave超 過第2臨界電流^ 時能輸出第2數位信號,等。When Isiave is greater than NX Ircf, it is greater than the intermediate voltage Vk. 〇 Therefore, if the current of the auxiliary switch circuit Isave (I__) is greater than the printed circuit current NX. A 髙 signal is output on line 4 4 c, and if the slave circuit current Islave is less than the critical current NX ^, a low signal is output and output on reference line 4 4 c. The two current detectors 40 and 42 can form different reference currents Iref to provide different critical currents IPercss and INe_. The first critical current IPeross of the first output detector 40 may be greater than the -17 of the second current detector 42 " This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 45llig Ministry of Economy « Printed by the Consumer Bureau of the Property Bureau A7 B7 V. Description of the invention (4) The second critical current INcross. Therefore, when the current detector 4tm attached to the rattan switching circuit current Isiave is greater than the critical current Ipm > ss, it outputs a high magnification number on the first output line 44c, otherwise it outputs a low signal. Similarly, when the current detector 4 2 苕 auxiliary switching circuit current Is ^ ve is greater than the critical current INcn) SS, it outputs a high signal on the output line 4 4 d * otherwise it outputs a low signal. These are simple critical output currents that provide the main controller 18 with information about the current flowing through the auxiliary switching circuit. Analog analog signals are less affected by exposure noise, consume less power, and eliminate the need for gold-level analog-to-digital current conversion. Massive interconnection. The selected current critical values INe_ and 1 cause the auxiliary switching circuit current Is] ave to cross at least one critical value during one switching cycle, that is, during the on-state of the PMOS and NMOS. The critical current 1poros should be greater than the critical current INc_ 俥 Increase the probability of the auxiliary switching circuit current Is ^ crossing the critical current Ipcross after the hb comparator is enabled. In one example, the first critical current IPcn) SS may be about 8 amps, and the second critical current INe_ may be about 2 amps. The current detector can form multiple digital signals. For example, the current detector can generate a first digital signal if the current of the attached switching circuit ISlav «exceeds the first critical current IPcross, and can output a second digital signal if the attached switching circuit current 〖slave exceeds the second critical current ^.
AP〇r〇SS 再回到第1圖,如前述,輸出端子22上之輸出電壓Vout 傜由主控制器18調整,或維持在實質恆常之位準上。主 控制器18測定輸出端子上之電壓及接收每値附靥切換電 路16之電流偵測器4t)及42在輸出線44c及44d上之數位輸 -1 8 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) II 11 1裝 i!!f 訂--— II-- ' V . / (請先閱讀背面之注意事項再填寫本頁) A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(/7 ) 出信號β镨應測定之輸出雷壓V〇ut及電流偵測器之輸出 電流,主控制器18産生控制每値咐屬切換電路16之第1 及第2電晶體30, 32之動作之控制信號。下文將細述主 控制器18之動作β 主控制器及附屬切換電路16可利用幾乎金部以數位及 開關罨容器為主之構件構成。因此,大部份之切換調整 器10能緒傳統之CMOS技術在單一晶片之實現或製造。但 是,最好是將每掴附靥切換電路16製造在單晶片上而將 主控制器18製造在分離之晶片上。替換地’每個附靥切 換電路能製造在單一 1C上,電壓偵測器能製造在分離之 晶片上,及剩餘之數位控制器能製造在再另外之1(3晶Η 上。毎個晶Η可利用傳统之CMOS技術製造。 參照第3圖,主控制器18含有锺壓採樣電路6D,此電 路60於切換電路之毎個週期期間之一傾或多痼離散時間 測定輸出端子22上之输出電壓Vout。採樣電路60可作成 實質地如Authony J. Stratakos氏等於1997年12月16日 提出之專利申請案,美P專利申請序號〇8/991, 334, 名稱為切換調整器使用之資料之離散探樣,並已譲渡給 本發明之受譲人中所敘述之構成,該專利申請案之全部 内容偽由本文採做為參考。採樣電路6 〇之接地點可直接 連接到徹處理器之接地點俾減少因寄生之電容及電感所 造成之錯誤。採樣電路60採樣之電壓藉類比對數位(A/D) 轉換器62轉換成數位電壓信號β 主控制器1 8 g包含數位控制蓮算法則6 4。數位控制蓮 -1 9- 本紙張尺度適用中國國家標準(CNS)A4規格<210 X 297公釐) -------------yM.--- i (請先閱讀背面之注意事項wt填寫本頁) 訂· 睡 4 〇 -線 451 π 5 A7 B7 五、發明說明(况) 算法則接收來自A/ D轉換器62之數位電壓信號.來自輸 出線44c和44d之輸出信號ci , c2 , ...cn及dU , , ____dn ,及來自外部時脈之時脈佶號66。時脈信號66 (晴先閱讀背面之注意事項再填寫本頁) 可藉與運作徹處理器者相同之時脈,負載内之其他1C装 置,或在主控制器晶Η上之時脈而産生。時脈頻率fclt)ck 應遠髙於切換電路24之切換頻率fswlteh ,例如1 D至1 〇 〇 個因數,俥確保快速迆應負載之變化但是,時脈頻率 fclock 不應高到使切換調整器及主控制器自電源汲取 大量之功率。典型地,時脈頻率fd(iek 並不似撤處理器 之時脈速率那麼高而能藉分割微處理器之時脈信號産生 。時脈信號66可具有介於約16至66HHZ,例如約33MHz, ^ mm fclock 。 參照第3A圖,主控制器IV之另外賁例包含接至輸出 端子22之電壓採樣和保持電路60'俾測定輸出電壓與標 稱電壓間之差,亦即 Vout(n)-Vnom ,及目前之輸出電壓 與前一時脈週期之輸出電壓間之差,亦即V_n)-V_(1>1) 經濟部智慧財產局員工消費合作社印製 。數位標稱電壓V ησινν可藉外部接腳設定並藉數位對類比 (D/A)轉換器68轉換成類比電壓。於本實例上,採樣電 路60'採樣之電壓差傜由兩個D/A轉換器62_轉換成兩値 數位電壓差佶號。電壓差所需之較小轉換範圍(相較於 A/D轉換1器6(]')容許使用較簡單及較快速之A/D轉換器 。數位控制蓮算法則接收來自A/D轉換器62'之數位電壓 差,來自輸出線44c和44d之輸出佶號Ci ,C2 , ...Cn 及di , d2.....dn ,來自外部時脈之時脈信號66, -2 0 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 451115 A7 B7 經濟部令慧財產局員工消費合作社印製 五、發明說明(β)數位標稱電壓vncm,及在限沆線44i (將於下文參照第1A 圖說明)上之限流倍號β 再參照第1及第3圖,數位控制運算法則64在時序線 4 4纹和4 41)上産生一組控制信號31,&2,.._&11及1)1, b ......bn以控制各個附屬切換電路16之電晶體30及 32。根據電流負載,數位控制蓮算法則64決定毎個附藤 切換電路之切換狀態,亦即電晶體30關閉和NMOS電 晶體32開啓,NMOS電晶體32關閉和PM0S電晶體30開啓》 或PMOS電晶體30和NHOS電晶體32兩者皆開啓,俾維持輸 出端子22上之輸出電壓La贲質地在標稱電壓Vnwn之電 壓容許度Δνη<)πι範圍之内。 替換地,參照第1Α,3Α及13Α圖,主控制器18'可産生 一或多個數位狀態、控制信號,這些信號藉毎値附靥切換電 路16之晶Μ上(on-chip)之解釋器48所解擇以産生控制線 44a,和44b'上之控制倍號。如所示,主控制器18'産生在 狀態控制線44e上之PH0S狀態控制信號h,c2, ...en,在狀態控制線44f上之NM0S狀態控制倍號f 1,f 2, · ‘·fn,及在狀態控制線44 h上之連缠/不連鑌模式蓮轉控制 倍號h t , h 2, ____hn 。具體言之,當附颶切換電路切換 為PM0S導通狀態時,主控制器則輸出在PH0S狀態控制線 4 4 e上之、脈衝49a。相反地,當附屬切換電路切換為NM0S導 通狀態時,主控制器18,則输出在NM0S狀態控制線44f上 之脈衝49be晶Η上之解譯器48解譯在狀態控制線44e上 脈衝49a之上舁緣為用於切換附屬切換電路16為PM0S狀態, -21- 面 之 注 意 事 項 再, 填 寫 本 頁 裝 訂 〇 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)AP〇r〇SS returns to Figure 1 again. As mentioned above, the output voltage Vout 输出 at the output terminal 22 is adjusted by the main controller 18 or maintained at a substantially constant level. The main controller 18 measures the voltage on the output terminal and receives the current detector 4t) and 42 digital output on the output lines 44c and 44d of each attached switch circuit. 8-This paper size applies Chinese national standards ( CNS) A4 specification (210 X 297 mm) II 11 1 pack i !! f order-II-'V. / (Please read the precautions on the back before filling this page) A7 B7 Intellectual Property Bureau, Ministry of Economic Affairs Printed by the employee's consumer cooperative V. Description of the invention (/ 7) The output signal β 镨 should be determined by the output lightning voltage Vout and the current of the current detector. The main controller 18 generates a Control signals for operation of 1 and 2 transistors 30, 32. The operation of the main controller 18 will be described in detail hereinafter. The main controller and the auxiliary switching circuit 16 can be composed of digital and switch / container components, which are almost gold parts. Therefore, most of the switching regulators 10 can implement or manufacture traditional CMOS technology on a single chip. However, it is preferable to fabricate each of the attached switching circuits 16 on a single wafer and the main controller 18 on a separate wafer. Alternatively, 'each attached switching circuit can be manufactured on a single 1C, the voltage detector can be manufactured on a separate chip, and the remaining digital controllers can be manufactured on another 1 (3 crystals. A crystal Η It can be manufactured using traditional CMOS technology. Referring to FIG. 3, the main controller 18 contains a voltage sampling circuit 6D. This circuit 60 tilts or multiplies the discrete time measurement output terminal 22 during each cycle of the switching circuit. Output voltage Vout. The sampling circuit 60 can be made substantially like the patent application filed by Authony J. Stratakos on December 16, 1997. The US patent application serial number is 0/991, 334, and the name is used for the switching regulator. The discrete sample has been transferred to the structure described in the trustee of the present invention. The entire content of this patent application is hereby incorporated by reference. The ground point of the sampling circuit 60 can be directly connected to the processor. The ground point reduces the errors caused by parasitic capacitance and inductance. The voltage sampled by the sampling circuit 60 is converted into a digital voltage signal by an analog to digital (A / D) converter 62. The main controller 1 8 g contains digital control Lotus algorithm is 6 4. Digitally controlled lotus-1 9- This paper size applies to China National Standard (CNS) A4 specifications < 210 X 297 mm) ------------- yM .-- -i (Please read the precautions on the back first to fill in this page) Order · Sleep 4 〇- 线 451 π 5 A7 B7 V. Description of the invention (status) The algorithm receives the digital voltage signal from the A / D converter 62. The output signals ci, c2, ... cn and dU, ____dn of the output lines 44c and 44d, and the clock number 66 from the external clock. Clock signal 66 (Read the precautions on the back before filling in this page) Can be generated by the same clock as those running the processor, other 1C devices in the load, or the clock on the main controller chip . The clock frequency fclt) ck should be much higher than the switching frequency fswlteh of the switching circuit 24, for example, 1 D to 100 factors, to ensure fast response to load changes. However, the clock frequency fclock should not be high enough to make the switching regulator And the main controller draws a lot of power from the power supply. Typically, the clock frequency fd (iek is not as high as the clock speed of the dismounted processor and can be generated by dividing the clock signal of the microprocessor. The clock signal 66 may have a frequency between about 16 and 66 HHZ, for example, about 33 MHz ^ Mm fclock. Referring to Figure 3A, another example of the main controller IV includes a voltage sampling and holding circuit 60 'connected to the output terminal 22 to measure the difference between the output voltage and the nominal voltage, which is Vout (n) -Vnom, and the difference between the current output voltage and the output voltage of the previous clock cycle, that is, V_n) -V_ (1 > 1) printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The digital nominal voltage V ησινν can be set by an external pin and converted to an analog voltage by a digital-to-analog (D / A) converter 68. In this example, the voltage difference sampled by the sampling circuit 60 'is converted by two D / A converters 62_ into two digital voltage difference signals. The smaller conversion range required by the voltage difference (compared to the A / D converter 1 (6 ')) allows simpler and faster A / D converters. The digital control algorithm receives signals from the A / D converter Digital voltage difference of 62 ', the output signals Ci, C2, ... Cn and di, d2 ..... dn from the output lines 44c and 44d, and the external clock signal 66, -2 0- This paper size applies to Chinese National Standard (CNS) A4 (210 X 297 mm) 451115 A7 B7 Printed by the Ministry of Economic Affairs and the Consumer Property Cooperatives of the Bureau of Intellectual Property. V. Description of invention (β) Digital nominal voltage vncm, The current limiting multiple β on line 44i (which will be described below with reference to Figure 1A). Referring to Figures 1 and 3 again, the digital control algorithm 64 generates a set of control signals 31 on the timing lines 4 4 and 4 41. &Amp; 2, .._ & 11 and 1) 1, b ... bn to control the transistors 30 and 32 of each auxiliary switching circuit 16. According to the current load, the digital control lotus algorithm 64 determines the switching state of a Futo switching circuit, that is, the transistor 30 is turned off and the NMOS transistor 32 is turned on, the NMOS transistor 32 is turned off and the PM0S transistor 30 is turned on. Both 30 and the NHOS transistor 32 are turned on, and the output voltage La at the output terminal 22 is maintained to be within a voltage tolerance Δνη <) π of the nominal voltage Vnwn. Alternatively, referring to FIGS. 1A, 3A, and 13A, the main controller 18 'may generate one or more digital states and control signals. These signals are explained by the on-chip of the switching circuit 16 attached thereto. The selector 48 is selected to generate control multiples on the control lines 44a, 44b '. As shown, the main controller 18 'generates the PH0S state control signals h, c2, ... en on the state control line 44e, and the NM0S state control times f1, f2, ·' on the state control line 44f. · Fn, and the continuous / non-flailing mode on the state control line 44 h, the turn control times ht, h 2, ____hn. Specifically, when the hurricane switching circuit is switched to the PM0S on state, the main controller outputs a pulse 49a on the PH0S state control line 4 4e. Conversely, when the auxiliary switching circuit is switched to the NMOS state, the main controller 18 outputs a pulse 49be on the NMOS state control line 44f, and the interpreter 48 interprets the pulse 49a on the state control line 44e. The upper edge is used to switch the auxiliary switching circuit 16 to the PM0S state. Please note that this page is bound. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm).
經濟部智慧財產局員工消費合作社印製 i'發明說明(k) 例如藉設定控制線44a_高及設定控制線44 IT低之命令。 相反地,在狀態控制線44 f上脈衝49 b之上昇緣藉晶片上 之解譯器48解譯成用於切換附屬切換電路16為NMOS狀態, 例如藉設定控制線44a,低及設定控制線44b1髙之命令。 晶片上之解譯器能將狀態控制線44e和44 f上脈衝之下降 銻分別為讓電流偵測器4 Q和4 2上之tb較器5 6使能(e n a U e ) 之命令β 如果連缠模式使能(例如控制線4 4 h低)時,則當附靥 切換電路I8]flve負值時,切換電路正常地動作。但是, 如果PMOS電晶體30關閉且不連績模式蓮轉控制信號失能 (disabled)(例如控制線44h高)時則在附靥切換電路電 流IsLave .下降到低於零之情況下,PM0S電晶體30及NM0S 電晶體32兩者皆開啓,俾阻止負電流通過附屬切換電路 。總體言之,主控制器18使附屬切換電路於不逋鑛模式 上蓮轉,因這種模式之效率高。但是,如杲負載大又快 速下降時,在連续模式上蓮轉較為有利。 附屬切換電路可、另包含故障保護電路68,此電路68如 果通過切換電路之電流超過危險位準,例如15安培,時 即自動停止附屬切換電路之運轉(蓋過主控制器送出之控 制信號)。如果故障保護電路68動作時附屣切換電路則可 送出在限流線44i(參照第3 Α圔)之數位信號以通知主控制 器18'附颶切換電路已停止動作。附颶切換電路可産生其 它之數位回授倍號β例如,附靥切換電路可包含用於産 生表示切換調整器之狀態,例如PM0S或NM0S導通狀態之 -22- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) —1- · --------訂--------- π 一·) {請先閱讀背面之注意事項再填寫本頁) 、 Α7 Β7 五、發明說明(巧) 數位狀態信號之狀態偵測器。 參照第4圖,毎値時脈週期Tclock ,例如時脈頻率 若約為3 3 M U z時則約為每3 Ο X 1 秒,數位控制蓮算法 則6 4坷執行控制方法1 〇 〇。控制蓮算法則64決定代表通 過附靥切換電路之電感器之電流之每锢附屬切換電路之 預估電流 Iestimate (步驟1D2)。控制蓮算法則64另計算 代表在輸出端子22上之目標輸出電壓Vdes (步驟104), 及計算代表應經電感器流至負載侔維持輸出電壓ν。^實 質地相等於窩要電壓Vdes之電流之需要之總電流 Itatal (步驟112)β下文將講述前面之各锢步驟。但是,應瞭 解這些步驗不需依特定之順序執行。例如,各種計算能 同時執行或於前一時脈週期執行及儲存結果。具體言之 ,需要之電壓及電流可予以計算及儲存做為次一時脈週 期使用。 參照第1及第5圖預估,電流Iestimate 俗在步驟1 0 2 上計算。通過電烕器之電流之變化率,亦即dI/dT,像 比例於加在電威器上之電壓,,俾 (請先閱讀背面之注意事項I填寫本頁)Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs i 'Invention Description (k) For example, by setting the control line 44a_high and the control line 44 IT low. Conversely, the rising edge of the pulse 49 b on the state control line 44 f is interpreted by the interpreter 48 on the chip to switch the auxiliary switching circuit 16 to the NMOS state, for example, by setting the control line 44 a, low and setting the control line. Command of 44b1. The interpreter on the chip can reduce the pulses of antimony on the state control lines 44e and 44f respectively to enable the tb on the current detectors 4Q and 4 2 to be enabled (ena U e). Β If When the continuous winding mode is enabled (for example, the control line 44 h is low), when the auxiliary switching circuit I8] flve is negative, the switching circuit operates normally. However, if the PMOS transistor 30 is turned off and the continuous transfer mode control signal is disabled (for example, the control line 44h is high), then the auxiliary switching circuit current IsLave. Drops to less than zero. Both the crystal 30 and the NMOS transistor 32 are turned on, preventing negative current from passing through the attached switching circuit. In general, the main controller 18 causes the auxiliary switching circuit to rotate in the non-mining mode because the efficiency of this mode is high. However, when the load is large and decreases rapidly, lotus rotation is more advantageous in continuous mode. The auxiliary switching circuit may also include a fault protection circuit 68. If the current through the switching circuit exceeds a dangerous level, such as 15 amps, the operation of the auxiliary switching circuit will be automatically stopped (overriding the control signal sent by the main controller) . If the fail-safe circuit 68 is activated, the auxiliary switching circuit may send a digital signal on the current limit line 44i (refer to 3A) to notify the main controller 18 'that the auxiliary switching circuit has stopped operating. The switching circuit with hurricane can generate other digital feedback multiples β. For example, the switching circuit with 靥 can include -22 for generating the state of the switching regulator, such as the ON state of PM0S or NM0S. CNS) A4 specification (210 X 297 mm) —1- · -------- Order --------- π a ·) {Please read the precautions on the back before filling this page) Α7 Β7 V. Description of the Invention (Clever) State detector for digital status signal. Referring to Figure 4, the clock cycle Tclock, for example, if the clock frequency is about 3 3 M Uz, it is about every 30 × 1 second, and the digital control algorithm is 64, and the control method 1 is executed. The control algorithm 64 determines the estimated current Iestimate for each auxiliary switching circuit representing the current through the inductor of the auxiliary switching circuit (step 1D2). The control algorithm 64 additionally calculates the target output voltage Vdes representing the output terminal 22 (step 104), and calculates that the representative should flow through the inductor to the load to maintain the output voltage ν. ^ Actually, the total current Itatal (step 112), which is equivalent to the current of the main voltage Vdes, is described in the following. However, it should be understood that these steps need not be performed in a particular order. For example, various calculations can be performed simultaneously or in the previous clock cycle and the results can be stored. Specifically, the required voltage and current can be calculated and stored for use in the next clock cycle. Referring to Figures 1 and 5, the current Iestimate is calculated at step 102. The rate of change of the current through the electronic device, that is, dI / dT, is proportional to the voltage applied to the electric device, 俾
經濟部智慧財產局員工消費合作社印製 上式中之L偽電流從中間端子26流至輸出端子22之電感 器之電感。在?《(^導通狀態期間,中間端子26條接至輸 入電源,且加於電SK器34兩端之電壓 ,亦ΕΠ vout -vimerme<liate .,葆正值,藉此使流過電感器之電流 增加》相反地,在N Μ (3 S導通狀態期間,中間端子2 6偽接 -23-本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 451115Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The L pseudo current in the above formula flows from the intermediate terminal 26 to the inductor of the inductor at the output terminal 22. in? << (During the on-state, the 26 intermediate terminals are connected to the input power and the voltage applied to the two ends of the electric SK device 34 is also ΠΠ vout -vimerme < liate., Positive value, thereby making the current flowing through the inductor Increasing >> Conversely, during N M (3 S on-state, the middle terminal 2 6 is pseudo--23)-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 451115
Af7 五、發明說明(A) 地俥加於電感器34兩端之電壓 VtoduetOT 傺負值,藉此 使流過電感器之電流減少。在PHOS導通狀態期間,附屬 切換電路電流Islave 之斜率(虛線70所示)係藉下式求出Af7 V. Description of the invention (A) The voltage VtoduetOT applied to ground across inductor 34 is negative, thereby reducing the current flowing through the inductor. During the PHOS on-state, the slope of the auxiliary switching circuit current Islave (shown as dashed line 70) is obtained by the following formula
d! X dT L (2) 至於在NM0S導通狀態期間,附靥切換電路電流I 之斜率傜由下式求出 f=rr- L (3) 每個時脈週期調整預估電流 Iestimate .(實線7 2所示)。 具體言之,在pkos導通狀態期間,預估電流 iestimate 在每個時脈週期僳以遞昇值Alup遞昇。相似地,在N Μ 0 S 導通狀態期間,預估電流 Ie3timate .,在每個畤脈週期傺 以遞降值 遞減。遞昇及遞降值及 可由下式求出 Δ/., V.. •Λί«* — L、h (4 ) 上式中之L傺電感器34之電感,而fdc>ek 偽時脈頻率。 在決定ΔΙ#及ΛΙαπ 上可使用檫稱值做為變數俥在 ,算遞 地重整 I 直 換來調if流 替用地ΕΪ電 。並態έΙΕ估 變值動 2 預 改之間L, 不 L 期流此 率及轉電因 降ck蓮入。 遞fclo器輸變 及 整及改 舁,諏L而· 0vout換感路24 間 切電電· 期’在,或 轉νώ俾是間 蓮傾 但時 1^down。# 器或'AId率隨 整 一降能 調定 遞且 換測IUP及曉 切可 △昇知 (請先閲讀背面之注意事項再填寫本頁> 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 451 1 1 5 A7 B7 五、發明說明(>>) 1 estimated! X dT L (2) As for the slope of the switching circuit current I during the ON state of the NM0S, f = rr-L is obtained from the following formula: (3) The estimated current Iestimate is adjusted for each clock cycle. Line 7 2). Specifically, during the pkos on-state, the estimated current iestimate is incremented by a step-up value Alup at each clock cycle. Similarly, during the N M 0 S on-state, the estimated current Ie3timate is decreased by a decreasing value at each pulse cycle. The ascending and descending values and can be obtained by the following formula: Δ /., V .. • Λί «* — L, h (4) The inductance of the L 傺 inductor 34 in the above formula, and fdc > ek is the pseudo clock frequency. In the determination of ΔΙ # and ΛΙαπ, the nominal value can be used as a variable 俥 in, and the I stream can be recursively recalculated to adjust the if current instead of the electric current. The estimated value of the parallel state changes 2 and the pre-modification rate is between L, L, and L. This current rate and the power transfer are reduced. Pass the fclo device to change and rectify and change 舁, 诹 L, and 0vout 24 sense circuits, cut electricity, period, ‘on’, or turn νώ 俾 is between, but time is 1 ^ down. # Device or 'AId rate can be adjusted with the whole energy reduction and change test IUP and Xiao cut can △ ascend to know (please read the precautions on the back before filling this page > This paper size applies Chinese National Standard (CNS) A4 Specifications (210 X 297 mm) 451 1 1 5 A7 B7 V. Description of the invention (> >) 1 estimate
會偏離實際之附屬切換電路電流I •slave 是 A estimate 下降到低於下臨界電流h 預估電流 以,需時時檢查預估電流 iestimate 對實際之附靥切換 電路電流 IsIave 。每個時脈週期檢査附靥切換電路之 預估電流 Iestimate .相對於電流偵測器4 0及4 2之輸出信號 。如果預估值與測定值不一致時,則諝整預估值俾使兩 者匹配。 參照第6 A及7A圃,在PMOS導通狀態期間,如果預估電 流 Iestimate 低於上臨界電流 IPc^ss ,但電流偵測器4 0 之輸出電流c i髙時則増加預估電流 Iestunate 俾匹配 Ipcr〇ss 。胃 6Β&7Ββ> MM® (古® @ Utim扯 m 過上臨界電流IPW(1SS ,但輸出電流Ci低時,預估電流 iestimate m iPcross 謂輸 mi言 μ p 胃 3 it 〇 # 照第6C及7C圖,在NM0S導通狀態期間,如果預估電流 Iestimate 高於下臨界電流IPe_ ,但電流偵換j器4 2之 輸出信號d i低時,預估電流 Iestimate 則立即上昇以匹 配Ιρππ 。參照第6D及70圖,如果預估H流 iNcross , m ii aw言 ^ d!胃 af , Iestimate 則保留在INen)SS直到輸出信號d i 降低為止。第1表示出預估電流 Iestimate 計算之摘妄 請 先 閱 讀 背 之 注 意 事 % 填 本 頁 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 4 5 1115 A7 B7 五、發明說明(岑) 第1表 PM0S導通 狀態 ^estimate > Ipcross C 1高 〇< 藉 ΔΙυρ 遞昇 C 1低 ^ ^ ^estimate ^ Across ^estimate 〈 I Process c 1高 增加 ^estimate 至 ^Process c i低 藉△ Iup 遞昇 Iestimate NM0S導通 狀態 T Aestimate > Ipcross d i高 藉△ Idcjwn 遞降 Intimate d !低 減少 Intimate 至 Iffcross ^estimate 、 < Ipcross d l高 保持 Intimate 於 IweiOM d i低 藉△ Id_ 遞降 iestimate -------------裝 i I <請先閱讀背面之注意事項&填寫本頁) 訂: -線; 經濟部智慧財產局員工消費合作社印製 數位控制蓮算法則在Ρ Μ 0 S與Ν Μ 0 S之導通狀態間切換後 之一或多個時脈週期可省略電流偵測器送出之信號俾防 止假倍號意外地調整預估電流。 跳脱比較器使用之切換時間所造成之遲延時間△T&b 及信號沿著輸出線44 c或44 d移動所需之傳播時間在決定 預估電流時或要計及。例如,如果在輸出信號Ci從低 -2 6 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 45彳彳彳5 A7 B7 五、發明說明(X) 切換為高之際校正預估電流Iestimate 時則將校正因數 ATdeky X AIUP x fswltch加於預估電流俾代表主控 制器收到輸出佶號c i之變化時之實際電流。相似地,It will deviate from the actual auxiliary switching circuit current I • slave is A estimate dropped below the lower critical current h. The estimated current is to check the estimated current iestimate for the actual auxiliary switching circuit current IsIave. Check the estimated current Iestimate of the attached switching circuit with each clock cycle. Relative to the output signals of the current detectors 40 and 42. If the estimated value does not match the measured value, the estimated value is rounded to match the two. Referring to 6A and 7A, during the PMOS on-state, if the estimated current Iestimate is lower than the upper critical current IPc ^ ss, but when the output current ci of the current detector 40 is increased, the estimated current Iestunate is added to match Ipcr. 〇ss. Stomach 6B & 7Bβ > MM® (古 ® @ Utim 拉 m Over critical current IPW (1SS, but when the output current Ci is low, the estimated current iestimate m iPcross is referred to as mi μμ stomach 3 it 〇 # According to 6C and Figure 7C. During the ON state of NMOS, if the estimated current Iestimate is higher than the lower critical current IPe_, but when the output signal di of the current detection device 4 2 is low, the estimated current Iestimate immediately rises to match Ιρππ. Refer to Section 6D And figure 70, if the estimated H current iNcross, m ii aw ^ d! Stomach af, Iestimate will remain in INen) SS until the output signal di decreases. The first shows the presumption of the estimated current Iestimate, please read first Note on the back% Fill in this page Printed by the Employees' Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs This paper is printed in accordance with Chinese National Standard (CNS) A4 (210 X 297 mm) 4 5 1115 A7 B7 V. Description of Invention (Cen) Chapter 1 Table PM0S conduction state ^ estimate > Ipcross C 1 high 〇 < borrow ΔΙυρ step-up C 1 low ^ ^ ^ estimate ^ Across ^ estimate <I Process c 1 high increase ^ estimate to ^ Process ci low borrow △ Iup step-up Ies Ultimate NM0S on-state T Aestimate > Ipcross di high borrow △ Idcjwn descending Intimate d! low decrease Intimate to Iffcross ^ estimate, < Ipcross dl high keep Intimate at IweiOM di low borrow △ Id_ descending iestimate -------- ----- Install i I < Please read the notes on the back & fill out this page) Order: -line; Digital Control Lotus algorithm printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs is printed in Μ 0 S and Ν The signal sent by the current detector can be omitted in one or more clock cycles after switching between the on-states of the M 0 S, preventing false multiples from accidentally adjusting the estimated current. The delay time △ T & b caused by the switching time used by the trip comparator and the propagation time required for the signal to move along the output line 44 c or 44 d may be taken into account when determining the estimated current. For example, if the output signal Ci goes from low to 2 6-this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 45 彳 彳 彳 5 A7 B7 V. Description of invention (X) switches to high When the international correction estimated current Iestimate is added, the correction factor ATdeky X AIUP x fswltch is added to the estimated current, which represents the actual current when the main controller receives a change in the output signal ci. Similarly,
如果在輸出信號di從高切換為低之際校正預估電流 Iestimate 時則自預估電流減去校彭! X AIdown . x fswitch 。替換地,臨界電流IPe„ss 可減少 一校正因數X Iup X fswitch ,而臨界電流 In«ms 可增加一校正因數X AIdown X fswitch (同時維持第1表使用之IPcross 及l!toc)SS 之原始值), 兩者可得相同之效果。 參照第8圖,在步驟104上選擇所需電壓Vdesired .以 改善輸出電壓ν。^俾雄持在標稱電壓vn<)m之電壓容許度 △vn()m之範圍内。負載變化對輸出電壓之效應係以 虛線80表示。具體言之,當負載突增時,電流從電容器 36流入負載14,藉此增加輸出電壓V;ut。相反地,當切 換調整器之負載突減時,電荷則累積往電容器36上,進 而增加輸出電壓V。^ 。此使輸出電壓VTOt超過容許度電 壓,例如過電壓 。 經濟部智慧財產局員工消費合作社印製 ------------V裝--- (請先閒讀背面之注意事項#··填寫本頁) 主控制器18選擇所需電壓 Vdesired 俾增加或消除過電 壓⑵一。當切换諏整器上之負載俗最小時,負載 能增加,,因此輸出電壓只能減少。相反地,當切換 調整器上之負載最大時,負載只能減少,因此輸出電壓 只能增加。當負載低時,所需電壓Vdesircd 能設定 稍髙於標稱電壓Vn(jm〇當負載高時,所需電壓vdesired "2 7 _ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 451115 A7 B7 五、發明說明(β) (請先閲讀背面之*一意事項再填寫本頁) 可設定稍低於標稱電壓义^。如實線82所示,此項技術 減少過電壓△ ναπα ,進而改善輸出電壓\^^維持在標 稱電壓V 之所要電壓容許度範圍内之機率。因 nom 此,對已知之負載,切換諏整器能使用較小電容器及維 持相同之電壓容許度。時脈週期n+l之所需電壓 ^de3ired[n+l] 可如下計算: 厂如《»*/(«+|】=十(;!(厂|«»1 —+ +Ci) (5) \ ^mix ) 上式中之Itoad傜通過負載1 4之電流(由下面之方程式8 算出),Imax傺容許流過負載14之最大電流,(^及^ 係回授常數,及傜容許電壓變化一電壓容許度 ,亦即。例如,如果標稱電壓VnQm傺 1 . 3 V及電壓容許度傜+ / - 6 %時則Λν_可約為7 8 △Vswing約為1 Q ra ν,c i可約為1 . Q及c 2可約為-Q . 9 3 7 5。 於步驟1Q4上一旦決定所需電壓Vdesired 後則在步驟 106上決定所需之總電流 Ilt>ad 。具體言之,設定所需 電流 以維持輸出端子22上之輸出電壓於需電壓 vdesired 。總而言之,假定輸出電壓Vmt等於所需電壓 經濟部智慧財產局員工消費合作社印製If the estimated current Iestimate is corrected when the output signal di is switched from high to low, then the correction is subtracted from the estimated current! X AIdown. X fswitch. Alternatively, the critical current IPe „ss can be reduced by a correction factor X Iup X fswitch, and the critical current In« ms can be increased by a correction factor X AIdown X fswitch (while maintaining the IPcross and l! Toc used in Table 1) SS original Value), both can get the same effect. Referring to FIG. 8, the required voltage Vdesired is selected at step 104 to improve the output voltage ν. The voltage tolerance Δvn is held at the nominal voltage vn <) m. Within the range of (m). The effect of load change on output voltage is indicated by dotted line 80. Specifically, when the load suddenly increases, current flows from capacitor 36 to load 14, thereby increasing the output voltage V; ut. Conversely, When the load of the switching regulator drops suddenly, the charge accumulates on the capacitor 36, which increases the output voltage V. ^. This causes the output voltage VTOt to exceed the allowable voltage, such as overvoltage. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ------------ V installation --- (please read the precautions on the back # ·· Fill in this page first) The main controller 18 selects the required voltage Vdesired 俾 Increase or eliminate overvoltage ⑵ The load is minimal when switching the conditioner The load can increase, so the output voltage can only decrease. On the contrary, when the load on the switching regulator is the maximum, the load can only decrease, so the output voltage can only increase. When the load is low, the required voltage Vdesircd can be set slightly髙 Nominal voltage Vn (jm〇 when the load is high, the required voltage vdesired " 2 7 _ This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) 451115 A7 B7 V. Description of the invention β) (Please read the * intentions on the back before filling this page) You can set the value slightly lower than the nominal voltage ^. As shown by the solid line 82, this technology reduces the overvoltage △ ναπα, and then improves the output voltage \ ^^ maintenance Probability within the required voltage tolerance range of the nominal voltage V. Therefore, for known loads, switching regulators can use smaller capacitors and maintain the same voltage tolerance. Required for the clock period n + 1 The voltage ^ de3ired [n + l] can be calculated as follows: Factory such as "» * / («+ |] = ten (;! (Factory |« »1 — + + Ci) (5) \ ^ mix) Itoad 傜 current through load 1 4 (calculated by Equation 8 below), Imax 傺 allowable current The maximum current of load 14, (^ and ^ are the feedback constants, and 傜 the allowable voltage change is a voltage tolerance, that is. For example, if the nominal voltage VnQm 傺 1.3 V and the voltage tolerance 傜 + /-6% Then Λν_ can be about 7 8 ΔVswing is about 1 Q ra ν, ci can be about 1. Q and c 2 can be about -Q. 9 3 7 5. Once the required voltage Vdesired is determined at step 1Q4, the total required current Ilt &ad; ad is determined at step 106. Specifically, the required current is set to maintain the output voltage on the output terminal 22 to the required voltage vdesired. All in all, assuming that the output voltage Vmt is equal to the required voltage, printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
Vdeaired 時,則通過電烕器流到負載之總電流應等於流 過負載之、電流,亦卽ItetaI = Itoad 。但是,如果電壓 不等於所需電壓 Vdesired '時,流過切換調整器10之 電流可調整以校正此電壓誤差。因此,所需總電流1_ 可用下式表示 -2 8 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 4 5 …5 A7 B7 五、發明說明(π) l|«ul ~【l»d + (6) 上式中之Iadjust 傺用於校正電路誤差之調整因數。 (請先閱讀背面之注意事項再填寫本頁) 參照第9圖,假設接到輸出端子之所有電容器皆設在 附屬切換電路内,則負載電流Ibad係等於每個附靥切換 電路16流出之電流之總和,亦卽,When Vdeaired, the total current flowing to the load through the electronic device should be equal to the current flowing through the load. ItetaI = Itoad. However, if the voltage is not equal to the required voltage Vdesired ', the current flowing through the switching regulator 10 can be adjusted to correct this voltage error. Therefore, the total required current 1_ can be expressed by the following formula-2 8-This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 4 5… 5 A7 B7 V. Description of the invention (π) l | « ul ~ [l »d + (6) Iadjust 傺 in the above formula is used to correct the adjustment factor of the circuit error. (Please read the precautions on the back before filling this page.) Referring to Figure 9, assuming that all capacitors connected to the output terminals are located in the auxiliary switching circuit, the load current Ibad is equal to the current flowing from each auxiliary switching circuit 16 The sum,
.V = (7) 每個附屬切換電路16 之輸出電流 偽等於流經 電感器34之電流,亦即附餳切換電路 IsIave[i) ,與流 進或流出電容器36之電流,亦即電容器電流 Ieap(i| 間 之差,亦即.V = (7) The output current of each auxiliary switching circuit 16 is pseudo-equal to the current flowing through the inductor 34, that is, the sugar switching circuit IsIave [i), and the current flowing into or out of the capacitor 36, that is, the capacitor current Ieap (i |
CiO = I,j»»t(i) - ⑻ 因此,於此種組態,所需之總電流Itotal可用下式表示CiO = I, j »» t (i)-⑻ Therefore, in this configuration, the total current Itotal required can be expressed by the following formula
U N ~ > : ^ : ^ee/l(0 ^ajjyst (9) 1 1 附屬切換電路電流 Islave(i) 之正確值不知曉,但可用 各個附屬切換電路之預估電流之總和做為近似值。另外, 電容器電流 IeapW 不知曉,且附鼷切換電路内之電容器 可加設一或多個電容器或被一或多個電容器如接至電感 器3 4之共通線之撤處理器之旁通電容器取代。但是,總 體上,如果輸出電壓難改變時則電流須流進或流出電容 經濟部智慧財產局員工消費合作社印製UN ~ >: ^: ^ ee / l (0 ^ ajjyst (9) 1 1 The correct value of the auxiliary switching circuit current Islave (i) is unknown, but the total of the estimated currents of the auxiliary switching circuits can be used as an approximate value. In addition, the capacitor current IeapW is not known, and the capacitor in the attached switching circuit may be provided with one or more capacitors or replaced by one or more capacitors such as a bypass capacitor of the processor connected to the common line of the inductor 34 However, in general, if the output voltage is difficult to change, the current must flow into or out of the capacitor. It is printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs.
器36。是故,總電容器電流Ieap(i>可用下式表示 AV器 36。 36. Therefore, the total capacitor current Ieap (i > can be expressed by AV
/Cy> = C △ Γ (10) 上式中之C像接在輸出端子與地間之電容器之總電容, △ T係時脈週期,及 Λν^偽在時脈週期内輸出電壓之 變化《因此,總電流 Itotal大體上可藉下式求出 -2 9 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 4 b ί π 5 五、發明說明(★) 經濟部智慧財產局員工消費合作社印製 Α7 _Β7 =έ, V Μ Jimcn .(0 AT -C (Π) 於 第 3 rst 圖 所 示 之實 例 9 可藉 數位控制 蓮算法 則 64計算 △V0ut > 亦 即 V〇ut[n]~* V〇ut[n-1 】 而第3A圖所示之賁例 則 藉 採 樣 和 保 持電 路 6 0 '提供電壓差 ▽outin广 V〇ut[u-1 】 0 調 整 器 電 流 ^adjust 可直線比例於測定之輸出電壓ν。^ 與 需 要 電 壓 ^desired 間 之 差。 因此,所 需之總 電 流 【total 可 藉 下 式 算 出 : Atf/w * iu 1 ,^0)- ΔΓ c + K(yulll~ Vik.'incd ) (»2) 上 式 中 之 K 條 決 定調 整 電 流 Iadjust 之回授常數。 在 步 驟 10 8上, 一旦決定所需之總電流後,主控制器 1 8 卽 決 定 多 少 附 颶切 換 電 路應 動作。目 前週期 動 作 之附 屬 切 換 電 路 之 數 目能 在 先 前之 時眤週期 上算出 0 大 體上 » 動 作 之 附 屬 切 換電 路 之 數目 傺成比例 於所需 之 總 電流 〇 例 如 ? 如 果 逋 過每 舾 切 換電 路16之最 大平均 電 流 約為 7 安 培 時 I total 在0 到 7 安培 内動作一 個附屬 切 換 電路 ,在7到1 4安培内則動作兩個附屬切換電路,依此類比 堆^更具體言之,動作之附'屬切換電路之數目可如表2 示 所 (請先閲讀背面之注意事項再填寫本頁) 裝 訂---------線、 本紙張尺度適用中國國家標準(CNSJA4規格(210 X 297公釐)/ Cy > = C △ Γ (10) The total capacitance of the capacitor with C image connected between the output terminal and ground in the above formula, △ T is the clock period, and Δν ^ the change of the output voltage during the clock period " Therefore, the total current Itotal can be roughly calculated by the following formula: 2 9-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 b ί π 5 V. Description of the invention (★) Ministry of Economic Affairs Printed by the Intellectual Property Bureau employee consumer cooperative A7 _Β7 = 7, V Μ Jimcn. (0 AT -C (Π) in the example shown in Figure 3 rst V〇ut [n] ~ * V〇ut [n-1] and the example shown in Figure 3A uses the sample and hold circuit 6 0 'to provide the voltage difference ▽ outin V〇ut [u-1] 0 adjustment The device current ^ adjust can be linearly proportional to the measured output voltage ν. ^ And the required voltage ^ desired. Therefore, the total required current [total can be calculated by the following formula: Atf / w * iu 1, ^ 0)- ΔΓ c + K (yulll ~ Vik.'incd) (»2) K in the above formula determines the adjustment Feedback constant of current Iadjust. At step 10 8, once the total required current is determined, the main controller 1 8 decides how many additional hurricane switching circuits should operate. The number of auxiliary switching circuits currently operating in a cycle can be calculated as 0 in the previous period. Generally »The number of auxiliary switching circuits in operation is proportional to the total current required. For example, if it exceeds 16 of each switching circuit The maximum average current is about 7 amps. I total operates an auxiliary switching circuit within 0 to 7 amps, and two auxiliary switching circuits operates within 7 to 14 amps. 'The number of switching circuits can be as shown in Table 2 (please read the precautions on the back before filling this page) Binding --------- The size of the paper is applicable to the Chinese national standard (CNSJA4 specification (210 X 297 mm)
fits A7 B7 L、發明說明(4 ) 第2表fits A7 B7 L, description of the invention (4) Table 2
Number of Active Slaves for Clock Cycle N Total Current lt0llJ (amps) Number of Active Slaves for dock cycle S-H 1 〇> I,mai 7>U4 14>Ι10,„>21 21iU>28 28> U 1 2 3 4 1 5 ^ 7 〇> ^ 6> Iroa^H 14>:Ilola, >21 21^,,1 >28 1 ? 3 Ί 4 5 3 〇> 匕 2:6 Iioui 112 12^ >21 21^ >28 4 2S> 1,«, 5 1 2 3 4 〇> Ιω〇ι >6 Itoiai h\2 ΐ2έ:Ι1Μΐ1ΗΠ 18i:U>28 4 28> It0lii 5 1 2 » J 5 〇> 1,0,.1 ^ \2^>^ l8>Itoul>24 4 24> ΙΙίΛΛι 5 I 2 3___j 於上下騒動110上一旦決定所需之總雷流 Itatal 及動 作之附靥切換電路之數目後可計算每個附靥切換電路之 所需電流 IdMired 具體言之,所需電流1desired 可簡單 地藉總電流itotal除以動作之附靥切換電路求出。 一旦計算出毎橱勤作之附靥切換電路之所需電流 Idesired 後即可控制毎個附屬切換電路之切換電路(步驟 112),俾使通過動作之附屬切換電路之平均電流實質等 於所需之電流Idesired ,及通過切換調整器102總電流 實質等於Itotal 。藉此流出切換調整器1 0之電流匹配流 入負載14之電流,進而維持輸出電壓於所需之電壓 V,.,。其餘,亦即不動作之附颶切換電路,則係截 v desired 斷,亦即PH0S電晶體3G和UM0S電晶體兩者皆開啓。 有各種用於控制動作之附靥切換電路之切換電路之控 制運算法則,俾使通過切換調整器之總電流實質等於所 箱之總電流itotaJ β大體上,控制蓮算法則係選擇以平 衡下述因數:1)使所有之附屬切換電路®速響應負載之 -31- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 請 閲讀 背 面 之 注 項 再,.,填11裝頁 訂 ik 5 經濟部智慧財產局員工消费合作社印製 4 β Α7 Β7 五 、發明說明(如) _化而同時切換為導通或截斷,2)確保所有之附屬切換 電路在所需之相位偏移下動作俾減少漣波至最小,3)保 持平均電流等於維持電壓於實質恆常位準所要之電流, 及4)在所要之切換頻率下進行切換。 參照第10圖,選擇,例如根據既定之選擇型樣動作之 附屬切換電路之一做為參考附屬切換電路(步驟120)。 例如可指定特定之附屬切換電路做為參考切換電路或可 輪流指定附颺切換電路做為參考附靥切換電路》如下文 所述,剩餘之附靥切換電路,亦即非參考附靥切換霍路 之舉動傜繫於參考附屬切換電路之舉動。參考附靥切換 電輅可在切換調整器接上電源時選擇,或每當改變動作 之附屬切換電路之數目時被選擇。參考附屬切換電路一 旦選擇後即計算每橱非參考附屬切換電路之所需相位偏 移(步驟122)。所需之相位偏移每當動作之附屬切換電路 改變時可被決定。非參考附屬切換電路被控制在需要之 相位偏移下動作。 每個時脈週期上計算參考附靥切換電路之兩個限流值, 亦卽電流上限Iupp„ 及電流下限 ^。胃(步驟1 2 4 )。最 後,根據參考附屬切換電路控制運算法則控制參考附屣 切換電路(步驟126)及根據非參考附屬切換電路蓮算法 則控制非參考附屬切换電路(步驟128)«»於一些移序與 步驟上,參考附屬切換電路傺根據預估電流Iestijnate 對上及下電流限制值Iuppw及I1(WOT之比較而控制,及 非參考附屬切換電&俗根掸所需之相位偏移而控制。當 -------------裝--- {請先閱讀背面之注意事項#填寫本頁) --線: -32 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 2 0 ° ,及時間遲延多(1) , 0 ( 2 )應分別等於切 匕1/ 3及2/ 3。藉附屬切換電路於相位差下蓮轉 Ϊ靥切換電路之電流漣波至少局部抵銷,進而提 哲之切換調整器之輸出電流。第3表摘要示出需 δ偏移。 g ί 5 A7 _B7_ 五、發明說明(疗) 然,第10圖所示之步驟之順序傜為舉例而已,這些步驟 亦能平行執行。例如,任何特定之時脈週期,能在計算 相位偏移前計算限流值及如果葆根據計算及儲存於前時 脈週期之限流值及相位偏移時則計算步驟能在控制步驟 之後執行。 , 於步驟122上,對每個非參考附屬切換電路,控制蓮 算法則計算代表參考與非參考附屣切換電路間,PHOS和 NMOS開始導通之所需時間遲延之所需相位偏移於(i)。 例如,如果兩個附屣切換電路動作時兩者之相位則相差 180° ,及時間遲延應等於切換週期T之一半,亦即iMi) =1 / 2 T。如果三個附屬切換電路動作時則它們之相位 應相差1 換週期 ,每個 供更恆 要之相 第3 -----------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製Number of Active Slaves for Clock Cycle N Total Current lt0llJ (amps) Number of Active Slaves for dock cycle SH 1 〇 > I, mai 7 > U4 14 > Ι10, „> 21 21iU > 28 28 > U 1 2 3 4 1 5 ^ 7 〇 > ^ 6 > Iroa ^ H 14 >: Ilola, > 21 21 ^ ,, 1 > 28 1? 3 Ί 4 5 3 〇 > Dagger 2: 6 Iioui 112 12 ^ > 21 21 ^ > 28 4 2S > 1, «, 5 1 2 3 4 〇 > Ιω〇ι > 6 Itoiai h \ 2 ΐ2έ: ΙΜΜ1ΗΠ 18i: U > 28 4 28 > It0lii 5 1 2» J 5 〇 > 1,0, .1 ^ \ 2 ^ > ^ l8 > Itoul > 24 4 24 > ΙΙίΛΛι 5 I 2 3___j Once the total lightning current Itatal and the number of auxiliary switching circuits required for the operation are determined on the up and down motion 110 After that, the required current IdMired of each auxiliary switching circuit can be calculated. Specifically, the required current 1desired can be simply calculated by dividing the total current itotal by the operating auxiliary switching circuit. Once the auxiliary operation of the cabinet is calculated After the desired current of the switching circuit is Idesired, the switching circuit of one auxiliary switching circuit can be controlled (step 112), so that the average current of the auxiliary switching circuit passing through the operation can be controlled. It is substantially equal to the required current Idesired, and the total current through the switching regulator 102 is substantially equal to Itotal. By this, the current flowing out of the switching regulator 10 matches the current flowing into the load 14, thereby maintaining the output voltage at the required voltage V,., The rest, that is, the hurricane switching circuit that does not operate, is cut off v desired, that is, both the PH0S transistor 3G and the UM0S transistor are turned on. There are various switching circuits with switching circuits that are used to control the operation. The control algorithm is such that the total current through the switching regulator is substantially equal to the total current of the box itotaJ β. In general, the control algorithm is selected to balance the following factors: 1) Make all the attached switching circuits -31- This paper size is in accordance with the Chinese National Standard (CNS) A4 (210 X 297 mm) Please read the note on the back again., Fill in 11 pages and bind ik 5 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 4 β Α7 Β7 V. Description of the invention (such as _) and switch to on or off at the same time, 2) Ensure that all auxiliary switching circuits operate at the required phase shift 俾 Reduce ripple to Small, 3) to maintain the average current is equal to the holding current at a voltage substantial constancy of a desired level, and 4) at the switching to the switching frequency. Referring to FIG. 10, for example, one of the auxiliary switching circuits that operates according to a predetermined selection pattern is selected as the reference auxiliary switching circuit (step 120). For example, a specific auxiliary switching circuit can be designated as the reference switching circuit or the auxiliary switching circuit can be designated as the reference auxiliary switching circuit in turn. As described below, the remaining auxiliary switching circuit, that is, the non-reference auxiliary switching circuit The behavior is not the behavior of the reference switching circuit. Refer to the attached switch. The switch can be selected when the regulator is connected to the power supply, or whenever the number of auxiliary switching circuits is changed. Once the reference auxiliary switching circuit is selected, the required phase offset of each non-reference auxiliary switching circuit is calculated (step 122). The required phase shift can be determined whenever the auxiliary switching circuit of the operation is changed. The non-reference auxiliary switching circuit is controlled to operate with the required phase shift. Calculate the two current limiting values of the reference attached switching circuit on each clock cycle, and also the current upper limit Iupp „and the current lower limit ^. Stomach (step 1 2 4). Finally, control the reference according to the reference attached switching circuit control algorithm The attached switching circuit (step 126) and the non-reference auxiliary switching circuit according to the non-reference auxiliary switching circuit control the non-reference auxiliary switching circuit (step 128). «» For some shifting sequences and steps, refer to the auxiliary switching circuit. And lower current limit values Iuppw and I1 (WOT for comparison and control, and non-reference auxiliary switching power & vulgar roots required phase offset control. When ------------- install --- {Please read the precautions on the back # Fill this page first) --Line: -32 This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 2 0 °, and the time delay is much ( 1), 0 (2) should be equal to 1/3 and 2 / 3. The auxiliary circuit is used to offset the current ripple of the switching circuit of the lotus to the switching circuit at least in part under the phase difference. Output current. Table 3 summarizes the delta offset required. G ί 5 A7 _B7_ V. Description of the Invention (Treatment) Of course, the sequence of steps shown in Figure 10 is just an example, and these steps can be performed in parallel. For example, for any specific clock cycle, the current limit value can be calculated before the phase offset is calculated. And if 葆 is calculated and stored in the current limit value and phase shift of the previous clock cycle, the calculation step can be performed after the control step. At step 122, for each non-reference auxiliary switching circuit, the control algorithm is Calculate the required phase delay between the time required for the PHOS and NMOS to start conducting between the representative and non-reference supplementary switching circuits, as shown in (i). For example, if the two supplementary switching circuits operate, their phases are different. 180 °, and the time delay should be equal to half of the switching period T, that is, iMi) = 1/2 T. If the three auxiliary switching circuits operate, their phases should differ by 1 switching period, each for a more constant phase Chapter 3 ----------- Installation --- (Please read the precautions on the back before filling out this page) Order printed by the Intellectual Property Bureau's Consumer Cooperatives
Desired phase offset Number of active slaves 1 2 3 4 5 Φ(0) [reference] 0 0 0 0 0 Φ(1) '/ϊΤ 1/3 T WT 1/5 Τ Φ(2) 2/3 Τ 'ΛΤ 2/5 Τ Φ(3) ]/. τ 3/5 Τ Φ(4) 4/5 Τ 步 於 聚124上計算參考附屬切換電路之上及下電流限 -3 3 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) Α7 Β7 五、發明說明(A) 制值IuppCr 及 俥使通過參考附靥切換電路16之 平均電流等於所需之電流 Idesin:d 。具體言之,上及下 電流限制值俗計算如下: Iupti<r 83 ^d«fred + _ I*,ired %△【0 上式中之俗參考附靥切換電路之頻寬。頻寬傺根鎮 據所需之切換頻率設定如下: Δ/〇 1 L + L· ) Xmitthn νΖ) 經濟部智慧財產局員工消費合作社印製 上式中之fswiteh.傺所需之切換頻率。所需之切換頻率 傺選擇以提供良好之動態饗應旦同時維持足夠之功率效 率。大體上,増高切換頻率會減少電流漣波但會降低切 換調整器之效率。相反地,減低切換頻率會改善切換 諝整器之功率效率但卻增加電流漣波《切換頻率應在約 0.5至5.0MH,亦即約1MHz之範圖内,提供需要之切換頻 率之頻寬可根據方程式14内之其它測定值或其它變數之 標稱值而計算出。 下面將參照第11〜12圖說明主控制器18控制參考附屬 切換電路之基本動作之一個程序和歩驟〇如前面提及, 主控制器18係於步驟102上計算預估電流 Iestimate (如 實線70)所示。主控制器在步驟122上另計算上電流限制 值 Iupper (如實線72所示)及下電流限制丨直1 lower (如實 線7 4所示)^數位控制蓮算法則6 4比較參者附靥切換電 路之預估電流 丄 e&timate 與上和下電流限制值 iupper和 -34 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -3)i)11..裝--------訂---------線/^ (請^讀背面之注意再填寫本頁) 、 .晒』 ί 經濟部智慧財產局貝工消費合作社印製 Ln ί 5 Α7 _____Β7____ 五、發明說明(衫) I1()Wu 以決定是否切換第1及第2電晶體3D及32。具體 言之,當預估電流lestimate 超過上電流限制值〖upper 時N Μ 0 S電晶體3 2則關閉而P Μ 0 S電晶體3 0則開啓,籍此使 中間端子2 6接地。相反地,當預估電流 Iestimate .下降 到低於下電流限制值15。胃時NMOS電晶體32則打開而· PMOS電晶體32則關閉,藉此將中間端子26接至輸入電源 12。是故,假設預估電流legate 正確地代表通過參考 附靥切換電路之電流I8lave 時參考附屬切換電路 ^lave (虛線7 6所示)則在上及下限制值 Iupper及 •間振邊 及參考附屬切換電路電流之約等於霈要電流 Lahd (it 線78所示)<* 於第1A_之切換調整器10'上,當預估電流 超過電流上限值Iupp„ 時主控制器1 8 1則輸出在狀態控制 線44f上之脈衝49be脈衝傺藉晶K上之解譯器48解譯成 開啓PMOS電晶體3〇ί第13A圖所示控制線44a下降)及闊閉 NMOS電晶體32之命令。相反地,當預估電流 Ie3timate 下 降到低於電流下限值ItowCT .時主控制器1 8則在狀態控制 線44e上輸出脈衝49a以使NM0S電晶體32開啓及PM0S電晶 體3Q關閉(第13A圔所示控制線44a上昇)。 電流上及下限值Iupper及 ^。胃僳用來控制切換電路 24以確保流出參者附屬切換電路之平均電流匹配所需之 電流。例如,如果負載增加時Idesired 及電流上下限值Desired phase offset Number of active slaves 1 2 3 4 5 Φ (0) [reference] 0 0 0 0 0 Φ (1) '/ ϊΤ 1/3 T WT 1/5 Τ Φ (2) 2/3 Τ' ΛΤ 2/5 Τ Φ (3)] /. Τ 3/5 Τ Φ (4) 4/5 Τ Calculate the upper and lower current limit of the reference auxiliary switching circuit on Poly 124-3 3-This paper size is applicable to China Standard (CNS) A4 specification (210 X 297 mm) A7 B7 5. Description of the invention (A) The value of IuppCr and the average current through the reference switching circuit 16 is equal to the required current Idesin: d. Specifically, the upper and lower current limit values are calculated as follows: Iupti < r 83 ^ d «fred + _ I *, ired% △ [0 The custom in the above formula refers to the bandwidth of the switching circuit. Bandwidth 傺 Genzhen The required switching frequency is set as follows: Δ / 〇 1 L + L ·) Xmitthn νZ) Printed by the employee co-operative cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. The required switching frequency is selected to provide good dynamic response while maintaining sufficient power efficiency. In general, a high switching frequency reduces current ripple but reduces the efficiency of the switching regulator. Conversely, reducing the switching frequency will improve the power efficiency of the switching converter but increase the current ripple. "The switching frequency should be within the range of about 0.5 to 5.0MH, that is, about 1MHz. The bandwidth to provide the required switching frequency can be Calculated based on the nominal values of other measured values or other variables in Equation 14. A procedure and steps for the basic operation of the main controller 18 to control the reference auxiliary switching circuit will be described below with reference to FIGS. 11 to 12. As mentioned earlier, the main controller 18 calculates the estimated current Iestimate at step 102 (as a solid line) 70). The main controller calculates the upper current limit value Iupper (as shown by the solid line 72) and the lower current limit at step 122. Straight 1 lower (as shown by the solid line 7 4) ^ The digital control algorithm is 6 4 Estimated current of switching circuit 丄 e & timate and upper and lower current limit values iupper and -34 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -3) i) 11..install- ------- Order --------- line / ^ (please read the note on the back and fill in this page again), .Sun "ί Printed by Shelley Consumer Cooperative of Intellectual Property Bureau of Ministry of Economic Affairs Ln ί 5 Α7 _____ Β7 ____ 5. Description of the Invention (Shirt) I1 () Wu to decide whether to switch the first and second transistors 3D and 32. Specifically, when the estimated current lestimate exceeds the upper current limit value [upper], the N M 0 S transistor 32 is turned off and the P M 0 S transistor 30 is turned on, thereby grounding the intermediate terminal 26. Conversely, when the estimated current Iestimate. Drops below the lower current limit value of 15. In the stomach, the NMOS transistor 32 is turned on and the PMOS transistor 32 is turned off, thereby connecting the intermediate terminal 26 to the input power source 12. Therefore, assuming that the estimated current legate correctly represents the current I8lave through the reference switching circuit, reference to the auxiliary switching circuit ^ lave (shown by dashed line 7 6) is the upper and lower limit values Iupper and • between the edge and the reference auxiliary The switching circuit current is approximately equal to the required current Lahd (shown by line 78) < * On the switching regulator 10 'of the 1A_, when the estimated current exceeds the upper current limit Iupp „, the main controller 1 8 1 Then the pulse 49be pulse output on the state control line 44f is interpreted by the interpreter 48 on the crystal K to turn on the PMOS transistor 3 (the control line 44a shown in FIG. 13A drops) and the wide-closed NMOS transistor 32 On the contrary, when the estimated current Ie3timate drops below the current lower limit ItowCT. When the main controller 18 outputs a pulse 49a on the state control line 44e to make the NMOS transistor 32 on and the PM0S transistor 3Q off ( Control line 44a rises as shown in Fig. 13A). Upper and lower current limit values Iupper and ^. Stomach is used to control the switching circuit 24 to ensure that the average current flowing out of the participant's auxiliary switching circuit matches the required current. Idesired and electricity increase Upper and lower limits
Iupp«及 .則增加。相反地,如果負載減少時, W.d及電流上下限值IuppM及則減少。另外 -3 5 _ 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公笼〉 --------1 — 裝--- (請先閱讀背面之注音筆項再填寫本頁) .靡j ij· 451115 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(外) ,當負載實質恆常時上下限值Iupper及IlOTW 間之頻寬 △1。則設定切換電路2 4之切換頻率。 能用各種控制蓮算法則控制非常參考附屬切換電路之 切換電路俾達成需要電流及相位偏移。參照第14及15圔 ,於控制蓮算法則64之一値程序和步驟二,非常參考附 屬切換電路俗根據參考附屬切換電路内一個電晶體之一 値限制流值及切換時間而被控制β簡言之,非參考附屬 切換電路僳由兩事件觸發:當附屬切換電路之預估電流 通過限制值之一,及當參考附靥切換電路由於其它限制 值而切換時啓動之計時器之計時*間到時。 具體言之,當非常參考附靥切換電路之預估電流Iestimate 超過電流上限值(藉方程式12對參考附靥切換電路算出者) 時非參考附屬切換電路開始其NMOS之導通狀態,亦即NM0S 電晶體3Q開啓而NMOS電晶體32閼閉β數位控制蓮算法則 另包含一或多個相位偏移計時器。相位偏移計時器係用 來觸發非參考附屬切換電路之PHGS導通狀態》具體言之 ,當非參考附靥切換電路開始其PMOS導通狀態時計時器 即啓動。每個時脈週期,比較計時器與毎個非參考附屬 切換電路之需要相位偏移(U。當與特定之非參考附· 屬切換電路關聯之相位偏移時間0 (i)到時非常參考附 屬切換霉路則開始其之PMOS導通狀態,亦卽OOS電晶體 3 2開啓及P Μ 0 S電晶體3 0關閉。如此,相位偏移0 1 )決 定在NMOS導通狀態啓動後參考與非參者附屬切換電路間 之遲延。當然,能倒反觸發糸統而變成當非參考附屬切 -36- (請先閲讀背面之注意事項再填窝本頁) 裝.!!訂·---- 4: MJ- 本紙張尺度適用争國國家標準(CNS)A4規格(210 X 297公釐) 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明(V) 換電路下降到低於電流下限值時即觭發PMGS導通狀態, 及當非參考附靥切換電路開始其之NMOS導通狀態時即啓 動計時器。 參照第1 6及1 7圖,於數位控制蓮算法則6 4之第2程序 和步驟上,計算每値非參考附靥切換電路之電流上下限 ^ Iupp,r(i) & Ilower(i) 。Έ±下限值選定為使通5®# 參考附屬切換踅路16之平均電流等於所需之電流Idesired 。因毎個附靥切換電路各有其限流值,故毎痼附屬切換 電路之頻寬控制該附屬切換電路之切換頻率。具體 言之,切換週期T可從下式算出:Iupp «and. Have increased. Conversely, when the load decreases, W.d and the current upper and lower limit values IuppM and decrease. In addition -3 5 _ This paper size is in accordance with China National Standard (CNS) A4 specification (210 X 297 male cage) -------- 1 — Loading --- (Please read the phonetic entry on the back before filling in this Page) .j ij · 451115 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (outside), when the load is substantially constant, the bandwidth between the upper and lower limits Iupper and IlOTW △ 1. Set the switching circuit The switching frequency of 2 4 can be controlled by various control algorithms. The switching circuit that is very referenced to the auxiliary switching circuit is used to achieve the required current and phase offset. Refer to sections 14 and 15 (1), which is one of the 64 control algorithms. Procedures and steps Second, very refer to the auxiliary switching circuit. It is controlled according to one of the transistors in the reference auxiliary switching circuit. Limit the current value and switching time. Β In short, the non-reference auxiliary switching circuit is triggered by two events: The estimated current passes one of the limit values, and the timer * of the timer started when the reference switching circuit is switched due to other limit values is up. Specifically, when the reference to the switching circuit of the supplement is estimated When the current Iestimate exceeds the upper limit of the current (calculated by Equation 12 for the reference attached switching circuit), the non-reference auxiliary switching circuit starts its NMOS conduction state, that is, the NMOS transistor 3Q is turned on and the NMOS transistor 32 is turned off. Β digital control The lotus algorithm also includes one or more phase offset timers. The phase offset timer is used to trigger the PHGS on state of the non-reference auxiliary switching circuit. Specifically, when the non-reference auxiliary switching circuit starts its PMOS on state The timer is started. For each clock cycle, the phase offset time of the timer and a non-reference auxiliary switching circuit is compared (U. When the phase offset time associated with a specific non-reference auxiliary switching circuit is 0 ( i) At that time, with reference to the auxiliary switching mold circuit, the PMOS conduction state will be started, that is, the OOS transistor 3 2 is turned on and the P MOS transistor 30 is turned off. Therefore, the phase shift 0 1) is determined to be in the NMOS conduction state Delay between the reference and non-participant auxiliary switching circuit after startup. Of course, it can reverse trigger the system and become a non-reference auxiliary cut -36- (Please read the precautions on the back before filling in this page) ....... Order 4: MJ- This paper size applies to the national standard (CNS) A4 specification (210 X 297 mm) Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention ( V) When the switching circuit drops below the lower limit of the current, the PMGS conducting state is generated, and when the non-reference auxiliary switching circuit starts its NMOS conducting state, the timer is started. Refer to Figures 16 and 17 and In the second procedure and step of the digital control algorithm, the upper and lower limits of the current of each non-reference attached switching circuit are calculated ^ Iupp, r (i) & Ilower (i). The Έ ± lower limit value is selected so that the average current of the 5 ## reference auxiliary switching circuit 16 is equal to the required current Idesired. Since each auxiliary switching circuit has its current limit value, the bandwidth of the auxiliary switching circuit controls the switching frequency of the auxiliary switching circuit. Specifically, the switching period T can be calculated from the following formula:
為調整參考與非參考附屬切換電路間之相位差,非常 參考附靥切換電路之頻寬All被調整以改變其切換錤 率。藉此減鍰或增快非參考附屣切換電路相對於參考附 屬切換電路,進而變更PMOS與NMOS導通狀態間之時差。 一旦達到需要之相位差後再度調整非參考附屬切換電路 之頻寬俾使兩個附屬切換電路切換頻率匹配。欲調整非 參考附屬切換電路之頻寬,數位控制蓮算法則6 4測定兩 附屬切換電路起動NM0S與PM0S導通狀態間之實際時間遲 延ΤΝ及ΤΡ。接著,設定頬寛Λΐι等於需要頻寬加上一 項回授項,此回授項偽與所需和實際時間延遲間之誤差 或差成比例。例如,頻寬ΛΙ1可由下式算出: ΔΙ, - ΔΙ0 +Κ,[Φ(ί)-ΤΝ] +Κ3[Φ(ί)·ΤΡ] (16) -3 7 - 本紙張尺度適用中國國家標準<CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁)In order to adjust the phase difference between the reference and non-reference auxiliary switching circuits, the bandwidth All of the very reference auxiliary switching circuits is adjusted to change its switching rate. This reduces or speeds up the non-reference auxiliary switching circuit relative to the reference auxiliary switching circuit, thereby changing the time difference between the on-state of the PMOS and the NMOS. Once the required phase difference is reached, adjust the bandwidth of the non-reference auxiliary switching circuit again to match the switching frequencies of the two auxiliary switching circuits. To adjust the bandwidth of the non-reference auxiliary switching circuit, the digital control algorithm 64 measures the actual time delays TN and TP between the two auxiliary switching circuits starting the ON state of NMOS and PM0S. Next, setting 頬 寛 Λΐι equals the required bandwidth plus a feedback term. This feedback term is pseudo proportional to the error or difference between the required and actual time delay. For example, the bandwidth ΛΙ1 can be calculated by the following formula: ΔΙ,-ΔΙ0 + Κ, [Φ (ί) -ΤΝ] + Κ3 [Φ (ί) · ΤΡ] (16) -3 7-This paper standard is applicable to Chinese national standard ; CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling this page)
. ϊί i 4尽"1 5 Α7 _____ Β7 五、發明說明(站) 上式中之Κι及K2^回授誤差常數,而Alo像方程式 13算出之所霈頻寬。接箸,藉下式算出電流之上下限值 Iupper(i) 及 : β wo+wo -1*^(〇- 電流上下限值 Iupper (i)及.11(}胃(i >傺用來觸發非 參#附靥切換電路之第1及第2電晶體3fl及32。具體言 之,當預估電流 Iestimate ( i )超過電流上限值 〗upper ( i ) 時Ρ Μ 0 S電晶體3 0則開啓而Ν Μ 0 S 3 2則關閉。相反地,當 預估電流 (i)下降到低於電流下限值 ^。胃(i ) 時,NMOS電晶體32則開啓及PMOS電晶體30關閉β是故, 假設預估電流 Ie3tiraate U)正確地代表通過附靥切換 電路之電流 Islave (i)時,附靥切換電路電流 I# ( i ) 則在電流上下限值 Iupper ( i )與 IWr ( i )間振盪β因 此,通過附屬切換電路之平均電流約等於 Idesired ( i ) ,而逋過切換調整器之總電流則約等於所需之總電流 Itotal 。電流之上下限值傜設定使附靥切換電路之平均 輸出電流匹配於負載β 參照第18〜23圃,於第3圖程序與步驟上,數位控制 運算法則6 4計算每値非參者附屬切換電路1 6之"虛影電 流。此虛影電流(U代表在已知之限流值及所需之相位 儸移下流、過該附靥切換電路之需要電流β每锢非參考附颳 切換電路藉比較每個非參考附靥切換電路之預估電流 Ie$tiraate ighost(i) 浪κ 虛影電流可以與計算預估電流者相同之方式計算:在 _ 3 8 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (諳讀背面之注意事項再填寫本頁) 7Ϊ· 裝--------訂--------- 經濟部%慧財產局員工消費合作社印製 五 5 A7 __B7、發明說明(外) 虚影PMOS導通狀態期間,虛影電流在毎個時脈週期係藉 $昇值 Δΐϋρ_8_ 遞昇(第22圖之實線84所示),而在 導通狀態期間,虛影電流I ( i )在每時 01週期傺藉遞降值 △d^gh# 遞減。但是,如果虛 影電流I( i )超過電流上限值Iupper 時虛影電流則 設定等於電流上限值 ▲upper 相似地,如果虛影電流 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 1产( i)下降到低於電流下限值 11(1胃.時,虛影電流 貝ϋ設定等於電流下限值ileww 。 虛影導通狀態傺藉參考附屬切換電路之切換及需要之相 熇移(參閲)第20及21圖)而觸發。具髏言之,虛影在 在參考附靥切換電路切換至PMOS導通狀態後即在所需之 相位镐移(i)下切換電路至虛影PM0S導通狀態。相似 地,虛影在參者附屬切換電路切換至NMOS導通狀態後即 在所餺之相位槭移(i)下切換至虛影NM0S導通狀態。 如上述,非參考附屣切換電路之切換偽藉比較非參考 附屬切換電路之預估電流 Iestimate ( i )(第2 3圖之實線 86所示與非參考附屬切換電路之虛影電流(如第 23_之虛線8 4所示)而控制。具體言之,如果非參考附 藤切換電路傺於PHOS導通狀態時虛影偽在NM0S導通狀態 ,而如果預估電流 Iestiniate ( i )超過虛影電流I d > 時,附羅切換電路則切換至Ν Η 0 S導逋狀態。相似地,如 果非參考附屬切換電路傜於N Μ 0 S導通狀態時虛影則是於 NM0S導通狀態,而如果預估電流 Iestimate (i)下降到 低於虛影電流 ( i)時,附屬切換電路則切換到 -39- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ·! — ------- (請先閱讀背面之注意事項#/填寫本頁) 言 ί 5 Τδι Α7 _Β7_ 五、發明說明(说) PMOS導通狀態。換言之,如果附靥切換電路切換預估電 流越過虛影電流時,則兩電流具有相反之斜率。如此, 附靥切換電路條有效率地銀隨虛影電流切換。另外,如 果虛影傜在PMOS導通狀態且預估電流 Iestimate ( i )超過 虛影電流 —電流偏移值I 時非參考附屬 切換電路則切換至N0S導通狀態,而如果虛影係在SH0S 導通狀態且預估電流( i )超過虛影電流 IundCT (i ) 一電流偏移值I 時非參考附屬切換電路則切換至 NM0S導通狀態,而如果虛影偽在NM0S導通狀態且預估電 流 lestoate U)下降到低於虛影電流-電流偏移值IundCT 時非參考附靥切換電路則切換至PM0S導通狀態。藉此確 保卽使虛影電流快速改變附靥切換電路之電流能跟隨虛影 電流改變。 參照第24〜27圖,於第4程序和步驟上,數位控制蓮 算法則64計算參考附屬切換電路及非參考附屬切換電路 之”虛影"電流,及參考附屬切換電路及非參考附屬切換 電路兩者傺藉比較預估電流 Iestimate ( i )與虛影電流 WW 而控制。 參照第2 5圖,數位控制蓮算法則6 4産生具有切換頻率 約等於需要之切換頻率,例如1MHz,及貴務週期D約等 於需要之、責務週期:例如 m 之時脈信號9 責 務週期可根據νώ與Vut之標稱值而固定時脈信號9 0 條用來控制每値虛影之虛影導通狀態。具體言之,時脈 信號可對每個動作之附屬切換電路産生,每痼時脈信號 -4 0 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝 ------訂---111— — — ^vly— 經 濟 部 .智 慧 財 產 局 員 工 消 費 合 作 社 印 製 45 ] 5 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明(畔) 傜藉所需之相位偏移Pbi(i)偏移。如果附屬切換電路關 聯之時脈信號90髙時虛影則傺在虛影PHOS導通狀態,而 當附騸切換電路關聯之時脈信號90低時虛影則在虛影NHOS 導通狀態例如,如果有三個附屬切換電路動作時則在 參考附靥切換電路切換至PH0S導通狀態後在所需之相位 偏移PhUi)下,第三個虛影葆在第二値虛影後之切換週 .期之1/3後及在第一舾虛影後之切換週期之2/3後切換。 第25及26圖清楚地示出以與參照第3程序和步驟及第 18圔討論之虛影電流之計算者相同之方式計算虛影電流 :在虛影PH0S導通狀態期間,每値時脈週期虛影電流 U3t (U (第26圃之實線92所示)僳以遞昇值 遞舁,而在虛影HMDS導通狀態期間,每個時脈週期,虛 影電流Igh〇st 係以遞降值 遞水牛。但是, 如果虛影電流 ( i )超過電流上限值 Iupper時虛影 電流則被設定等於電流上限值IuppCT 。相似地,如果虛 影電流 Igh〇st ( i )下降到低於電流下限值 ^。胃時虛影 電流則被設定等於電流下限值 It()WCT 。 參照第24及27圖,如上述,非參考附靥切換電路之切 換係藉比較非參考附靥切換電路之預估電流 Iestimate U ) (實線94所示)與非參考附屬切換電路之虛影電流 (i)(虛線92所示)而被控制,具體言之,如果非參考附® 切換電路傺在PM0S導通狀態時虛影係在NM0S導通狀態, 如果預估電流 Iestimate ( i )超過虛影電流 IghD3t ( i)時 ,附屬切換電路則切換至N Μ 0 S導通狀態。相似地,如果 ' -41- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) -----------?-裝--------訂--------- (請先閱讀背面之注意事項再填寫本k)ϊί i 4 Do " 1 5 Α7 _____ Β7 V. Description of the invention (station) The feedback error constants of Kι and K2 ^ in the above formula, and Alo is calculated as the bandwidth of Equation 13. Then, calculate the upper and lower current limit values Iupper (i) and: β wo + wo -1 * ^ (〇- Upper and lower current limit values Iupper (i) and .11 (} stomach (i > 傺) Trigger non-parameters # 1 and 2 transistor 3fl and 32 of the switching circuit. Specifically, when the estimated current Iestimate (i) exceeds the upper current limit value upper (i), P M 0 S transistor 3 0 is on and NM 0 S 3 2 is off. Conversely, when the estimated current (i) drops below the lower current limit ^. When the stomach (i), the NMOS transistor 32 is turned on and the PMOS transistor 30 is turned on When β is closed, it is assumed that when the estimated current Ie3tiraate U) correctly represents the current Islave (i) passing through the auxiliary switching circuit, the auxiliary switching circuit current I # (i) is between the upper and lower current limit values Iupper (i) and IWr (i) inter-oscillation β. Therefore, the average current through the auxiliary switching circuit is approximately equal to Idesired (i), and the total current through the switching regulator is approximately equal to the required total current Itotal.平均 The average output current of the switching circuit is matched to the load β. Algorithm 6 4 calculates the “phantom current” of each non-participant auxiliary switching circuit 1 6. This phantom current (U stands for a known current-limit value and the required phase shift down, passes through the additional switching circuit The required current β per non-referenced attached switching circuit is compared by comparing the estimated current Ie $ tiraate ighost (i) of each non-referenced attached switching circuit. The wave κ ghost current can be calculated in the same way as the estimated current: In _ 3 8-This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (read the notes on the back and fill in this page) 7 ------- Printed by the Consumers Cooperative of% Hui Property Bureau of the Ministry of Economic Affairs 5 A7 __B7. Explanation of the invention (outside) During the PMOS on-state, the ghost current is borrowed by $ for each clock cycle Δΐϋρ_8_ step up (Shown by the solid line 84 in FIG. 22), and during the on-state, the ghost current I (i) is decremented by the descent value △ d ^ gh # every 01 cycles. However, if the ghost current I (i ) When the current upper limit Iupper is exceeded, the ghost current is set equal to the current upper limit ▲ upper Similarly, such as When ghost current economic portion wise property Office employee consumer cooperatives PRINTED 1 production (i) falls to limit 11 (1 stomach lower than current, phantom current shell ϋ set temperature equal to current limit ileww. The ghost conduction state is triggered by referring to the switching of the auxiliary switching circuit and the required phase shift (see Figures 20 and 21). In other words, after the ghost image is switched to the PMOS conduction state by referring to the attached switching circuit, the circuit is switched to the ghost image PM0S conduction state with the required phase shift (i). Similarly, the ghost image is switched to the ghost image NMOS on-state at the phase shift (i) after the auxiliary switching circuit of the participant is switched to the NMOS conduction state. As mentioned above, the switching pseudo of the non-reference auxiliary switching circuit is compared with the estimated current Iestimate (i) of the non-reference auxiliary switching circuit (shown in solid line 86 in Fig. 23 and the ghost current of the non-reference auxiliary switching circuit (such as 23_ (shown by dashed line 8 4)). Specifically, if the non-referenced Fujitsu switching circuit is in the PHOS on state, the ghost is in the NM0S on state, and if the estimated current Iestiniate (i) exceeds the ghost, When the current I d >, the Fu Luo switching circuit is switched to the N Η 0 S conduction state. Similarly, if the non-reference auxiliary switching circuit is in the N M 0 S conduction state, the ghost is in the NM 0S conduction state, and If the estimated current Iestimate (i) drops below the ghost current (i), the auxiliary switching circuit will switch to -39- This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ·! — ------- (Please read the note on the back # / Fill this page first) 言 ί 5 Τδι Α7 _Β7_ V. Description of the invention (say) PMOS conduction state. In other words, if the attached switching circuit switches the estimated current When the ghost current is crossed, the two currents have On the contrary, the slope. In this way, the switching circuit strip with silver switches efficiently with the ghost current. In addition, if the ghost shadow is in the PMOS conduction state and the estimated current Iestimate (i) exceeds the ghost current-current offset value I, it is not a reference. The auxiliary switching circuit is switched to the N0S conducting state, and if the ghost system is in the SH0S conducting state and the estimated current (i) exceeds the ghost current IundCT (i) a current offset value I, the non-reference auxiliary switching circuit is switched to NM0S ON state, and if the ghost is in the NMOS state and the estimated current lestoate U) drops below the ghost current-current offset value IundCT, the non-reference attached switching circuit switches to the PM0S state. This ensures that the ghost current can be quickly changed and the current of the switching circuit can follow the ghost current. With reference to Figures 24 to 27, in the fourth procedure and step, the digital control algorithm 64 calculates the "phantom" current of the reference auxiliary switching circuit and the non-reference auxiliary switching circuit, and the reference auxiliary switching circuit and the non-reference auxiliary switching The two circuits are controlled by comparing the estimated current Iestimate (i) with the ghost current WW. Referring to Figure 25, the digital control algorithm 64 generates a switching frequency with a switching frequency approximately equal to the required switching frequency, such as 1MHz, and expensive The duty cycle D is approximately equal to the required duty cycle: for example, the clock signal 9 of m can be fixed according to the nominal value of νώ and Vut. 90 clock signals are used to control the ghost conduction state of each ghost. Specifically, the clock signal can be generated for the auxiliary switching circuit of each action. Each clock signal is -4 0-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please read first Note on the back, please fill in this page again.) ------ Order --- 111— — — ^ vly— Printed by the Ministry of Economic Affairs. Intellectual Property Bureau employee consumer cooperatives 45] 5 Intellectual Property Bureau employee consumption Printed by the company Α7 Β7 V. Description of the invention (Pan) 傜 borrow the required phase offset Pbi (i) offset. If the clock signal associated with the auxiliary switching circuit is 90 髙, the ghost is in the on state of the ghost PHOS, When the clock signal 90 associated with the auxiliary switching circuit is low, the ghost image is in the ghost NHOS on state. For example, if three auxiliary switching circuits are operating, the reference signal is switched to the PH0S conducting state after the reference auxiliary circuit is switched on. With phase shift (PhUi), the third ghost image is switched after the second ghost period. It is switched after 1/3 of the period and after the first ghost period is switched by 2/3. Figures 26 and 26 clearly show that the ghost current is calculated in the same way as the calculator of the ghost current discussed with reference to 3rd procedure and step and 18th: During the ghost PHOS on-state, the ghost image per clock cycle The current U3t (U (shown by the solid line 92 on the 26th floor)) is progressively increased, and during the on-state of the ghost HMDS, the ghost current Igh〇st is delivered to the buffalo with a decreasing value during each clock cycle. However, if the ghost current (i) exceeds the upper current limit Iupper, the ghost current is It must be equal to the current upper limit value IuppCT. Similarly, if the ghost current Igh0st (i) drops below the current lower limit value ^. The stomach ghost current is set equal to the current lower limit value It () WCT. Figures 24 and 27. As mentioned above, the switching of the non-reference auxiliary switching circuit is by comparing the estimated current Iestimate U of the non-reference auxiliary switching circuit (shown by the solid line 94) with the ghost current of the non-reference auxiliary switching circuit. (i) (shown as dashed line 92) and is controlled, specifically, if the non-reference attached ® switching circuit 虚 is in the NM0S on state when the PM0S is on, if the estimated current Iestimate (i) exceeds the virtual current At IghD3t (i), the auxiliary switching circuit is switched to the N M 0 S conducting state. Similarly, if '-41- this paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -----------?-Packing -------- order --------- (Please read the notes on the back before filling this k)
Is A7 __B7 發明說明( 非參考附屣切換電路係在NMOS導通狀態,虛影僳在PM〇s 導通狀態及預估電流 Iestimate (i)下降到低於虛影電流 Ighostfi) 時,附屬切換電路則切换為PM0S導通狀態。 换言之,如果附屬切換電路切換預估電流越過虛影電流 時則此兩電流具有相反之斜率。如此,附屬切換電路俾 有效率地追隨虛影電流。 另外,如果預估電流 Iestimate (1)超過電流上限值 Iupper 時非參考附靥切換電路則切換為MO S導通狀態 ,或如果預估電流 Iestimate ( i )下降到低於電流下限值 Ibww 時非參考附屬切換電路則切換為PM0S電流狀態β 為避免過度切換導致效率之降低,虛影之遞舁及遞降值· △lup.ghoet及△Idmvn.ghesst 可藉人為没定預估電流低 於遞昇及遞降值ΛΙυρ及 /\Id(Wn ,例如約2 0〜2 5 %。 替換地,虛影電流能容許超過或低於電流上下限值 Lpper 及 1^^ 些許事先設定之容許度。 符號之說明 10......切換調整器 12......電源 14......負載 16......附展切換電路 1 8 ......主控制器 20......輸入端子 22......輸出端子 24......切換電路 -42- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) --------訂-! — - 經 濟 部 .智 慧 財 產 局 員 工 消 費 合 作 社 印 製 經濟部智慧財產局員工消費合作社印製 45? ί 丨 g ° A7 _B7 五、發明說明(^/) 2 6......中間端子 28......輸出濾波器 30......第1電晶體 32......第1電晶體 34......電感器 36......電容器 4 0,4 2 ...電流偵測器 52......參考電晶體 54......電流源 56......比較器’ 60......採樣和保持電路 62......類比/數位轉換器 64......數位控制運算法則 68......數位/類比轉換器 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁)Is A7 __B7 Description of the Invention (The non-reference attached switching circuit is in the NMOS conduction state, and the ghost switch is in the PM0s conduction state and the estimated current Iestimate (i) drops below the ghost current Ighostfi). Switch to PM0S on state. In other words, if the auxiliary switching circuit switches the estimated current over the ghost current, the two currents have opposite slopes. In this way, the auxiliary switching circuit 随 efficiently follows the ghost current. In addition, if the estimated current Iestimate (1) exceeds the current upper limit value Iupper, the non-reference auxiliary switching circuit is switched to the MO S conducting state, or if the estimated current Iestimate (i) drops below the lower current limit value Ibww The non-reference auxiliary switching circuit is switched to the PM0S current state β. To avoid the reduction of efficiency caused by excessive switching, the ghosting and decrementing values of △ lup.ghoet and △ Idmvn.ghesst can be artificially estimated that the current is lower than the increasing And decreasing values ΛΙυρ and / \ Id (Wn, for example, about 20 to 25%. Alternatively, the ghost current can be allowed to exceed or fall below the upper and lower limits of the current Lpper and 1 ^^ with some pre-set tolerance. Symbol of Description 10 ... Switching regulator 12 ... Power supply 14 ... Load 16 ... Supplied switching circuit 1 8 ... Main controller 20 ... input terminal 22 ... output terminal 24 ... switching circuit-42- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) (Please (Please read the notes on the back before filling out this page) -------- Order-!--Ministry of Economic Affairs. Printed by the Ministry of Economy Printed by the Intellectual Property Bureau employee consumer cooperative 45? Ί 丨 g ° A7 _B7 V. Description of the invention (^ /) 2 6 ...... Middle terminal 28 ... Output filter 30 ..... 1st transistor 32 ... 1st transistor 34 ... inductor 36 ... capacitor 4 0, 4 2 ... current detector 52 ... .. reference transistor 54 ... current source 56 ... comparator '60 ... sample and hold circuit 62 ... analog / digital converter 64 ... .... Digital control algorithm 68 ... Digital / analog converter This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) (Please read the precautions on the back before filling in this page)
Claims (1)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/183,325 US6100676A (en) | 1998-10-30 | 1998-10-30 | Method and apparatus for digital voltage regulation |
US09/183,326 US6031361A (en) | 1998-10-30 | 1998-10-30 | Voltage regulation using an estimated current |
US09/183,448 US6268716B1 (en) | 1998-10-30 | 1998-10-30 | Digital voltage regulator using current control |
US09/183,337 US6198261B1 (en) | 1998-10-30 | 1998-10-30 | Method and apparatus for control of a power transistor in a digital voltage regulator |
Publications (1)
Publication Number | Publication Date |
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TW451115B true TW451115B (en) | 2001-08-21 |
Family
ID=27497560
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW088119930A TW451115B (en) | 1998-10-30 | 1999-11-16 | Method and apparatus for digital voltage regulation |
Country Status (6)
Country | Link |
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EP (1) | EP1125178A4 (en) |
JP (1) | JP2002530036A (en) |
KR (1) | KR20010085986A (en) |
AU (1) | AU1336700A (en) |
TW (1) | TW451115B (en) |
WO (1) | WO2000026740A1 (en) |
Cited By (1)
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TWI448869B (en) * | 2008-01-18 | 2014-08-11 | Seiko Instr Inc | Voltage regulator |
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US6476566B2 (en) | 2000-12-27 | 2002-11-05 | Infocus Systems, Inc. | Method and apparatus for canceling ripple current in a lamp |
US6909266B2 (en) | 2002-11-14 | 2005-06-21 | Fyre Storm, Inc. | Method of regulating an output voltage of a power converter by calculating a current value to be applied to an inductor during a time interval immediately following a voltage sensing time interval and varying a duty cycle of a switch during the time interval following the voltage sensing time interval |
US6906502B2 (en) | 2002-11-14 | 2005-06-14 | Fyre Storm, Inc. | Method for regulating an output voltage of a power coverter |
US7075278B2 (en) | 2003-03-13 | 2006-07-11 | Tdk Corporation | Switching power supply controller and switching power supply |
US7119606B2 (en) * | 2003-07-10 | 2006-10-10 | Qualcomm, Incorporated | Low-power, low-area power headswitch |
AU2003903787A0 (en) | 2003-07-22 | 2003-08-07 | Sergio Adolfo Maiocchi | A system for operating a dc motor |
AT501998B1 (en) * | 2003-08-20 | 2008-06-15 | Siemens Ag Oesterreich | SWITCHING REGULATOR |
EP1700371B1 (en) * | 2003-12-22 | 2010-09-01 | Koninklijke Philips Electronics N.V. | Switched mode power supply |
US7221130B2 (en) | 2005-01-05 | 2007-05-22 | Fyrestorm, Inc. | Switching power converter employing pulse frequency modulation control |
JP4947986B2 (en) | 2006-02-02 | 2012-06-06 | 株式会社アドバンテスト | Test apparatus and test method |
JP4974653B2 (en) * | 2006-11-21 | 2012-07-11 | ローム株式会社 | Step-up switching regulator control circuit, step-up switching regulator using the same, and electronic equipment using them |
WO2009001615A1 (en) * | 2007-05-29 | 2008-12-31 | Nagasaki University, National University Corporation | Prediction control system |
JP5251594B2 (en) * | 2009-02-26 | 2013-07-31 | 富士通セミコンダクター株式会社 | POWER CONTROL DEVICE, POWER CONTROL METHOD, AND ELECTRONIC DEVICE |
WO2011010349A1 (en) * | 2009-07-23 | 2011-01-27 | 株式会社アドバンテスト | Testing device |
US8558559B2 (en) | 2009-07-23 | 2013-10-15 | Advantest Corporation | Test apparatus, additional circuit and test board for calculating load current of a device under test |
US8558560B2 (en) | 2009-07-23 | 2013-10-15 | Advantest Corporation | Test apparatus, additional circuit and test board for judgment based on peak current |
US8587152B2 (en) * | 2011-03-27 | 2013-11-19 | The Boeing Company | Sequential shunt regulator with analog fill control |
CN110750061B (en) * | 2019-10-18 | 2023-02-03 | 天津津航计算技术研究所 | Method for enhancing transmission reliability of discrete signal |
WO2024202769A1 (en) * | 2023-03-27 | 2024-10-03 | 株式会社村田製作所 | Tracker circuit and voltage-supplying method |
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US3978393A (en) * | 1975-04-21 | 1976-08-31 | Burroughs Corporation | High efficiency switching regulator |
US4034232A (en) * | 1976-06-01 | 1977-07-05 | Burroughs Corporation | System for synchronizing and phase shifting switching regulators |
JPS58218868A (en) * | 1982-06-15 | 1983-12-20 | Nec Corp | Control system of parallel-operation power supply |
US4716267A (en) * | 1984-02-22 | 1987-12-29 | Weldex, Inc. | Three phase high frequency spike welding system |
JPH065965B2 (en) * | 1988-02-17 | 1994-01-19 | 山洋電気株式会社 | DC power supply |
JP2858825B2 (en) * | 1989-11-13 | 1999-02-17 | 日本電気株式会社 | Parallel operation power supply control method |
US5477132A (en) * | 1992-01-10 | 1995-12-19 | Space Systems/Loral, Inc. | Multi-sectioned power converter having current-sharing controller |
US5675480A (en) * | 1996-05-29 | 1997-10-07 | Compaq Computer Corporation | Microprocessor control of parallel power supply systems |
EP0901215A4 (en) * | 1996-06-24 | 2000-01-05 | Tdk Corp | Switching power unit |
-
1999
- 1999-11-01 JP JP2000580058A patent/JP2002530036A/en active Pending
- 1999-11-01 WO PCT/US1999/025720 patent/WO2000026740A1/en not_active Application Discontinuation
- 1999-11-01 AU AU13367/00A patent/AU1336700A/en not_active Abandoned
- 1999-11-01 KR KR1020017005467A patent/KR20010085986A/en not_active Application Discontinuation
- 1999-11-01 EP EP99956843A patent/EP1125178A4/en not_active Withdrawn
- 1999-11-16 TW TW088119930A patent/TW451115B/en not_active IP Right Cessation
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI448869B (en) * | 2008-01-18 | 2014-08-11 | Seiko Instr Inc | Voltage regulator |
Also Published As
Publication number | Publication date |
---|---|
EP1125178A4 (en) | 2003-05-28 |
JP2002530036A (en) | 2002-09-10 |
AU1336700A (en) | 2000-05-22 |
EP1125178A1 (en) | 2001-08-22 |
WO2000026740A8 (en) | 2000-06-15 |
WO2000026740A1 (en) | 2000-05-11 |
KR20010085986A (en) | 2001-09-07 |
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