JP2002530036A - Digital voltage adjustment method and device - Google Patents

Abstract

(57) [Summary] A digital voltage regulator has an input terminal (20) connected to an input voltage source (12), an output terminal (22) connected to a load (14), and an input terminal (20) connected to an output terminal. It has a plurality of switching circuits (24) for alternately connecting or disconnecting to (22). An estimated current is calculated for each switching circuit (24), each estimated current representing a current flowing through an inductor (34) associated with the switching circuit (24). The total desired output current through the inductor (34) that keeps the output voltage at the output terminal (22) substantially constant is calculated. The switching circuit (24) is controlled based on the estimated current and the total desired output current, such that the total current flowing through the inductor (34) is approximately equal to the total desired output current.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

【background】

The present invention relates generally to voltage regulators, and more particularly to a control system for a switching voltage regulator.

[0002] A voltage regulator such as a DC / DC converter is used to provide a stabilized voltage source for an electronic system. Efficient DC / DC converters are especially needed for battery management in low power devices such as laptops and mobile phones. Switching voltage regulators (or more simply "switching regulators")
It is well known that this is an efficient form of DC / DC converter. The switching regulator converts an input DC voltage into a high-frequency voltage, and generates an output voltage by filtering the high-frequency voltage to generate an output DC voltage.
Switching regulators usually have an input D that is not regulated, such as a battery.
A switch for alternately connecting and disconnecting the C voltage source to a load such as an integrated circuit is included. The output filter typically includes an inductor and a capacitor, and is connected between the input voltage source and the load to filter the output of the switch, thereby providing a DC voltage at the output. The controller measures electrical characteristics of the circuit, such as, for example, voltage and current flowing through the load, and sets a switching duty cycle to maintain the output DC voltage at a substantially constant level.

[0003] Voltage regulators for microprocessors must meet more stringent performance requirements than before. One trend is to operate at higher currents, for example, 35-50 amps. Another trend is to turn on and off different parts of the microprocessor every cycle to save energy. This requires that the voltage regulator respond very quickly to load changes, for example, from a minimum load to a maximum load in a few nanoseconds. Yet another trend is to place voltage regulators near the microprocessor to reduce parasitic capacitance, resistance and / or inductance in the distribution lines, and thereby prevent current loss,
be able to. However, in order to place the voltage regulator near the microprocessor, the voltage regulator must have a small and easy-to-use form factor.

[0004] In addition to these special trends, high efficiency is generally desirable to avoid thermal overload at high loads and to extend battery life in portable systems. Another desirable feature is that the voltage regulator has a "standby" mode that reduces power consumption at low loads.

A conventional controller is configured by an analog circuit such as a resistor, a capacitor, and an operational amplifier. Unfortunately, analog circuits are expensive and / or difficult to fabricate as integrated circuits. In particular, special techniques are needed to fabricate resistors and semiconductor devices. In addition, analog signals degrade in performance due to noise, resulting in loss of information.

[0006] In view of the above, there is room for improvement in voltage regulators and control systems for voltage regulators.

[0007]

【Overview】

In general, according to one aspect, the present invention is directed to a method of operating a voltage regulator that outputs an input terminal connected to an input voltage source, an output terminal connected to a load, and an input terminal. It has a plurality of switching circuits that alternately connect and disconnect to terminals. The method calculates an estimated current for each switching circuit. Each estimated current represents a current flowing through an inductor associated with the switching circuit. The desired total output current through the inductor is calculated, which keeps the output voltage at the output terminal substantially constant. The switching circuit is controlled based on the estimated current and the desired total output current, so that the total current flowing through the inductor is substantially equal to the desired total output current.

According to another aspect, the present invention is directed to a voltage regulator having an input terminal connected to an input voltage source, and an output terminal connected to a load. The plurality of switching circuits intermittently connect the input terminal and the output terminal in response to the digital control signal. A plurality of filters, each including an inductor, provide a substantially DC output at an output terminal. The plurality of current sensors generate a feedback signal derived from a current flowing through the switching circuit. The digital controller receives and uses the plurality of feedback signals to calculate an estimated current for each switching circuit. Each estimated current represents a current flowing through an inductor associated with the switching circuit. The total desired output current through the inductor is calculated, which keeps the output voltage at the output terminal substantially constant. A digital control signal is generated based on the estimated current and the total desired output current, such that the total current flowing through the inductor is substantially equal to the total desired output current.

According to another aspect, the present invention is directed to a method of determining a total desired current through a switching circuit of a voltage regulator to maintain an output voltage at an output terminal substantially constant. The switching circuit intermittently connects an input terminal connected to an input voltage source to an output terminal connected to a load. The voltage regulator includes at least one capacitor connected to the output terminal. A first output voltage is measured at an output terminal at a first time and a second output voltage is measured at an output terminal at a second time. An estimated current representing the current flowing through the inductor is calculated, a capacitance current representing the current flowing to or from the at least one capacitor is calculated based on a difference between the first output voltage and the second output voltage, and a correction current is calculated. Is calculated based on the difference between the first voltage and one of the first and second output voltages. The total desired current of the voltage regulator is calculated from the difference between the sum of the estimated and corrected currents and the capacitance current.

[0010] According to another aspect, the invention is directed to a voltage regulator. The regulator has an input terminal connected to an input voltage source and an output terminal connected to a load. A switching circuit intermittently connects the input terminal and the output terminal in response to the digital control signal. A filter provides a substantially DC output voltage at the output terminal. A current sensor generates a digital first feedback signal representing the current flowing through the switching circuit. A voltage sensor generates a second feedback signal representing the output voltage. A digital controller receives and uses the digital feedback signal to generate a digital control signal. The digital controller is configured such that the output voltage at the output terminal maintains a substantially constant level.

According to another aspect, the present invention is directed to a voltage regulator having an input terminal connected to an input voltage source, and an output terminal connected to a load. The voltage regulator has a plurality of slaves, each slave responding to a digital control signal, a switching circuit intermittently connecting an input terminal and an output terminal, a filter providing an almost DC output voltage to an output terminal, and a switching circuit. A current sensor that generates a digital feedback signal representing a current flowing through the circuit; and a digital controller that receives and uses digital feedback signals from a plurality of slaves that generate a plurality of digital control signals. The digital controller is configured such that the output voltage at the output terminal maintains a substantially constant level.

According to another aspect, the present invention is directed to a method of operating a voltage regulator, the voltage regulator having an input terminal connected to an input voltage source, and an output terminal connected to a load. The input terminal and the output terminal are intermittently connected by a switching circuit in response to a digital control signal. The output of the switching circuit is filtered to provide a substantially DC output voltage at the output terminal. A digital feedback signal is generated to represent the current flowing through the switching circuit having the current sensor. The digital controller receives and uses the digital feedback signal from the slave to generate a digital control signal. The digital controller is configured to maintain the output voltage at the output terminal at a substantially constant level.

According to another aspect, the present invention is directed to a voltage regulator having an input terminal connected to an input voltage source, and an output terminal connected to a load. The switching circuit intermittently connects the input terminal and the output terminal in response to the control signal. The filter provides a substantially DC output voltage at the output terminal. The digital controller operates at a clock frequency f _clock , which is significantly faster than the switching frequency f _switch desired for the switching circuit. At each clock cycle, the digital controller receives a first digital feedback signal derived from the output voltage at the output terminal and a second digital feedback signal derived from the current flowing through the switching circuit, and controls the switching circuit And the output voltage is maintained at a substantially constant level.

According to another aspect, the present invention is directed to a method of operating a voltage regulator having an input terminal connected to an input voltage source and an output terminal connected to a load.
The input terminal and the output terminal are intermittently connected by a switching circuit in response to a digital control signal. The output of the switching circuit is filtered to provide a substantially DC output voltage at the output terminal. Digital controller operates at a clock frequency f _{cloc k,} which is significantly faster than the desired switching frequency _{f: switch} to the switching circuit. The digital controller receives a first digital feedback signal derived from the output voltage at the output terminal and a second digital feedback signal derived from the current flowing through the inductor at each clock cycle. The control signal is generated by a digital controller to control the switching circuit, thereby maintaining the output voltage at a substantially constant level.

According to another aspect, the present invention is directed to a method for estimating a current flowing through an inductor of a voltage regulator, wherein the voltage regulator includes a switching circuit intermittently connecting an output terminal to an input terminal. The initial estimated current is stored and represents the current flowing through the inductor, and the initial estimated current is adjusted based on the state of the switching circuit to generate a new estimated current.

According to another aspect, the present invention provides an input terminal to be connected to an input voltage source, an output terminal to be connected to a load, a switching circuit connecting the input terminal to an intermediate terminal, and an output terminal. And a filter having an inductor for generating a substantially DC voltage. The initial estimated current is stored and represents the current flowing through the inductor. The initial estimated current is adjusted based on the state of the switching circuit to generate a new estimated current. The total desired output current through the inductor is determined, which keeps the output voltage at the output terminal substantially constant. The switching circuit is controlled based on the estimated current and the total desired output current, such that the total current flowing through the inductor is substantially equal to the total desired output current.

According to another aspect, the invention is directed to a method for estimating a current flowing through an inductor in a voltage regulator, the voltage regulator including a switching circuit intermittently connecting an output terminal to an input terminal. The initial estimated current represents the current flowing through the inductor. When the output terminal is connected to the input terminal, the increasing current is added to the initial estimated current, and when the output terminal is grounded, the decreasing current is subtracted from the initial estimated current.

According to another aspect, the present invention is directed to a voltage regulator having an input terminal to be connected to an input voltage source, and an output terminal to be connected to a load. The voltage regulator includes a switching circuit intermittently connecting the input terminal and the output terminal in response to a control signal, a filter including an inductor for providing a substantially DC output voltage to the output terminal, and a digital controller. The digital controller stores an initial estimated current representing the current flowing through the inductor, adjusts the initial estimated current based on the state of the switching circuit to generate a new estimated current, and makes the output voltage substantially constant. A control signal based on the adjusted estimated current and the total desired output current is generated to determine the total desired output current through the maintaining inductor and to control the switching circuit, so that the output voltage is substantially constant Maintained at the level.

According to another aspect, the present invention provides an input terminal connected to an input voltage source, an output terminal connected to a load, and at least one switching circuit intermittently connecting the input terminal and the output terminal. And a method of operating a voltage regulator having the same.
An estimated current is calculated for each of the at least one switching circuit, each estimated current representing a current flowing through an inductor in the associated switching circuit. The total desired output current through the inductor that maintains the output voltage at the output terminal at a substantially constant level is calculated, and the upper and lower current limits are calculated. The average of the upper and lower current limits is equal to the individual desired output current for one inductor. For one or more switching circuits, the switching circuit connects the input terminal to the output terminal when the estimated current falls below the lower limit current, and when the estimated current rises above the upper limit current, Connect the output terminal to ground.

According to another aspect, the invention relates to an input terminal to be connected to an input voltage source, an output terminal to be connected to a load, and at least one switching intermittently connecting the input terminal and the output terminal. The present invention is directed to a method of operating a voltage regulator having a circuit. An estimated current is determined for each switching circuit, and each estimated current represents a current flowing through an inductor associated with the switching circuit. The desired total output current through the inductor is calculated to maintain the output voltage at the output terminal at a substantially constant level.
For one or more switching circuits, an individual desired current is calculated, and the estimated current is compared to the individual desired current, and the switching circuit is switched so that the current flowing through the switching circuit is equal to the desired current. It is almost equal.

According to another aspect, the present invention relates to an input terminal to be connected to an input voltage source, an output terminal to be connected to a load, and a plurality of switching circuits intermittently connecting the input terminal and the output terminal. And a method of operating a voltage regulator having the same. One of the plurality of switching circuits is selected as a reference circuit, and a desired phase offset is determined for the remaining switching circuits. An estimated current is calculated for each switching circuit, each estimated current representing a current through an inductor associated with the switching circuit. The desired total output current through the inductor is calculated and the output voltage at the output terminal is maintained at a substantially constant level, and the switching circuit is configured to substantially achieve the desired phase offset and the desired total output current. Connect the output terminal to the input terminal or the ground by the method.

Advantages of the present invention may include the following. The voltage regulator handles relatively large currents that respond quickly to load changes. The voltage regulator may use a small capacitor with an easy-to-use form factor. The voltage regulator may include a plurality of slaves operating in opposite phases to reduce ripple current. The use of analog circuits is minimized by converting analog measurements of the controller to digital signals. The controller is implemented largely using digital circuits and can be produced using known processes by conventional complementary MOS (CMOS) production techniques. This reduces the number of components not included on the chip in the controller. The controller operates with a digital control algorithm, in which case the operating parameters can be corrected to suit the voltage regulator for different applications. Digital control algorithms can operate at clock frequencies that are significantly higher than the switching frequency, and can respond quickly to load changes. The master and the slave can communicate by digital signals, thereby improving the reliability of communication +.

[0023]

【detailed explanation】

Referring to FIG. 1, a switching regulator 10 is connected to a non-constant DC input voltage source 12 such as a battery by an input terminal 20. The switching regulator 10 is also connected to a load 14 such as an integrated circuit by an output terminal 22. Load 14 _typically has an expected nominal voltage V _nom and a voltage tolerance ΔV _nom . The nominal voltage V _nom of a microprocessor chip is _typically about 1.0 to 5.0
Volts, eg, about 1.2 to 1.8 volts, and the voltage tolerance ΔV _nom is _typically ± 6% of the nominal voltage V _nom , ie, about 80 volts for a nominal voltage of 1.2 volts.
mV. The switching regulator 10 functions as a DC / DC converter between the input terminal 20 and the output terminal 22. The switching regulator 10, the input voltage V _in at the input terminal 20, a nominal voltage V _Ndjom tolerance one or more slaves 16 for converting the output voltage V _out of _the [Delta] V _nom is within an output terminal 22, and slave 16 Includes a master controller 18 for controlling the operation of. Master controller 18 is powered by voltage source 12 (as shown) or another voltage source.

In short, the master controller 18 uses a digital current reference control algorithm. Based on the output voltage V _out from the slaves and the feedback, the control algorithm of the master controller 18 changes the state of each slave 16 to maintain the output voltage V _out at a substantially constant level, ie, within a voltage tolerance range. judge. The master controller 18 generates a set of control signals for controlling each slave 16 and sets it to an appropriate state. More specifically, master controller 18 ensures that the current from switching regulator 10 matches the current into load 14, thereby maintaining the output voltage at a substantially constant level. For example,
As the current load (or simply "load") increases, the amount of current flowing through the slave increases. This causes the current to “slope up” until the desired load is reached. On the other hand, when the load decreases, the amount of current passing through the active slave decreases.
This causes the current to "fall down" until the desired load is reached.

Each slave 16 includes a switching circuit 24 serving as a power switch for alternately connecting and disconnecting the input terminal 20 to the intermediate terminal 26. The switching circuit 24 also includes a rectifier such as a switch or a diode, and connects the intermediate terminal 26 to ground. The intermediate terminal 26 of each slave is connected to the output terminal 22 via the output filter 28. Opening and closing of the switching circuit 24 generates an intermediate voltage V _int having a rectangular wave at the intermediate terminal 26. Output filter 28 converts this square wave into an output voltage that is substantially DC at output terminal 22. Although this switching regulator is illustrated and described below as a buck converter topology, the invention is also applicable to other voltage regulator topologies, such as, for example, a boost converter or a buck-boost converter topology.

As shown, the switching circuit 24 and the output filter 28 are configured in a buck converter topology. In particular, the switching circuit 24 of each slave 16 includes a switch such as a first transistor 30 having a source connected to the input terminal 20 and a drain connected to the intermediate terminal 26. Switching circuit 24 also includes a rectifier, such as second transistor 32, having a source connected to ground and a drain connected to intermediate terminal 26. The first transistor 30 is a P-type MOS
(PMOS) device, and the second transistor 32 is an N-type MOS (NMOS)
) Devices are fine. Alternatively, the second transistor 32 may be replaced by a diode or complemented by a diode to allow rectification. First and second transistors 30 and 32 are driven by switching signals on control lines 44a and 44b, respectively. The output filter 28 includes an intermediate terminal 26 and an output terminal 2
And a capacitor 36 connected in parallel with the load 14.
And Further, the capacitors 36 from each slave 16 may be supplemented or replaced by one or more capacitors connected to a common line from the inductor 34.

When the first transistor 30 is closed and the second transistor 32 is open (PMOS conduction state), the intermediate terminal 26 is connected to the voltage source 12, and the voltage source 12
Energy is supplied to the load 14 and the inductor 34 via the first transistor 30. On the other hand, when the first transistor is open and the second transistor is closed (NMOS conduction state), the intermediate terminal 26 is connected to ground, and energy is supplied to the load 14 by the inductor 34.

Each slave 16 includes first and second current sensors 40 and 42 that measure the respective currents of first and second transistors 30 and 32. The master controller 18
The information of the current sensors 40 and 42 is used in the state of the current reference control algorithm. Each current sensor generates a digital output signal on one or more output lines. With a single bit signal, the digital output signal on the output line is switched from high to low when the current through the slave exceeds or falls below the trigger current, and vice versa. In particular, the signal on the first output line 44c from the first current sensor 30 _indicates that when the current through the first transistor exceeds the first trigger current I _pcross
Switch from low to high. Similarly, the output signal on the second output line 44 from the second current sensor 42 switches from high to low when the current through the second transistor 32 _drops below the second trigger current _Incross. .

As shown in FIG. 1, each output line 44 c and 44 d is connected to the master controller 18.
May be directly connected. Alternatively, as shown in FIG. 1A, the first and second output lines may be coupled together to form a single output line 44g. In this case, the master controller 18 'determines that the signal g ₁ on the output line 44g is based on whether the slave is in a PMOS (first transistor) or NMOS (second transistor) conducting state. , g ₂ ,..., g _n represent the current of the first or second transistor.

Referring to FIG. 2, each current sensor such as, for example, the first current sensor 40 includes a reference transistor 52, a current source 54 and a comparator 56. A similar current sensor is An
No. 09 / 183,417, entitled "Current Measurement Techniques," co-filed by Thony Stratakos et al. and assigned to the assignee of the present invention, the entire disclosure of which is incorporated herein by reference. Incorporated in The reference transistor 52 has a source connected to the source of the transistor being measured or the first transistor 30, a drain connected to the current source 54, and a gate connected to the control line 44e. The reference transistor 52 is the same as the power transistor 30. That is, since the transistor elements are manufactured on the same chip with the same dimensions and using the same process, both have substantially the same electrical characteristics. Known current I _{re f} flows through the current source 54. The positive input of the comparator 56 is connected to a node 58 between the drain of the reference transistor 52 and the current source 54, and the negative input of the comparator 56 is connected to the intermediate terminal 26. The output of the comparator is connected to reference line 44c. The second current sensor 42 is similarly configured, but has a polarity associated with the NMOS transistor.

In operation, assuming that both power transistor 30 and reference transistor 52 are closed, slave current I _slave will flow through power transistor 30 and reference current I _ref will flow through reference transistor 52. The voltage V _node at node 58, V _node = V _in - given by _(R R × I _ref), where R _R is the equivalent resistance of the transistor 52, while the voltage V _int at the intermediate terminal 26 , V _{i nt} = V _in - is given by (R _P × I _slave), wherein R _P is a power transistor 30
Resistance. Since the reference transistor 52 is made of a single transistor element, while the power transistor is made of an N transistor element,
Resistance R _P of the power transistor is substantially equal to 1 / N times the R _R of the reference transistor 52, thus _{V node = V in - (R} P × N × I ref) , and the slave current I _{sl ave} is N × If greater than I _ref , node voltage V _node will be greater than intermediate voltage V _int . Thus, if the slave current I _slave is greater than the threshold current N × I _ref , the current sensor 40 outputs a high signal on the output line 44c, while if the slave current I _slave is lower than the threshold current N × I _ref , 44c
To output a low signal.

The two current sensors 40 and 42 have different threshold currents T_pcrossAnd
And T_ncrossTo provide different reference currents I_refMay be used. No.
1st threshold current T for one current sensor 40_pcrossIs the second current sensor
The second threshold current T for the capacitor 42_ncrossIt may be larger. Therefore,
Reave current I_slaveIs the threshold current T_pcrossIf greater, current sensor
40 outputs a high signal and the slave current I_slaveIs the threshold current T_pcross
If less, a low signal is output. Similarly, the current sensor 42 detects the slave current I _slave Is the threshold current T_ncrossIf greater, high on output line 44d
Output the signal and the slave current I_slaveIs the threshold current T_ncrossLess than
Outputs a low signal. These simple threshold output signals are
Provides information about the slave current to the controller 18 and reduces noise from analog signals.
Less power consumption and less A / D conversion of current
, Eliminating the need for multiple interconnects.

The current thresholds T _ncross and T _pcross are selected so that the slave current I _slave is changed at each switching cycle, ie at each PMOS and NM
At least one threshold can be crossed while the OS is conducting. The threshold current T _pcross must be higher than the threshold current T _ncross to increase the likelihood that the slave current I _slave crosses the threshold after the comparator is enabled. In one embodiment, the first threshold current T _pcross may be about 8 amps, while the second threshold current T _ncross may be about 2 amps.

The current sensor can be configured to output more than one digital signal. For example, if the slave current I _slave exceeds a first threshold current T _pcross , the current sensor can generate a first digital signal, and if the slave current I _slave exceeds a second threshold current T _pcross2 , the second Can generate digital signals,
And so on.

Returning to FIG. 1, as described above, the output voltage V _out of the output terminal 22 is made constant by the master controller 18 or maintained at a substantially constant level. Master controller 18 measures the voltage at output terminal 22 and receives digital output signals on output lines 44c and 44d from current sensors 40 and 42 of each slave 16. In response to the measured output voltage _Vout and the output signal from the current sensor, the master controller 18 generates a control signal to control the operation of the first and second transistors 30, 32 in each slave 16. The operation of master controller 18 will be described in further detail below.

The master controller 18 and the slave 16 may be configured utilizing components that are largely digital and based on switched capacitors. Thus, most switching regulators 10 are implemented on or fabricated on a single chip utilizing conventional CMOS technology. However, preferably, each slave 16 is manufactured on a single chip and the master controller 18 is manufactured on a separate chip. Alternatively, each slave is manufactured on a single IC, the voltage sensor is manufactured on a separate IC chip, and the rest of the digital controller is
It may be manufactured on a C chip. Each chip may be manufactured utilizing conventional CMOS technology.

Referring to FIG. 3, the master controller 18 includes a voltage sampling circuit 60 that measures the output voltage V _out of the output terminal 22 at one or more discrete times during each cycle of the switching circuit. This sampling circuit 60 is based on Anthony Stratakos
No. 08 / 991,3 filed Dec. 16, 1997, assigned to the assignee of the present invention, the entire disclosure of which is incorporated herein by reference.
No. 94, "Discrete Time Sampling of Data for Use in Switching Regulators". The sampling circuit 60 may be grounded directly to the microprocessor ground to reduce errors caused by parasitic capacitance and inductance. The voltage sampled by the sampling circuit 60 is supplied to an analog / digital (A / D) converter 6.
2 converts it into a digital voltage signal.

The master controller 18 also includes a digital control algorithm 64. The digital control algorithm uses a digital voltage signal from the A / D converter 62 and output signals c ₁ , c ₂ ,..., C _n from the output lines 44 c and 44 d and d ₁ , d _{2 ,.} And a clock signal 66 from an external clock. Clock signal 66 may be generated by the same clock running the microprocessor, by other IC devices in the load, or by a clock on the master controller chip. Clock frequency f _clock may have to significantly higher than the switching frequency _{f: switch} of the switching circuit 24, for example, in order to ensure to respond quickly to load change, it is preferable to 10 to 100 times higher. However, the clock frequency f _clock should not be so high that the switching regulator and the master controller constitute a large drain on the voltage source. Normally, the clock frequency f _clock is not as high as the clock speed of the microprocessor, but is generated by dividing the clock signal of the microprocessor. The frequency of the clock signal 66 is between about 16 and 66 MHz, for example a frequency f _clock of about 33 MHz.

Referring to FIG. 3A, another implementation of the master controller 18 ′ is the difference between the output voltage and the nominal voltage, ie, V _{out [n]} −V _nom , and the current output voltage and the previous clock. It includes a voltage sampling and holding circuit 60 'connected to the output terminal 24 to measure the output voltage difference in the cycle, _{Vout [n]} -Vout _[n-1] . The digital nominal voltage V _nom may be set by an external pin and converted to an analog voltage by a digital / analog (D / A) converter 68.
In this implementation, the voltage difference sampled by sampling circuit 60 'is
The signals are converted into two digital voltage difference signals by two A / D converters 62 '. In the case of a voltage difference, the conversion required is narrower (compared to A / D converter 60 '), so that a simpler and faster A / D converter can be used.
Digital control algorithm, A / D converter digital voltage difference signal from the 62 ', the output signal c ₁ from the output line 44c and _{44d, c 2, ..., c} n, and d _1, d _2, ... ,
d _n, (described with reference to FIG. 1A below) the clock signal 66 from an external clock, the digital nominal voltage V _nom, and receives the current limit signal on a current limit line 44h.

Returning to FIG. 1 and FIG. 3, the digital control algorithm 64
To control the transistor 30 and 32 in the control signals a _1, a ₂ in timing lines 44a and _44b, ..., a _n and b _1, b _2, ..., to produce a set of b _n . Based on the current load, the digital control algorithm 64 operates such that the switching state of each slave, ie, the output voltage V _{out at the} output terminal 22, is substantially maintained within the voltage tolerance ΔV _nom of the nominal voltage V _nom. , PMOS transistor 30
Is closed and the NMOS transistor 32 is opened and the NMOS transistor 32 is closed and the PMOS transistor 30 is opened, or the PMOS transistor 30 and the NMO
It is determined that both S transistors 32 are open.

As an alternative, referring to FIGS. 1A, 3A and 13A, the master controller 1
8 'generates one or more digital state control signals, which are
Interpreted by on-chip interpreter 48 in each slave 16 'to generate control signals on 4a and 44b. As shown, the master controller 18 '
But on the state control line 44h, PMOS state control signal _{e 1, e 2, ...,} e N, NM
OS state control signals _{f 1, f 2, ...,} f N and continuous / discontinuous mode operation control signal _{h 1, h 2,, ...} , h N, to produce a. In particular, when the slave is switched to the PMOS conduction state, the master controller outputs a pulse 49a on the PMOS state control line 44e. On the other hand, when the slave is switched to the NMOS conducting state, the master controller 18 'sends the pulse 4
9b is output. On-chip interpreter 48 interprets the rising edge of pulse 49a on state control line 44e as a command to switch slave 16 to the PMOS state. For example, switching is performed by setting control line 44a 'high and control line 44b' low. Conversely, the rising edge of pulse 49b on state control line 44f is interpreted by on-chip interpreter 48 as a command to switch slave 16 to the NMOS state. For example, switching is performed by setting control line 44a 'low and control line 44b' high. The on-chip interpreter detects the falling edges of the pulses on state control lines 44e and 44f,
Interpret as an instruction to enable the comparator 56 in 0 and 42.

When continuous mode operation is enabled (eg, when control line 44g is low), the switching circuit typically operates when slave current I _slave is negative. However, if the NMOS transistor 30 is closed and the discontinuous mode operation control signal is disabled (eg, when the control line 44g is high),
Both NMOS transistor 30 and PMOS transistor 32 open to prevent negative current from flowing through the slave if slave current I _slave is below zero. Generally, the master controller 18 operates the slaves in a more efficient discontinuous mode. However, when the load is large and causes a rapid voltage drop, it is advantageous to operate in continuous mode.

The slave also includes a fault protection circuit 68, and the current of the switching circuit is, for example, 15
Automatically shuts down the slave if the dangerous ampere level is exceeded (disables the control signal from the master controller). When the failure protection circuit 68 is activated,
The slave sends a digital signal on the current limit line 44i (see FIG. 3A) to inform the master controller 18 'that the slave has been deactivated. The slave may generate another digital feedback signal. For example, the slave may include a state sensor and generate a digital state signal that indicates the state of the switching regulator, such as being in a PMOS or NMOS conducting state.

Referring to FIG. 4, each clock cycle T_clockEach time, for example, clock frequency f_{c lock} Is approximately 33 MHz, the digital control algorithm
64 may execute the control method 100. The control algorithm 64 is used for each slave.
The estimated current I representing the current of the slave inductor 34_estimateJudge
(Step 102). Control algorithm 64 also determines the target on output terminal 22
Desired voltage V representing output voltage_desIs calculated (step 104), and
Desired current I that represents the current that would flow into the load_totalIs calculated.
Pressure V_outIs substantially the desired voltage V_des(Step 106). Next,
Control algorithm, the desired number of clocks to be activated in the next clock cycle.
The slaves are determined (step 108) and the desired current I_desTotal
(Step 110). Finally, the control algorithm determines the first and
2 transistors 30 and 32 so that the total current of the slave is equal to the desired total current I _total Substantially, for example, the desired current error ΔI_totalWithin the range (step
112). Each of these steps is described in further detail below. However,
It will be appreciated that they need not be performed in a fixed order. For example, various calculations are performed in parallel
Or may be executed and stored in a previous clock cycle. Special
In addition, the desired voltage and current are calculated and stored for use in the next clock cycle.
Is done.

Referring to FIGS. 1 and 5, an estimated current I _estimate is calculated in step 102.
Variation rate of current passing through the inductor, i.e. dI / dT is proportional the voltage V _Inductor across the inductor,

[0046]

(Equation 1)

Here, L is the inductance of the inductor for the current flowing from the intermediate terminal 26 to the output terminal 22. During the PMOS conduction state, the intermediate terminal 26 is connected to an input voltage source, the voltage V _Inductor across the inductor 34, i.e. _{V out} -V intetmed _iate is positive, thereby increasing the current in the inductor. On the other hand, during the NMOS conduction state, since the intermediate terminal 26 is grounded, the voltage V _Inductor across the inductor 34 becomes negative, thereby reducing the current in the inductor. PMOS
During the conduction state, the slope of the slave current I _slave (indicated by phantom line 70) is given by:

[0048]

(Equation 2)

On the other hand, during the NMOS conduction state, the slope of the slave current I _slave is given by the following equation.

[0050]

(Equation 3)

The estimated current I _estimate (indicated by solid line 72) is adjusted every clock cycle.
In particular, during the PMOS conduction state, the estimated current I _estimate is increased by a value ΔI _up that rises with a constant slope every clock cycle. Similarly, during NMOS conduction,
The estimated current I _estimate is reduced by a value ΔI _down that falls at a constant slope every clock cycle. ΔI _up and ΔI _down that rise and fall at a constant gradient may be given by the following equations.

[0052]

(Equation 4)

Here, L is the inductance of the inductor 34, and f _clock is the clock frequency.

The nominal value may be used as a variable in the determination of ΔI _up and ΔI _{down so} that the rate of rising and falling at a constant slope does not change during operation of the switching regulator. Alternatively, one or more of the values of V _in , V _out , f _clock and L may be ΔI _up and ΔI _down to allow for dynamic adjustment of the rate of rise and fall with a constant slope during operation of switching regulator 10. May be measured and used for recalculation. Unfortunately, the inductance L and the input current V _in is, exactly not know will vary with the time, also changes from circuit to circuit. Therefore, the estimated current I _estimate deviates from the actual slave current I _slave . As a result, it is sometimes necessary to check the estimated current I _estimate against the actual slave current I _slave . At each clock cycle, the estimated current I _estimate for the slave is checked against the output signals from current sensors 40 and 42. If the estimates do not match the measurements, the estimates are adjusted to match.

Referring to FIG. 6A and FIG. 7A, during the PMOS conduction state, the estimated current I_estimateIs above
Threshold current I_pcrossLess than the output signal c from the current sensor 40 ₁ Is high, the estimated current is I_pcrossIs increased to match. FIG. 6B
7B, the estimated current I_estimateIs the upper threshold current I_pcross , But the output signal c₁Is low, the estimated current I_estimateIs the output signal c₁ Until I goes high_pcrossIs kept. Referring to FIG. 6C and FIG.
During the passing state, the estimated current I_estimateIs the lower threshold current I_ncrossAbove
However, the output signal d from the current sensor 42₁Is low, the estimated current I_estimateIs
I_ncrossIs immediately reduced to match. Referring to FIG. 6d and FIG.
Style I_estimateIs the lower threshold current I_ncrossBut falls below
Signal d₁Is high, the estimated current I_estimateIs the output signal d₁Until I is low_{ncro ss} Is held. Estimated current I_estimateThe calculation of is summarized in Table 1.

[0056]

[Table 1]

The digital control algorithm ignores the signal from the current sensor in one or more clock cycles immediately after switching between the PMOS and NMOS conduction states to prevent spurious signals from incorrectly adjusting the estimated current. May be.

[0058] Delay time by the switching time required for operating the comparator and [Delta] T _{dela y,} a propagation time required for the signal is transmitted along the output line 44c or 44d is factored into the determination of the estimated current You. For example, if the estimated current I _estimate is corrected when the output signal c ₁ is switched from low to high, then the correction factor ΔT _delay × ΔI _up × f _switch will cause the master controller to receive a change in the output signal c ₁ It is added to the estimated current to represent the actual current. Similarly, if the estimated current I _estimate is corrected when the output signal d ₁ is switched from high to low, the correction factor ΔT _delay × ΔI _down × f _switch is subtracted from the estimated current. Alternatively, the threshold current I _Pcross in order to obtain the same effect (while maintaining the original value of I _Ncross and I _Pcross used in Table 1), the correction coefficient T _delay × I _up × f _switch
, And the threshold current _Incross is reduced by the correction factor T _delay
xI _down × f _switch may be increased. Referring to FIG. 8, the desired voltage V _{des ired} is selected in step 104 so that the output voltage V _out is within the voltage tolerance ΔV _nom of the nominal voltage V _nom . The effect of load fluctuations on the output voltage V _out that increases the likelihood of being maintained at is shown by phantom line 80. In particular, if the load suddenly increases, current flows from the capacitor 36 to the load 14, thereby causing the output voltage V _out
Drops. Conversely, if the load on the switching regulator suddenly decreases, charge is stored on the capacitor 36, thereby increasing the output voltage _Vout . This causes the output voltage V _out to exceed the allowable voltage range, for example, up to the _excess voltage ΔV _excess .

The controller 18 selects the desired voltage V _desired to reduce or eliminate the _excess voltage ΔV _excess . If the switching regulator load is minimal,
The load can only be increased and therefore the output voltage _Vout can only be reduced. Conversely, when the load of the switching regulator is at its maximum, the load can only be reduced and thus the output voltage _Vout can only be increased. When the load is low, the desired voltage V _desired is set to be slightly higher than the nominal voltage V _nom . If the load is high, the desired voltage V _{desir ed} is set to be slightly lower than the nominal voltage V _nom. As shown by the solid line 82, this technique reduces the excess voltage [Delta] V _excess, thereby increasing the likelihood that the output voltage V _{ou t} remains within the desired voltage tolerance [Delta] V _nom nominal voltage V _nom. Thus, for a given load, the switching regulator can use smaller capacitors and maintain the same voltage tolerance. The desired voltage V _{desired [n + 1]} for clock cycle n + 1 may be calculated as follows:

[0060]

(Equation 5)

Where I _load is the current flowing through the load 14 (calculated from Equation 8 below), I _max is the maximum allowable current of the load 14, c ₁ and c ₂ are the feedback constants, and ΔV _swing is the voltage allowable range. It is an allowable voltage fluctuation, that is, ΔV _swing <ΔV _nom . For example, if the nominal voltage V _nom is 1.3 volts and the voltage tolerance is ± 6%, ΔV _nom is about 78 mV, ΔV _swing is about 30 mV, and c ₁ is about 1.0 mV.
, C ₂ would be about -0.9375.

[0062] Once the desired voltage V _Desired is when it is determined in step 104, the desired total current I _{tot al} is determined in step 106. In particular, the desired current I _total is set to maintain the output voltage V _out at the output terminal 22 at the desired voltage V _desired . In general, when the output voltage V _out is assumed to be equal to the desired desired voltage V _Desired, the total current flowing to the load through the inductor, should be equal to the current through the load, that is, I _{to tal} = I _load. However, if the voltage _Vout is different from the desired voltage _Vdesir , the current flowing through the switching regulator 10 may be adjusted to correct this voltage error. Thus, the desired total current I _total is expressed as:

[0063]

(Equation 6)

Here, I _adjust is an adjustment coefficient for correcting a voltage error.

Referring to FIG. 9, assuming that all capacitors connected to the output terminals are in the slave, the load current I _load is _equal to the output current I _out (i
) Is equal to the sum of, ie:

[0066]

Equation 7

The output current I _out (i) of each slave 16 is equal to the difference between the current flowing through inductor 34, ie, slave current I _slave (i), and the current flowing into or _{out of} capacitor 36, ie, capacitor current I _cap (i). And the result is:

[0068]

(Equation 8)

Thus, in this configuration, the desired total current I _total is expressed as:

[0070]

[Equation 9]

The slave current I _slave (i) is not exactly known, but will be approximated as the sum of the estimated currents I _estimate from each slave. In addition, the capacitor current I _cap (i) is not known, and the capacitors in the slave are supplemented by one or more capacitors, such as a microprocessor bypass capacitor connected to a common line from inductor 34, or It may be replaced. In general, however, if the output voltage V _out is fluctuating, current must flow to and from the capacitor 36. As a result, the total capacitor current I _CAP is given by:

[0072]

(Equation 10)

Here, C is the total capacitance of the capacitor connected between the output terminal and the ground, Δ
T is the clock period, and ΔV _out is the change in output voltage during the clock period. Therefore, the load current I _load is generally determined by the following equation:

[0074]

[Equation 11]

In the implementation shown in FIG. 3, the calculation of ΔV _out , ie, V _{out [n]} −V _{out [n−1]} , may be performed by the digital control algorithm 64, whereas FIG. 3A shows In the implementation, the voltage difference V _{out [n]} −V _{out [n−1]} is the sampling and holding circuit 60 ′.
Given by

The adjustment current I _adjust is directly proportional to the difference between the measured output voltage V _out and the desired voltage V _desired . Therefore, the desired total current I _total is calculated as follows:

[0077]

(Equation 12)

Here, K is a feedback constant that determines the adjustment current I _adjust .

Once the total desired current I _total has been determined, the controller 18 determines how many slaves are to be activated in step 108. The number of slaves for the current cycle can be calculated in the previous clock cycle. Generally, the number of active slaves is proportional to the total desired current. For example, each slave 1
Assuming that the maximum average current of 6 is about 7 amps, one slave may be active if I _total is 0-7 amps, two slaves may be active if I _total is 7-14 amps, etc. It is. More specifically, the number of active slaves is given by Table 2.

[0080]

[Table 2]

Once the desired total current I _total and the number of active slaves have been determined, the desired voltage I _desired may be calculated at step 110 for each slave. In particular, the desired voltage I _desired may simply be the total current I _total divided by the number of active slaves.

Once the desired current I _desired has been calculated for each active slave, the switching circuit of each active slave is controlled (step 112) so that the average current flowing through the active slave is substantially the desired The current becomes equal to I _desired and the total current flowing through the switching regulator is substantially equal to I _total . Therefore, the current flowing from the switching regulator 10 matches the current flowing to the load 12, thereby maintaining the output voltage at the desired voltage V _desired . The remaining or inactive slaves are not connected. That is, both the PMOS transistor 30 and the NMOS transistor 32 remain open.

Various control algorithms are possible for controlling the switching circuit of the active slave, so that the total current flowing through the switching regulator is substantially equal to the desired total current I _total . Generally, the control algorithm is chosen to balance the following factors: 1) all slaves can be switched on or off simultaneously to respond quickly to load changes; 2) slaves should minimize voltage ripple. Ensuring operation at the desired phase offset, 3) maintaining the average current equal to the desired current to maintain the voltage at a substantially constant level, and 4) switching at the desired switching frequency.

Referring to FIG. 10, one of the active slaves is selected as a reference slave based on, for example, a predetermined selection pattern (step 120). For example, a particular slave may be designated as a reference slave, or the reference slave may alternate slaves in order. As discussed below, the operation of the remaining slaves, ie, the non-reference slaves, is combined with the operation of the reference slaves. The reference slave is
It may be selected when the switching regulator is powered up or every time the number of active slaves is changed. Once the reference slave is selected, the desired phase offset is calculated for each non-reference slave (step 122). The desired phase offset may be determined each time the number of active slaves changes. Non-reference slaves are controlled to operate at the desired phase offset.

In each clock cycle, the upper limit current I_upperAnd the lower limit current I_lowerTwo currents including
A limit is calculated for the reference slave (step 124). Finally, the criteria
The slave is controlled based on a reference slave control algorithm (step 12).
6), and the non-reference slave is controlled based on the non-reference slave control algorithm
Is performed (step 128). In some implementations, the reference slave uses the estimated current I _estimate Current limit I above and below_upperAnd I_lowerControlled based on the comparison with the
The non-reference slave is controlled based on the desired phase offset. Of course, the figure
The order of the steps shown in FIG. 10 is by way of example and the steps are performed in parallel in another order
I can do it. For example, at any particular clock cycle, the current limit
It can be calculated before the phase offset, and the slave can calculate it in the previous clock cycle.
When controlled based on the stored current limit and phase offset, the calculation step is
It can be performed after the control step.

In step 122, for each non-reference slave, the control algorithm calculates a desired phase offset Φ (i) representing the desired time delay between the reference slave and the non-reference slave at the beginning of the PMOS and NMOS conduction states. . For example, if two slaves are active, they are 180 ° out of phase and the time delay should be equal to half the switching period T, ie, Φ (1) = 1 / (2T). If the three slaves are active, they are 120 ° out of phase and the time delays Φ (1) and Φ (2) should be equal to ３ and ／ of the switching period, respectively. By operating the out-of-phase slaves, the current ripple from each slave is at least partially canceled, thereby providing a more constant output current from the switching regulator. The desired phase offset is summarized by Table 3.

[0087]

[Table 3]

The _upper and _lower current limits I _upper and I _lower are calculated for the reference slave at step 124, so that the average current through the reference slave 16 equals the desired current I _desired . In particular, the upper current I _upper and the lower current I _lower are calculated as follows:

[0089]

(Equation 13)

Here, ΔI ₀ is the bandwidth of the reference slave. The bandwidth ΔI ₀ is set based on the desired switching frequency as follows:

[0091]

(Equation 14)

Here, f _switch is a desired switching frequency. The desired switching frequency is selected to provide good dynamic response while maintaining adequate power efficiency. In general, increasing the switching frequency reduces current ripple, but makes switching regulators inefficient. Conversely, lowering the switching frequency improves the power efficiency of the switching regulator but increases the current ripple. The switching frequency is in the range of about 0.5-5.0 MHz, for example, about 1 MHz. The bandwidth calculation that gives the desired switching frequency is based on either measured or nominal values of the other variables in Equation 14.

One of the basic operations of the master controller 18 in the control of the reference slave is
The implementation is described with reference to FIGS. As mentioned above, the master control
The controller 18 determines in step 102 that the estimated current I_estimate(Solid line 70)
). The master controller 18 also determines in step 122 that the upper limit current I_upper
(Shown by a solid line 72) and the lower limit current I_lower(Shown by solid line 74) is also calculated. Digital
Control algorithm 64 determines the estimated current I of the reference slave._estimateIs the upper limit current I_{up per} And lower limit current I_upperIn comparison with the first and second transistors 30 and 32
Determine whether to switch. In particular, the estimated current I_estimateIs the upper limit current I _upper Is exceeded, the NMOS transistor 32 is closed and the PMOS transistor is closed.
The terminal 30 opens, thereby grounding the intermediate terminal 26. On the other hand, the estimated current I_{estima te} Is the lower limit current I_lower, The NMOS transistor 32 opens and the PM transistor
OS transistor 30 is closed, thereby connecting intermediate terminal 26 to input voltage source 12.
Continued. Therefore, the estimated current I_estimateIs the current I flowing through the reference slave_slaveTo
Assuming accurate representation, the reference slave current I_slave(Shown by imaginary line 76)
Upper limit current I_upperAnd the lower limit current I_lowerBetween the reference slave current I_slaveof
The average current is the desired current I_desired(Indicated by imaginary line 78).

In the switching regulator 10 ′ shown in FIG. 1A, when the estimated current I _estimate exceeds the _upper limit current I _upper , the master controller 18 ′ outputs a pulse 49b to the state control line 44f. This pulse is output from the on-chip interpreter 4
8 is interpreted as a command to open the PMOS transistor 30 (indicated by the control line 44a going low in FIG. 13A) and close the NMOS transistor 32.
If, on the other hand, the estimated current I _estimate drops below the _lower limit current I _lower , the master controller outputs a pulse 49a on the control line 44a that opens the NMOS transistor 32 and closes the PMOS transistor 30 (the control line going high in FIG. 13A). 44a).

[0095] Upper limit current I_upperAnd the lower limit current I_lowerIs the average current flowing from the reference slave
It is used to control the switching circuit 24 to ensure that they actually match.
For example, as the load increases, I_desiredIncreases and the limiting current I_upperAnd I_lowerBut
To increase. On the other hand, when the load decreases, I_desiredDecreases and the limiting current I_upperAnd I _lower Decrease. In addition, if the load is substantially constant, the upper limit current I_upperWhen
Lower limit current I_lowerBandwidth ΔI between₀Is the switching frequency of the switching circuit 24.
Set the wave number.

Various control algorithms are possible for controlling the switching circuit of the non-reference slave to achieve the desired current and phase offset. 14 and 15
Referring to, in one implementation of the digital control algorithm 64, the non-reference slave is controlled based on one of the current limits and the switching time of one of the transistors in the reference slave. In summary, the switching of a non-reference slave is due to two events: when the estimated current for the slave passes one of the current limits, and at the end of the phase offset timer, which starts when the reference slave switches with the other current limit. Be attracted.

In particular, the estimated current I _estimate of the non-reference slave is (Equation 12 for the reference slave)
When the upper reference current I _upper is exceeded, the non-reference slave starts its NMOS conduction state, that is, the PMOS transistor 30 is opened and the NMOS transistor 32 is closed. The digital control algorithm can include one or more phase offset timers. The phase offset timer is used to trigger the non-reference slave PMOS conduction state. In particular, the timer is started when the reference slave starts its PMOS conduction state. At each clock cycle, the timer is compared to the desired phase offset Φ (i) of each non-reference slave. When the offset time Φ (i) associated with a particular non-reference slave expires, the non-reference slave begins to conduct PMOS, ie, the NMOS transistor 32 is opened and the PMOS transistor 30 is closed. Therefore, the phase offset Φ (i)
Determines the delay between the reference and non-reference slaves at the start of the NMOS conduction state. Of course, the mechanism of the attraction is that the PMOS conduction state that is attracted when the non-reference slave falls below the _lower limit current I _lower and that the reference slave has its NMO
A timer that operates when the S-conduction state is started can be inverted.

Referring to FIGS. 16 and 17, in a second implementation of the digital control algorithm 64
Is the upper and lower current limit I_upper(I) and I_lower(I) for each non-reference slave
Is calculated. The upper and lower current limits are such that the average current of the non-reference slave 16 is equal to the desired current I _desired Is chosen to be equal to Each slave has its own current limit
And the bandwidth ΔI of each slave_iControls the switching frequency of that slave
You. In particular, the switching period T can be calculated from the following equation:

[0099]

(Equation 15)

To adjust the phase difference between the reference slave and the non-reference slave, the bandwidth ΔI _i of the non-reference slave is adjusted to change its switching frequency. This changes the time difference between the PMOS and NMOS conduction states by making the non-reference slave slower or faster relative to the reference slave. Once the desired phase difference has been achieved, the bandwidth of the non-reference slave is readjusted, thereby
The switching frequencies of the two slaves match. To adjust the bandwidth of the non-reference slave, the digital control algorithm 64 measures the actual time delays T _N and T _p of the onset of NMOS and PMOS conduction of the two slaves. The bandwidth ΔI _i is then set equal to the desired bandwidth plus a feedback term proportional to the error or difference between the desired and actual time delay. For example, the bandwidth ΔI _i is calculated as follows:

[0101]

(Equation 16)

Here, K ₁ and K ₂ are feedback error constants, and ΔI ₀ is a desired bandwidth calculated by Expression 13. Next, the upper limit current I _upper (i) and the lower limit current I _lower (i) are
It is calculated as follows:

[0103]

(Equation 17)

The _upper and lower currents I _upper (i) and I _lower (i) are used to trigger the first and second transistors 30, 32 of the non-reference slave. In particular, when the estimated current I _{es timate} (i) exceeds the _upper limit current I _upper (i), the PMOS transistor 3
0 is open and NMOS transistor 32 is closed. On the other hand, the estimated current I _estimate (i
) _Falls below the _lower limit current I _lower (i), the NMOS transistor 32 opens,
PMOS transistor 30 closes. As a result, if the estimated current I _estimate (i) accurately represents the slave current I _slave (i), the slave current I _slave (i) is between the upper I _upper (i) the lower limit I _lower (i) Vibrates at Thus, the average current flowing through the slave is approximately equal to I _desired (i), and the total current flowing through the switching regulator is approximately equal to the desired total current I _total . Upper and lower current limits are set so that the average total output current from the slave matches the load.

Referring to FIGS. 18 to 23, in a third implementation, the digital control algorithm 64 calculates a “ghost” current for each non-reference slave 16. The ghost current I _ghost (i) represents the desired current flowing through the slave, given the current limit and the desired phase offset. Each non-reference slave is controlled by comparing the estimated current I _estimate (i) for the non-reference slave with the ghost current I _ghost (i).

The ghost current is calculated in the same manner as the calculation of the estimated current. That is, during the ghost PMOS conduction state, the ghost current I _ghost (i) (indicated by the solid line 84 in FIG. 22) is increased by a constant gradient rise value ΔI _up-ghost every clock cycle,
Then, during the ghost NMOS conduction, the ghost current I _ghost (i) is reduced by a constant gradient falling value I _down-ghost every clock cycle. However, if the ghost current I _ghost (i) exceeds the _upper limit current I _upper , the ghost current is set equal to the upper limit current I _{up per} . Similarly, ghost current I _ghost (i) if below the lower limit current I _{lo wer,} ghost current is set equal to the upper limit current I _lower.

The ghost conduction state is triggered by the switching of the reference slave and the desired phase offset (see FIGS. 20 and 21). In particular, the ghost switches to the ghost PMOS conducting state at the desired phase offset Φ (i) after the reference slave switches to the PMOS conducting state. Similarly, the ghost switches to the ghost NMOS conducting state at the desired phase offset Φ (i) after the reference slave switches to the NMOS conducting state.

As described above, the switching of the non-reference slave is a non-reference slave.
Constant current I_estimate(I) (indicated by solid line 86 in FIG. 23) for non-reference slave
Ghost current I_ghost(I) (compare dashed line 84 shown in FIG. 23)
Is controlled by In particular, the non-reference slave is in PMOS conduction and the ghost
Is in the NMOS conducting state and the estimated current I_estimate(I) is the ghost current I _ghost If (i) is exceeded, the slave switches to the NMOS conducting state.
Similarly, the non-reference slave is NMOS conductive and the ghost is PMOS conductive.
And the estimated current I_estimate(I) is the ghost current I_ghost(I) down
If so, the slave switches to PMOS conduction. In other words, the thread
When the node switches the estimated current, it crosses the ghost current and the two currents
Has the opposite slope. In this way, the slave can efficiently track the ghost current.
Is switched on. In addition, when the ghost is in PMOS conduction,
The reference slave uses the estimated current I_estimate(I) is the current offset I_overBy
Ghost current I_ghostIf it exceeds (i), it switches to the NMOS conduction state.
And if the ghost is in NMOS conduction, the non-reference slave will
I_estimate(I) is the current offset I_underGhost current I_ghost(I
), It switches to the PMOS conduction state. This allows the ghost current
The current slave can reliably track the ghost current even if changes rapidly.

Referring to FIGS. 24-27, in a fourth implementation, the digital control algorithm 64 calculates a “ghost” current for both reference and non-reference slaves, where both the reference and non-reference slaves It is controlled by comparing the estimated current I _estimate (i) with the ghost current I _ghost (i).

Referring to FIG. 25, the digital control algorithm 64 determines the desired switching frequency.
A switching frequency of approximately equal to the wave number, for example 1 MHz, and the desired duty cycle.
Cycle, for example, V_out/ V_inDuty cycle D_sWith
A lock signal 90 is generated. The duty cycle is V_inAnd V_nomBased on the nominal value of
May be fixed accordingly. Ghost derivation for each ghost using clock signal 90
Control the communication status. In particular, the clock signal is subject to the desired phase offset phi (i).
Generated for each active slave using each clock signal offset by
Can be done. The ghost has a clock signal 90 associated with the slave.
Is high, the ghost is in the PMOS conduction state, and the ghost is
Ghost NMOS conduction state when clock signal 90 associated with
Is within. For example, if three slaves are active, the third ghost is
, One third of the switching period after the second ghost, and after the first ghost
Is switched after 2/3 of the switching period of the switch. Reference slave is PMOS
At the desired phase offset phi (i) after switching to the active state, the ghost current, as best shown in FIGS.
In the same manner as the calculation of the ghost current discussed with reference to the third embodiment and FIG.
Is calculated. That is, during the ghost PMOS conduction state, the ghost current I_ghost
(I) (indicated by the solid line 92 in FIG. 26) is the rising value of a constant slope in each clock cycle.
ΔI_up-ghostThe ghost current I during the ghost NMOS conduction state. _ghost (I) is a falling value ΔI having a constant gradient in each clock cycle._down-ghostOnly the minute
Is reduced. However, the ghost current I_ghost(I) is the upper limit current I_upperA place beyond
The ghost current is the upper limit current I_upperIs set equal to Similarly, ghost
Current I_ghost(I) is the lower limit current I_lowerGhost current is below the upper limit current I _lower Is set equal to

Referring to FIGS. 24 and 27, as described above, the switching of the non-reference slave causes the estimated current I _estimate (i) for the non-reference slave (shown by solid line 94) to be:
Ghost current I _ghost (i) for non-reference slave (indicated by dotted line 92)
Is controlled by comparing with In particular, if the non-reference slave is in PMOS conduction, the ghost is in NMOS conduction, and the estimated current I _estimate (i) exceeds the ghost current I _ghost (i), the slave switches to NMOS conduction. Similarly, if the non-reference slave is in NMOS conduction, the ghost is in PMOS conduction, and the estimated current I _estimate (i) is _less than the ghost current I _{gh ost} (i), the slave switches to PMOS conduction. . In other words, when the slave switches the estimated current, it crosses the ghost current and the two currents have opposite slopes. In this way, the slave is switched to efficiently track the ghost current.

In addition, the non-reference slave switches to the NMOS conduction state if the estimated current I _estimate (i) exceeds the upper current I _upper , or the non-reference slave switches the estimated current I _{es timate} (i) to the lower current I _lower , Switching to the PMOS conduction state. In order to suppress excessive switching that reduces the efficiency, the constant gradient rise value ΔI _up-ghost and the constant gradient fall value ΔI _down-ghost of the _ghost are determined by the constant gradient rise value ΔI _up and the constant gradient value ΔI _up for the estimated current. It may be set artificially to less than the slope down value [Delta] I _down , for example to about 20-25%. Alternatively, the ghost current by some margin which is set in advance, beyond the upper and lower current limit I _upper and I _{low er,} or fall below an acceptable.

[Brief description of the drawings]

FIG. 1 is a block diagram of a switching regulator according to the present invention.

FIG. 1A is a block diagram of another embodiment of a switching regulator according to the present invention.

FIG. 2 is a block diagram of a current sensor of the switching regulator of FIG. 1;

FIG. 3 is a block diagram of a controller of the switching regulator of FIG. 1;

FIG. 3A is a block diagram of a controller of the switching regulator of FIG. 1A.

FIG. 4 is a flowchart illustrating a method performed by the controller of FIG. 3;

FIG. 5 is a timing diagram comparing the estimated current with the actual current flowing through the slave.

FIG. 6 is a timing chart illustrating correction of an estimated current.

FIG. 7 is a timing diagram illustrating an output signal from a current sensor associated with the correction of the estimated current in FIGS. 6A to 6D.

FIG. 8 is a timing diagram for comparing a desired voltage with an actual output voltage of a switching regulator.

FIG. 9 is a simplified block diagram used to determine a desired current.

FIG. 10 is a flowchart illustrating steps for controlling a switching circuit from the method of FIG. 4;

FIG. 11 is a flowchart illustrating a method for controlling a reference slave of the switching regulator of FIG. 1;

FIG. 12 is a timing diagram illustrating the current flowing through a reference slave resulting from the method of FIG.

FIG. 13 is a timing chart for explaining a control signal to the reference slave in FIG. 11;

FIG. 13A is a timing chart illustrating a control signal from the switching regulator of FIG. 1A to a reference slave.

FIG. 14 is a flowchart illustrating a method of controlling a phase relationship of a slave, where one transistor is switched at a preset time following switching of a reference slave, and another transistor is switched between an estimated current and a current limit. Is switched based on the comparison with.

FIG. 15 is a timing diagram illustrating the current flowing through a reference slave and a non-reference slave resulting from the method of FIG.

FIG. 16 is a flowchart illustrating a method for controlling a phase relationship of a slave, in which a current limit of a non-reference slave is adjusted.

FIG. 17 is a timing diagram illustrating the current flowing through the reference and non-reference slaves resulting from the method of FIG.

FIG. 18 is a flowchart illustrating a method for generating a ghost current for a non-reference slave.

FIG. 19 is a flowchart illustrating a method of controlling a phase relationship of a slave, in which an estimated slave current is compared with a ghost current.

FIG. 20 is a timing diagram illustrating the current flowing through the reference slave when performing the method of FIGS. 18 and 19;

FIG. 21 is a timing diagram illustrating a ghost conduction state for one non-reference slave resulting from the reference slave current shown in FIG.

FIG. 22 is a timing chart illustrating a ghost current generated by the method shown in FIG. 18 and a ghost conduction state shown in FIG. 21;

FIG. 23 is a timing diagram illustrating reference slave performance resulting from the method shown in FIG. 19 and the ghost current shown in FIG. 22.

FIG. 24 is a flowchart illustrating a method of controlling a phase relationship of a slave, in which ghost currents are generated for a reference slave and a non-reference slave, and an estimated slave current is compared with a ghost current controlling the slave. .

FIG. 25 is a timing diagram illustrating a ghost conduction state for one of the non-reference slaves resulting from a clock signal.

26 is a timing chart for explaining a ghost current generated by the method shown in FIG. 18 and a ghost conduction state shown in FIG. 25;

FIG. 27 is a timing diagram illustrating slave performance resulting from the method shown in FIG. 24 and the ghost current shown in FIG. 26.

────────────────────────────────────────────────── ─── Continued on the front page (31) Priority claim number 09 / 183,326 (32) Priority date October 30, 1998 (Oct. 30, 1998) (33) Priority claim country United States (US) ( 31) Priority claim number 09 / 183,337 (32) Priority date October 30, 1998 (Oct. 30, 1998) (33) Priority claim country United States (US) (81) Designated country EP (AT, BE, CH, CY, DE, DK, ES, FI, FR, GB, GR, IE, IT, LU, MC, NL, PT, SE), OA (BF, BJ, CF, CG, CI, CM, GA, GN, GW, ML, MR, NE, SN, TD, TG), AP (GH, GM, KE, LS, MW, SD, SL, SZ, TZ, UG, ZW), EA (AM, AZ) , BY, KG, KZ, MD, RU , TJ, TM), AE, AL, AM, AT, AU, AZ, BA, BB, BG, BR, BY, CA, CH, CN, CR, CU, CZ, DE, DK, DM, EE, ES , FI, GB, GD, GE, GH, GM, HR, HU, ID, IL, IN, IS, JP, KE, KG, KP, KR, KZ, LC, LK, LR, LS, LT, LU, LV, MA, MD, MG, MK, MN, MW, MX, NO, NZ, PL, PT, RO, RU, SD, SE, SG, SI, SK, SL, TJ, TM, TR, TT, TZ , UA, UG, UZ, VN, YU, ZA, ZW (72) Schulz, Aaron, M. United States, California, Sunnyvale, Coolidge Avenue 896 (72) Inventor Christenson, Michael United States, California, Berkeley, Martin Luther King Jr. Way 1429 A (72) Inventor Ridsky, David, Bee. United States, California, Oakland, Colton Boulevard 5739 (72) Inventor Stratacos, Anthony United States of America, California, Fremont, Red Hawk Ranch 39241 Bee 201 (72) Inventor Sullivan, Charlie United States of America, New Hampshire, Hanover, South Park Street 7 (72) Inventor Clark, William Terrace drive, Fremont, CA, USA 35624 F-term (reference) 5H730 BB11 BB82 DD04 DD34 FD31 FF09 FG05 FG11 FG22

Claims (122)

[Claims] 1. A voltage regulator having an input terminal connected to an input voltage source, an output terminal connected to a load, and a plurality of switching circuits for alternately connecting and disconnecting the input terminal to the output terminal. The method comprising: a) calculating an estimated current for each switching circuit, ie, each estimated current representing a current flowing through an inductor associated with the switching circuit; b) substantially calculating an output voltage at the output terminal. Calculating the total desired output current through the inductor, which is kept constant, and c) the estimated current and the total desired output such that the total current through the inductor is approximately equal to the total desired output current. Controlling the switching circuit based on a current. 2. The method of claim 1, wherein steps (a) to (c) are repeated. 3. The method of claim 1, wherein steps (a) to (c) are repeated at a clock frequency f _clock which is significantly faster than a desired switching frequency f _switch of said switching circuit. 4. The step of calculating the total desired output current includes determining the total current flowing through the switching circuit and determining a capacitive current flowing to or from a capacitor connected to the output terminal. 2. The method of claim 1, comprising the step of: 5. The method of claim 4, wherein determining the total current flowing through the switching circuit comprises summing the estimated current for each inductor. 6. The method of claim 4, wherein determining the capacitive current comprises measuring a variation in the output voltage. 7. The capacitive current is calculated from the following equation: I _CAP = C · ΔV _out / ΔT where C is the total capacitance of the capacitor connected to the output terminal, and ΔV _out is the clock cycle. 7. The method of claim 6, wherein said variation in said output voltage throughout, and T is said period of said clock cycle. 8. The method of claim 4, wherein calculating the total desired output current further comprises determining an adjustment current to correct for the output voltage error. 9. The method of claim 8, wherein said regulating current is proportional to a difference between said output voltage and a desired voltage. 10. The method of claim 9, further comprising: increasing the desired voltage if the current is above a predetermined current level; and decreasing the desired voltage if the current is below the predetermined current level. Method. 11. The method of claim 1, further comprising determining a number of active switching circuits. 12. The method of claim 11, wherein said number of active switching circuits is approximately proportional to said total desired current. 13. The method of claim 12, wherein the new number of active slaves is based on the old number of active switching circuits and the total desired current. 14. The method of claim 1, wherein the determining of the number of active slaves includes a hysteresis effect that avoids excessively changing the number of active switching circuits.
Method 2. 15. The method of claim 11, further comprising the step of calculating an individual desired output current for each switching circuit, wherein said sum of said individual desired output currents is equal to a previous total desired output current. 16. The individual desired current of the active switching circuit,
16. The method of claim 15, wherein said total desired current divided by said number of active switching circuits is approximately equal. 17. The method of claim 15, wherein said individual desired current for said inactive slave is substantially zero. 18. The method of claim 1, wherein calculating the desired total current comprises determining a desired voltage that is within a voltage tolerance of a nominal voltage. 19. The method of claim 19, further comprising: setting the desired voltage above the nominal voltage if the current is near a maximum current; and determining the desired voltage below the nominal voltage if the current is near zero. 19. The method of claim 18, including the step of setting a desired voltage. 20. The method of claim 18, wherein determining the desired voltage comprises adjusting the desired voltage by a term proportional to the difference between the desired voltage and the current voltage from a previous clock cycle. . 21. The desired voltage V _{desired [ n + 1]} for clock cycle n + 1 is determined by the following equation: Where V _nom is the nominal voltage, V _{desired [n]} is the desired voltage from clock cycle n, I _load is the current flowing through the load, I _max is the allowable maximum current flowing through the load, ΔV _swing is Fluctuations in the voltage allowed by the voltage tolerance,
Then c ₁ and c ₂ is a feedback constant The method of claim 20. 22. A voltage regulator having an input terminal connected to an input voltage source and an output terminal connected to a load, comprising: a) intermittently connecting the input terminal and the output terminal in response to a digital control signal. A plurality of switching circuits to connect; b) a plurality of said filters each providing an approximately DC output voltage at said output terminal including an inductor; c) a plurality of feedback signals derived from said current flowing through said switching circuits. And d) a digital controller for receiving and using the plurality of feedback signals, the digital controller: i) calculating an estimated current for each switching circuit, wherein each estimated current is Ii) representing a current flowing through the inductor associated with a switching circuit; Calculating a total desired output current through the inductor that maintains an output voltage at an output terminal substantially constant; and iii) estimating the total current through the inductor to be approximately equal to the total desired output current. Generating the digital control signal based on a current and the total desired output current; a voltage regulator. 23. A method for determining a total desired current flowing through a switching circuit of a voltage regulator to maintain an output voltage at an output terminal substantially constant.
The switching circuit intermittently connects an input terminal connected to an input voltage source to the output terminal connected to a load, the voltage regulator includes at least one capacitor connected to the output terminal, Measuring a first output voltage at the output terminal at a first time; measuring a second output voltage at the output terminal at a second time; Calculating an estimated current representing the current; calculating a capacitance current representing a current flowing to or from the at least one capacitor based on a difference between the first output voltage and the second output voltage; Calculating a correction current based on a difference between one of the first and second output voltages; and the estimated current and the correction Method comprising; sum of the flow, calculating the total desired current to said voltage regulator from the difference between the capacitance current. 24. A voltage regulator having an input terminal connected to an input voltage source and an output terminal connected to a load: intermittently connecting the input terminal and the output terminal in response to a digital control signal. A switching circuit; a filter for providing a substantially DC output voltage at the output terminal; a current sensor for generating a digital first feedback signal representing the current flowing through the switching circuit; a second feedback signal representing the output voltage. And a digital controller for receiving and using the digital feedback signal to generate the digital control signal, ie, configured to maintain the output voltage at the output terminal at a substantially constant level. A voltage regulator comprising the digital controller. 25. The voltage regulator of claim 24, wherein said switching circuit includes a commutator connecting said output terminal to ground at least intermittently. 26. The switching circuit, a filter and a current sensor, wherein:
25. The voltage regulator of claim 24, wherein the digital controller is manufactured on a second IC chip and the digital controller is manufactured on a second separate IC chip. 27. The voltage regulator of claim 24, wherein the digital feedback signal indicates whether the current exceeds a threshold current. 28. The current sensor generates a plurality of digital feedback signals, each signal indicating whether the current has exceeded another threshold current.
28. The voltage regulator of claim 27. 29. The voltage regulator of claim 27, wherein the current sensor generates a plurality of digital feedback signals, each of the signals indicating whether the current has crossed another threshold current. 30. The voltage regulator of claim 27, further comprising a fault protection circuit that disables the digital control signal and opens the switching circuit if the current flowing through the switching circuit exceeds a safety limit greater than the threshold current. . 31. The voltage regulator of claim 30, wherein the fault protection circuit generates a second digital feedback signal received by the digital controller when the current exceeds the safety limit. 32. The voltage regulator of claim 27, wherein said switching circuit includes a first transistor connecting said output terminal to said input terminal and a second transistor connecting said output terminal to ground. 33. A current sensor comprising: a first sensor for generating a first digital feedback signal on a first feedback line indicative of a current flowing through the first transistor; and a current flowing through the second transistor. 33. The voltage regulator of claim 32, including a second sensor that generates a second digital feedback signal on a second feedback line that represents a second feedback signal. 34. The first and second feedback lines are connected to a third feedback line connected to the digital controller. 34. The voltage regulator of claim 33, wherein the digital controller includes logic to determine which transistor is represented by the signal on the third feedback line. 35. The voltage regulator of claim 32, further comprising an interpreter located on the slave that receives the digital control signal and converts the digital control signal into a command to switch the first and second transistors. . 36. The digital control signal generated by the digital controller includes a first control signal on a first control line and a second control signal on a second control line, the interpreter comprising: The first control signal is converted into a command to open the first transistor and close the second transistor, and the second control signal is transmitted to the second transistor when the first transistor is closed. 36. The voltage regulator of claim 35, converting to a second instruction to open. 37. The digital control signal generated by the digital controller includes a third control signal on a third control line, and the interpreter transmits a third control signal to the first and second control lines. 37. The voltage regulator of claim 36, which translates into a command to open a transistor. 38. The interpreter translates a third control signal into an instruction to open the first and second transistors when the second transistor closes and the current drops below zero. 37 voltage regulators. 39. The voltage regulator of claim 24, further comprising a state sensor for generating a digital state signal indicative of said state of said switching regulator received by said digital controller. 40. The voltage regulator of claim 24, wherein the slave includes an interpreter that receives the digital control signal and converts the digital control signal into a command to switch the switching circuit. 41. A voltage regulator having an input terminal connected to an input voltage source and an output terminal connected to a load, comprising: a) a plurality of slaves each comprising: I) responsive to a digital control signal. A switching circuit that intermittently connects the input terminal and the output terminal; ii) a filter that provides a substantially DC output voltage to the output terminal; iii) a current sensor that generates a digital feedback signal representing a current flowing through the switching circuit. B) a digital controller for receiving and using the digital feedback signals from the plurality of slaves to generate a plurality of digital control signals, wherein the digital controller maintains the output voltage at the output terminal at a substantially constant level; A voltage regulator, comprising: the digital controller configured to: 42. A method of operating a voltage regulator having an input terminal connected to an input voltage source and an output terminal connected to a load, comprising: switching the input terminal and the output terminal in response to a digital control signal. Intermittently connecting in a circuit; filtering the output of the switching circuit to provide a substantially DC output voltage at the output terminal; a digital feedback signal representing a current flowing through the switching circuit having a current sensor. Generating and receiving the digital feedback signal from the slave in a digital controller to generate the digital control signal, wherein the digital controller substantially reduces the output voltage at the output terminal. At a constant level Method comprising; configured in order. 43. A voltage regulator having an input terminal connected to an input voltage source and an output terminal connected to a load: a switching device intermittently connecting the input terminal and the output terminal in response to a control signal. A filter for providing a substantially DC output voltage at the output terminal; and a digital controller operating at a clock frequency f _clock that is significantly faster than a desired switching frequency f _switch of the switching circuit, wherein the digital controller comprises: Receiving, at each clock cycle, a first digital feedback signal derived from an output voltage at the output terminal and a second digital feedback signal derived from a current flowing through the switching circuit, wherein the output voltage is substantially constant; The switching circuit is maintained at a level of Generating the control signal for controlling. 44. The voltage regulator of claim 43, further comprising a current sensor that generates the first digital feedback signal. 45. The voltage regulator of claim 44, further comprising a voltage sensor that generates the second digital feedback signal. 46. The voltage regulator according to claim 45, wherein said voltage sensor includes an A / D converter. 47. The voltage regulator of claim 46, wherein said voltage sensor further comprises a voltage sampling circuit. 48. The voltage regulator of claim 45, wherein said switching circuit, filter and current sensor are manufactured on a first IC chip, and said digital controller and voltage sensor are manufactured on a second different IC chip. 49. The switching circuit, the filter and the current sensor are manufactured on a first IC chip, the voltage sensor is manufactured on a second IC chip, and the digital controller is manufactured on a third IC chip. 46. The voltage regulator of claim 45 assembled. 50. The voltage regulator of claim 43, wherein said first digital feedback signal is representative of said difference between said output voltage and a nominal voltage. 51. The voltage regulator of claim 43, wherein the first digital feedback signal is representative of the difference between the output voltage in a current clock cycle and an output voltage in a previous clock cycle. 52. The voltage regulator of claim 43, wherein the digital controller receives a third digital feedback signal derived from an output voltage at the output terminal every clock cycle. 53. The first digital feedback signal is equal to the difference between the output voltage and a nominal voltage, and the third digital feedback signal is different from the output voltage in a current clock cycle and the output voltage in a previous clock cycle. 53. The voltage regulator of claim 52, wherein said voltage regulator equals said difference in output voltage. 54. The voltage regulator of claim 43, wherein said first digital feedback signal is said output voltage. 55. A digital controller connected to the output terminal, the controller including a sampling circuit for capturing a difference between the output voltage and a reference voltage,
44. The voltage regulator according to claim 43, wherein said digital controller further includes an A / D converter for converting said charge held by said sampling circuit into a digital signal. 56. The voltage regulator of claim 32, wherein said reference voltage is grounded. 57. The voltage regulator of claim 32, wherein said reference voltage is a nominal voltage. 58. The voltage regulator of claim 32, wherein said reference voltage is an output voltage from a previous clock cycle. 59. The system further comprises a plurality of switching circuits for intermittently connecting the input terminal and the output terminal, wherein the digital controller provides a second digital feedback signal to each switching circuit every clock cycle. And generating a control signal for the switching circuit, wherein each second digital feedback signal is derived from a current flowing through an associated switching circuit.
44. The voltage regulator of claim 43. 60. A method of operating a voltage regulator having an input terminal connected to an input voltage source and an output terminal connected to a load, the method comprising: switching the input terminal and the output terminal in response to a control signal. Intermittently connecting; filtering the output of the switching circuit to provide a substantially DC output voltage at the output terminal; at a clock frequency f _clock which is significantly faster than the desired switching frequency f _{switch of the} switching circuit. Operating a digital controller; receiving a first digital feedback signal derived from an output voltage at the output terminal at each clock cycle in the digital controller; Receiving a second digital feedback signal derived from a flowing current; and generating the control signal by the digital controller to control the switching circuit such that the output voltage is maintained at a substantially constant level. A method comprising the steps of: 61. An input terminal connected to an input voltage source, an output terminal connected to a load, a switching circuit connecting the input terminal to an intermediate terminal, and an inductor for generating a substantially DC voltage at the output terminal. Operating a voltage regulator having a filter comprising: storing an initial estimated current representing the current flowing through the inductor; replacing the initial estimated current based on the state of the switching circuit with a new estimated current. Adjusting the total output current through the inductor to maintain the output voltage at the output terminal substantially constant; and the total current flowing through the inductor being the total desired output. The switch based on the estimated current and the total desired output current to be approximately equal to the current. Comprising the step of controlling the ring circuit. 62. The switching circuit includes a first transistor that intermittently connects the input terminal to the intermediate terminal and a second transistor that intermittently connects the intermediate terminal to ground. the method of. 63. The method of claim 62, wherein the adjusting step comprises adding an increasing current to the initial estimated current when the first transistor is closed. 64. The method of claim 6, wherein the adjusting step comprises subtracting a reduced current from the initial estimated current when the second transistor is closed.
Method 2. 65. The method of claim 61, wherein said switching circuit includes a first transistor intermittently connecting said input terminal to said intermediate terminal, and a diode intermittently connecting said intermediate terminal to ground. 66. The method of claim 61, wherein said storing and adjusting steps occur at a clock frequency. 67. The method of claim 66, wherein said clock frequency is significantly faster than a desired switching frequency of said switching circuit. 68. The adjusting step includes adding an increasing current to the initial estimated current when the intermediate terminal is connected to the input terminal, and adding a decreasing current when the intermediate terminal is connected to the ground. 67. Subtract from the initial estimated current.
the method of. 69. The increased current is based on an input voltage at the input terminal, an output voltage at the output terminal, an inductance of an inductor disposed between the switching circuit and the output terminal, and the clock frequency. Claim 6 selected
Method 8. Wherein 70, wherein said increased _{current, (V in -V out) /} L × calculated from f _clock, wherein, V _in is the input voltage, V _out is the output voltage, L is the inductance, and f _70. The method of claim 69, wherein clock represents the clock frequency. 71. The reduced current is selected based on an output voltage at the output terminal, an inductance of an inductor disposed between the intermediate terminal and the output terminal, and the clock frequency. the method of. 72. The reduced current is V_out/ L × f_clockWhere V _out Is the output voltage, L is the inductance, and f_clockIs the clock
72. The method of claim 71, representing frequency. 73. The method of claim 68, wherein said increasing and decreasing currents are based on a nominal value. 74. The method of claim 68, wherein said increasing and decreasing currents are dynamically adjusted. 75. The method of claim 61, further comprising: generating a feedback signal representing the actual current flowing through the switching circuit; and correcting the estimated current based on the feedback signal. 76. The method of claim 75, wherein said storing and adjusting steps occur at a higher frequency than said correcting step. 77. The method of claim 76, wherein said storing and adjusting steps are performed in a series of clock cycles, and wherein said correcting steps occur within a number of said clock cycles. 78. The method of claim 61, wherein the feedback indicates whether the actual current is above or below a threshold current. 79. When the intermediate terminal is connected to the input terminal, if the addition of the increased current causes the estimated current to exceed the threshold current,
79. The method of claim 78, further comprising, if the feedback signal indicates that the actual current is less than the threshold current, holding the estimated current near the threshold current. 80. When the intermediate terminal is connected to ground, when the subtraction of the increased current causes the estimated current to be less than the threshold current, and when the actual current exceeds the threshold current. 79. The method of claim 78, further comprising maintaining the estimated current near the threshold current when the feedback signal indicates. 81. When the switching circuit is closed, when the estimated current is less than the threshold current, and when the feedback signal indicates that the actual current exceeds the threshold current, the estimated current is reduced to the threshold. 79. The method of claim 78, further comprising setting equal to a current. 82. When the output terminal is grounded, when the estimated current is greater than the threshold current, and when the feedback signal indicates that the actual current is less than the threshold current, the estimated current 78. The method of claim 78, further comprising: setting the threshold current equal to the threshold current. 83. A delay time generated by the switching time required to activate the in-sensor comparator that generates the feedback signal, and a delay time required for the feedback signal to travel from the sensor to a controller that controls the switching circuit. 69. The method of claim 68, further comprising adjusting the estimated current for the propagation time. 84. The method of claim 68, wherein said adjusting is based on said increment, said clock cycle and said switching frequency. 85. The method of claim 68, wherein said adjusting is based on said decrement, said clock cycle and said switching frequency. 86. A method for estimating a current flowing through an inductor of a voltage regulator, wherein the voltage regulator includes a switching circuit for intermittently connecting an output terminal to an input terminal, the method comprising: Storing an initial estimated current representing said current;
And adjusting the initial estimated current based on the state of the switching circuit to generate a new estimated current. 87. A method of evaluating a current flowing through an inductor of a voltage regulator, the voltage regulator including a switching circuit intermittently connecting an output terminal to an input terminal, the method comprising: Storing an initial estimated current representing the following: if the output terminal is connected to the input terminal, adding an increasing current to the initial estimated current; and if the output terminal is grounded, Subtracting the reduced current from the initial estimated current. 88. A voltage regulator having an input terminal connected to an input voltage source and an output terminal connected to a load, comprising: a) intermittently connecting the input terminal and the output terminal in response to a control signal. B) a filter for providing a substantially DC output voltage at said output terminal, said filter comprising an inductor; and c) a digital controller; said digital controller comprising: i) storing an initial estimated current representing the current flowing through the inductor; ii) adjusting the initial estimated current to produce a new estimated current based on the state of the switching circuit; iii). Determining the total desired output current through the inductor that maintains the output voltage substantially constant; and iv) keeping the output voltage substantially constant. In order to maintain the bell, it generates the control signal based on the adjusted estimated current and the total desired output current to control said switching circuit; voltage regulators. 89. A voltage regulator having an input terminal connected to an input voltage source, an output terminal connected to a load, and at least one switching circuit intermittently connecting the input terminal and the output terminal. Determining an estimated current for each of the at least one switching circuit, wherein each estimated current represents a current flowing through an inductor of an associated switching circuit; substantially determining an output voltage at the output terminal. Calculating a desired total output current flowing through the inductor to maintain a constant level; calculating an upper current and a lower current; wherein the average of the upper current and the lower current is individually calculated for one of the inductors. And for one or more of said switching circuits, Connecting the input terminal to the output terminal when the estimated current is lower than the lower limit current; and connecting the output terminal to the ground when the estimated current exceeds the upper limit current. A method comprising: 90. The method of claim 89, wherein said voltage regulator includes a plurality of switching circuits. 91. The method of claim 90, further comprising selecting one of said plurality of switching circuits as a reference circuit, wherein said remaining switching circuits are non-reference circuits. 92. The method of claim 91, further comprising determining a desired phase offset for each non-reference switching circuit. 93. The reference circuit connects the input terminal and the output terminal when the estimated current falls below the lower limit current, and connects the output terminal to ground when the estimated current exceeds the upper limit current. 94. The method of claim 92, wherein 94. The method of claim 92, further comprising calculating a plurality of upper currents and a plurality of lower currents, wherein there is one upper current and one lower current associated with each non-reference circuit. 95. Each non-reference circuit connects the input terminal and the output terminal when an associated estimated current drops below an associated lower current limit, and wherein the associated estimated current exceeds an associated upper limit current. 95. The method of claim 94, wherein said output terminal is grounded. 96. The method of claim 95, wherein said plurality of upper and lower current limits are derived from a desired switching frequency and said desired phase offset. 97. The method of claim 95, further comprising measuring the actual phase offset between the reference circuit and the non-reference circuit. 98. The method of claim 95, wherein said difference between said upper and lower current limits is adjusted by said difference between said actual phase offset and said desired phase offset. 99. The method of claim 92, wherein each non-reference circuit connects the input terminal and the output terminal at the desired phase offset after the reference circuit connects the input terminal and the output terminal. 100. The method of claim 99, wherein each non-reference circuit connects the output terminal to ground if the associated estimated current exceeds the associated upper limit current. 101. The method of claim 92, wherein each non-reference circuit grounds the output terminal at the desired phase offset after the reference circuit grounds the output terminal. 102. The method of claim 101, wherein each non-reference circuit connects the input terminal and the output terminal if the associated estimated current is below the associated lower limit current. 103. A method of operating a voltage regulator having an input terminal connected to an input voltage source, an output terminal connected to a load, and at least one switching circuit intermittently connecting the input terminal and the output terminal. Determining an estimated current for each of the at least one switching circuit, each estimated current representing a current flowing through an inductor associated with each switching circuit; and substantially reducing an output voltage at the output terminal. Calculating a desired total output current through the inductor to maintain a constant level; calculating an individual desired current for one or more of the switching circuits; calculating the estimated current for one or more of the switching circuits. The current flowing through the switching circuit is compared with each of the desired currents. As but substantially equal to the desired current, the method comprising the step of switching the switching circuit. 104. The voltage regulator includes a plurality of switching circuits.
104. The method of claim 103. 105. The method of claim 104, further comprising determining a desired phase offset for each switching circuit. 106. The method of claim 105, further comprising determining a phantom condition for at least one of said switching circuits. 107. The method of claim 106, further comprising selecting one of said plurality of switching circuits as a reference circuit, wherein said remaining switching circuits are non-reference circuits. 108. The method of claim 107, wherein a phantom condition is determined for each non-reference circuit. 109. The method of claim 107, further comprising calculating upper and lower current limits for said reference circuit. 110. When the estimated current falls below the lower limit current, the reference circuit connects the input terminal to the output terminal; and when the estimated current exceeds the upper limit current, the reference circuit 110. The method of claim 109, further comprising connecting the output terminal to ground. 111. The method of claim 110, wherein the phantom state of the non-reference circuit is derived from the state of the reference circuit and the desired phase offset. 112. The method of claim 106, wherein the desired current is calculated for each switching circuit. 113. The method of claim 112, wherein a phantom condition is determined for each switching circuit. 114. The method of claim 112, wherein said phantom state of said switching circuit is based on a clock signal and said desired phase offset. 115. The step of determining a desired current comprises storing an initial desired current for the at least one switching circuit based on the phantom state to generate a new desired current, and 107. The method of claim 106, comprising adjusting 116. If the step of adjusting the initial desired current is such that the phantom state indicates that the output terminal is connected to the input terminal, an increasing current is added to the initial desired current; and 115. If the phantom condition indicates that the output terminal is connected to ground, subtracting a reduced current from the initial estimated current. 117. The method of claim 106, further comprising: switching to the at least one switching circuit if the estimated current crosses the desired current and the state of the reference circuit is not the same as the phantom state. Method. 118. The method of claim 11, wherein if the estimated current exceeds the desired current, the switching comprises grounding the output terminal.
Method 7. 119. The method of claim 117, wherein said switching comprises connecting said output terminal and said input terminal if said estimated current falls below said desired current. 120. When the estimated current falls below the lower limit current, the at least one switching circuit connects the input terminal to the output terminal;
12. The method according to claim 11, further comprising: when the estimated current exceeds the upper limit current, connecting the output terminal to the at least one switching circuit.
Method 7. 121. If the estimated current drops below the desired current due to a first preset margin, the at least one switching circuit connects the input terminal to the output terminal, and the estimated current is the second current. 118. The method of claim 117, further comprising the step of: grounding the output terminal to the at least one switching circuit if the desired current is exceeded by the preset margin. 122. A method for operating a voltage regulator having an input terminal connected to an input voltage source, an output terminal connected to a load, and a plurality of switching circuits intermittently connecting the input terminal and the output terminal. Selecting: one of the plurality of switching circuits as a reference circuit; determining a desired phase offset for the remaining switching circuits; determining an estimated current for each switching circuit; Calculating a desired total output current through the switching circuit that maintains an output voltage at the output terminal at a substantially constant level; representing the current through an inductor associated with the circuit; the desired phase offset and the desired total; In order to substantially achieve the output current, The output terminal to the etching circuit comprises the step of the input terminal or ground connections.