經濟部中央樣準局員工消費合作社印製 f 3 ' A7 B7 五、發明説明（） 發明領域： 本發明與-種半導想製程之動態隨機存取記憶胞 (DRAM)有關，特别是一種具有粗糙化之表面堆疊於溝渠 式之動態隨機存取記憶胞t之電容製作方法。 發明背景： 動態隨機存取記憶體（DRAM)具有許多之記憶胞 (mem〇ry cell)，記憶胞通常由電容器與電晶體所構^用 來儲存一位元（blt)之訊號.，電容之源極與電容之一端連 接’電容之另-端則與參考電位連接，電晶體之源極、 閘極則分别與位元線（bit 1丨11〇與字語線（w〇rd nne)連接 。因此製造DR AM記憶胞包含了電晶體與電容之製程， 藉由電容器與源極區之電性接觸，數位資訊儲存在電容 器並藉金氧丰場效電晶體、位元線（bit丨ine)、字語線 (word ! i ne)陣列來取得電容器之數位資料。 爲了符合高密度之積體電路設計趨勢，動態隨機存 取記憶體（DRAM)製程之尺寸必須降至次微米，因爲元件 之综小化而DRAM中之電容也相對的減小，故其儲存載 子之性能亦相對的降低。因此坪统的電容則不適合應用 於高密度之DRAM製造，爲使電容儲存能力不會降低之 電容製造方法與結構是電容製程努力之一個方向。假使 繼續使用傳統之平坦式電容器，那蘑將會遭遇到如上述 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） (請先聞讀背面之注意事項再填寫本頁) -裝-- 訂 449913 經濟部中央標孪局負工消费合作杜印製Printed by the Consumers 'Cooperative of the Central Sample Bureau of the Ministry of Economic Affairs f 3' A7 B7 V. Description of the invention () Field of the invention: The present invention relates to a dynamic random access memory cell (DRAM) of a semi-conductive process, and in particular, it has a Capacitor manufacturing method for roughened surface stacked in trench type dynamic random access memory cell t. Background of the invention: Dynamic random access memory (DRAM) has many memory cells. Memory cells are usually composed of capacitors and transistors. They are used to store a single bit (blt) signal. One end of the source is connected to the capacitor. The other end of the capacitor is connected to the reference potential. The source and gate of the transistor are connected to the bit line (bit 1 丨 110) and the word line (word nne), respectively. Therefore, the manufacture of DR AM memory cells includes the process of transistors and capacitors. Through the electrical contact between the capacitor and the source region, digital information is stored in the capacitor and borrowed from the field-effect transistor and bit line. ), Word line (word! In) array to obtain the digital data of the capacitor. In order to meet the high-density integrated circuit design trend, the size of the dynamic random access memory (DRAM) process must be reduced to sub-micron because of the component In general, the capacitance in DRAM is relatively reduced, so the performance of storage carriers is also relatively reduced. Therefore, the capacitors of Ping Tong are not suitable for high-density DRAM manufacturing, so that the storage capacity of capacitors will not be reduced. Capacitor manufacturer Structure is one of the efforts in the capacitor manufacturing process. If traditional flat capacitors continue to be used, the mushroom will encounter the Chinese paper standard (CNS) Λ4 specification (210X297 mm) as described above. (Please read the back first (Please note this page before filling out this page)-Assemble-Order 449913 Printed by the Central Ministry of Economic Affairs
A7 B7五、發明説明（） 之電容儲存能力降低之問題以及電容信賴度降低之問題 ’例如電容器在讀取資料時受雜質之影響如α fe子所產 生之軟記錯（soft errors)將大大提高，並且“再補充 (refresh)”之頻率增加。 · 爲了解決上述之問題，電容朝向增加電容表面積之 方向發展。囡此’發展了溝渠式電容，如MA 0.6 μηι2 2 56Mb Trench DRAM Ceil With Self Aligned BuriEd STrap (BEST), L. Nesbit et al., 1 993, IEEE, IEDM 93-627”。然而，此種方法無法製作具有較高之深寬比 (aspect ratio)之深溝渠電容，以應用於高密度之dram 〇 溝渠式電容另外一個重要之議題爲漏電流之問題 。隨著溝渠之尺寸縮小至次微米，溝渠間之抵穿漏電 Λ 流（punch through leakage)變成了溝渠式電容中一項重 要之問題。其他之漏電流，諸如記憶胞間的表面通道 漏電流（surface channel leakage between cells)，閘極 產生之漏電流（gate-induced diode leakage)、溝渠侧壁 漏電流（trench side wall diode leakage)也因爲尺寸之 縮小而產生❶囡此如何防止溝渠式電容之漏電流在製 作電容時是一重要議題，文獻中也有_相關議題之探討 ，請參閲 ’’Scalability of A Trench Capacitor Cell For 64 Mbit DRAM, B. W. Shen, et al., 1 989, IEEE, IEDM 1*'--I --'^衣------—,?T {請先閱讀背面之注意事項再填寫太頁) 本紙張尺度適用中國國家標準（CNS ) Λ4规格（210X297公釐） 449913 A 7 B7 五，發明説明（） 89-27，、 此外，在文獻中亦發現複晶發可以利用澄氧化以 及溼蝕刻製程而將複晶矽表面1粗糙化，此方式可以類 著地增加電容.電極之表面積，請參閲文獻 ^Thin Nitride Films on Textured Polysilicon to Increa se Multimegabit DRAM Cell Charge Capacitor, PIERR E C. FAZAN et al_，199Q，IEEE”。本發明也利用將離 子擴散進入基板之方法，此方法由下列之文獻所發表 ’’Analysis of Polysilicon Diffusion Sources, V. Probst ，.J. Electrochem, Soc. Solid State Science and Techn ology，Vol. 135，No. 3，p_. 671”。 發明目的及概述： ' 本發明之目的爲一種動'態隨機存取記憶體（DRAM)之 形成方珐。 本發明之另一目的爲提供一種溝渠式動態隨機存取 記憶體以增加電容之表面積並且提昇動態隨機存取記憶 胞性能之方法。 Μ濟部中央標隼局員工消费合作社印製A7 B7 V. Description of the invention (capacity storage capacity reduction problem and capacitance reliability reduction problem) For example, capacitors are affected by impurities when reading data, such as soft errors generated by α fe Increases and the frequency of "refresh" increases. In order to solve the above problems, the capacitor is developed in the direction of increasing the surface area of the capacitor. Here's the development of trench capacitors, such as MA 0.6 μηι2 2 56Mb Trench DRAM Ceil With Self Aligned BuriEd STrap (BEST), L. Nesbit et al., 1 993, IEEE, IEDM 93-627 ". However, this method It is not possible to make deep trench capacitors with a high aspect ratio, which is applied to high density dram trench capacitors. Another important issue is the problem of leakage current. As the size of trenches is reduced to sub-microns, Punch through leakage between trenches becomes an important issue in trench capacitors. Other leakage currents, such as surface channel leakage between cells, are generated by the gate. Gate-induced diode leakage and trench side wall diode leakage are also generated due to the reduction in size. How to prevent the leakage current of trench capacitors is an important issue when making capacitors. There are also _ related issues in the literature, please refer to `` Scalability of A Trench Capacitor Cell For 64 Mbit DRAM, BW Shen, et al., 1 989, IEEE, I EDM 1 * '-I-' ^ 衣 -------- ,? T {Please read the precautions on the back before filling in the page) The paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297) (Centi) 449913 A 7 B7 V. Description of the invention () 89-27, In addition, it is also found in the literature that the polycrystalline hair can be roughened by using the oxidation and wet etching process. This method can be similar Ground to increase capacitance. The surface area of the electrode, please refer to the document ^ Thin Nitride Films on Textured Polysilicon to Increa se Multimegabit DRAM Cell Charge Capacitor, PIERR E C. FAZAN et al_, 199Q, IEEE ". The present invention also utilizes a method of diffusing ions into a substrate. This method is published by `` Analysis of Polysilicon Diffusion Sources, V. Probst, '' J. Electrochem, Soc. Solid State Science and Technology, Vol. 135, No. 3, p. 671 ". Purpose and summary of the invention: 'The purpose of the present invention is to form a dynamic SRAM random access memory (DRAM). Another object of the present invention is to provide a channel-type dynamic random access. A method of accessing memory to increase the surface area of capacitors and improve the performance of dynamic random access memory cells.
Hi· ^^^1 Til I 1^1 . 士 I _ I HI ^^^1 ill 一eJ (請先閱讀背面之注意事項再填寫本頁) 本發明利用矽做爲基板，一二氧化声層形成於基板 之上做爲墊氧化層，氮化矽層接蓍沈積於上述之二氧化 矽層之上。以微影製程定義溝渠之區域，然後以触刻方 本紙張尺度適用中國國家標準（CNS ) Α4規格（2Ι0Χ297公釐） “99 1 3 經濟部中央榡準局員工消费合作.社印製 A7 ______B7 _ 五、發明说明（） 式將矽基板蝕刻形成溝渠於基板之中。完成溝渠之後則 將光阻去除。摻雜之複晶矽層形成於氮化矽層之上以及 沿著溝渠之表面之上沈積.然後，—粗糙化製程 (texturing pr〇cess)將複晶矽之表面粗糙化。利用澄氧化 製程於溫度約爲650至丨〇〇〇度C將複晶矽轉變成表面粗糙 化之複晶矽層。同時形成—氧化層於粗糙化之複晶矽層 之上。複晶矽層中之離子也因氧化而擴散連入基板之中 ’囡此形成離子摻雜區域環繞溝渠之四周。隨後，利用 氫孰酸將氧化層去除。利’用非等向性蝕刻將粗糙化之複 晶矽層蝕刻，殘留之粗糙化之複晶矽將附著於溝渠之側 •之上0以大角度斜向没極離子植人方法 (large ang丨e titled drain ; LATID)施以斜向離子植入摻雜 離子進入基板之中以形成汲極，沿著上述之結構表面沈 積一介電薄膜做爲電容之介電層。然後，—導電層形成 於上述之電容介電薄膜之上以及回塡進入溝渠之中用以 做爲電容之第二電極。最後，製作電晶體於基板之上且 雜由離子摻雜區域與電容相連。 凰_^_簡簞説昍： 第一圖爲本發明之形成溝渠於基板中之截面圖。 弟一'圖爲本發明之形成複晶梦層於溝渠中之截面圖。 第三圖爲本發明之圖案化複晶矽層之截面圖。 第四圖爲本發明之去除氧化層之截面圖。 第五囷爲本發明將触刻複晶石夕之截面圖。 弟、圖爲本發明施以離子植入之截面圖。 本紙^尺度埼用中國國家標準 S ) A4規格（210X297公釐） I* I 11一 —n - - - -iti衣- I !ϋ - II ,ιτ (婧先閱讀背面之注意事項再填寫本頁) 4 49913 A7 B7 經濟部中央標隼局員工消費合作杜印裝 五、發明説明（） 第七圖爲本發明之形成電容介電層與導電層之截面圖。 第八圖爲本發明之形成電晶體之截面圖。 發明詳細説明： . 本發明所要揭示的爲利用增加表面積方式以提昇動 態隨機存取記憶體性能之方法，另外本發明利用複晶矽 作爲離子擴散源，本發明形成粗糙之溝渠表面結構以大 量增加電容表面積來提异童容之特性，本發明之方法將 於下述之。 . 參閱第一圖，一晶向爲< 100>之p型單晶矽做爲基 板2，接著一二氧化矽層4以熱氧化法形成於基板2之上做 爲墊氧化層，氮化矽層6接著沈積於上迷之二氧化矽層4 之上。接著’以微影製程形成一光阻於氮化矽雇6之上， 光阻曝露將用以製作場氡化層之區域，以蝕刻製程將未 被光阻遮蓋之區域蝕刻至基板2表面，然後以蝕刻方式將 矽基板2蝕刻形成至少一個之溝渠8，以較佳實施例而言 ，此蝕刻步驟爲利用非等向性活性離子蝕刻製二 (reactive ion etch; RIE)將上述之膜層蝕刻’此步驟所使 用蝕刻複晶矽之蝕刻劑爲sic丨4 /Cl2、Bcl3 /Cb、 /〇2' ΗΒΓ/〇2' SF6或SF6D完成溝渠\之後則將 光阻去除。 如第二圖所示，摻雜之複晶矽層】〇形成於氮化矽層6 本纸浪尺度適用中g國家轉（CNS ) M規格（別乂加公瘦 -----Γ I -----•裝-*------訂 {請先閱讀背面之注意事項再填寫本頁) 4499 1 3 經濟部中央嘌準局員工消费合作杜印裝 A 7 B7 五、發明説明（） 之上以及沿著溝渠8之表面之上沈積。例如，此複晶矽層 1 0可以利用P H3作爲離子源摻雜磷離子於複晶矽層1 〇之 中。複晶矽層10之厚度约爲200至1 500埃，參閲第三圖， 然後’ 一圖案化製程（texturing process)將複晶石夕10之表 面于以粗糙化。以一最佳實施例而言，利用溼氧化製程 於溫度約爲650至1 〇〇〇度c，此步驟可以增加複晶矽晶界 之氧化程度’因爲晶界之氧化速率大於晶粒本身。因此 複晶矽1 0將轉變成表面粗糙化之複晶矽層1 〇a。同時，一 氧化層1 2由於氧化製程而形成於粗糙化之複晶矽層i 0a之 上。 · 上述之提供溼氧化製程之溫度亦造成在複晶矽層j 0 中之離子擴散進入基板2之中，因此形成離子摻雜區域14 環繞溝渠8之四周。參閲第四圖，隨後，利用氫氟酸將氧 化層12去除’形成粗糙化之複晶矽層i〇a於溝渠8之表面 〇 « 參閲第五圖，利用非等向性蝕刻將粗糙化之複晶矽 層1 〇a触刻，蝕刻完成之後，氮化矽層6以及溝渠8之底部 將被曝露’殘留之粗糙化之複晶矽1 〇a將附著於溝渠8之 側莹之上。 參閲弟六圓，以最少兩個相對於基板2表面之傾斜角 施以斜向離子植入用以摻雜離子（例如坤離子）進入基板2 之中以形成没極丨6，此没極16位於上述離子择雜區域14 本紙張尺度適用巾國國家椟$ (CNS) M規格（2]0><297公楚） tr-ϊ* In I— 1^1 .^1^1 - I 1 «. I - s. - (請先閲讀背面之注意事項再填寫本頁) 4 499 1 3 A 7 [------------- 五、發明説明（） 之上部。此步驟可以使用稱爲大角度斜向汲極離子植入 方珐完成（large angle titled drain ; LATID)。上述之離子 摻雜區域1 4與粗糙化之複晶矽層i 〇 a將用以作爲溝渠式電 容之第一電極。此種溝渠式電容具有粗糙化之複晶矽層 10a堆要於溝渠8之表面’因此可以稱做RST(rugged stacked trench)電容 ° 如第七圖所示’下一步驟爲沿著上述第一電極以及 氮化矽層6之結構表面沈積一介電薄膜18做爲電容之介電 層’ 一般此介電層22可以利用O/N、0/N/0之複合薄膜或 是利用高介電之薄膜如Ta2Os、BST、PZT。然後，一導 電層20形成於上述之電容介電薄膜18之上以及回塡進入 溝渠8之中用以做爲電容之第二電極，利用掺雜複晶矽 (doped polysilicon) ' 同步摻雜複晶矽（in_ situ doped p〇lySilicon)、銅、鋁、鈦、鎢、白金或合金 等可以作爲上述之第二電極‘。形成位於溝渠8間氮化矽層 6上導電層20作爲記憶胞之電極板2〇。將未被電極板2〇遮 蓋之氮化矽層6以及氧化矽層4去除以曝露基板2。參閲第 八圖’以習知之技術製作電晶體22於基板2之上且藉由離 子掺雜區域14與電容相連。 經濟部中央標隼局員工消費合作社印製 ΡΓ-1 fl 11 -- n n 'Hoi. I I I ---,.—— 0¾ 、-0 (請先閱讀背面之注意事項再填寫本頁) 本發明之電容將大量增加.電容之表面積，其次本發 明利用粗糙化之複晶矽層形成起伏表面之溝渠式電容結 構’囡此本發明將提昇電容之儲存能力。本發明以較佳 實施例説明如上，而熟悉此領域技藝者，在不脱離本發 本紙張尺纽财_ 449913 五、發明説明（）明之精神範圍内，當可作些許更動潤飾，其專利保護範 圍更當視後附之申請專利範圍及其等同領域而定。 t ."衣 n 訂 ί (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作杜印裝 9 本紙張尺度適用中國國家標準（CNS ) A4規格（210Χ297公釐）Hi · ^^^ 1 Til I 1 ^ 1. 士 I _ I HI ^^^ 1 ill one eJ (please read the precautions on the back before filling this page) The present invention uses silicon as the substrate and a sound oxide layer It is formed on the substrate as a pad oxide layer, and a silicon nitride layer is successively deposited on the above silicon dioxide layer. The area of the ditch is defined by the lithography process, and then the Chinese national standard (CNS) A4 specification (2Ι0 × 297 mm) is applied to the printed paper standard. "99 1 3 Employees' cooperation cooperation of the Central Bureau of the Ministry of Economic Affairs. Printed by A7 ______B7 _ 5. Description of the invention () The silicon substrate is etched to form a trench in the substrate. After the trench is completed, the photoresist is removed. The doped polycrystalline silicon layer is formed on the silicon nitride layer and along the surface of the trench. On the deposition. Then,-the roughening process (texturing prOcess) roughens the surface of the polycrystalline silicon. Using a clear oxidation process at a temperature of about 650 to 1000 ° C to convert the polycrystalline silicon into a surface roughened Multicrystalline silicon layer. Simultaneously formed-the oxide layer is on the roughened polycrystalline silicon layer. The ions in the polycrystalline silicon layer are also diffused into the substrate due to oxidation. 'This forms an ion doped region surrounding the trench. Then, the oxide layer is removed by using hydrofluoric acid. The roughened polycrystalline silicon layer is etched by anisotropic etching, and the remaining roughened polycrystalline silicon will adhere to the side of the trench. Oblique angle The implantation method (large ang 丨 e titled drain; LATID) uses oblique ion implantation to dope ions into the substrate to form a drain, and a dielectric film is deposited along the surface of the structure as the dielectric layer of the capacitor. Then, a conductive layer is formed on the above-mentioned capacitive dielectric film and is re-entered into the trench to be used as the second electrode of the capacitor. Finally, a transistor is fabricated on the substrate and doped with an ion-doped region and The capacitors are connected. The first figure is a cross-sectional view of the trench formed in the substrate of the present invention. The first one is a cross-sectional view of the polycrystalline dream layer formed in the trench of the present invention. The figure is a cross-sectional view of a patterned polycrystalline silicon layer of the present invention. The fourth figure is a cross-sectional view of removing the oxide layer of the present invention. The fifth figure is a cross-sectional view of the present invention which will be etched with polycrystalline stone. The present invention is a cross-sectional view of ion implantation. The paper ^ dimensions (Chinese national standard S) A4 size (210X297 mm) I * I 11-n----iti clothing-I! Ϋ-II, ιτ ( Jing first read the notes on the back before filling out this page) 4 49913 A7 B7 Standards Bureau employee consumer cooperation Du Yinzhuang 5. Description of the invention (7) The seventh diagram is a cross-sectional view of the capacitor dielectric layer and the conductive layer of the present invention. The eighth diagram is a cross-section view of the transistor of the invention. Details of the invention Explanation: The method disclosed by the present invention is to improve the performance of dynamic random access memory by increasing the surface area. In addition, the present invention uses polycrystalline silicon as an ion diffusion source. The present invention forms a rough trench surface structure to greatly increase the capacitance surface area. To improve the characteristics of different children, the method of the present invention will be described as follows. Referring to the first figure, a p-type single crystal silicon with a crystal orientation of < 100 > is used as the substrate 2 and then a silicon dioxide layer 4 A thermal oxidation method is used to form a pad oxide layer on the substrate 2. A silicon nitride layer 6 is then deposited on the silicon dioxide layer 4. Then, a photoresist is formed on the silicon nitride film 6 by a lithography process. The photoresist exposes the area to be used to make the field-induced layer, and the area not covered by the photoresist is etched to the surface of the substrate 2 by an etching process. Then, the silicon substrate 2 is etched to form at least one trench 8 by an etching method. In a preferred embodiment, the etching step is to use reactive anion etch (RIE) to form the above-mentioned film layer. Etching 'The etchant used to etch the polycrystalline silicon used in this step is sic 丨 4 / Cl2, Bcl3 / Cb, / 〇2' ΗΒΓ / 〇2 'SF6 or SF6D, and then the photoresist is removed. As shown in the second figure, the doped polycrystalline silicon layer] 0 is formed on the silicon nitride layer. 6 This paper is suitable for China National Standards (CNS) M specifications (do n’t add thinness to Γ I.) ----- • Equipment-* ------ Order {Please read the notes on the back before filling out this page) 4499 1 3 Consumption cooperation between employees of the Central Purification Bureau of the Ministry of Economic Affairs Du printed A 7 B7 V. Invention Note () and above the surface along the trench 8. For example, the polycrystalline silicon layer 10 can use Ph 3 as an ion source to dope phosphorus ions into the polycrystalline silicon layer 10. The thickness of the polycrystalline silicon layer 10 is about 200 to 1 500 angstroms. Refer to the third figure, and then a texturing process roughens the surface of the polycrystalline silicon layer 10. In a preferred embodiment, the wet oxidation process is used at a temperature of about 650 to 1000 degrees c. This step can increase the degree of oxidation of the polycrystalline silicon grain boundaries' because the oxidation rate of the grain boundaries is greater than that of the crystal grains themselves. Therefore, the polycrystalline silicon 10 will be transformed into a roughened polycrystalline silicon layer 10a. At the same time, an oxide layer 12 is formed on the roughened polycrystalline silicon layer i 0a due to the oxidation process. The above-mentioned temperature for providing the wet oxidation process also causes the ions in the polycrystalline silicon layer j 0 to diffuse into the substrate 2, so that an ion-doped region 14 is formed around the trench 8. Referring to the fourth figure, subsequently, the oxide layer 12 is removed by using hydrofluoric acid to form a roughened polycrystalline silicon layer i0a on the surface of the trench 8. See the fifth figure, using anisotropic etching to roughen The polycrystalline silicon layer 10a is etched. After the etching is completed, the bottom of the silicon nitride layer 6 and the trench 8 will be exposed. The residual roughened polycrystalline silicon 10a will be attached to the side of the trench 8. on. Refer to Di Liuyuan, apply oblique ion implantation at least two inclination angles with respect to the surface of the substrate 2 to dope ions (such as Kun ions) into the substrate 2 to form a pole 丨 6, this pole 16 Located in the above-mentioned ion-selective impurity region. 14 This paper size is applicable to the country 椟 $ (CNS) M specification (2) 0 > < 297 Gongchu. Tr-ϊ * In I— 1 ^ 1. ^ 1 ^ 1-I 1 «. I-s.-(Please read the notes on the back before filling out this page) 4 499 1 3 A 7 [------------- V. Description of the invention () Upper part. This step can be done using a large angle titled drain (LATID) called a large angle oblique drain ion implantation. The above-mentioned ion-doped region 14 and the roughened polycrystalline silicon layer i 0 a will be used as the first electrode of the trench capacitor. This type of trench capacitor has a roughened polycrystalline silicon layer 10a stacked on the surface of trench 8. Therefore, it can be called a RST (rugged stacked trench) capacitor. As shown in the seventh figure, the next step is to follow the first A dielectric film 18 is deposited on the surface of the structure of the electrode and the silicon nitride layer 6 as a dielectric layer of the capacitor. Generally, the dielectric layer 22 can be a composite film of O / N, 0 / N / 0, or a high dielectric film. Thin films such as Ta2Os, BST, PZT. Then, a conductive layer 20 is formed on the above-mentioned capacitive dielectric film 18 and reenters into the trench 8 as a second electrode of the capacitor. The doped polysilicon is used to synchronize the doped polysilicon. In-situ doped silicon, copper, aluminum, titanium, tungsten, platinum or alloy can be used as the second electrode. A conductive layer 20 on the silicon nitride layer 6 between the trenches 8 is formed as an electrode plate 20 of the memory cell. The silicon nitride layer 6 and the silicon oxide layer 4 not covered by the electrode plate 20 are removed to expose the substrate 2. Referring to FIG. 8 ', a transistor 22 is fabricated on the substrate 2 by a conventional technique and connected to the capacitor through an ion doped region 14. Printed by the Consumers 'Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Γ-1 fl 11-nn' Hoi. III ---, .—— 0¾, -0 (Please read the precautions on the back before filling this page) The capacitance will greatly increase. The surface area of the capacitor. Secondly, the present invention uses a roughened polycrystalline silicon layer to form a trench-type capacitor structure with an undulating surface. This invention will increase the storage capacity of the capacitor. The present invention has been described in the preferred embodiment above, and those skilled in the art can make some changes and modifications without departing from the spirit of this paper. 449913 The scope of protection depends more on the scope of the attached patent application and its equivalent. t. " clothing n order ί (please read the precautions on the back before filling out this page) Duty Packing for Employees of the Central Standards Bureau of the Ministry of Economic Affairs 9 This paper size applies to China National Standard (CNS) A4 (210 × 297 mm)