^49892^ 49892
五、發明說明（1) 發明領域 本案有關一種積體電路（以下簡稱1C)封裝，尤其有 關球閘陣列式（BGA )積體電路封裝之改進方案》 發明背景 如圖1所示習用之1C封裝體1，係採用錫球（solder ball)ll連接外部電路或裝置。其因受限於錫球u之高 度’基板12所承載的晶片16 (bottom chip，也就是與踢 球1 1同位於基板1 2的一表面1 21之晶片）必須很薄，但這 樣的薄晶片在製造過程中（pr〇cess)容易破裂，也要多出 背面研磨（back grinding)成本。如要克服上述問題就必 須把錫球（solder ball)加大，以增加錫球的高度，但這 會使得球間距（ball pitch)與基板尺寸必須加大，也就 5個封裝體也隨之並|導致基板成本/封裝成本增 發明說明 為解決習用技藝上述缺點，太安 代習用錫4，而與晶片同裝-種柱形端子取 本案使用柱形端子表面的封裝架構。 點： 、·種曰日片封裝，至少有下列三優 1.柱形端子可以包含—接古p , …而包含-較低於其内層 Material) 供迴銲作業時的彼此自動V. Description of the invention (1) Field of the invention The present invention relates to an integrated circuit (hereinafter referred to as 1C) package, and in particular to an improvement scheme of a ball gate array (BGA) integrated circuit package. The body 1 is connected to an external circuit or device with a solder ball 11. Because it is limited by the height of the solder ball u, the wafer 16 carried on the substrate 12 (bottom chip, that is, the wafer located on the same surface of the substrate 12 as the kicker 11) must be very thin, but such a thin Wafers are prone to cracking during the manufacturing process, which also requires more back grinding costs. In order to overcome the above problems, it is necessary to increase the solder ball to increase the height of the solder ball, but this will make the ball pitch and the size of the substrate must be increased. | Increase the substrate cost / encapsulation cost. In order to solve the above-mentioned shortcomings of conventional technology, Tai'an used tin 4 instead, and was mounted with the chip-a kind of cylindrical terminal. This case uses the packaging structure of the cylindrical terminal surface. Points:, · Semi-Japanese package, there are at least the following three advantages 1. The cylindrical terminal can include-then ancient p, ... and include-lower than its inner Material) for each other automatically during reflow operations
4 4989 2 五、 發明說明（2) 柱 η 齊（sel f - alignment) 效 果。 2. 形 端 子 較 錫 球高 所 以 可 容許 較 厚的 半導 m 元件 ( 例 如 晶 片 ) 裝於 端 子 伸 出 的同 一 面， 卻不 需 如錫' 琛般 加 大 間 距 〇 容 許 本 案 主 要 的 在 於， 提 供 -- 種 嶄新 的 1C封 裝體 ， 其能 較 厚 的 半 導 體 元 件（ 例 如 晶 片 )裝 於 其内 ’卻 不 需力Π 大 半 導 體 元 件 的 載 具 (例 如 基 板 )尺 寸 ，既 免去 半 導體 元 件 背 面 研 磨 成 本 又可 以 顯 著 降 低半 導 I84L 一 m 7C 件太 薄 而易 裂 所 導 致 的 不 良 率 ϊ 卻不 會 增 加 封 裝體 尺 寸0 雖 然 美 國 專 利5468995案也採用柱形端子做為ic封裝 體 的 對 外連接 單 元 j 但其 採 用 柱 形 端子 的 目的 在於 1 應付 封 裝 體 連 接 作 業 ( 例 如連 接 印 刷 線 路板PWB的作業） 所峰 的 熱 應 力（therma1 ly induced S tress) 〇 該案 係針 對 ，内 裝 晶 片 與 外 向 連 接 端 子位 於 基 板 不 同面 的 封裝 體， 而 不涉 及 本 案 容 許 下 側 晶 片 (bottom chi P，也就是 ’與外向連 接 端 子 同 位 於 基 板 之 一表 面 的 晶 片 )厚 度 較大 的發 明 的 也 當 然 無 從 提 供 ，本 案 無 需 研 磨下 側 晶片 背面 卻 仍然 可 以 有 同 樣 尺 寸 封 裝 體的 效 果 更 當然 無 從提 供， 本 案無 需 研 磨 下 側 晶 片 背 面 的成 本 節 省 效 果。 簡 而 言 之 ， 本 案 這種 容 許 較 厚 半導 體 零件 裝於 其 内的 封 裝 體 之 基本 架 構 可 以包 含 * 半 _ 載 具 ( 例 如 —— 基板 、 或 片 物體 或任 何可 以 掛載 導 體 零 件 與 提供 電 連接 之 物 體 ) ，其 包 含一 第一 表 面， 該 第 表 面 包 含 至 少 導 體 連 接 區與 端子 連接 區 ；4 4989 2 V. Description of the invention (2) sel f-alignment effect. 2. The shape of the terminal is higher than the solder ball, so it can allow thicker semi-conducting m components (such as wafers) to be mounted on the same side of the terminal, but it does not need to increase the pitch as tin tin. The main point of this case is to provide -A brand new 1C package, which can be used for thicker semiconductor components (such as wafers), but does not require a large carrier (such as a substrate) size of semiconductor components, which avoids the cost of polishing the backside of semiconductor components It can also significantly reduce the defect rate of the semiconducting I84L-m 7C parts that are too thin and easy to crack. However, it will not increase the package size. 0 Although the US patent 5468995 also uses cylindrical terminals as the external connection unit of the IC package j However, the purpose of using cylindrical terminals is to cope with the peak thermal stress (therma1 ly induced stress) of the package connection operation (such as the connection to the printed circuit board PWB). This case is directed to the internal chip and external connection Packages with terminals on different sides of the substrate do not involve the invention, which allows lower thickness chips (bottom chi P, that is, "wafers on the same surface of the substrate as the outward connection terminals). Of course, the invention cannot be provided. The effect of having the same size package without polishing the back surface of the lower wafer is not provided, and the cost saving effect of polishing the back surface of the lower wafer is not required in this case. In short, the basic architecture of this package, which allows thicker semiconductor components to be contained in it, can include a * semi-_ carrier (for example, a substrate, or a sheet object or any device that can mount conductors and provide electrical connections). Object), which includes a first surface including at least a conductor connection area and a terminal connection area;
第5頁 4_并 “9892 五、發明說明（3) 至少一半導 接區；以及 至少一柱形 連接該半導體零 柱形）之長度大 本案這種容 可以用下列方式 體零件C例如一晶片）附著於該半導體連 —片形載具 至少一半導 至少一柱形 及 一連接系統 到該第一表面的 形端子兩者之間 端子附著於 件’該桂形 於截面最大 許較厚半導 說明之。也 ，其包含一 體零件； 端子’其長 ’用於將該 不同位置， 的電連接。 該端子連接區，經由該載具電 端子（可以呈圓柱形或任何角 寬度。 體零件裝於其内的封裝體，也 就是，其可以包含： 第一表面； 度大於其截面之最大寬度，以 半導體零件與該柱形端子連接 並且提供該半導體零件與該柱 圖式簡介 圖1表示一種習知BGA (球閘陣列）封裝技藝 圖2〜8分別表示本案各種實施例 圖9表示本案封裝體所用枉形端子之結構 圖號說明 1 習知BGA封裝體 2 本案採用柱形端子之一種封裝體實施例 11 錫球（solder bal 1)Page 5 4_ "9892 V. Description of the invention (3) at least half of the lead-on area; and at least one column connected to the semiconductor zero column) The length of this case is large. In this case, the component C can be a body such as a wafer ) Attach to the semiconductor connector-at least half of the chip carrier, at least one pillar, and a terminal system connecting the system to the first surface. The terminal is attached to the piece. Note. Also, it contains integral parts; the terminal 'its length' is used for the electrical connection of the different positions. The terminal connection area, via the carrier's electrical terminals (can be cylindrical or any angular width. Body parts assembly The package body therein, that is, it may include: a first surface; a degree greater than the maximum width of its cross-section, connected with the semiconductor component to the cylindrical terminal and providing a brief introduction of the semiconductor component and the column diagram FIG. 1 shows a Known BGA (Ball Gate Array) packaging technology Figures 2 to 8 show various embodiments of this case, respectively Figure 9 shows the structure of the U-shaped terminal used in the package of this case Drawing number description 1 Known BGA package 2 is an embodiment of a case using the package 11 of the cylindrical terminal solder balls (solder bal 1)
第6頁 449孖兮十 ^ /IQRC) 2__ 五、發明說明（4) 12 基板（substrate) 16 晶片（半導體零件） 21 載具（carrier) 22 載具第一表面 23 載具第二表面 24 半導體連接區 25 端子連接區 26 半導體零件 27 枉形端子 28 柱形端子之長度 29 端形端子截面最大寬度 30 覆晶之突塊（bump) 36 半導體零件（覆晶也就是il ip chip ) 37 半導體零件（銲線型晶片） 40 覆晶之突塊（bump) ’ 47 銲線型晶片 50 銲線（bonding wire) 51 密封體（例如封膠結構） 52 黏性物質 57 覆晶（flip chip) 60 銲線（bonding wire) 61 密封體（例如封膠結構） 70 突塊（bump) 91 穿孔（v i a)Page 6 449 孖 十 / / IQRC) 2__ V. Description of the invention (4) 12 substrate 16 wafer (semiconductor part) 21 carrier 22 carrier first surface 23 carrier second surface 24 semiconductor Connection area 25 Terminal connection area 26 Semiconductor component 27 Crimp terminal 28 Length of cylindrical terminal 29 Maximum width of end terminal section 30 Bump on chip 36 Semiconductor component (Il-IP chip) 37 Semiconductor component (Wide wire type wafer) 40 bumps of flip chip '' 47 Welding type wafer 50 Bonding wire 51 Sealing body (such as sealant structure) 52 Viscous substance 57 Flip chip 60 Welding wire ( bonding wire) 61 sealing body (such as sealant structure) 70 bump (bump) 91 perforation (via)
第7頁 4 4 -9 β兮十 -4^989 2-, ------ 五、發明說明.（5) 92 載具凹入處 121載具12的第一表面 271柱形端子核心部份（c〇re) 272柱形端子外圍部份 詳細說明 圈2所示為本案提供之容許較厚半導體零件裝於其内 的封裝體之一種實施例，這封裝體2包含： —載具21，該載具21包含一第一表面22，該第一表面 22包含至少一半導體連接區24 (例如：圖中較粗黑之區域 )與至少一端子連接區25 ; 至少一半導體零件（例如一覆晶2 6 )，經由突塊 (bump ) 30附著於半導體連接區24 (例如·圖中較粗黑之區 域）； ' Μ及至少一柱形端子27附著於該端子連接區託，經由 接該半導體零件·26 ’該柱形端子之長度28大 於戰面最大寬度29。 可以該載具21可以係-種基板’而該半導體零件26 巧以係一種晶片。 ^ ΙΤώυ 圖2中該裁具21可以包含至少一去砬 中），爾执3 ν 走線trace (未示於圖 ;電連接該柱形端子27與該半, 如：圖中軔刼里女f m 丹碌午等體連接區24 (例 區25而電連接該柱形端子27，以達成電垃^子連接 區24 (例如：时較粗黑之區域）i:;;邊半導體連接 -所示者與圖2所示者…二 =端二^^ nun 五、發明說明（6) 例的載具21之第二表面23附著有另一半導艘零件36 士 一包含突塊40的覆晶）’其與柱形端子27之間的電連^士 可經由走線trace (未示於圖中）與穿孔。 圖4所示者與圖2所示者之差別在於，圖4中本 例的載具21之第二表面23附著有另一半導體零件3?、 辉線型晶片’也就是Wire bonding晶片），經由鲜線 (bonding wire)50電連接走線（位於栽具2〗，但^ 中）。較佳實施例係提供銲接手指（位於載具2ι，=夫圖 於圖中）’用於電連接辉線50與該走線（未示於圖中^。^ 銲線型晶片37與鮮線5〇可用密封體51保護之。 & 圖5所示者與圖2所示者之差別為，圊5中在 例之載具21的第一表面22，半導體連接區 如、 所附著的是銲線型晶片…其經由銲= 電連接該走線（位於載具21，夫 田杆深Μ 連接區24 (例如：圖中較粗里.^铋 ，而"與半導體 由各種黏性物質52 之間的連接可以藉 51保護之。 ^線型晶片37與銲線50可用密封體 =示者⑽所示者之差別a 例之載具21的第二表面23 :厂本案實知 鈈線60、載具中的走線（未示於 等電連接該柱形端子27。 固"^ 與穿孔91 圖7所示者與圖5所示者 例之載具2〗的第二表品m # 圖中本案實施 子27的電連接之可能方」著有覆晶57 ’覆晶57與柱形增 此方式為，經由突塊70、走線（位於載 k ^ 4 49-8-91 4 498 9 2 五、發明說明（7) 具21，未示於圖）、與穿孔91(via)。 圖8所示者與圓5所示者之差別在於，圖8的半導雜連 接區24係位於載具21的第一表面22之凹入處92。 顧然地’上述本索之各種實施例中，枉形端子27之數量可 以是多個’而且是平均、或對稱分佈於該半導體24之外； 又各實施例中’該柱形端子2 7之結構可以如圖9所示，包 含—核心部份271與一外園部份272，該核心部份271之稼 點高於該外圍部份2 7 2。 另上述每—實施例皆可以包含一密封體（如圖5與圖6 的密封體51)，用以覆蓋該半導體零件（不管其係何 8日片）與該焊線〇 .物哲上述之本案各實施例中該半導體連接區可以包含連接 而談’用於該半導體零件與該半導體連接區之間的連接， 二端子迷接區也可以包含連用於該 該端:連接區之間的連接。. 用下，種‘許較厚半導體零件裝於其内的封裝體，也可以 捉认3方式說明之。也就是，這一種容許較厚半導體零件 裝於其内的封裝體可以包含： 月形栽具，其包含—第—表面 至少一半導體零件； 至少—柱形端子；以及 該第一連接系統’用於連接該半導體零件、該柱形端子到 迪；面的不同位置’並且提供該半導體零件與該柱形 之間的電連接。例如：該連接系統包含至少一位Page 7 4 4 -9 β 西 十 -4 ^ 989 2-, ------ V. Description of the invention. (5) 92 The recess of the carrier 121 The first surface of the carrier 12 271 cylindrical terminal core Part (core) 272 cylindrical terminal peripheral part detailed description Circle 2 shows an embodiment of the package provided in this case that allows thicker semiconductor parts to be accommodated therein. This package 2 contains:-a carrier 21, the carrier 21 includes a first surface 22, and the first surface 22 includes at least one semiconductor connection region 24 (for example, a thicker black area in the figure) and at least one terminal connection region 25; at least one semiconductor component (for example A flip chip 2 6) is attached to the semiconductor connection area 24 (for example, the thicker black area in the figure) via a bump 30; ′ and at least one cylindrical terminal 27 is attached to the terminal connection area holder, via The length of the cylindrical terminal 28 is greater than the maximum width of the battle surface 29. The carrier 21 may be a substrate, and the semiconductor component 26 may be a wafer. ^ ΙΤώυ The cutting tool 21 in FIG. 2 may include at least one of them), Erzhi 3 ν wiring trace (not shown in the figure; electrically connecting the cylindrical terminal 27 and the half, such as: 轫 刼 里 女 in the figure) fm Dan Luwu isotope connection area 24 (eg, area 25 and electrically connects the cylindrical terminal 27 to achieve electrical connection area 24 (for example, a thicker and darker area) i: ;; side semiconductor connection-all Shown and shown in Figure 2 ... Two = End two ^^ nun V. Description of the invention (6) The second surface 23 of the carrier 21 of the example is attached with another semi-conductor part 36 + a flip chip including a bump 40 ) 'Its electrical connection with the cylindrical terminal 27 can be through a trace (not shown) and through-holes. The difference between the one shown in FIG. 4 and the one shown in FIG. 2 is that this example in FIG. 4 The second surface 23 of the carrier 21 is attached with another semiconductor component 3 ′, a wire-shaped wafer 'that is, a Wire bonding wafer), and the wiring is electrically connected through a bonding wire 50 (located at the tool 2), but ^ in). The preferred embodiment is to provide a soldering finger (located on the carrier 2m, the figure is shown in the figure) 'for electrically connecting the glow wire 50 to the trace (not shown in the figure ^.) Welded wire chip 37 and fresh wire 5 〇 It can be protected by the sealing body 51. & The difference between the one shown in FIG. 5 and the one shown in FIG. 2 is that the first surface 22 of the carrier 21 in FIG. 5 is an example, and the semiconductor connection area is soldered. Linear chip ... It is electrically connected to the trace via soldering (located on carrier 21, Futian rod deep M connection area 24 (for example: thicker in the picture. Bismuth, and " and semiconductor by various adhesive substances 52 of The connection between the two can be protected by 51. ^ The difference between the seal of the linear chip 37 and the bonding wire 50 can be shown as shown below: a. The second surface 23 of the carrier 21: The factory knows the wire 60, the carrier The wiring in the tool (not shown for isoelectric connection to the cylindrical terminal 27. Fixing & ^^ and perforation 91 The second table product m # of the example shown in FIG. 7 and the example shown in FIG. 5} The possible side of the electrical connection of the implementation member 27 in this case is “Flip-Chip 57 'Flip-Chip 57 and the column increase. This method is through the bump 70, the wiring (located at k ^ 4 49-8-91 4 498 92 V. Description of the invention (7) 21 (not shown) and perforation 91 (via). The difference between the one shown in Fig. 8 and the one shown in circle 5 is that the semiconducting heterojunction region 24 of Fig. 8 is located at The recesses 92 of the first surface 22 of the carrier 21. Incidentally, in the above-mentioned embodiments of the present invention, the number of the 枉 -shaped terminals 27 may be plural, and they are evenly or symmetrically distributed among the semiconductors 24. In the other embodiments, the structure of the cylindrical terminal 27 can be as shown in FIG. 9 and includes a core portion 271 and an outer circle portion 272. The core portion 271 has a higher crop point than the peripheral portion. 2 7 2. In addition, each of the above-mentioned embodiments may include a sealing body (such as the sealing body 51 of FIG. 5 and FIG. 6) for covering the semiconductor component (regardless of the 8-day film) and the bonding wire. In the above embodiments of the present invention, the semiconductor connection area may include a connection, and is used for the connection between the semiconductor part and the semiconductor connection area. The two-terminal junction area may also include a connection for the end: the connection area. The connection between .. With the use of a package that allows thicker semiconductor components This is explained in the third way. That is, this type of package that allows thicker semiconductor parts to be contained therein may include: a moon-shaped fixture that includes—a first surface of at least one semiconductor component; at least—a cylindrical terminal; and the The first connection system is used to connect the semiconductor part, the cylindrical terminal to different positions of the surface; and provides an electrical connection between the semiconductor part and the column. For example, the connection system includes at least one bit
第10頁 '4 49 8 9 4- / /1Q R 9 2 _ _____ 五、發明說明（8) 於該第一表面的端子連接區（如圖2的25)，供該柱形端 子27連接該載具21 :也包含至少一位於該第一表面的半導 艘連接區（如圖2或圖5中的24) 5供該半導體零件（圖2 中26或圖5中37)連接該載具21 ;又包含至少一位於該載 具21的走線（未示於圊），供電連接該检形端子27與該半 導體零件（圖2中26或圖5中的37)。這裡所謂的半導體零 件可以係一覆晶（如圖2所示26 )，該覆晶之突塊3〇銲接 於該半導體連接區24，並且電連接該走線（未示於圖）， 該走線係經由該端子連接區2 5而電連接該柱形端子2 7。這 裡所謂的半導體零件也可以係一銲線型晶片，而所謂的該 連接系統可以更包含至少一銲線，用以電連接該銲線型晶 片到該走線’另所謂的該半導體連接區可以包含黏性物 (如圖4、圖5中的52 )，用以連接該銲線型晶片到該載 具。當然，該端子連接區也可以包含銲接物質（未示於圖 )’用以連接該柱形端子到該，端子連接區。Page 10 '4 49 8 9 4- / / 1Q R 9 2 _ _____ 5. Description of the invention (8) The terminal connection area on the first surface (see 25 in Figure 2) for the cylindrical terminal 27 to connect to the Vehicle 21: It also includes at least one semi-conductor connection area (such as 24 in FIG. 2 or FIG. 5) on the first surface 5 for the semiconductor component (26 in FIG. 2 or 37 in FIG. 5) to be connected to the vehicle. 21; further comprising at least one trace (not shown) located on the carrier 21, which electrically connects the test terminal 27 and the semiconductor component (26 in FIG. 2 or 37 in FIG. 5). The so-called semiconductor part here can be a flip chip (as shown in FIG. 2, 26). The flip chip bump 30 is soldered to the semiconductor connection region 24 and is electrically connected to the trace (not shown). The wire system is electrically connected to the cylindrical terminal 27 via the terminal connection area 25. The so-called semiconductor part here may also be a wire-bond wafer, and the so-called connection system may further include at least one wire for electrically connecting the wire-bond wafer to the traces. Another so-called semiconductor connection region may include a bonding wire. A physical object (such as 52 in FIG. 4 and FIG. 5) is used to connect the wire-type wafer to the carrier. Of course, the terminal connection area may also contain a soldering substance (not shown in the figure) 'for connecting the cylindrical terminal to the terminal connection area.