448238 五、發明說明（1) 本發明為一種防止氧化矽層中產生空隙的方法，尤指 一種防止填入淺溝的氧化層產生空隙的方法。 淺溝隔離（shal low trench isolation，簡稱STI)製 程是將一氧化矽層填入一淺溝内，用來作為一半導體晶片 上之電子元件的電隔絕。在次微米的半導體製程中，ST I 製程是一項廣為使用的技術。 請參閱圖一至圖四，圖一至圖四為習知將氧化矽層16 填入淺溝1 4的方法的示意圖。習知將氧化矽層1 6填入淺溝 14的方法，是於一半導體晶片10上進行。如圖一所示，半 導體晶片10包含有一石夕基底（silicon substrate)12，以 及一淺溝14設於石夕基底12表面。習知方法是在一大氣壓之 環境下進行一化學氣相沉積（atmosphere pressure chemical vapor deposition，APCVD)製程，以 TEOS(tetraethyl orthosilicate)為一反應氣體，在石夕基 底1 2表面形成一氧化矽層1 6。以這種方式形成的氧化矽層 16俗稱為APTE0S ’其具有很好的同形度（c〇mf〇rmity)，能 夠把淺溝1 4填滿。但是在形成氧化層1 6的過程中，於淺溝 1 4的正中央上方會形成一條又細又深的狹縫，使得反應氣 體難以進出狹縫。因此當淺溝〗4完全地被氧化層丨6填滿 時，位於狹縫區域的氧化層16包含有未完全反應之反應氣 體而形成一脆弱區1 7，如圖二所示。隨後進行一蝕刻製448238 V. Description of the invention (1) The present invention is a method for preventing voids in a silicon oxide layer, especially a method for preventing voids in an oxide layer filled in a shallow trench. In the shallow trench isolation (STI) process, a silicon oxide layer is filled into a shallow trench, which is used to electrically isolate electronic components on a semiconductor wafer. In the sub-micron semiconductor process, the ST I process is a widely used technology. Please refer to FIGS. 1 to 4, which are schematic diagrams of a conventional method for filling the silicon oxide layer 16 into the shallow trenches 14. The conventional method for filling the silicon oxide layer 16 into the shallow trench 14 is performed on a semiconductor wafer 10. As shown in FIG. 1, the semiconductor wafer 10 includes a silicon substrate 12, and a shallow trench 14 is provided on the surface of the stone substrate 12. A conventional method is to perform an atmospheric pressure chemical vapor deposition (APCVD) process under an atmosphere of atmospheric pressure, and use TEOS (tetraethyl orthosilicate) as a reactive gas to form a silicon oxide layer on the surface of the stone evening substrate 12 1 6. The silicon oxide layer 16 formed in this way is commonly referred to as APTEOS, and it has a good isomorphism (comfmrmity), which can fill the shallow trenches 14. However, in the process of forming the oxide layer 16, a thin and deep slit will be formed above the center of the shallow trench 14, making it difficult for the reaction gas to enter and exit the slit. Therefore, when the shallow trench 4 is completely filled with the oxide layer 6, the oxide layer 16 located in the slit region contains incompletely reacted reactive gas to form a fragile region 17, as shown in FIG. 2. Etching
第5頁 448238 五、發明說明（2) 矽層16的表面高度約略與矽基底12表面切齊，如圖三所 示。矽基底1 2表面可以用來製作半導體元件’而氧化矽層 1 6則用來作為半導體元件彼此間的電性隔絕。 接下來對半導體晶片1 0進行至少一次清洗製程，使用 稀释的氩氟酸溶液或稀釋的氨水等蝕刻溶液，來去除殘留 於半導體晶片1〇表面上的氧化矽層16。由於氣化矽層16之 脆弱區17包含有反應氣體而具有較高之蚀刻速率，因此在 進行清洗製程後，淺溝1 4内之氧化矽層1 6的正中央便會產 生一條空隙1 8，如圖四所示。空隙1 8會使半導體晶片1 〇表 面產生—向低落差（a worse topology)，容易使後序進行 之餘刻製程產生蝕刻未淨（etching residue)的情形，進 而導致半導體晶片10内之半導體元件故障。 ^ 因此本發明之主要目的在於提供一種防止填入淺溝的 巩化層產生空隙的方法，可以避免氧化矽層中形成脆弱區 而於後序的清洗製程中產生空隙。 圖示之簡單說明 g —至圖四為習知將氧化矽層填入淺溝的方法的示意圖。 五至圖八為本發明防止填入淺溝的氧化層產生空隙的方 法的示意圖。 圖示之符號說明Page 5 448238 V. Description of the invention (2) The surface height of the silicon layer 16 is approximately aligned with the surface of the silicon substrate 12, as shown in Figure 3. The surface of the silicon substrate 12 can be used to make semiconductor elements', and the silicon oxide layer 16 can be used to electrically isolate the semiconductor elements from each other. Next, the semiconductor wafer 10 is cleaned at least once, and an etching solution such as a dilute hydrofluoric acid solution or diluted ammonia is used to remove the silicon oxide layer 16 remaining on the surface of the semiconductor wafer 10. Because the fragile region 17 of the vaporized silicon layer 16 contains a reactive gas and has a high etching rate, after the cleaning process is performed, a gap 18 will be generated in the center of the silicon oxide layer 16 in the shallow trench 14 , As shown in Figure 4. The gap 18 causes a worse topology on the surface of the semiconductor wafer 10, which can easily cause etching residues in the remaining processes of the subsequent processes, which in turn leads to semiconductor elements in the semiconductor wafer 10. malfunction. ^ Therefore, the main object of the present invention is to provide a method for preventing voids in the sclerosis layer filled in shallow trenches, which can prevent the formation of fragile regions in the silicon oxide layer and generate voids in the subsequent cleaning process. Brief description of the diagrams g to FIG. 4 are schematic diagrams of a conventional method for filling a shallow trench with a silicon oxide layer. 5 to 8 are schematic diagrams of a method for preventing voids from being formed in an oxide layer filled in a shallow trench according to the present invention. Symbol description
38 五、發明說明（3) 42矽基底 4 6氧化矽層 4 0半導體晶片 44淺溝 請參閱圖五至圖八’圖五至圖八為本發明防止填入淺 溝4 4的氧化層4 6產生空隙的方法的示意圖。本發明防止氧 化矽層中產生空隙的方法是用於半導體晶片40所進行的 ST I製程’以防止填入淺溝44的氡化層46產生空隙。如圖 五所示半導體晶片40包含有一石夕基底42，以及一淺溝44設 於石夕基底4 2表面上用來作為淺溝隔離中之電性隔絕用。 本發明方法是先進行一化學氣相沉積製程，以TE〇S或 是TEOS加上臭氧（ozone, 〇3)做為一反應氣體，在大約一 大氣壓之環境下於半導體晶月40表面形成一氧化石夕廣46， 以填滿淺溝4 4。如圖六所示，淺溝4 4内之氧化石夕層4 6中會 含有一些未反應之反應氣體’而絕大多數未反應之反應氣 體會分布在淺溝44正中央上方的氧化石夕層46中，因此淺漢 4 4之正中央上方的氧化矽層46可以定義為一脆弱區47。 然後在含氧的環境j對半導體晶片4〇進行一高溫熱退 火（thermal annealing')製程，含氧環境可為一含有氧氣 (〇2)或是水氣（stream)的環境，溫度為攝氏8〇〇至12〇〇 度，進行時間為20至40分鐘。這個高溫退火製程可使氧氣 或疋水氣於南溫下擴散而進入氧化砍層4 6中，讓脆弱區$ 7 中所含之反應氣體完全反應，如圖七所示。38 V. Description of the invention (3) 42 silicon substrate 4 6 silicon oxide layer 4 0 semiconductor wafer 44 shallow trench Please refer to FIG. 5 to FIG. 8 ′ FIG. 5 to FIG. 6 Schematic illustration of a method for generating voids. The method for preventing voids in the silicon oxide layer of the present invention is used in the ST I process' performed on the semiconductor wafer 40 to prevent voids from being generated in the hafnium layer 46 filled in the shallow trench 44. As shown in FIG. 5, the semiconductor wafer 40 includes a stone substrate 42 and a shallow trench 44 provided on the surface of the stone substrate 42 for electrical isolation in shallow trench isolation. The method of the present invention first performs a chemical vapor deposition process, using TEOS or TEOS plus ozone (ozone, 03) as a reaction gas, and forming a semiconductor gas moon 40 surface under an atmosphere of about one atmosphere of pressure. Oxide stone Xiguang 46 to fill the shallow trench 4 4. As shown in FIG. 6, the oxidized stone layer 46 in the shallow trench 44 will contain some unreacted reactive gas, and most of the unreacted reactive gas will be distributed over the oxidized stone layer just above the center of the shallow trench 44. In the layer 46, the silicon oxide layer 46 above the center of the shallow hole 44 can be defined as a fragile region 47. Then, the semiconductor wafer 40 is subjected to a high-temperature thermal annealing process in an oxygen-containing environment j. The oxygen-containing environment may be an environment containing oxygen (〇2) or water vapor (temperature). The temperature ranges from 800 to 1200 degrees, and the duration is 20 to 40 minutes. This high-temperature annealing process allows oxygen or tritium to diffuse at the south temperature and enter the oxide cutting layer 46, allowing the reaction gas contained in the fragile zone $ 7 to fully react, as shown in Figure 7.
笫7頁 4 4823 五、發明說明（Ό 接著進行一蝕刻製程以去除淺溝44外之氧化矽層46， 並使淺溝44中之氧化石夕層46表面和基底42表面大略齊平， 如圖八所示。這個蝕刻製程可以是一個濕回蝕刻（we t etch-back)製程或者是化學機械研磨（CMP)製程。最後進 行一清洗製程，以一含有氧化矽之蝕刻溶液來清洗半導體 晶片4 0。蝕刻溶液可以是稀釋氫氟酸溶液或稀釋氨水。 本發明方法所進行之高溫熱退火製程不但能使氧化石夕 層46中所含之反應氣體完全反應’還能使反應後氣體擴散 出來而不會累積在氧化矽層4 6中。在進行清洗製程時，由 於氧化矽層4 6不 氧化矽層4 6的蝕 液因對含有反應 淺溝内的氧化矽 晶片4 0經由電子 以避免該淺溝4 4 退火製程還可以 化而形成氧化石夕 (corner roundi 的電性表現變得 含有反應氣體’因此餘刻溶液對各區域之 刻速率約略相同。本發明可以防止蝕刻溶 氣體的氧化矽部份具有較高的蝕刻率而使 層產生空隙。本發明方法所製作的半導體 顯微鏡（SE Μ)的觀察，本發明方法確實可 内之氧化石夕層4 6產生空隙。此外，高溫熱 將淺溝44兩側壁上方轉角處的矽基底氧 ，使矽基底42表面的轉角處更加圓滑 ng) ’因此半導體晶片内之半導體元件 更加良好。 明 相較於習知在淺溝14 防止填入淺溝4 4的氣化 内填入氧化矽層1 6的方法，本發 層4 6產生空隙的方法，是於淺溝笫 Page 7 4 4823 V. Description of the invention (Ό Then an etching process is performed to remove the silicon oxide layer 46 outside the shallow trench 44 and make the surface of the oxide layer 46 in the shallow trench 44 and the surface of the substrate 42 approximately flush, such as Figure 8. This etching process can be a wet etch-back process or a chemical mechanical polishing (CMP) process. Finally, a cleaning process is performed to clean the semiconductor wafer with an etching solution containing silicon oxide. 40. The etching solution may be a dilute hydrofluoric acid solution or a dilute ammonia solution. The high temperature thermal annealing process performed by the method of the present invention can not only completely react the reaction gas contained in the oxidized stone layer 46, but also make the gas after the reaction It diffuses out and does not accumulate in the silicon oxide layer 46. During the cleaning process, the silicon oxide layer 46 does not oxidize the silicon layer 46, and the etching solution causes the silicon oxide wafer 40 in the shallow trench to react through the electrons. In order to avoid the shallow trench 4 4 annealing process can also be transformed into the formation of stone oxide (corner roundi's electrical performance has become reactive gas' so the remaining solution of the etching rate in each region is about the same. This issue It can prevent the silicon oxide portion of the etching gas from having a higher etching rate and cause the layer to generate voids. According to the observation of the semiconductor microscope (SE M) produced by the method of the present invention, the method of the present invention can indeed be used for the oxide layer 4 6 Voids are generated. In addition, the high temperature heat will oxygen the silicon substrate at the corners above the two sidewalls of the shallow trench 44 to make the corners of the surface of the silicon substrate 42 smoother. Therefore, the semiconductor elements in the semiconductor wafer are better. Compared with Xi The method of filling the silicon oxide layer 16 in the shallow trench 14 to prevent the filling of the shallow trench 4 4 is known. The method of generating voids in the hair layer 46 is the shallow trench.
44内形成氧化矽層46之後進行高溫熱退火製程，可以使氧 化石夕層4 6中所包含之反應氣體完全反應，可以防止於後續 '凊洗製程時，蝕刻溶液會因為對含有反應氣體之氧化矽層 部分具有較高之蝕刻率而使淺溝内之氧化矽層產生空隙氧 化石夕層46在後序的清洗製程中產生空隙。因此本發明防止 填入淺溝44的氧化層46產生空隙的方法，可以提高半導體 晶片40的良率。 實施例，凡依本發明申請 ’皆應屬本發明專利之涵 以上所述僅為本發明之較佳 專利範圍所做之均等變化與修飾 蓋範圍。After the silicon oxide layer 46 is formed in 44, a high-temperature thermal annealing process is performed, which can completely react the reaction gas contained in the oxidized stone layer 46. It can prevent the etching solution from containing reactive gases during the subsequent 'cleaning process'. The silicon oxide layer portion has a higher etch rate, which causes voids in the silicon oxide layer in the shallow trench. The stone oxide layer 46 generates voids in the subsequent cleaning process. Therefore, the method for preventing voids in the oxide layer 46 filled in the shallow trench 44 of the present invention can improve the yield of the semiconductor wafer 40. In the embodiments, any application according to the present invention should fall within the scope of the patent of the present invention. The above description is only an equivalent change and modification of the preferred patent scope of the present invention.