TW447093B - Encapsulating method and encapsulating mold for semiconductor apparatus - Google Patents

Encapsulating method and encapsulating mold for semiconductor apparatus Download PDF

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Publication number
TW447093B
TW447093B TW089103201A TW89103201A TW447093B TW 447093 B TW447093 B TW 447093B TW 089103201 A TW089103201 A TW 089103201A TW 89103201 A TW89103201 A TW 89103201A TW 447093 B TW447093 B TW 447093B
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TW
Taiwan
Prior art keywords
cavity
mold
dummy
sealing
semiconductor device
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TW089103201A
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Chinese (zh)
Inventor
Chun-Hung Lin
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Advanced Semiconductor Eng
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Abstract

A kind of encapsulating method for semiconductor apparatus includes the following steps: (a) providing a molding die that includes a molding portion having a cavity used to accept the semiconductor apparatus, a dummy cavity connected with the cavity, and an air vent connected with the dummy cavity; (b) tightly clipping this molding die so as to make semiconductor apparatus locate in the cavity; (c) injecting the encapsulating material into the cavity and the dummy cavity; (d) curing the encapsulating material; and (e) opening the molding die to take out the molded product. The encapsulating method of this invention is characterized in that the injection head will continuously move the compressed encapsulating material and make the encapsulating material continuously flow into the dummy cavity when the cavity loaded with semiconductor apparatus is filled with the encapsulating material. On the other hand, the present invention provides a kind of molding die used for encapsulating a semiconductor apparatus, in which the molding die mainly contains a pot, a molding portion and a runner. The molding portion has a cavity used to accept the semiconductor apparatus, a dummy cavity connected with the cavity, and an air vent connected with the dummy cavity. One terminal of the runner is connected with the pot, and the other terminal is connected with the cavity via a gate. The channel connected with the cavity and the dummy cavity has approximately the same size as the gate such that, when performing the encapsulating process, this encapsulating material will first fill up the cavity through the runner and the gate, and then fill up the dummy cavity via the channel.

Description

447 0 93 五、發明說明(l) 發明領域: 本發明係有關於一種半導體裝置之製造方法,特別有 關於一種半導體裝置封膠方法。本發明亦有關於一種用於 封膠一半導體裝置的模具。 先前技術: 隨著更輕更複雜電子裴置需求的日趨強烈,晶片的速 度及複雜性相對越來越高’因此需要更高之封裝效率 (packaging efficiency)。微型化(miniaturization)是447 0 93 V. Description of the Invention (l) Field of the Invention: The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for sealing a semiconductor device. The invention also relates to a mold for sealing a semiconductor device. Previous technology: With the increasing demand for lighter and more complex electronic devices, the speed and complexity of the chip are relatively higher and higher, therefore higher packaging efficiency is required. Miniaturization is

使用先進封裝技術(例如晶片尺寸級封裝(chip scale package)以及覆晶(flip chip))的主要驅動力。相較於 球格陣列封裝或薄小輪廓封裝(thin small outline package, TSOP)而言,晶片尺寸級封裝以及覆晶這兩種技 術均大幅增加封裝效率,藉此減少所需之基板空間β 一般 而言,一個晶片尺寸級封裝大約比晶片本身大百分之二 十,然而覆晶被描述為終極之封裝技術因為其大約與晶片 本身一樣大。該晶片本身係直接利用固設於晶片上之錫鉛 凸燒(solder bump)與基板(substrate)進行接合。 第一圖揭示一習用覆晶封裝構造,其包含一晶片】〇利 用覆晶技術安裝於一基板2〇 ^由於該晶片1〇與基板2〇熱膨 服係數差異相當大(半導體晶片之熱膨脹係數The main driving force for using advanced packaging technologies, such as chip scale packages and flip chips. Compared to ball grid array packages or thin small outline packages (TSOP), both chip-scale packaging and flip-chip packaging technologies significantly increase packaging efficiency, thereby reducing the required substrate space β General In terms of a wafer-scale package, it is approximately 20% larger than the wafer itself. However, flip chip is described as the ultimate packaging technology because it is approximately as large as the wafer itself. The wafer itself is directly bonded to the substrate by solder bumps fixed on the wafer. The first figure reveals a conventional flip-chip package structure, which includes a wafer]. It is mounted on a substrate 2 using flip-chip technology. ^ Since the thermal expansion coefficient of the wafer 10 and the substrate 20 is quite different (the thermal expansion coefficient of a semiconductor wafer)

^coefficient of thermal expansion, CTE)約為3-5ppm °C-1,基板之熱膨脹係數(CTE)约為20_30ppm七―i ),因 此該晶>110與基板20間較佳具有一填膠(undei*fill)3〇用 以密封該錫鉛連接1 2間之空隙。該填膠3 0可以減輕在錫鉛^ coefficient of thermal expansion (CTE) is about 3-5ppm ° C-1, and the coefficient of thermal expansion (CTE) of the substrate is about 20_30ppm VII-i), so the crystal > 110 and the substrate 20 preferably have a filler ( undei * fill) 30 is used to seal the gap between the tin-lead connections 12 and 12. The filler 3 0 can lighten tin-lead

__

4 47 Ο 9.3 五、發明說明(2) 逮接12上的熱膨脹係數不一致所導致的應力。 該填勝3 0 —般係利用一自動化點膠系統(a u t m a t e d underfill dispense sy stem )將填膠材料點在該晶片1 〇之 邊緣。然而’由於填膠材料係經由毛細作用吸到晶片1 〇之 下’因此將填膠材料由晶片1 〇側邊滲入晶片1 〇與基板2 〇間 之空隙需要花費相當長的時間。 因此’半導體業界發展出利甩習知的傳遞模塑法 (transfer molding)形成一封膠體來密封晶片與基板間之 空隙。請參照第二圖,其係為一傳遞模塑法習用模具裝上 一晶片利用覆晶技術安裝於一基板之剖面圖。如圖所示, ( 該模具設有一罐(pot) 40供封膠材料置放。該罐40係經由 一澆道(runner)42以及一澆道口(gate)44連接一模穴 (cavity)46。將封膠材料置於罐4〇中,並且將模具密合夾 緊後,一壓注頭4 8開始移動向上壓縮封膠材料,使其經由 澆道42以及澆道口44而充滿模穴46以密封晶片10與基板20 間之空隙。然而,由於晶片1 〇與基板2 〇間之空隙非常小 (一般為0.05〜1毫米),因此空氣很容易被包覆在晶片 1 0與^基板20間而產生孔隙(v〇id) 32。這些孔隙32將會導致 晶片1 0及基板2 0之間的機械以及電性連接(即錫鉛連接1 2 )的可靠性降低。 因此’美國專利第5998243號揭示一半導體裝置製造方 法,其藉由將模穴保持在高度真空(1〇 陶爾(torr)以下 )’來減少在晶片與基板間產生孔隙之機率。請參照第三 圓’根據美國專利第5 9 9 8 2 4 3號,一較佳實施例之模具係4 47 Ο 9.3 V. Description of the invention (2) Stress caused by inconsistent thermal expansion coefficient on the catch 12. The filling 30 — generally uses an automated dispensing system (a u t m a t e d underfill dispense sy stem) to place the filling material on the edge of the wafer 10. However, 'because the filling material is sucked under the wafer 10 by capillary action', it takes a considerable time to penetrate the filling material from the side of the wafer 10 into the space between the wafer 10 and the substrate 20. Therefore, the semiconductor industry has developed a conventional transfer molding method to form a gel to seal the gap between the wafer and the substrate. Please refer to the second figure, which is a cross-sectional view of a conventional mold for transfer molding method, a wafer is mounted on a substrate using flip-chip technology. As shown in the figure, (The mold is provided with a pot 40 for placing the sealing material. The pot 40 is connected to a cavity 46 through a runner 42 and a gate 44. After the sealing material is placed in the tank 40 and the mold is tightly clamped, an injection head 48 begins to move upward to compress the sealing material to fill the cavity 46 through the runner 42 and the runner 44. The gap between the wafer 10 and the substrate 20 is sealed. However, since the gap between the wafer 10 and the substrate 20 is very small (usually 0.05 to 1 mm), the air is easily covered by the wafer 10 and the substrate 20 Voids 32 will be generated from time to time. These voids 32 will cause the reliability of the mechanical and electrical connection (ie, the tin-lead connection 12) between the wafer 10 and the substrate 20 to decrease. Therefore, the 'US Patent No. No. 5998243 discloses a method for manufacturing a semiconductor device, which reduces the probability of generating voids between a wafer and a substrate by maintaining a cavity at a high vacuum (less than 10 torr). Please refer to the third circle according to the United States Patent No. 5 9 9 8 2 4 3, a mold system of a preferred embodiment

447093 五、發明說明(3) 刹用一真空幫浦(来示於圖中),經由抽 vent)50來降低模穴46之壓力。一炉 道(exhaust 50與模穴46之通道54,其 σ連接抽氣孔道 粒的直徑,藉此阻止封膠材料 .7中填充物顆 丰導體裝置劁诰* ^ Γ料進抽氣孔道5 0。然而,該 牛导體裝罝製造方法之缺點為真空幫 且增加模具之成本。 约保養維修,並 發明概要: 本發明之主要目的係提供一種半導體裝置之 法,其可^決前述先前技術的孔隙(v〇id)問題,並且 形成一封膠體來密封晶片與基板間之空隙。 、速 b 本發明之另一目的係提供一種用於封膠一 的模具,其可用以快速形成一封膠體來密封 之空隙,並且阻止孔隙之發生。 曰曰月與基板間 根據本發明之半導體裝置封膠方法,其包含 驟:(a)提供一模具(molding die),其包含一模造部 (molding portion)具有一模穴用以容納該半導體裝^, 一假模穴(dummy cavity)連接於該模穴,以及一浪氣孔 (air vent)連接於該假模穴;(b)密合夾緊該1使 半導體裝置係位於該模穴中;(c)將封膠材料注义 =;; 以及假模穴中;(d )硬化該封膠材料;及(e ) 談 以取出該模製品》根據本發明之封膠方法,其 ^^ ^ 裝有半導體裝置之模穴被封膠材料填滿時,壓注 繼二 移動向上壓縮封膠材料,使其繼續流入假模穴中。因此, 原先包覆在晶片與基板間的空氣將會順著模流前進而被推447093 V. Description of the invention (3) The brake uses a vacuum pump (shown in the figure) to reduce the pressure in the cavity 46 by venting 50. A furnace channel (exhaust 50 and channel 54 of the mold cavity 46, whose σ is connected to the diameter of the exhaust hole particles, thereby preventing the sealing material. 7 filling conductors in the filling device 劁 诰 * ^ Γ material into the exhaust hole 5 0. However, the shortcomings of the method for manufacturing the cattle conductor decoration are vacuum help and increased mold cost. Maintenance and repair, and summary of the invention: The main purpose of the present invention is to provide a method for semiconductor devices, which can be determined according to the foregoing. The technology has a problem of voids, and forms a gel to seal the gap between the wafer and the substrate. Another object of the present invention is to provide a mold for sealing a mold, which can be used to quickly form a mold. The sealing compound seals the voids and prevents the occurrence of pores. The method for sealing a semiconductor device according to the present invention between the moon and the substrate includes the steps of: (a) providing a molding die including a molding section ( (molding portion) has a mold cavity to accommodate the semiconductor device, a dummy cavity is connected to the mold cavity, and an air vent is connected to the dummy cavity; (b) a close clamp Tight the 1 make half The conductor device is located in the mold cavity; (c) the sealant material is noted = ;; and in the dummy mold cavity; (d) the sealant material is hardened; and (e) talk to remove the mold product according to the present invention In the sealing method, when the cavity containing the semiconductor device is filled with the sealing material, the injection molding moves upward and compresses the sealing material to continue to flow into the dummy cavity. Therefore, it is originally covered in The air between the wafer and the substrate will be pushed along the die flow and pushed

麵 447093 五、發明說明(4) 擠入假糢穴中,因而不會在模穴内產生孔隙。 本發明另提供一種用於封膠一半導體裝置的模具,其 主要包含一罐、一模造部以及一澆道。該罐係用以容納封 膠材=、。該模泌部具有一模穴用以容納該半導體裝置,— 穴連接於該模穴’以及一洩氣孔道連接於該假模穴。 ^二道尤―端連接於該罐’另一端經由一澡道口連接於該 夬其中,連接該模穴以及假模穴之通道與洗道口具有 同的尺寸’藉此在封膠時,該封膠材料會先經由該 ^。以及繞道口而充滿模穴,然後經由該通道而填滿假模 圖示說明: 明顯為了下讓文本發明之上二和其^ 詳細說明如^舉本發月較佳實施例,並配合所附圖示,作 5 習用覆晶封裝構造之剖面圖; 兩模穴分別Z遞習用模具之剖面圖’該模具包含 第3 ®裝&上一晶片利用覆晶技術安裝於一基板; 具剖面圖隸模據且美白國冬專第5 9 9 8 24 3 1 -較佳實施例之模 術安裝於一^ Ϊ 兩模穴分別裝上一晶片利用覆晶技 該/具4包\兩t本第一__較佳實施例之s模具剖^面圖, 基板;及 、 、上一晶片利用覆晶技術安裝於— 第5圖·根據本發明第二較佳實施例之模具剖面圖,Face 447093 V. Description of the invention (4) Squeeze into the dummy cavity, so there will be no pores in the cavity. The invention also provides a mold for sealing a semiconductor device, which mainly comprises a can, a molding part and a runner. The tank is used to contain the sealing material = ,. The die cavity has a die cavity for accommodating the semiconductor device, a cavity is connected to the die cavity 'and a vent hole is connected to the dummy die cavity. ^ Erdaoyou-the end is connected to the tank, and the other end is connected to the pot through a bath opening. The channel connecting the mold cavity and the false mold cavity has the same size as the wash channel opening. The glue material will go through this first. And the detour is filled with mold cavities, and then filled with dummy molds through the passage. Graphical illustrations: Obviously in order to let the text invent the above two and its ^ Detailed description such as ^ the preferred embodiment of this month, and cooperate with the attached As shown in the figure, it is a cross-sectional view of a conventional flip-chip packaging structure. The two mold cavities are respectively cross-sectional views of a conventional mold. The mold contains the third chip and the previous chip is mounted on a substrate using flip-chip technology. According to the model and the whitening country winter special 5-9 9 8 24 3 1-the preferred embodiment of the mold is installed in a ^ Ϊ two mold cavities are respectively equipped with a chip using the flip chip technology / with 4 bags \ two t this The first __ preferred embodiment of the s mold is a cross-sectional view of the substrate; and, the last wafer is mounted using flip-chip technology on-Figure 5 · A cross-sectional view of the mold according to the second preferred embodiment of the present invention,

447093 五、發明說明(5) 基 玆掇具包含一模穴裝上一晶片利用覆晶技術安裝於 板。 圖號說明: 10 晶片 12 錫鉛連接 20 基板 30 填膠 3 2 孔隙 4 0 罐 42 澆道 44 澆道口 46 模穴 47 模穴 48 壓注頭 5 0 抽氣孔道 54 通道 60 假模穴 62 茂氣孔道 64 通道 70 空間 d 間距 C 邊長 發明說明: 第四圖揭示根據本發明第一較佳實施例之模具。如圖 所示,該模具設有一罐(P〇t)40供封膠材料置放。該罐4〇 係經由一洗道(runner)42以及一;堯道口(gate)44連接一模 穴(cavity)46。根據本發明第一較佳實施例之模具,其# 有一假模穴60連接於該模穴46,以及一洩氣孔道“連接二 該假模穴60。 ' 剔請再献參Λ第四圖’ 一晶片10利用覆晶技術安裝於—基 ί製r ί ίϊίϊ穴“中。該模穴46之形狀係大致符合最 ί i且ί封膠外型:將封膠材料置於罐40 3 膠材料。該;萬具以及二^ ’壓注頭弋開始移動向上壓縮封 頭48向上壓縮封膘、膠材料係先經過預熱使得當該壓注 澆道42以及澆道料時,該封膠材料會液化並且經由該 4而充滿模穴4 6以包覆該半導體晶片i 〇447093 V. Description of the invention (5) The kit includes a mold cavity and a wafer mounted on the board using flip chip technology. Description of drawing number: 10 wafers 12 tin-lead connection 20 substrate 30 filling 3 2 pores 4 0 cans 42 runner 44 runner gate 46 mold cavity 47 mold cavity 48 injection head 5 0 exhaust hole 54 channel 60 dummy cavity 62 Description of the invention: The fourth figure shows a mold according to the first preferred embodiment of the present invention. As shown in the figure, the mold is provided with a pot (Pot) 40 for the sealing material to be placed. The tank 40 is connected to a cavity 46 through a runner 42 and a gate 44. According to the mold of the first preferred embodiment of the present invention, # a dummy mold cavity 60 is connected to the mold cavity 46, and a vent hole "connects the two dummy mold cavity 60." Please check and refer to the fourth picture " A wafer 10 is mounted in a base-based system using a flip-chip technology. The shape of the cavity 46 is approximately the same as the sealant shape: the sealant material is placed in the can 40 3 sealant material. The mold and the two injection heads began to move upwards to compress the seal heads 48 to compress the seals upwards. The rubber material was first preheated so that when the injection gate 42 and the runner material were pressed, the sealant material would Liquify and fill the cavity 4 6 via the 4 to cover the semiconductor wafer i 〇

第9頁 447093Page 9 447093

五、發明說明(6) 以及密封#a片1 〇輿墓板2 0 Pa〗之空隙〇當模穴4 6被封膠枒 填滿時’壓注頭4 8會繼續移動向上壓縮封膠材料,‘其繼 續流入假模穴60中》因此,原先包覆在晶片1〇與基板2'〇間 的空氣將會順著模流前進而被推擠入假模六6 〇中,藉此避 免工氣.留在模穴46内而產生孔隙。較佳,每一假模穴係 相互連通’以增加封膠材料於模穴4 6及假模穴6 〇内之模流 壓力均衡。當封膠材料充滿模穴4 6以及假模穴6 〇後,壓注 頭48保持靜止且持續一預定時間直至封膠材料硬化。然 後’壓注頭4 8下降且將模具打開,取出模製產品。V. Description of the invention (6) and sealing #a 片 1 〇 The gap of the grave board 20 Pa 〇 When the mold cavity 4 6 is filled with the sealant 'The injection head 4 8 will continue to move upward to compress the sealant material "It continues to flow into the dummy cavity 60." Therefore, the air originally enclosed between the wafer 10 and the substrate 2'0 will be pushed along the mold flow and pushed into the dummy mold 60, thereby avoiding Industrial gas. Remains in the cavity 46 and generates pores. Preferably, each dummy cavity system is interconnected to increase the mold flow pressure of the sealing material in the cavity 46 and the dummy cavity 60. After the sealant material fills the cavity 46 and the dummy cavity 60, the injection head 48 remains stationary for a predetermined time until the sealant material hardens. Then the 'injection head 48' is lowered and the mold is opened, and the molded product is taken out.

該封勝塑料不僅填滿該模穴4 6而且也會填滿該澆道口 44、堯道42以及罐4〇。因此當該封膠塑料固化後,豈不僅 包巧該晶片並且還會沿該基板片2〇表面延伸(即經由澆道 :4在锱Ϊ 延伸至罐4〇 )。該已固化多餘之封膠塑料- 叙係稱為鑄澆道而且必須在該模製產品切割前去除。因 ΐ 土 ΐ Ϊ道口 “之截面積一般係小於該凌•道42用以繁助 #封视撤^」製程一亦即移除該多餘的封膠塑料。此外’ Π:Π ί填滿該假模穴60。因此,將該模製產品之 刑坱4> 除時,可以—起除去假模穴60所形成之成 構造。< ,莫製品切割成個別單元,而完成該覆晶封裝 W,請第四圖’連接該模穴46以及假模穴60之通道 匕:ΐΪίί:44具有大致相同的尺寸。特別言之,該通 此不妨礙封大於該封膠材料中填充物顆粒的直徑’藉 此不妨礙封膠材料進人假模穴Μ。但該通州之尺寸不可The Fengsheng plastic not only fills the mold cavity 46, but also fills the runner gate 44, Yaodao 42, and the tank 40. Therefore, when the sealant plastic is cured, does it not only envelop the wafer, but also extend along the surface of the substrate sheet 20 (that is, via the runner: 4 at 罐 to the tank 40). The cured excess sealant-the system is called a runner and must be removed before the molded product is cut. Because of the 土 面积 ΐ Ϊ 道口 "The cross-sectional area is generally smaller than the Ling • Road 42 used to help # 封 视 脱 ^" The first process is to remove the excess sealing plastic. In addition, Π: Π ί fills the dummy cavity 60. Therefore, when the mold 4 of the molded product is removed, the structure formed by removing the dummy cavity 60 can be taken together. < Mo products are cut into individual units to complete the flip-chip package W. Please refer to the fourth figure 'for connecting the cavity 46 and the dummy cavity 60. Dagger: 44: approximately the same size. In particular, this does not prevent the seal from being larger than the diameter of the filler particles in the sealant material, thereby preventing the sealant material from entering the dummy cavity M. But the size of this Tongzhou is not

447093 五、發明說明⑺ . 太大而妨礙假模穴60所形成之成型塊之去除。@ 道64之尺寸較佳係介於0‘丨5_0. 25毫米。此外,該此’ k通 道62必須小於該封膠材料中填充物 孔 封膠材料溢出模具。 稽此阻止 -第五圖揭示根據本發明第二較佳實施例之模具。 - Ϊ道ί Ξ ; Tilt ί膠材料置放。該罐40係經由 :覆晶技術安裝於一基板2。,然後裝入模;4::= =一較佳實施例之特徵在於離澆道口最遠之 與該模穴側壁之最小間距d係不小 晶片1 〇 向(如第五圖中箭頭所干)二Γ於該曰:片千行於模流方 协磁j π 士 = 所不)邊長C之一半。將封膠材料罾 壓縮钟腺枓^且f該模具密合後,壓注頭48開始移動向下 :i = ΐ 以包覆該半導體晶片10以及密封晶ΐ1〇 膠材料包覆時,壓注頭48會繼嫌f f之+ f體sa片10被封 使其繼續流入其與模穴4 7門額,動向下壓縮封膠材料, 券台濟s 5 7 T 間額外保留之空間70、因此,用 推擠入該:外保留之=的J:將會順著模流前進而被 通,以增加封膠材料;;二=係 材料充滿模穴47後,壓注^模&壓力均衡。當封膠 直至封膠材料硬&。然灸頭48 ^持靜止纟持續一預定時間 取出模製產品。將模製ϊ „ i f頭48上升且將模具打開, 割成個別單元,即;錢道口去除後,並切447093 V. Description of the invention ⑺. Too large to prevent the removal of the forming block formed by the dummy cavity 60. The size of @ 道 64 is preferably between 0 ’丨 5_0. 25 mm. In addition, the 'k channel 62 must be smaller than the filler hole in the sealant material and the sealant material overflows the mold. Prevent this-The fifth figure discloses a mold according to a second preferred embodiment of the present invention. -Ϊ 道 ί Ξ; Tilt ί glue material placement. The can 40 is mounted on a substrate 2 via a flip-chip technology. 4 :: = = A preferred embodiment is characterized in that the minimum distance d from the gate to the side wall of the cavity is not small, and the direction is not small (as indicated by the arrow in the fifth figure). ) Two Γ Yu Gai said: The piece is thousands of lines in the mold flow side and the magnetic field j π 士 = no) half of the side length C. After the sealing material 罾 is compressed into the bell gland 枓 and f the mold is tightly closed, the injection head 48 starts to move downward: i = 时 When the semiconductor wafer 10 is covered with the sealing crystal 10 and the sealing material is covered, the injection The first 48 will follow the ff + f body sa sheet 10 is sealed to continue to flow into its and the cavity 4 7 gate, and the sealant material is compressed downwards, the additional space 70 between the 5 and 7 T coupons, so Use the push to push in: the J that is retained outside = will be passed along the die flow to increase the sealant material;; 2 = after the material fills the die cavity 47, the injection mold & pressure equalization . When sealing until the sealing material is hard &. Ran the moxibustion head 48 for a predetermined time to remove the molded product. Raise the mold i i f head 48 and open the mold, cut into individual units, that is, after removing the money gate, and cut

447093 五、發明說明(8) 如前所述,根據本發明之覆晶接合式半導體裝置封膠 方法,其可避免晶片與基板間之產生氣泡孔隙,並且快速 形成一封膠體來密封晶片與基板間之空隙。此外本發明另 提供一種用於封膠一覆晶接合式半導體裝.置的模具,其可 用以快速形成一封膠體來密封晶片與基板間之空隙,並且 阻止氣泡孔隙:之發生。雖然本發明之較佳實施例係以一覆 晶接合式半導體裝置加以說明,然其他利用傳遞模塑法封 膠之半導體裝置,包含,但不限於,球格陣列(BG A )半導 體封裝體,薄小輪廓封裝體(TS0P),及晶片陣列(Chip Array)封裝體,亦可使用本發明之模具及方法,而達成本 發明之目的及功效。 雖然本發明已以前述較佳實施例揭示,然其並非用以 限定本發明,任何熟習此技藝者,在不脫離本發明之精神 和範圍内,當可作各種之更動與修改。因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 〇 穩447093 V. Description of the invention (8) As mentioned above, according to the method for sealing a flip-chip bonded semiconductor device according to the present invention, it can avoid bubble voids between the wafer and the substrate, and quickly form a gel to seal the wafer and the substrate. The gap between. In addition, the present invention also provides a mold for encapsulating a flip-chip bonded semiconductor device, which can be used to quickly form a gel to seal the gap between the wafer and the substrate, and prevent the occurrence of bubble voids. Although the preferred embodiment of the present invention is described with a flip-chip bonding semiconductor device, other semiconductor devices using transfer molding encapsulation include, but are not limited to, a ball grid array (BG A) semiconductor package. The thin small outline package (TS0P) and chip array (Chip Array) package can also use the mold and method of the present invention to achieve the purpose and effect of the invention. Although the present invention has been disclosed by the aforementioned preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. 〇 stable

第12頁Page 12

Claims (1)

447093 六、申請專利範圍 、一種車導體裝置封膠γ法,其包含下列步驟: 提供一模具(molding die),其包含一模造部 / (molding portion),其具有一模穴用以容納該半導艎裝 置,一假模穴(dummy cav. ity)連接於該模穴,以及一洩氣 孔道(air vent)連接於該假模穴; 密合夾緊該模具使得該,半導體裝置係位於該模穴中; 將封膠材料注入該模穴以及假模穴中; 硬化該封膠材料;及 打開該模具以取出該模製品。 假模穴所形成 2、依申請專利範圍第1項之半導體裝置封膠方法 包含一去鑄澆道(degating)之步騎,其中該 之成型塊亦同時去除。 中一 其於 ’設 法式 方方 膠的 封合 置接 裝晶 體覆 導以 半片 之晶 項體 1導 第半 圍一 範含 利包 專置 請裝 申體 依導。 、半板 該基 4\、依申請專利範圍第1項之半導 該模具另包含: 一罐(pot〉,用以容納封膠材料(m〇ldi compound); 一澆道口(gate);及 一澆道(runner),—端連接於該罐,另 體裝置封膠方法, 其中 ng 端經由該 澆447093 6. Scope of patent application, a method for encapsulating a vehicle conductor device γ, comprising the following steps: providing a molding die, which includes a molding portion / (molding portion), which has a cavity to accommodate the half A guide device, a dummy cav.ity is connected to the cavity, and an air vent is connected to the dummy cavity; the mold is tightly clamped so that the semiconductor device is located in the mold. In the cavity; injecting the sealing material into the cavity and the dummy cavity; hardening the sealing material; and opening the mold to take out the molded product. Formation of dummy cavity 2. The method for sealing the semiconductor device according to item 1 of the patent application scope includes a step for removing the casting runner, wherein the molding block is also removed at the same time. S1 has set up the seal of French cubes to install the crystals and cover them with a half piece of crystals. The first half of the first half is a fan-shaped package. Please install the application body for guidance. The semi-conductor base 4 and the semi-conductor according to item 1 of the patent application scope include: a pot (pot) for holding a sealing compound (m0ldi compound); a gate (gate); and A runner, where the end is connected to the tank, and the other device is a method of sealing, wherein the ng end passes through the pouring 447093 六、申請專利範圍 道口(gate)遑接於該模穴。 依申請專利範圍第4項之半導體裝置封膠方法,其中 該模具另包含一通道連接該模穴以及假模穴,其中該通道 與澆道口具有大致相同的尺寸。 6 、依申請專利範圍第5項之半導體裝置封膠方法,其中 該通道之尺寸係介於0.15-0, 25毫米。 7/ —種用於封膠一半導體裝置的模具,其包含: 一罐,用以容納封膠材料; 一模造部,其具有一模穴用以容納該半導體裝置,一 假模穴連接於該模穴,以及一洩氣孔道連接於該假模穴; 一澆道口;及 一澆道,一端連接於該罐,另一端經由該澆道口連接 於該模穴, 其t,在封膠時,該封膠材料會經由該澆道以及澆道 口而充滿模穴以及假模穴。 模道 的通 置該 裝中 體其 導, 半穴 一模 膠假 封及 於以 用穴。 之模寸 項該尺 7接的 第連同 圍道相 範通致 利-—大 專含.有 請包具 申另口 依其道 、,澆 8具與 模 的 置 裝 體 導 半 勝 封 於 用 之 項 8 第 圍 利 專 請 申 依 V· .—1 — : —i-.-'a·/·/— t447093 VI. Scope of patent application The gate is connected to this cavity. The method for sealing a semiconductor device according to item 4 of the patent application, wherein the mold further comprises a channel connecting the cavity and the dummy cavity, wherein the channel and the runner gate have approximately the same size. 6. The method for sealing a semiconductor device according to item 5 of the scope of patent application, wherein the size of the channel is between 0.15-0, 25 mm. 7 / —A mold for sealing a semiconductor device, comprising: a pot for containing the sealing material; a molding part having a cavity for receiving the semiconductor device, and a dummy cavity connected to the A cavity, and a vent hole connected to the dummy cavity; a sprue mouth; and a sprue, one end of which is connected to the tank, and the other end connected to the cavity through the sprue mouth, which t, when sealing, the The sealing material will fill the cavity and the dummy cavity through the runner and the gate of the runner. The opening of the mold path should be used to guide the body, and the half-hole and one-mold rubber seals should be applied to the points. The model inch item of this rule 7 is the same as the encirclement of the road. It is profitable. It is a college diploma. You must ask Bao Shen to apply it separately. Item 8: We are invited to apply for V. .—1 —: —i -.- 'a · / · / — t 第14頁 4 47 0 9 3 六、申請專利範圍 具,萁中該通道之尺寸係介於0. 15-0, 25亳来。 1 0 、依申請專利範圍第7項之用於封膠一半導體裝置·的 模具,其中該每一假模穴係相互連通。 含複數個 該封膠方法係包 提 納封膠材 半導體裝置以及 一繞道,一端:連 1 1 、一種半導體裝置封膠方法,其中該半導體裝置係包 半導體晶片設於一基板並且電性連接至該基板, 含下列步驟: 供 料 模穴,其 小間距係 密 中; 將 硬 打 ΙΓ 具(molding die),其包含一罐1用以容 模造部,其具有一模穴用以容納該複數個 一洩氣孔道連接於該模穴;一澆道口;及 接於該罐,另一端經由該澆道口連接於該 中離澡道口最遠之半導體晶片與該模穴侧壁之最 不小於該晶片平行於模流方向邊長之一半; 合夾緊該模具使得該半導體裝置係位於該模穴 封膠材料注入該模穴中; 化該封膠材料;及 開該模具以取出該模製品。Page 14 4 47 0 9 3 VI. Scope of patent application With the size of the channel in the range of 0. 15-0, 25 亳 来. 10. The mold for sealing a semiconductor device according to item 7 of the scope of the patent application, wherein each of the dummy mold cavities is in communication with each other. The sealing method includes a plurality of semiconductor devices and a bypass, and one end: 1 1, a semiconductor device sealing method, wherein the semiconductor device includes a semiconductor wafer provided on a substrate and electrically connected to the substrate. The substrate includes the following steps: a feeding die cavity, which is densely spaced at a small distance; a hard die, which includes a pot 1 for containing a mold forming part, and has a cavity for containing the plural number A vent hole is connected to the cavity; a sprue mouth; and connected to the tank, the other end is connected to the semiconductor wafer farthest from the bath mouth and the side wall of the cavity through the sprue mouth and the least side wall of the cavity is not less than the wafer One-half of the side length parallel to the direction of the mold flow; clamping the mold together so that the semiconductor device is located in the cavity of the mold cavity sealing material injected into the cavity; turning the sealing material; and opening the mold to take out the molded product. 第15頁 1 2 、依申請專利範圍第1 1項之半導體裝置封膠方法 其中該每一模欠係相互連通。Page 15 1 2. The method for sealing a semiconductor device according to item 11 of the scope of patent application, wherein each of the molds is connected to each other.
TW089103201A 2000-02-22 2000-02-22 Encapsulating method and encapsulating mold for semiconductor apparatus TW447093B (en)

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