A7 B7 五、發明說明（r ) [發明領域] (請先閲讀背面之注意事項再填寫本頁) 本發明係有關於一種半導體封裝技術，特別是有關於 一種覆晶式（flip chip)半導體封裝技術，其可用以製造出不 易變形且散熱效能良好之覆晶式半導體封裝結構。 [發明背景] 經濟部智慧財產局員工消費合作社印製 覆晶式半導體封裝技術為一種先進之半導體封裝技 術’其與一般習知之非覆晶式封裝技術的最主要之不同點 即在於其所封裝之晶片係以倒置方式安置於基板上，亦即 B曰片之電路面及銲塾係面對基板表面安置，並藉由球柵陣 列技術（Ball Grid Array, BGA)而銲接及電性連接至基板。 然而於晶片安置於定位之後’由於球栅陣_列中之銲球的隔 離’因此晶片與基板之間會存在有一間隙。若不將此間隙 填以絕緣性之膠質填料’則由於晶片與基板二者具有不同 之熱膨脹係數’因此於高溫處理時，將易導致晶片及基板 形成疲乏性之結構破裂及電性失能。因此覆晶式半導體封 裝製程中的一項必要步驟即為覆晶底部填膠（flip_chip iinderf⑴）’藉此而將一絕緣性之膠質填料，例如為樹脂 (resin) ’填入至晶片與基板之間的間隙。 以下即配合第1A至1B圖，以圖解方式簡略說明一習 知之覆晶式半導體封裝結構及其製程。 請首先參閱第1A圖，此習知之覆晶式半導體封裝製 程之第一個步驟為預製一基板10,其材質一般為有機材 料。接著將一半導體晶片20以覆晶方式安置於基板10上， 並藉由複數個銲球30而電性連接至基板1〇。由於此些銲 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1 16002 A7A7 B7 V. Description of the Invention (r) [Field of Invention] (Please read the precautions on the back before filling out this page) The present invention relates to a semiconductor packaging technology, especially to a flip chip semiconductor package Technology, which can be used to manufacture flip-chip semiconductor packaging structures that are not easily deformed and have good heat dissipation performance. [Background of the Invention] Printed flip-chip semiconductor packaging technology by the Intellectual Property Bureau of the Ministry of Economic Affairs's consumer cooperative is an advanced semiconductor packaging technology. The main difference between it and the conventional non- flip-chip packaging technology is its packaging. The wafer is placed on the substrate in an inverted manner, that is, the circuit surface and solder pads of the B chip are placed on the surface of the substrate, and are soldered and electrically connected to each other by Ball Grid Array (BGA) technology. Substrate. However, after the wafer is placed in position, there is a gap between the wafer and the substrate due to the isolation of the solder balls in the ball grid array_row. If this gap is not filled with an insulating colloidal filler ', since both the wafer and the substrate have different thermal expansion coefficients', high-temperature processing will easily cause the wafer and substrate to form fatigued structural cracks and electrical disability. Therefore, a necessary step in the flip-chip semiconductor packaging process is to flip-chip underfill (flip_chip iinderf⑴) to fill an insulating gel filler, such as resin, into the wafer and substrate. Gap. The following is a brief description of a conventional flip-chip semiconductor package structure and its process in a diagrammatic manner with reference to FIGS. 1A to 1B. Please refer to FIG. 1A first. The first step of the conventional flip-chip semiconductor packaging process is to prefabricate a substrate 10, which is generally made of an organic material. Next, a semiconductor wafer 20 is placed on the substrate 10 in a flip-chip manner, and is electrically connected to the substrate 10 through a plurality of solder balls 30. Because these welding paper sizes are in accordance with China National Standard (CNS) A4 (210 X 297 mm) 1 16002 A7
五、發明說明（z ) 經濟部智慧財產局·員工消費合作社印製 球3〇之隔離，因此晶片20與基板1〇之 -若不將此間隙20a填以絕緣性之膠質填料丄= 於在尚溫處.理時，導致晶片2〇 ' 構破裂及電性失能。 及基板10形成疲乏性之結 請接著參閱第則，上述問題之解決方法即為進行 一覆晶底部填膠製程’於此製程中 朴Μ Λ丄 取杜τ便用一點膠針4〇來將一 絕緣性之膠質填料41，例如為谢 們马樹月曰，施加至晶片20旁側 之基板表面上。所施加之膠質填料41接著會藉由毛細作用 而自行流入至晶片20之底部間隙2〇a ’直至將間隙2〇a大 致填滿為止。此底部填膠製程完成之後’所填入之膠質填 料41即形成一底部填膠層，且此底部填膠層41會包含一 突緣部分（fi〗let)41 a於間隙20a之外側。 理論上，此突緣部分41a之寬度係大致與覆晶底部間 隙20a之南度成正比；亦即覆晶底部間隙的高度愈大，則 底部填膠層的突緣部分的寬度也就愈大；反之，覆晶底部 間隙的高度愈小’則底部填膠層的突緣部分的寬度也就愈 小。此關係如第2A至2B圖所示；其中第2A圖所示之晶 片20的底部間隙高度以好！表示，其造成之底部填膠層的 突緣部分的寬度則以K表示；而第2B圖所示之晶片20 的底部間隙高度以7/2表示，其造成之底部填膠層之突緣部 分的寬度則以％表示。於第2A圖與第2B圖所示之情況 下，若//! < //2，則％ <妒2。換言之，若將上述之習知封 裝製程應用於不同型式之晶片上，則所造成之各個底部填 膠層的突緣部分將具有不一致之寬度。而過大或過小之寬 本紙張又度適用办國菡家標準規格（210x297公釐） 16002 — 1— — — ]— — —— — - - - -----^------I I (請先閱讀背面之注意事項再填寫本頁) 447089 A7 五、發明說明（3 ) 度’均會導致晶片20與基板10易於因熱應力之影響，而 產生不必要之變形或結構破裂’因而使得所製成之半導體 封裝產品具有不佳之品質及信賴性。 有鑒於上述之缺點，半導體封裝業界因此需求一種新 的覆晶式半導體封裝技術’其可用以使得所製成之底部填 膠層的突緣部分’無論覆晶底部間隙高度之大小，均可具 有一預定之寬度。 此外’除了上述之底部填膠層突緣寬度問題外，習知 之覆晶式半導體封裝技術所製成之封裝結構體，由於其令 之基板係由剛性較小之有機材質所製成’因此易於受到應 力之影響而變形。此問題的一個解決方法即為美國專利第V. Description of the invention (z) The isolation of the printed ball 30 by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Employee Consumer Cooperative, so the wafer 20 is separated from the substrate 10-if this gap 20a is not filled with an insulating gel filler 丄 = 于 在When processed at a high temperature, the wafer's 20 ′ structure is broken and electrical disability is caused. And the substrate 10 form a fatigued knot. Please refer to the next rule. The solution to the above problem is to perform a flip-chip underfill process. In this process, Pu M Λ 丄 takes Du τ and uses a little glue pin 40. An insulative colloidal filler 41, such as Xiemen Ma Shuyue, is applied to the surface of the substrate on the side of the wafer 20. The applied colloidal filler 41 then flows into the bottom gap 20a 'of the wafer 20 by capillary action by itself until the gap 20a is substantially filled. After the completion of the underfill process, the filled underfill 41 will form an underfill layer, and the underfill layer 41 will include a flange portion 41a outside the gap 20a. Theoretically, the width of this flange portion 41a is approximately proportional to the south of the flip-chip bottom gap 20a; that is, the greater the height of the flip-chip bottom gap, the greater the width of the flange portion of the bottom filler layer. On the contrary, the smaller the height of the bottom gap of the flip-chip is, the smaller the width of the flange portion of the bottom filler layer is. This relationship is shown in Figs. 2A to 2B; the height of the bottom gap of the wafer 20 shown in Fig. 2A is good! Indicates that the width of the flange portion of the underfill layer caused by it is represented by K; and the height of the bottom gap of the wafer 20 shown in FIG. 2B is represented by 7/2. The width is expressed in%. In the cases shown in Figures 2A and 2B, if //! ≪ // 2, then% < In other words, if the above-mentioned conventional packaging process is applied to different types of wafers, the flange portions of the respective underfill layers will have inconsistent widths. Too large or too small wide paper is also applicable to the standard specifications of the country (210x297 mm) 16002 — 1 — — —] — — — — — — — — — — — — — — — II (Please read the precautions on the back before filling this page) 447089 A7 V. Description of the invention (3) Degrees 'will cause the wafer 20 and the substrate 10 to be easily affected by thermal stress and cause unnecessary deformation or structural cracking'. So that the manufactured semiconductor package products have poor quality and reliability. In view of the above-mentioned shortcomings, the semiconductor packaging industry therefore needs a new flip-chip semiconductor packaging technology 'which can be used to make the flange portion of the underfill layer produced' regardless of the height of the bottom gap of the flip-chip. A predetermined width. In addition, in addition to the above-mentioned problem of the width of the underfill layer flange, the conventional packaging structure made of flip-chip semiconductor packaging technology is easy to use because its substrate is made of a less rigid organic material. Deformation under the influence of stress. One solution to this problem is U.S. Patent No.
6,020,221 號"PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A STIFFENER MEMBER"所揭露之封裝製程此專利技術之特點在於安置 一強化構件（stiffener member)於基板上，藉此強化構件來 增加基板的應力抵抗能力，因而可防止基板因受到應力之 影響而變形。此外，該強化構件亦可同時作為一散熱結構， 用以散發晶片於實際操作時所產生之熱量。然而此專利技 術並未揭露出如何可以使得底部填膠層具有預定寬度之突 緣部分，因此其仍可能造成過大或過小之突緣寬度，致使 晶片及基板易於受到熱應力之不良影響。 [發明概述] 蓉於以上所述習知技術之缺點，本發明之主要目的便 是在於提供一種新穎之覆晶式半導體封裝技術，其可用以 i紙張尺度適用中國標準（CNS)A4 y各⑵0 χ - * ' 3 16002 經濟部智慧財產局員工消費合作杜印製 A7 B7 五、發明說明u ) j得所製成之底部填膠層的突緣部分，無論覆晶底部間隙 高度之大小’均可具有一預定之寬度β 本發明之另一目的在於提供一種新穎之覆晶式半導體 封裝技術，其可強化基板的應力抵抗能力，藉此而防止基 板因受到應力之影響而變形。 本發明的又一目的在於提供一種新穎之覆晶式半導體 封裝技術，其可使得製成之封裝結構體具有更佳之散熱效 能。 根據以上所述之目的，本發明即提供了一種新穎之覆 晶式半導體封裝結構及其製程。 廣義而言，本發明之覆晶式半導體封裝技術所提供之 封裝結構包含以下構件：（a)一基板；（b)一半導體晶片，其 以覆晶方式安置於該基板上；而安置完成後，該半導體晶 片與該基板之間存在有一覆晶底部間隙：（幻一金屬層攔霸 結構，其形成於該基板上位於該半導體晶片周圍之表面 上；該金屬層攔霸結構具有一預定厚度，且與該半導體晶 片間隔一預定寬度之狹帶區域；以及（d)—底部填膠層，其 形成於該覆晶底部間隙中，並具有一突緣部份位於該狹帶 區域上；該突緣部份之寬度大致等於該狹帶區域之寬度。 本發明之覆晶式半導體封裝技術所提供之封裝製程包 含以下步驊：（1)預製一基板，且該基板之一中央表面區域 係預定為一置晶區；（2)形成一金屬層攔霸結構於該基板上 位於該置晶區周圍之表面上；該金屬層攔霸結構具有一預 定厚度’並與該置晶區間隔一預定距離，以於該金屬層攔 裝----K----訂---------線 (請先閱讀背面之注意事項再填寫本頁) 本紙張又度適用Τϋ冢料（CNS)W規格⑵〇 x 297公爱〉 4 16002 經濟部智慧財產局員工"費合作社印製 Α7 _____Β7______ 五、發明說明（5 ) 霸結構與該置晶區之間定義出一預定寬度之狭帶區域；（3) 將一半導趑晶片以覆晶方式安置於該基板之置晶區上；安 置完成後，該半導體晶片與該基板之間存在有一覆晶底部 間隙；以及（4)將一膠質填料施加至該狹帶區域上；所施加 之膠質填料接著將自行藉由毛細作用而填入至該覆晶底部 間隙之中，且可大致被該金屬層攔霸結構所阻擋，不會流 至該狹帶區域以外之區域，藉此在該覆晶底部間隙之中形 成一底部填膠層；該底部填膠層具有一突緣部份位於該狹 帶區域上，且該突緣部份之寬度大致等於該狹帶區域之寬 度。 本發明之特點在於上述之金屬層攔霸結構可同時提供 以下三項功能：（1)可將覆晶底部填膠製程中所施加之樹脂 限制於晶片周圍之狹帶區域範圍内，不會使其流至狹帶區 域以外之區域，藉此而使得所形成之底部填膠層的突緣部 分具有預定寬度；（2)可作為一結構強化構件，使得基板不 易因受到應力而產生變形；（3)可作為散熱結構，用以散發 晶片於操作時所產生之熱量》此些特點可使得採用本發明 之封裝技術所製成之半導體封裝產品具有更佳之品質及信 賴性。 [圖式簡述] 本發明之實質技術内容及其實施例已用圖解方式詳細 揭露繪製於本說明書所附之圖式之中。此些圖式之内容簡 述如下： 第1A至1B圖（習知技術）為剖面示意圖，其中顯示一 (Μ----Κ----^--------- (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 5 16002 A7 A7 經濟部智慧財產局員工消費合作社印製 30 40 41 41a no 110a 111 120 120a 130 I 40 141 141aNo. 6,020,221 " PROCESS FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A STIFFENER MEMBER " The packaging process disclosed is characterized by placing a stiffener member on the substrate, thereby strengthening the component to increase the stress resistance of the substrate, Therefore, the substrate can be prevented from being deformed due to the influence of stress. In addition, the reinforcing member can also be used as a heat dissipation structure to dissipate heat generated by the chip during actual operation. However, this patent technology does not reveal how to make the underfill layer have a flange portion with a predetermined width, so it may still cause an excessively large or too small flange width, which makes the wafer and substrate vulnerable to the adverse effects of thermal stress. [Summary of the Invention] The shortcomings of the conventional technology described above, the main purpose of the present invention is to provide a novel flip-chip semiconductor packaging technology, which can be used in accordance with the Chinese standard (CNS) A4 y each ⑵0 χ-* '3 16002 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs, printed A7 B7 V. Description of the invention u) The flange portion of the underfill layer made by j, regardless of the height of the bottom gap of the flip chip May have a predetermined width β Another object of the present invention is to provide a novel flip-chip semiconductor packaging technology, which can strengthen the stress resistance of the substrate, thereby preventing the substrate from being deformed by the influence of the stress. Yet another object of the present invention is to provide a novel flip-chip semiconductor packaging technology, which can make the manufactured package structure have better heat dissipation performance. According to the above-mentioned object, the present invention provides a novel flip-chip semiconductor package structure and a manufacturing process thereof. Broadly speaking, the package structure provided by the flip-chip semiconductor packaging technology of the present invention includes the following components: (a) a substrate; (b) a semiconductor wafer, which is placed on the substrate in a flip-chip manner; and after the placement is completed There is a flip-chip bottom gap between the semiconductor wafer and the substrate: (a magic layer metal barrier structure formed on the substrate on the surface surrounding the semiconductor wafer; the metal layer barrier structure has a predetermined thickness And a narrow band region spaced apart from the semiconductor wafer by a predetermined width; and (d) a bottom sizing layer formed in the bottom gap of the flip-chip and having a protruding edge portion located on the narrow band region; the The width of the flange portion is approximately equal to the width of the narrow band region. The packaging process provided by the flip-chip semiconductor packaging technology of the present invention includes the following steps: (1) a substrate is prefabricated, and a central surface area of the substrate is Predetermined as a crystal placement region; (2) forming a metal layer stopper structure on a surface of the substrate located around the crystal placement area; the metal layer stopper structure has a predetermined thickness' Separate a predetermined distance from the crystal setting area for the metal layer to block ---- K ---- order --------- line (Please read the precautions on the back before filling this page) This paper is again suitable for the specifications of Tsaw Materials (CNS) W 0x 297 Public Love> 4 16002 Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs " Feed Cooperatives A7 _____ Β7 ______ V. Description of the invention (5) Ba structure and the crystal area A narrow band region with a predetermined width is defined between them; (3) half of the semiconductor wafer is placed on the wafer placement region of the substrate in a flip-chip manner; after the placement is completed, there is a flip-chip between the semiconductor wafer and the substrate; Bottom gap; and (4) applying a colloidal filler to the narrow band region; the colloidal filler applied will then fill the bottom gap of the flip chip by capillary action by itself, and can be roughly covered by the metal layer Blocked by the tyrant structure, it will not flow to the area outside the narrow zone, thereby forming a bottom glue layer in the bottom gap of the flip-chip; the bottom glue layer has a flange portion located in the narrow band Area, and the width of the flange portion is approximately equal to that of the narrow band area The feature of the present invention is that the above-mentioned metal layer barrier structure can simultaneously provide the following three functions: (1) the resin applied in the flip-chip underfill process can be limited to the narrow band area around the wafer, without It will make it flow to the area other than the narrow band area, so that the flange portion of the underfill layer formed has a predetermined width; (2) can be used as a structural strengthening member, so that the substrate is not easily deformed due to stress (3) It can be used as a heat dissipation structure to dissipate the heat generated by the chip during operation. These characteristics can make semiconductor packaging products made with the packaging technology of the present invention have better quality and reliability. [图 式[Brief description] The essential technical content of the present invention and its embodiments have been disclosed in detail in the drawings attached to this specification. The contents of these diagrams are briefly described as follows: Figures 1A to 1B (known techniques) are schematic cross-sectional diagrams, in which one (Μ ---- Κ ---- ^ --------- (Please Please read the notes on the back before filling this page) This paper size is applicable to the Chinese National Standard (CNS) A4 (210 X 297 mm) 5 16002 A7 A7 Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs Consumer Cooperatives 30 40 41 41a no 110a 111 120 120a 130 I 40 141 141a
B7 五、發明說明Ο ) 習知之覆晶式半導體封裝結構及其製程； 第2A至2B圖（習知技術）為剖面示意圖，其用以說 採用習知技術時，其所造成之底部填膠層之突緣寬度與覆 晶底部間隙高度二者之間的關係； 第3 A至3D圖為剖面示意圖，其中顯示本發明之覆晶 式半導體封裝結構及其製程；以及 第4圖顯示第3A圖所示之封裝結構的上視圖。 [圖式之標號j 10 基板 20 半導體晶片 20a 覆晶底部間隙 銲球 點膠針 膠質填料（或稱為”底部填勝層"） 底部填膠層41之突緣部分(fillet) 基板 狹帶區域 金屬層攔霸結構 半導體晶片 覆晶底部間隙 銲球 點膠針 膠質填料（或稱為’'底部填膠層"） 底部填膠層⑷之突緣部分㈤let) 16002 --------------- I---：----訂--------- {請先閱讀背面之注意事項再填寫本頁) 447089 A7 B7 五、發明說明（7 ) 150 散熱塊（heat sink) 151 散熱塊150之凹穴部分 [發明實施例詳細說明] 以下將配合第3A至3D圖及第4圖詳細揭露說明本發 明之覆晶式半導體封裝技術之一實施例。 請同時參閱第3A圖和第4圖，本發明之覆晶式半導 體封裝製程之第一個步驟為預製一基板110,其材質例如 為一有機材料’並將此基板110之一中央表面區域預先定 義成為一置晶區DBA。 接著形成一金屬層攔霸結構（metal dam)lll於基板110 上位於該置晶區DBA周圍之表面上。此金屬層攔霸結構 Π1具有一預定厚度：Γ’並與置晶區〇ΒΑ間隔一預定距離 V，藉此於金屬層攔霸結構111與置晶區DBA之間定義出 一寬度為#之狹帶區域ll〇a ^於此實施例中’金屬層攔霸 結構111之厚度Γ例如為介於5 μιη至7 0 μιη (micrometer) 之間；而狹帶區域11 〇a之寬度妒則例如為介於〇 5 mm至 2.5 mm (millimeter)之間。 請接著參閲第3B圖，下一個步驟為將一半導體晶片 120以覆晶方式安置於基板11〇之置晶區dba上，並藉由 複數個鲜球130而電性連接至基板11〇β由於此些銲球13〇 之隔離’因此晶片120與基板11 〇之間會存在有一間隙 120a，其高度以//表示。須注意的一點是，此間隙高度孖 必須預先量测得知，並於前述之形成金屬層攔霸結構j j j 的步驟中，將金屬層攔霸結構Hi之厚度『預先設計成小 Μ氏張尺度適用t國國家標準（CNS)A4規格（21Q x 297公£) (請先閱讀背面之注意事項再填寫本頁) \.裝---- K--ιί 訂------— 1·^· 經濟部智慧財產局員工消費合作社印製 16002 續： 經濟部智慧財產局員工消費合作社印製 A7 --------_ B7__ 五、發明說明（S ) 於覆晶底部間隙120a的高度斤；否則，若厚度7大於高度 孖，則將會影響覆晶銲接製程（fHp ehip bonding)之後的清 洗程序。 請接著參閱第3C圖，下一個步驟為使用一點膠針]4〇 將疋量之膠質填料141，例如為樹脂，直接施加至位於金 屬層攔霸結構U 1與晶片1 20之間的狹帶區域n 0a上。所 施加之穆質填料141接著將自行藉由毛細作用而填入至晶 片1 20與基板11 〇之間之間隙】2〇a，且可被金屬層摘霸結 構π 1所阻擋’不會流至狹帶區域n〇a以外之區域，而僅 會流向間隙120a，直至將間隙u〇a大致填滿為止。 於此覆晶底部填躁製程完成之後’所施加之膠質填料 141即形成一底部填膠層’且此底部填膠層ι41具有一突 緣部分141a位於狹帶區域η 〇3上。本發明之一項特點即 在於此突緣部分141a之寬度可大致相等於狹帶區域u〇a 之預定寬度ff;亦即於事先之佈局設計上，可將狹帶區域 110a之預定寬度妒設計成等於最佳之底部填膠層突緣寬 度’使得晶片12 0與基板π 〇二者之結合結構，具有最佳 之熱應力抵抗能力。此最佳之底部填勝層突緣寬度可預先 以實際試驗方法求得。 本發明之覆晶式半導體封裝技術的最主要優點為所形 成之金屬層攔霸結構111，其可同時提供三項功能D第― 項功能為金屬層攔霸結構111可用以將覆晶底部填膠製程 中所施加之躍質填料限制於狹帶區域11〇3之範圍内，而不 會使其流至狹帶區域ll〇a以外之區域，因此不易造成溢膠 裝----r I---訂---------線 <請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（C]N：S)A.j規格（210> 297公t ) Η 16002 447089 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（9 ) 現象’並使得所製成之底部填膠層141的突緣部分141a 可具有預定寬度《第二項功能為金屬層攔霸結構ln之金 屬材質其剛性遠大於有機材質製成之基板no，因此金屬 層攔霸結構111可作為一結構強化構件，使得基板11〇不 易因受到應力而產生變形。第三項功能為金屬層攔霸結構 111之金屬材質具有良好之導熱性，因此其可進一步作為 一散熱結構’用以散發晶片120於操作時所產生之熱量。 請接著參閱第3D圖’如要更進一步增加本發明之覆 晶式半導體封裝結構之散熱效能，可在金屬層攔霸結構 111上另再安置一散熱塊（heat sink) 150 ;此散熱塊150具 有一凹六部分151 ’用以容納晶片120。此措施可使得晶片 120於操作時所產生之熱量，可經由金屬層摘霸結構IU 和散熱塊150而散發至大氣中。 綜而言之’本發明提供了 一種具有進步性之覆晶式半 導體封裝技術’其特點在於所形成之金屬層攔霸結構可同 時提供以下三項功能：（1)可將覆晶底部填膠製程中所施加 之樹脂限制於晶片周圍之狹帶區域範圍内，不會使其流至 狹帶區域以外之區域，藉此而使得所形成之底部填膠層的 突緣部分具有預定寬度；（2)可作為一結構強化構件，使得 基板110不易因受到應力而產生變形；（3)可作為散熱結 構，用以散發晶片於操作時所產生之熱量。此些特點可使 得採用本發明之封裝技術所製成之半導體封裝產品具有更 佳之品質及信賴性°本發明因此較習知之覆晶式半導體封 裝技術具有更進步之實用性。 * _ Id n * It t i f / ^-eJI I {清先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準<CNS)A4規格<210 X 297公釐） 9 16002 A7 b/ i、發明說明（ίο ) 以上所述僅為本發明之較佳實施例而已’並非用以限 定本發明之實質技術内容的範圍。本發明之實質技術内容 係廣義地定義於下述之申猜專利範圍中。任何他人所完成 之技術實體或方法，若是與下述之申請專利範圍所定義者 為完全相同、或是為-種等效之變更’均將被視為涵蓋於 此專利範圍之中。 (請先閲讀背面之注意事項再填寫本買) 經濟部智慧財產局員工消費合作社印製 (CNS)A.i 規格（21Q X 297^^7 10 16002B7 V. Description of the invention 0) The conventional flip-chip semiconductor package structure and its manufacturing process; Figures 2A to 2B (known technology) are schematic cross-sectional diagrams, which are used to describe the underfilling caused by the conventional technology The relationship between the width of the flange of the layer and the height of the gap at the bottom of the flip-chip; Figures 3A to 3D are schematic cross-sectional views showing the flip-chip semiconductor packaging structure and its process of the present invention; and Figure 4 shows 3A Top view of the package structure shown in the figure. [Symbol of the figure j 10 substrate 20 semiconductor wafer 20a flip chip bottom gap solder ball dispensing needle gel filler (also called "bottom filling layer") fillet of the bottom filling layer 41 (fillet) substrate strip Regional metal layer stopper structure semiconductor wafer flip-chip bottom gap solder ball dispensing needle glue filler (also known as `` bottom filler ") the bottom edge of the filler layer ⑷let) 16002 ------ --------- I ---: ---- Order --------- {Please read the notes on the back before filling this page) 447089 A7 B7 V. Description of the invention (7 ) 150 heat sink 151 The recessed part of the heat sink 150 [Detailed description of the embodiment of the invention] The following will explain in detail the implementation of one of the flip-chip semiconductor packaging technologies of the present invention in conjunction with Figures 3A to 3D and Figure 4 For example, please refer to FIG. 3A and FIG. 4 at the same time. The first step of the flip-chip semiconductor packaging process of the present invention is to prefabricate a substrate 110, whose material is, for example, an organic material, and to place a central surface of the substrate 110. The area is defined in advance as a crystalline area DBA. A metal layer dam is then formed. The substrate 110 is located on a surface around the crystal-receiving region DBA. The metal layer barrier structure Π1 has a predetermined thickness: Γ ′ and is spaced a predetermined distance V from the crystal-receiving region 〇Α, thereby the metal layer barrier structure 111 A narrow region with a width # is defined between the substrate and the crystal placement area DBA. In this embodiment, the thickness of the metal layer barrier structure 111 is Γ, for example, between 5 μm and 70 μm (micrometer). The width of the narrow region 11 〇a is, for example, between 0.05 mm and 2.5 mm (millimeter). Please refer to FIG. 3B. The next step is to flip a semiconductor wafer 120 in a flip-chip manner. It is placed on the crystal placement area dba of the substrate 11 and is electrically connected to the substrate 11 through a plurality of fresh balls 130. Because of the isolation of these solder balls 13, there will be a gap between the wafer 120 and the substrate 11 There is a gap 120a whose height is indicated by //. It should be noted that the height of this gap 孖 must be measured in advance, and in the aforementioned step of forming the metal layer barrier structure jjj, the metal layer barrier structure Hi The thickness "pre-designed into a small M-scale scale suitable for t country Standard (CNS) A4 size (21Q x 297 kg) (Please read the notes on the back before filling out this page) \. 装 ---- K--ιί Order ------ 1 · ^ · Economic Printed by the Intellectual Property Bureau's Consumer Cooperatives of the Ministry of Economic Affairs 16002 Continued: Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 --------_ B7__ V. Description of the Invention (S) Height 120g at the bottom gap of the flip chip; Otherwise, if the thickness 7 is greater than the height 孖, it will affect the cleaning process after the fHp ehip bonding process. Please refer to FIG. 3C. The next step is to use a small plastic needle. 4 〇 Apply a large amount of colloidal filler 141, such as resin, directly to the gap between the metal layer stopper structure U 1 and the wafer 1 20 Band area n 0a. The applied filler 141 will then fill itself into the gap between the wafer 12 and the substrate 11 by capillary action] 2a, and can be blocked by the metal layer abstraction structure π 1 'no flow To the area other than the narrow band area noa, and only flows to the gap 120a until the gap uoa is substantially filled. After the flip-chip underfill process is completed, the applied “glue filler 141” forms an underfill layer and the underfill layer ι41 has a flange portion 141a located on the narrow band area η 03. A feature of the present invention is that the width of the flange portion 141a can be approximately equal to the predetermined width ff of the narrow band region u0a; that is, the predetermined width of the narrow band region 110a can be designed in advance in the layout design. It is equal to the optimal underfill layer flange width ', so that the combined structure of the wafer 120 and the substrate π 0 has the best thermal stress resistance. The optimal width of the underfill layer flange can be obtained in advance by actual test methods. The most important advantage of the flip-chip semiconductor packaging technology of the present invention is the formed metal layer barrier structure 111, which can provide three functions at the same time. The first function is the metal layer barrier structure 111, which can be used to fill the bottom of the flip chip. The jumping filler applied in the rubber process is limited to the narrow band area of 1103, and it will not flow to the area outside the narrow band area 110a, so it is not easy to cause overflowing .---- r I --- Order --------- line < Please read the notes on the back before filling this page) This paper size is applicable to Chinese national standard (C) N: S) Aj specification (210 > 297mm t ) 002 16002 447089 Printed A7 B7 by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (9) Phenomenon 'and make the flange portion 141a of the underfill layer 141 produced can have a predetermined width "second function The metal material of the metal layer barrier structure ln is much more rigid than the substrate no made of organic materials, so the metal layer barrier structure 111 can be used as a structural strengthening member, so that the substrate 11 is not easily deformed due to stress. The third function is that the metal material of the metal barrier structure 111 has good thermal conductivity, so it can be further used as a heat dissipation structure 'to dissipate the heat generated by the chip 120 during operation. Please refer to FIG. 3D. 'To further increase the heat dissipation performance of the flip-chip semiconductor package structure of the present invention, a heat sink 150 can be placed on the metal barrier structure 111; this heat sink 150 There is a concave six portion 151 ′ for receiving the wafer 120. This measure enables the heat generated by the chip 120 during operation to be dissipated into the atmosphere through the metal layer extraction structure IU and the heat sink 150. In summary, the present invention provides a progressive flip-chip semiconductor packaging technology, which is characterized in that the formed metal layer barrier structure can simultaneously provide the following three functions: (1) the bottom of the flip-chip can be filled with glue The resin applied in the process is limited to the narrow band area around the wafer and will not flow to the area outside the narrow band area, so that the flange portion of the underfill layer formed has a predetermined width; ( 2) It can be used as a structural strengthening member, so that the substrate 110 is not easily deformed due to stress; (3) It can be used as a heat dissipation structure to dissipate the heat generated by the wafer during operation. These features can make semiconductor packaging products made with the packaging technology of the present invention have better quality and reliability. The present invention is therefore more practical than conventional flip-chip semiconductor packaging technology. * _ Id n * It tif / ^ -eJI I (Please read the precautions on the back before filling in this page) This paper size applies to Chinese National Standards < CNS) A4 Specifications < 210 X 297 mm) 9 16002 A7 b / i. Description of the invention (ίο) The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the essential technical content of the present invention. The essential technical content of the present invention is broadly defined in the scope of the following patent applications. Any technical entity or method completed by another person, if it is exactly the same as defined in the scope of patent application below, or an equivalent change 'will be deemed to be covered by this patent scope. (Please read the precautions on the back before filling out this purchase) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (CNS) A.i Specification (21Q X 297 ^^ 7 10 16002