TW446954B - Test structure and test method for dynamic random access memory - Google Patents

Abstract

This invention is about the test structure and test method for a kind of dynamic random access memory. The characteristic of this invention is to select several test structures and to conduct the analysis of leakage currents for the word line in ON and OFF states, respectively, such that, under the condition of eliminating the factor of background noise leakage current, the leakage currents from each different sources are obtained.

Description

44695 4 V. Description of the invention (1) The present invention is based on a kind of dynamic random testing for the use of some test structures. The leakage caused by the point will inevitably produce the memory density and the accuracy of the noise leakage current test results. In addition, The traditional noise leakage current cannot be improved due to the accuracy of the contact window node. In addition, the source of traditional current, such as the leakage current at the interface, according to the above, the test structure and the test party have a large number of contact windows to precipitate the node contact window current. Its characteristics Then, the leakage current in the off state is different. The following diagrams show that the access state is random or the test flow is improved. The test is relative to the decline. This test is only required, and the test results must be tested. The method of the present invention is suitable for improving the source and drain of the selection process and the test structure and the test structure of the test memory and the electrical properties or methods of the access memory to measure the bit line nodes. However, The noise leakage current is underway, and the 'leakage current must also follow the proportion of the overall leakage current due to the structure and measurement. Diluted back to be formed about the configuration and expensive test to find contact window so to provide a manufacturing method of the electric leakage test 64Mb accuracy for a number of test analysis, current. The better implementation of the test method is due to the cost of tens of thousands to tens of noise leakage. The method can not leak the process problems caused by the process. It can be stored in the DRAM above the dynamic random, and it can remove the structure of the current and the doped region, and eliminate the background noise, especially related to the test method. For the efficiency, the storage of the capacitor and the leakage current must be reduced randomly with the dynamic measurement. At this time, the increase cannot cause the background to have a large proportion of hundreds of thousands of currents. It analyzes the leakage current and the doped region. Take the measurement of the memory ’It is not necessary to use the leakage of the junction surface in the body leakage current, and the reason why the character line is at the opening leakage current to explain the invention

Page 4 4 46 954 _ / ________________ V./Explanation (2) Brief description of formulas > Figures 1 to 5 are schematic diagrams of the test structure of dynamic random access 6 memory in one embodiment of the present invention. [Description of symbols] P ~ plug; C2 ~ storage node; C1C ~ bit line node; N-~ doped region; CI ~ contact window ion doping region, WL ~ word line; LOCOS ~ local silicon oxide layer; BL ~ bit line. Example The following is a schematic diagram of the test structure of a dynamic random access memory in an example using Figures 1 to 5. In order to eliminate the influence of background noise (J0), two test structures with different numbers of contact windows of N1 and N2 bit line nodes are first selected, for example, 5000 and 2500 bit line node contact windows, and The leakage currents obtained through electrical measurement are JN1 and JM2, respectively. Among them, the source is the background noise leakage current and the total junction leakage current of each element line node C1 C, so we can get the T column relationship: JN1 = JC1C This N1 + J0 JN2 = JC1C wood N2 + J0 According to the foregoing, the total junction leakage current of each line node c 丨 C can be obtained

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446 ^ 〇4 V. Description of the invention (3) ~ JC1C 'is as follows: JC1C = | JN2-JN1 | / | N2-N1 | In the same way, 'choose to form two test structures with different numbers of contact windows of N3, N4 storage nodes', such as 5,000 and 2500 storage node contact windows, respectively, and obtain it after electrical testing The leakage currents are JN3 and JN4, and since the source is the background noise leakage current and the total leakage current of each storage node C2 ^ the leakage current JC2 ', the following relationship can be obtained: JN3 = JC2 木 N3 + J0 JN4 = JC2 * N4 + J〇 According to the foregoing, the total junction leakage current JC2 of each storage node C2 can be obtained as follows:-JC2 = 丨 JN4-JN3 丨 / | N4-N3i. The following analysis was performed. Referring to FIG. 1, a test structure of a dynamic random access memory 'includes the following components. A semiconductor substrate 100 is, for example, a silicon substrate having a p-type well region, which has two gate regions 40, a first doped region 20, and two second doped regions 10, 30. In the case of contact windows and plugs, the N-type ion doped region can be selected as the doped region, and a contact window ion doping step must be added to form the contact window to fill the plug system. Contact γ The design of the test structure of this embodiment is also based on this principle in the subsequent Figures 2 to 5 of the holding region CI '. A one-bit line node C1C having a one-bit line plug P1C is formed on the first doped region 20 described above.

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Ir 4 4 6 9 5 4- V. Description of the invention (4) Two word lines WL 'are formed on the gate regions 40. The two storage nodes C2 'each have a storage plug p2 formed on the second doped regions 10, 30. The bit line BL is electrically connected to the bit line plug p 1 c and the storage plug P2 ′ to measure the channel inversion current j I NV when the word line WL is turned on. The aforementioned test method is as follows. First, when the character line WL is turned off, the following relationship is obtained: J (WL-OFF) = JC1C + 2JC2 + J〇; When the sub-element line WL is turned on, the following relationship is obtained: J (WL-ON) = JC1C + 2JC2 + JINV + J〇; According to the foregoing, the channel inversion current j I NV can be obtained as follows: JINV = J (WL-ON)-J (WL-OFF). Among them, J (WL-OFF): total leakage current when the character line is turned off; J (WL-ON): total leakage current when the character line is turned on; J 0: background noise leakage current; JC1C: each element line The total junction leakage current of node C1C; JC 2: the total junction leakage current of each storage node C 2; JINV; channel reversal current.

Secondly, please refer to FIG. 2 for another dynamic random access memory test structure including the following components. A semiconductor substrate 100 is, for example, a silicon substrate having a p-type well region, which has two gate regions 40, a first doped region 20, and two second doped regions 10, 30.

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A bit line plug p 1 C is formed on the first doped region 20 described in the previous bit line node C1C. Formed on the two sub-element lines W L ′ are formed on the open electrode regions 40, and the two storage Ip points C2 ′ have storage plugs μ, respectively, on the dopant regions 10 and 30. The bit line BL is electrically connected to the bit line plug pK, and is used to measure the bit line node leakage current JC1C0 caused by the contact line process of the bit line node C1C when the storage plug C2 is formed. The aforementioned test method is as follows. First, when the character line WL is closed, the following relationship is obtained: J (WL-OFF) -JC1C + JO; when the character line WL is turned on, the following relationship is obtained: J (WL-ON) = JC1C + 2JN- + JINV + JO; According to the foregoing, the leakage current at the junction between the second doped region 10 and 30 when the storage plug P2 is formed, that is, from the N-diffusion region to the P-well region, jn-: JN- = 1/2 [J (WL-ON) -J (WL-OFF) -JINV]; further, a bit line node leakage current JC1C0 caused by the contact line process of the bit line node C1C when the storage plug P2 is formed is obtained. JC1C0 = JC1C-JN-; Among them, J (WL-OFF): Total leakage current when the character line is turned off; J (ffL-ON): Total leakage current when the character line is turned on; J 0: Background noise leakage Current; JC1C: total junction leakage current of each element line node C1C;

V. Description of the invention (6) JC2: Each storage node C2 4 F $ P 4t r · The second doped region 10 and 30 when the storage plug P2 is formed is the expansion of the junction to the P well area Current; The contact window C1 C is above the doped region, that is, the N-diffusion region, and the bit line node C contacts the bit line node leakage current caused by the process. ^ Refer to Figure 3, another test structure of dynamic random access memory 'includes the following components. For example:-a silicon substrate with a p-type well region,-a first doped region 20 and two second doped regions-a semiconductor substrate 100 which has two gate regions 40, 10'30 and a single bit The line plug P 1C is formed on the first doped region 20 of the previous bit line node C 1C. Two Yuyuan lines W L 'are formed on the gate regions 40. Two storage nodes C2 are formed on the second doped regions 10 '30 [a bit line 乩, which is electrically connected to the bit line plug ρΐ (:, and is used to measure when no storage plug C2 is formed. The bit line node leakage current JC1C0 + caused by the bit line node C1C contact window process. The aforementioned test method is as follows. First, when the word line WL is closed, 'the following relationship is obtained ... J (WL-〇FF) -JC1C + JO; then when the character line WL is turned on, 'the following relationship is obtained: J (WL-〇N) = JC1C + 2JNO- + JINV + J〇; according to the foregoing, the second when no storage plug P2 is formed Leakage current at the junction between the doped regions 10 and 30 from the N-diffusion region to the p-well region JN__:

5 '446954 V. Description of the invention (Ό JN〇- = 1/2 [J (WL-ON)-J (WL-0FF) -J INV]; Further, when a storage plug P2 is not formed, Bit line node C1C contact window process caused by bit line node leakage current JC1C0 +. JC1CO + = JC1C-JN〇-; Among them, J (WL-OFF): total leakage current when the word line is closed; J (WL-0N) : Total leakage current when the word line is turned on; J 0: background noise leakage current; JC1 C: total interface leakage current of each element line node c 1 c; JN0-: the first when no storage plug P2 is formed Leakage current at the junction between the two doped regions 10 and 30N-diffusion region to the p-well region; DuniCiC0 +: above the first doped region, that is, the 1 ^ -diffusion region, is contacted by the bit line node C1C Bit line node leakage current caused by the window process. Secondly, please refer to Fig. 4, another dynamic random test structure, including the following components. Welcome to the semiconductor substrate 100, which has two hidden gate regions. 40, 10'30, for example, a silicon substrate with a P-type well region, a first doped region 20 and two second doped regions

A bit line plug p 1 C is formed on the first doped region 20 described in the previous bit line node C1 C. The: ^ word line WL is formed on the gate regions 40. The second doping J: node =: each has a storage plug P2 1 formed on the bit lines BL, and is electrically connected to the storage plug p2 for forming a bit

446954 * V. Description of the invention (8) " a '-When the element line plugs PC1C, the leakage current JC20 of the storage node is measured by the contact window process of the storage node c2. secluded

The foregoing test method is as follows. D When the character line WL is turned off, the following relationship is obtained: J (WL-OFF) = 2JC2 + J〇; When the character line WL is turned on, the following relationship is obtained: J (WL- 0N) = 2JC2 + JN- + JINV + J0; According to the foregoing, the first doped region 20 when the bit line plug P1C is formed, that is, the junction leakage current from the N-diffusion region to the P-well region jn-: JN -= J (WL-ON)-J (WL-OFF) -JINV; Further, when the bit line plug P1 C is formed, the storage node leakage current JC2 0 caused by the contact window process of the storage node C2 is obtained. JC20 = JC2-JN-. Among them, J (WL-OFF): total leakage current when the character line is turned off; J (WL-ON): total leakage current when the character line is turned on; J0: background noise leakage current; JC2: each storage node C2 The total junction leakage current: JN-: The junction leakage current of the _-doped region 20 when the bit line plug P1C is formed, that is, from the N-diffusion region to the P-well region; JC20: in the second doped region, that is, The leakage current of the storage node caused by the contact window process of the storage node C2 above the N-diffusion region. Please refer to Figure 5, another test structure of dynamic random access memory, including the following components. Page 11

5. Description of the invention (9) A semiconductor substrate 100 having two gate regions 4 0 10 and 30. The bit line node C1 C doped region is formed on the aforementioned first doped two word lines WL, and is formed on the gate regions 40. The two storage nodes C2 each have a storage insert on the second doped region 10'30. This is done by measuring the -bit secret 'electrical connector plug p2 when the bit line plug P1C is not, and measuring the storage node leakage current JC20 + from the storage node C2 contact window. The aforementioned test method is as follows ^ First, when the character line WL is turned off, the following relational formula is obtained: J (WL-OFF) = 2JC2 + J〇; then when the character line WL is turned on, the following relational formula is obtained: J (WL -〇N) = 2JC2 + JN0- + JINV + J0 > According to the foregoing, the leakage current at the junction of the first doped region 20 when the bit line plug P1C is not formed, that is, from the N-diffusion region to the p-well region jn〇—: JN0- = J (WL-〇N)-J (WL-OFF) -J INV; further, a storage caused by the contact window process of the storage node C2 when the bit line plug P1C is not formed is obtained The node leakage current JC20 + is listed below. JC20 + = JC2 ~ JN0-. Among them, J (WL-OFF): the total leakage current when the character line is closed;

1 446954 V. Description of the invention (ίο) J (WL-ON): total leakage current when conducting word lines; J 0: background noise leakage current; JC 2: total junction leakage current of each storage node C 2; JN0-: the first doped region 20 when the bit line plug pic is not formed, that is, the junction leakage current from the N-diffusion region to the P-well region; JC20 +: the first doped region is the N-diffusion region. The leakage current of the storage node caused by the contact window process of the storage node C2. In summary, the above embodiment of the present invention provides a test structure and test method for dynamic random access memory, which is applicable to 64Mb Dram and above. It does not need to use the contact window of the director to improve the test accuracy, and it can reduce the overall leakage current. In the analysis, the leakage current caused by the node contact window process and the leakage current of the doped region junction T are characterized by selecting several test structures and analyzing the leakage current of their word lines in the switching state, and then The leakage current of various sources can be obtained by eliminating the background noise leakage current. Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application.

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Claims (1)

446954 VI. Scope of patent application --- 1. Two kinds of dynamic random access memory test structures, including: a semiconductor substrate with two gate regions, a first doped region and two second doped regions A 7L line node with a bit line plug formed on the first doped region; two word lines 'formed on the gate regions; two storage nodes' each having a storage plug Is formed on the second doped regions; and a bit line is electrically connected to the bit line plug and the storage plug to measure a channel inversion current when the word line is turned on. γ 2. A test structure of dynamic random access memory, including: a semiconductor substrate 'with two gate regions, a first-doped region and two second doped regions: a bit line node, with A bit line plug is formed on the first doped region; two word lines are formed on the gate regions; and two storage nodes respectively have storage plugs formed on the second doped regions. On the miscellaneous area; and a bit line electrically connected to the bit line plug 'for measuring the bit line γ node leakage current caused by the bit line node contact window process when the storage plug is formed. 3. —A test structure of a dynamic random access memory ’includes: a half-lead chain substrate having two gate regions, a first doped region and two second doped regions; 4469 5 4 VI. Patent Application One-bit line node with one-bit line plug formed on the first doped region; two word lines formed on the gate regions; two storages A node formed on the second doped regions; and a bit line electrically connected to the bit line plug for measuring a contact window process by the bit line node when the storage plug is not formed Bit line node leakage current caused. 4. A test structure for dynamic random access memory, comprising:-a semiconductor substrate having two gate regions, a first doped region and two second doped regions; γ a bit line node having a A bit line plug is formed on the first doped region, and two word lines are formed on the gate regions; two storage nodes, each having a storage plug, are formed on the second doping regions; And a bit line electrically connected to the storage plugs to measure the storage node leakage current caused by the storage node contact window process when the bit line plug is formed. 5. A dynamic random access memory test structure, including: a semiconductor substrate having two gate regions, a first doped region and two second doped regions; a bit line node forming On the first doped region; two word lines formed on the gate regions; and two storage nodes, each having a storage plug, formed on the second Page 15 446954 t, on the doped area of the patent application range; and a bit line electrically connected to the storage plugs for measuring the contact window process of the storage node when the bit line plug is not formed Caused by storage node leakage current. 6. —A test method for the first test structure of the scope of patent application, including closing the character line and obtaining the following relationship: J (WL-〇FF) = JC1C + 2JC2 + J0; Turn on the character line and obtain the following Relational formula: J (WL-〇N) = JC1C + 2JC2 + JINV + J0; Obtain a channel inversion current JINV according to the foregoing, as described in the following formula: JINV = JKWI ^ -ON)-J (WL-OFF); Where J (WL-OFF): total leakage current when the character line is turned off; J (WL-ON): total leakage current when the character line is turned on; J 0: background noise leakage current; J C1 C: each element Line junction total junction leakage current; JC 2: Total junction leakage current of each storage node; JINV: Channel reversal current. 7. —A test method for the second test structure of the scope of patent application, including closing the character line and obtaining the following relationship: J (WL-0FF) = JC1C + J0; turning on the character line and obtaining the following relationship: 4469 54 6. Scope of patent application J (WL-〇N) = JClC + 2JN- + JINViJ〇 According to the foregoing, a leakage current at the junction of the second doped region when the storage plug is formed JN-: JN- = 1/2 [J (WL-0N)-JUI ^ -OFFVJINV]; Further, when the storage plug is formed, the bit line node leakage current JC1C0 caused by the bit line node contact window process is obtained as follows: Said: JC1C0 = JC1C-JN-; Among them, J (WL-0 FF): total leakage current when the word line is closed; J (WL-ON): total leakage current when the word line is turned on; J 0: Background noise leakage current: J C1 C: Total junction leakage current of each element node; JC 2 · _Total junction leakage current of each storage node JN-: The second doped region when a storage plug is formed Surface leakage current; JC1C0: above the first doped region, the bit line node leakage current caused by the bit line node contact window process. 8. —A test method for the third test structure of the scope of patent application, including: closing the character line and obtaining the following relationship. J (WL-0FF) = JC1C + J0; when the character line is turned on, the following relationship is obtained Formula: J (WL-ON) = JC1C + 2JN0-rJINV + J〇 · According to the rule, a second doped region is formed when there are no __xiu 4 memory plugs Page 17 446954 Junction leakage current J Ν Ο · ~: JN〇- = 1/2 [J (WL-ON)-J (WL-0FF) -J INV]; Further, when the storage plug is not formed, Bit line node leakage current caused by bit contact window process JC1C0 +: JC1C0 + = JC1C-JN0-; Among them, J (WL-OFF): Total leakage current when the word line is closed; J (WL-0 N): On Total leakage current when word line; J 0: background noise leakage current; J C1C: total junction leakage current of each element line node; JN 0-: second doping F when no storage plug is formed ^ Junction leakage JC1C0 +: above the first doped region, the bit line node leakage current caused by the bit line node process. #Touch_ 制 9_ A test structure for the fourth test scope of the patent application scope: '、 成 方法' includes closing the character line and obtaining the following relationship: J (WL-OFF) = 2JC2 + JO; connected by the storage node First doped region Turn on the word line WL to obtain the following relationship: J (WL-ON) = 2JC2 + JN- + JINV + J0; According to the foregoing, a junction leakage current JN formed with the bit line plug JN: JN- = J (WL-ON)-J (WL-〇FF) -JINV; Further, when the bit line plug is formed, Page 446 954 6. Leakage current of storage node caused by the window-touching process of patent application scope JC20: JC20 = JC2-JN-; Among them, J (WL-OFF): Total leakage current when the character line is closed; J (WL-ON): On Total leakage current when word line; J 0: Background noise leakage current; JC 2: Total junction leakage current of each storage node; JN-: Technique of forming the first doped region when bit line plug is formed & ~ Leakage current of money surface; JC20: Above the second doped region, the storage node leakage current caused by the storage node contact window process. 1 0.—A test method for the fifth test structure of the scope of patent application, including: ^ Close the character line and obtain the following relationship: J (WL-0FF) = 2JC2 + J0; Connect the character line to obtain The following relationship: J (WL-〇N) = 2JC2 + JN0- + JINV + J0; According to the foregoing, a junction leakage current JN 0 of the first doped region when the bit line plug is not formed is obtained according to the foregoing: JNO- = J (WL-ON)-J (WL-0FF) -J INV; further, a storage node leakage current JC20 + caused by the storage node contact window process when the bit line plug is not formed is as follows Listed by the formula: JC20 + = JC2-JN0-; Page 19 • 446954 VI. Patent application scope J (WL-OFF) ·· Total leakage current when the character line is turned off; J (WL-ON): Total leakage current when the character line is turned on; J 0: Background is miscellaneous Signal leakage current: JC2 ·· Total junction leakage current of each storage node C2; J NO-: Interface leakage current in the first doped region when no bit line plug is formed; JC20 +: In the second doping region Above the region, the leakage current of the storage node caused by the process of the contact window of the storage point. 11. A test method for dynamic random access memory, comprising: forming two test structures with N1 and N2 bit line node contact windows; and, conducting electrical tests to obtain leakage currents JN1 'jN2, respectively, of which The source is a background noise leakage current j 〇 and the total junction leakage current JC1C of each element line node according to the following relationship: JN1 = JCIC ^ NI + J0; JN2 = JC1C * N2 + J0; get each element line according to the foregoing The total junction leakage current at the node JC1 c is as follows: JC1CHJN2-JN1 | / | N2-N1 丨. 1 y. The test method described in item 11 of the scope of patent application, comprising: forming two test structures with N3, N4 storage node contact windows; conducting electrical tests to obtain leakage currents jN3, JN4, respectively, where Its origin = is a background noise leakage current J0 and the total junction leakage current JC2 of each storage node according to the following relationship: 446954 6. Scope of patent application JN3 = JC2 * N3 + J0; JN4 = JC2 wood N4 + J0; According to the foregoing, the total junction leakage current JC2 of each storage node is obtained as follows: JC2 = | JN4-JN3! / | N4-N3 |. Page 21