TWI230997B - Test pattern for cell capacitance measurement - Google Patents

Abstract

A test pattern for measuring the capacitance of capacitors in a dynamic random access memory (DRAM) is presented. This invention is providing a test pattern similar to the desired circuit, parallel running a plurality of desired deep trench capacitors, and measuring the capacitance of the desired capacitors. The gate oxide producing most noise in the capacitance measurement is removed from said test pattern. Therefore, not only more exactly monitor can be provided for capacitance measurement, but also more process control monitor (PCM) parameter can be offered to customers.

Description

1230997 ___--- 5. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a test pattern of a kind / integrated circuit, and in particular to a 4-channel trench for checking dynamic random access memory Test pattern for capacitor capacitance. 2. [Previous Technology] In the manufacturing process of integrated circuits, 'the test of each component in the integrated circuit can not only provide accurate monitoring of the process of forming each component, but also provide a copy when the final product is output' Detailed information about the electrical parameters (P r 0 cess control m ο nitor) of each component in the integrated circuit is given to the customer as the quality guarantee of the output product. The first figure is a top view of a dynamic random access memory layout. The first figure includes the first bit line 1 1 0, the second bit line 1 2 0, the third bit line 1 3 0, and the first word line 1 4 0, and the second word line 1 5 0, the third character line 16 0, the fourth character line 1 70, the fifth character line 1 8 0, and the sixth character line 1 9 0. The word lines are parallel to each other, the bit lines are parallel to each other, and the word lines and bit lines are perpendicular to each other. The above-mentioned trench dynamic random access memory also includes a complex array of deep trench capacitors located at the intersection of the character line and the bit line. For example, the first ice trench capacitor 200, the second deep trench capacitor 210, the third deep trench electric valley device 2 2 0, the fourth deep trench capacitor 2 3 0, the fifth deep trench capacitor 2 4 0 ′, and The sixth deep trench capacitor is 250 °. The above ditch dynamics

1230997 V. Description of the invention (2) The machine access memory further includes a bit line contact window (bit 1 inec ο ntact) of the complex array located between two adjacent word lines, such as the first bit in the first figure Yuan line contact window 260, second bit line contact window 270, third bit line contact window 280, and fourth bit line contact window 290. Because each group of deep trenches has a capacitance measuring instrument, if you want to measure the above, you need to set more than 1000 deep deep trench capacitor banks. However, in addition to the capacitance of the container in the conventional technology, the equivalent capacitance , Gate oxygen signal. Therefore, the capacitance of the device is known. This is because the capacitance of each of the deep trench trench capacitors that can be detected by the trench capacitor is sufficient when the deep trench device formed by the parallel connection also contains the capacitance of the complex array container. The resistance method of the layer is not that the gate oxide layer formed by the above-mentioned channel capacitor bank will have a gate capacitance of about 30 ~ 40 fF, and a small value of about 7 ~ 10 pF. Due to the capacitance of the capacitors, they must be connected at least in parallel, so that they can be measured by measuring instruments. Measure the gate oxide of the deep trench you want to measure, and other miscellaneous and accurate measurements of the deep trench capacitance. At least 1 000 groups of deep trench capacitors, in addition to containing deep trench capacitance. Therefore, the measurement of the electrical oxidation layer in deep trenches is included in the calculation. Therefore, in order to provide more detailed electrical parameters, the present invention provides a test pattern capable of accurately measuring the capacitance of a deep trench capacitor on an integrated circuit. Summary of the Invention

Page 6 1230997 V. Description of the invention (3) In view of the above-mentioned background of the invention, the conventional technology has many shortcomings in measuring the capacitance of a deep trench capacitor. The main purpose of the present invention is to provide a product. The test pattern of the bulk circuit enables the above-mentioned deep trench capacitors to measure their capacitance without incorporating noise from the gate oxide layer into the measured values, which causes errors in the measurement of deep trench capacitors, and The electrical parameters of the capacitance of the deep trench capacitor can be obtained smoothly. ρ According to the above-mentioned object, the present invention provides a method for inspecting the capacitance of a deep trench capacitor in an integrated circuit. The above method is to provide a set of test patterns that are similar to the circuit device to be measured, and then connect a sufficient number of deep trench capacitors in parallel to measure the capacitance of the deep trench capacitors with a measuring instrument. Since the gate oxide layer that may cause the main noise in the capacitance measurement has been removed from the test pattern of the present invention in the present invention, in addition to detecting the deep trench capacitor, it is not in the present invention. The noise of the gate oxide layer will be measured in the same way as the conventional technique. Therefore, the test pattern in the present invention can effectively check the capacitance of the deep trench capacitor to be tested, and thus can provide more detailed electrical parameters for the produced product. 4. [Embodiments] Some embodiments of the present invention will be described in detail as follows. However, in addition to the detailed description, the present invention can be widely implemented in other embodiments, and the scope of the present invention is not limited, which is subject to the scope of subsequent patents.

1230997 V. Description of the invention (4) A preferred embodiment of the present invention is a test pattern of a dynamic random access memory (DRAM). The second figure is a top view of a partial area of the test pattern of the dynamic random access memory formed according to the present invention. The above test pattern includes a plurality of arrayed conductive band patterns, such as the first bit line pattern 300, the second bit line pattern 310, and the third bit line pattern 32, as shown in the second figure. The bit line patterns are parallel to each other. The above test pattern also includes a complex array of deep trench capacitor (^ e ^ p trench capacitor) patterns. As shown in the second figure, the first person pattern 31S) has a first deep trench capacitor pattern 3 3 0 and a second deep trench capacitor pattern 3 4 0; a third bit line pattern 3 1 0 has a third Deep trench = electrical = device pattern 3 5 0 and fourth deep trench capacitor pattern 3 6 0; on the first: 1 * Ergu cloth-Weifan line pattern 3 2 0 has a fifth deep trench capacitor pattern 3 7 0 and the first器 380。 380. 2. Ice trench capacitance The above test pattern further includes a line array of bit contact windows. The first bit line contact window pattern ^ is on the first bit line pattern 300, and is located between the first deep trench capacitor "and the second deep trench capacitor pattern 3 4 0; the second bit line ^ back, 3 3 0 Case 4 0 and the third bit line contact window pattern 4 are located on the second bit-touch 1 picture 310 and are located on the third deep trench capacitor pattern 37. Fish = line pattern trench capacitor pattern 36 Relative outer side of 0; fourth bit line 觞, brother four deep ditch funeral window pattern 420

Page 8 1230997 V. Description of the invention (5) is located on the third bit line pattern 3 2 0 and between the fifth deep trench capacitor pattern 3 7 0 and the sixth deep trench capacitor pattern 3 8 0. From the above description of the test pattern, it can be found that the greatest feature of the present invention is that the test pattern used in the above embodiment does not include any character line pattern used to define the character line. This is because the purpose of the present invention is to accurately measure the capacitance of a deep trench capacitor on a semiconductor substrate after transferring the above measurement pattern to a group of semiconductor substrates. However, in the conventional art, when measuring the capacitance between deep trench capacitors, in addition to measuring the required deep trench capacitor capacitance, some other noise (no ise) will also be measured, making the above measurement The correct capacitance of deep trench capacitors cannot be obtained. The noise that affects the detection includes the equivalent capacitance of the gate oxide layer, the resistance of the gate oxide layer, and other electronic noise such as this. The most significant influence is the gate oxide layer of the word line. Therefore, the biggest feature of the test pattern of this embodiment is to keep other elements and remove all the word line patterns. Since no character line pattern is formed in the above measurement pattern, after transferring the above measurement pattern to the semiconductor substrate, when measuring the capacitance of the deep trench capacitor, no and word will be measured. Noise related to the gate oxide of the element wire. In this way, noise during capacitance measurement can be reduced, and the accuracy of capacitance measurement can be greatly improved. Therefore, after sufficient deep trench capacitors are connected in parallel to form a deep trench capacitor bank, the above deep trench can be measured using a measuring instrument.

1230997 V. Description of the invention (6) The capacitor bank is measured, and then the total capacitance measured is evenly distributed to each deep trench capacitor in the above deep trench capacitor bank, and the capacitance of each deep trench capacitor can be obtained. Another preferred embodiment of the present invention is a method for measuring the capacitance of a deep trench capacitor of a dynamic random access memory (DRAM). First, a set of test patterns as described in the above embodiments is formed on a set of photomasks. The test pattern is then transferred to a group of semiconductor substrates, so that the semiconductor substrate includes a first bit line, a second bit line, a third bit line, a first deep trench capacitor, and a second deep Trench capacitor, third deep trench capacitor, fourth deep trench capacitor, fifth deep trench capacitor, sixth deep trench capacitor, first bit line contact window, second bit line contact window, third bit line contact window And the fourth bit line contact window and other components corresponding to the above test pattern. After the transfer of the test pattern is completed, the capacitance measurement of the deep trench capacitor can be started. The deep trench capacitors in the above 1000 semiconductor substrates are connected to each other in parallel, so that the total capacitance of the deep trench capacitor bank formed after the parallel connection can be measured using a capacitance measuring instrument. Then use a measuring instrument to detect the total capacitance of the deep trench capacitor bank, and divide the obtained total capacitance by the number of deep trench capacitors contained in the above deep trench capacitor bank. The capacitance of each group of deep trench capacitors can be obtained. As mentioned above, no word line pattern is formed in the test pattern used, in other words

Page 10 1230997 V. Description of the invention (7) In the above, no word line will be formed on the above semiconductor substrate. Therefore, in this embodiment, when measuring the capacitance of the deep trench capacitor, in addition to the capacitance of the deep trench capacitor, no noise about the gate oxide layer of the word line is detected. When measuring the capacitance of deep trench capacitors, in addition to the noise related to the gate oxide layer described above, the noise has a very small impact on the detection results. It's even negligible. Therefore, the method of the present invention can accurately measure the capacitance of a deep trench capacitor in a dynamic random access memory (DRAM), and it will not add the speculative result to the measurement result when measuring the capacitance as in the conventional art. Too much noise. The electric circuit of the Central Electricity Bureau in the electric trench of the electric test canal is located in the deep road. The electric power is borrowed from the system, and the deposit is stored. The machine description is based on the current state of ilfc. As the example shows, the depth of the telecommunications channel is described in the above measurement, and it can be added. The low-capacity and large-capacity large-capacity device 'Yongshi Mingpin' is the real thing, and it is true that the time to get the electricity is equal to the time. The effect of the electric power station is to make sure that the static elimination is correct and detailed for the delivery. 'The outdoor guest's rationality of the number and parameters of the parameters is limited to show the use of IPP Jin and Mingming, the original has been issued, but the exception is not implemented, it is better and more extraordinary. The application is clearly stated in the statement of the application, and the package should be repaired or modified. End within the range IF— ΊΊ 神 ^ 1

1230997 The drawings briefly explain the above-mentioned objects and advantages of the present invention. The following examples and diagrams will be used to explain in detail as follows. Among them: The first picture is a test of deep trench capacitors used to measure integrated circuits in the conventional art. A top view of the pattern; and a second view is a top view of a test pattern according to the disclosed technology. Symbols of the main part ... 110 first bit line 120 second bit line 130 third bit line 140 first character line 150 second character line 160 third character line 170 fourth character line 180 Fifth character line 190 Sixth character line 2 0 0 First deep trench capacitor 210 Second deep trench capacitor 2 2 0 Third deep trench capacitor 2 3 0 Fourth deep trench capacitor 24 0 Fifth deep trench capacitor

Page 121230997 Brief description of the drawing 2 5 0 Sixth deep trench capacitor 2 6 0 First bit line contact window 2 7 0 Second bit line contact window 2 8 0 Third bit line contact window 2 9 0 No. Four bit line contact window 3 0 0 First bit line pattern 310 Second bit line pattern 3 2 0 Third bit line pattern 3 3 0 First deep trench capacitor pattern 34 0 Second deep trench capacitor pattern 3 5 0 Third deep trench capacitor pattern 3 6 0 Fourth deep trench capacitor pattern 3 7 0 Fifth deep trench capacitor pattern 3 8 0 Sixth deep trench capacitor pattern 3 9 0 First bit line contact window pattern 4 0 0 Second Bit line contact window pattern 410 Third bit line contact window pattern 42 0 Fourth bit line contact window pattern

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Claims (1)

1230997 VI. Application for patent scope 1. A test pattern for measuring capacitance in a integrated circuit, the test pattern includes: a plurality of conductive band patterns in which the conductive band patterns are parallel to each other; a plurality of capacitor patterns in which the capacitor patterns Located on the conductive strip patterns; and a plurality of contact window patterns on the conductive strip patterns, wherein the contact window patterns and the capacitor patterns are separated from each other. 2. The test pattern of item 1 in the scope of patent application, wherein the integrated circuit is a dynamic random access memory. 3. For the test pattern in the first patent application, the conductive band patterns are used to define the current line. 4. For the test pattern in the scope of patent application item 1, the capacitor patterns are used to define trench electrical appliances. 5. For example, the test pattern of the scope of patent application, wherein the capacitor patterns include a first capacitor pattern, a second capacitor pattern, a third capacitor pattern, a fourth capacitor pattern, a fifth capacitor pattern, and A sixth capacitor pattern, wherein the first capacitor pattern and the second capacitor pattern are located on one of the conductive band patterns, and the third capacitor pattern and the fourth capacitor pattern are located on the other of the conductive band patterns. One pass Page 14 1230997 VI. Scope of patent application The conduction band pattern is on, and the fifth capacitor pattern and the sixth capacitor pattern are on another conduction band pattern of the conduction band patterns. 6. The test pattern of item 1 in the scope of patent application, wherein the contact window patterns are used to define bit line contact windows. 7. For example, the test pattern in the scope of the patent application, wherein the contact window patterns include a first contact window pattern, a second contact window pattern, a third contact window pattern, and a fourth contact window pattern, wherein The first contact window pattern and the first capacitor pattern are located on the same conductive strip pattern, and between the first capacitor pattern and the second capacitor pattern, the second contact window pattern and the third contact window pattern and the A third capacitor pattern is located on the same conductive strip pattern, and is located on the opposite outer side of the third capacitor pattern and the fourth capacitor pattern, and the fourth contact window pattern and the fifth capacitor pattern are located on the same conductive strip pattern, and Located between the fifth capacitor pattern and the sixth capacitor pattern. 8. —A test method for measuring capacitance in a integrated circuit, the method includes at least: providing a test pattern, the test pattern includes a plurality of arrays of conductive band patterns parallel to each other, and the plurality of array capacitor patterns are located on the conductive band patterns, And a plurality of contact window patterns on the conductive strip patterns, wherein the conductive strip patterns and the contact window patterns are separated from each other; transferring the test pattern to a semiconductor substrate so that the semiconductor substrate has Page 15 1230997 6. The scope of the application for a patent includes the conductive band of the complex array, the capacitor of the complex array, and the contact window with the complex array; the capacitors of the complex array are connected in parallel to form a capacitor bank; the total power of the capacitor bank is measured Capacity; and the total capacitance of the capacitor bank divided by the number of capacitors in the capacitor bank to obtain the capacitance of each capacitor. 9. The test method according to item 8 of the scope of patent application, wherein the integrated circuit is a dynamic random access memory. 10. The test method according to item 8 of the scope of patent application, wherein the capacitor patterns are used to define trench capacitors. 1 1. The test method according to item 8 of the scope of patent application, wherein the conductive band patterns are used to define bit lines. 1 2. According to the test method of claim 8 in the scope of patent application, the step of transferring the test pattern to the semiconductor substrate includes forming a first conductive tape and a second conductive tape on the semiconductor substrate. A third conduction band, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a first contact window, a second contact window, a first Three contact windows and a fourth contact window, wherein the capacitors and the contact windows are formed on the conductive strips. Page 16 1230997 VI. Application for patent scope 1 3. For the test method of patent application scope No. 1.2, in the above steps of transferring the test pattern to the semiconductor substrate 1 2 3 4 5 further includes forming the first A capacitor pattern and the second capacitor pattern on the first conduction band pattern, forming the third capacitor pattern and the fourth capacitor pattern on the second conduction band, and forming the fifth capacitor pattern and the sixth capacitor A pattern is formed on the third conductive strip. The test item in the French test is more intermediate -2 on the IX material d bottom circle 々 巳 fi "r J Daohe-F semi-specialists please call Li to Shen η case as shown in Figure 4 1 test Φ 彡 the first move spear Haicheng included in 1 package, connected to the first shape, and the case of the pattern device, the container capacitor, the third battery, the second one, the window and the case, the third device, the capacity, and the one window, and the connection. The second window should touch the fourth window. In this case, there are six pairs of capacitors and capacitors on the outside side of the case. Figures and devices on the side of the case are shown in Figure 5. The test method for item 8 in the scope of patent application, where The contact window pattern is used to define a bit line contact window. Page 17 1 6. A test pattern for measuring capacitance in a dynamic random access memory, the test pattern includes: 2 a conductive strip pattern, including a first conductive strip pattern, and a second conductive strip pattern. And a third conductive band pattern, wherein the conductive band patterns are parallel to each other; 4 a first capacitor pattern, the first capacitor pattern is located on the first conductive band 5 pattern; 1230997 VI. Patent application scope a second capacitor pattern The second capacitor pattern is located on the first conductive band pattern and is separated from the first capacitor pattern; a third capacitor pattern, the third capacitor pattern is located on the second conductive band pattern; a fourth capacitor pattern The fourth capacitor pattern is located on the second conductive band pattern and is separated from the first capacitor pattern; 'a fifth capacitor pattern, the fifth capacitor pattern is located on the third conductive band pattern; a sixth capacitor pattern The sixth capacitor pattern is located on the third conductive band pattern and is separated from the first capacitor pattern; a first A touch window pattern, the first contact window pattern is located on the first conductive strip pattern and between the first capacitor pattern and the second capacitor pattern; a second contact window pattern and a third contact window pattern, wherein The contact window patterns are located on the second conductive strip pattern, and are located outside of the third capacitor pattern and the fourth capacitor pattern; and a fourth contact window pattern, the fourth contact window pattern is located on the third conduction On the strip pattern and between the fifth capacitor pattern and the sixth capacitor pattern, wherein the conductive strip patterns and the contact window patterns are separated from each other. 1 7. The test pattern according to item 16 of the patent application scope, wherein the capacitor pattern is used to define a deep trench capacitor. 18. The test pattern of item 16 in the scope of patent application, wherein the conductive bands Page 18 1230997 6. Scope of patent application The pattern is used to define bit lines. 19. The test pattern of item 16 in the scope of patent application, wherein the contact window patterns are used to define bit line contact windows.