TW445651B - Thin film transistor device structure and manufacturing method thereof - Google Patents

Abstract

A thin film transistor device structure and manufacturing method thereof are revealed, wherein a planarized layer formed of a polymer material is added on the dielectric layer to reduce the probability of short circuit among different metals. This planarized layer can reduce the capacitance value of the crossover capacitance to thereby reduce the circuit delay time of the liquid crystal display panel. In addition, to increase the transmittance of the liquid crystal display panel, the gate of this thin film transistor device is formed under the data line.

Description

445 65 1

The invention relates to a thin film transistor (Thin Fi im Transistor 'abbreviated as ft) element structure and a manufacturing method thereof, and in particular to a thin film transistor element structure and a manufacturing method thereof for reducing short circuit between different metal layers. As far as today's displays are concerned, the liquid crystal display (Li qUid Crystal Display 'referred to as LCD) is a kind of display with great potential. Because of its advantages of low radiation and small size, LCD monitors can be used in many applications, such as screens used in notebook computers. Due to the low radiation of LCDs, which are relatively harmless to the human body, some desktop computers have also begun to use liquid crystal displays to replace traditional cathode ray tube (CRT) displays. According to the components used in liquid crystal displays, they include: Super-Twisted Nematic (STN) -LCD and Thin Film Transistor (TFT) -LCD. In terms of viewing angle breadth, since STN-LCD systems are more restricted, they are gradually being replaced by TFT-LCDs with larger viewing angle breadths. Please refer to Figure 1, which shows the equivalent circuit diagram of the LCD panel. FIG. 1 only illustrates a case where three scan lines 101 and three data lines 102 are included. Of course, the actual LCD panel contains not only three data lines and scan lines, but Figure 1 is a simple diagram. In FIG. 1, a crossover capacitor exists at a crossover of each of the scanning lines 101 and the data lines 102. The cross capacitor is used to determine the delay time of the LCD panel. If the capacitance of this cross capacitor is larger, the delay time is longer.

445651 V. Description of Invention (2) The same is true. FIG. 2 is a cross-sectional view showing a structure of a cross capacitance region in a conventional TFT element. Please refer to FIG. 2 'The cross capacitance region 200 is formed by a scan line layer 201, a dielectric layer 202, and a data line layer 203. The scan line layer 201 and the data line layer 203 are metal layers. As the name suggests, the scan line layer 201 / data line layer 203 is used to form the scan lines and data lines as shown in Figure 1. The scan line layer 201 is, for example, the gate of a TFT element. The second figure is to omit the source and the drain of the TFT element. Those skilled in the art can know the source and the drain by this. position. The process of the dielectric layer 202 in Figure 2 can be divided into the following two methods: (1) SiOx is deposited and then obtained by hydrogen plasma hydrogenat ion; or (2) silicon nitrogen Compounds (SiNx) are obtained by high-temperature tempering (anneai ing) deposition. However, in the manufacturing process of TFT elements, in addition to maintaining the minimum characteristics of the element, such as the magnitude of the on-current and the threshold voltage, the short circuit between metal wires must also be reduced. Because the short circuit between different metal layers will cause the system to be overloaded during driving, and the system will not work properly. Please refer to Figure 3, which shows a cross-sectional view of a structure with holes in the capacitor region of a traditional TFT element. The cross capacitor region 300 includes a scan line layer 301, a dielectric layer 302, and a data line layer 303. In FIG. 3, the defect refers to the appearance of a pin hole 304. Because when the dielectric layer 302 is formed, the holes 304 will appear on the edges of the scan line layer 301. If there are holes 3 04

445 65 1 V. Description of the invention (3) Appears at the position as shown in Fig. 3 '. In the subsequent process, when the data line layer 303 is deposited, the data line layer 303 will fill this hole 304. This will cause the data line layer 303 to contact the scanning line layer 301. ^ Because the data line layer 303 and the scanning line layer 301 are both conductive layers, when the holes appear as shown in Figure 3, this cross Capacitor area 300 will produce short between different metal layers.

Road condition D In order to reduce the chance of short circuits between different metal layers, traditional methods have been developed to etch the edges of the bottom layer (ie, the scan line layer) metal into tapes. FIG. 4 is a cross-sectional structure diagram of a cross capacitance region of a TFt device obtained by a conventional improvement method. As shown in FIG. 3, the alternating capacitor region includes a scan line layer 401, a dielectric layer 402, and a data line layer 403. The edge of the scanning line layer 401 is etched into a strip shape. In this way, the subsequent dielectric layer 402 can have a better step coverage effect to reduce the probability of occurrence of holes. To reduce the occurrence of different metal layers

The probability of a short circuit. However, this method needs to etch the underlying gold layer into a strip, which increases the complexity of the process. D In addition, the probability of hole formation can be reduced by improving the cleaning step before the dielectric layer is deposited. However, 'improved cleaning steps must After a considerable number of experimental verifications, and the stability of each process must be strictly controlled to maintain a fixed level, it also leads to an increase in the complexity of the process. In view of this, an object of the present invention is to provide an effective structure of a thin film transistor (TFT) device and a method for manufacturing the same. With the present invention, it is not necessary to etch the underlying metal c (ie, the scan line layer) into a strip, and

44565 1 V. Description of the invention (4) Special control of the yield of metal parts with low dielectric layer. According to the present structure and its manufacturing layer. The occurrence of shortness between the flat metal layers can reduce the circuit delay of the board. 1§ The panel is under the data line. For the sake of understanding, the following is specifically explained as follows: ---- Cleaning steps before layer deposition. a ^ Use of the present invention can greatly reduce the ^ base of the short circuit between the wires '' human network drop ^ ^, and significantly improve the TFT element's purpose of the method " layering system of the machine's turn-on and turn-off time. The light transmittance can be used to indicate a better 'proposed ~ recorded β 士士 政 ⑽ "special film transistor (TFT) element # Α π a # I In the example, the system is increased-flat ^ above, use To reduce different gold rates. By appropriately selecting the capacitance value of the material capacity of the flattening layer, ^^ can be reduced to further reduce the liquid crystal display surface. In addition, using this rhyme V ΗΒ -Λ- -Γ ® JiA V-a 夂 fming, you can also increase the liquid crystal 'only It is necessary to set the gate of this thin transistor element. The purpose, features, and advantages can be more obvious and easy to implement. In conjunction with the accompanying drawings, a simple explanation of the drawings is given in detail: FIG. 1 shows a liquid crystal display panel. Equivalent circuit diagram. The structure of the cross-capacitance area in the device is quite different. Fig. 3 is a cross-sectional view of the structure of the cross capacitance region with holes formed in the conventional TFT element. Fig. 4 is a green cross-sectional view of the structure of the cross capacitance region in the conventional TFT element after modification. $ 5A ~ 5C are cross-sectional views showing the structure of a TFT device process according to a preferred embodiment of the present invention. Label description:

445 65 1 V. Description of the invention (5) Data line 102 101: Scan line 103: Cross capacitor 200, 300, 400, 500: TFT element structure 201, 301, 401: Scan line layer 202, 302, 402, 504: Dielectric layers 203, 303, 403: data line layer 304: hole G: gate S / D source / drain 501: silicon substrate 502 buffer layer 503: gate insulating layer 505 planarization layer 506 '507 via hole 508 '509 Source / liquid metal wire 510: Protective layer 511 Indium tin oxide 520: Active layer preferred embodiment (refer to Figures 5A-5C)' continued and shown according to a preferred embodiment of the present invention A structural cross-sectional view of a thin film transistor (TFT) device manufacturing process. First, as shown in FIG. 5A, the TFT element structure of the present invention is formed on a silicon substrate 501 and a buffer layer 502. The material of the Shixi substrate 501 may be polysilicon (p-Si), or amorphous silicon (a-Si). Then, an active layer 520 is formed on the buffer layer 502, and then a source / drain (30.11 / 6 / (1 factory 3 111) 5/0 is formed on the active layer 52 by an ion implantation method, Among them, the active layer is used as Ding?> 1 element

445651 V. Channel Region of Invention Description (6). Next, a gate insulator 503 is formed on the buffer layer 502, for example, a gate insulating layer 503 is formed by a method called Plasma Enhanced Chemical Vapor Deposition (PECVD). The gate insulating layer 503 covers both the source / dead S / D and the active layer 520 at the same time. The material of the gate insulating layer 503 can be SiOx or SiNx. As shown in FIG. 5A, the step cover age formed by the gate insulating layer 503 covering the source / drain S / D and the active layer 520 is to make the subsequently formed interlayer have a good Step coverage effect. Then, a gate G is formed on the gate insulating layer 503. The gate electrode g is formed on the step of the gate insulating layer 503. This structure is called a gate gate structure. In addition, the gate G is used to form a scanning line of an LCI panel as shown in FIG. Next, as shown in FIG. 5B, a dielectric layer 504 is formed on the gate insulating layer 503 and the gate G. The manufacturing process of the dielectric layer 504 can be the following two methods: (1) Obtaining silicon oxide (SiOx) through deposition and rehydrogenation (hydrogen plasma hydrogenation); or (2) PECVD It is deposited by the method described above, and then obtained by high temperature annealing. It can be seen from Fig. 5B that the dielectric layer 504 has better step coverage. Then, a planarization layer 505 is formed on the dielectric layer 504. The planarizing layer 505 is a method in which a polymer compound is coated on the dielectric layer 504 by a spin method. Among them, the planarizing layer 505 is one of the features of the present invention. By forming the flattening layer 505, it is possible to greatly reduce

Page 9 445651 V. Description of the invention (7) The probability of short circuit between metal wires in the same layer, thereby improving the yield of LCD panels. In addition, in the selection of the polymer material of the planarization layer 505, its transparency and dielectric constant need to be considered to meet the requirements of the LCD. For example, the dielectric constant is about 丨. 5 ~ 3 Five, of course, 'the choice of two molecular materials can also be positive and negative photoresistance. The higher the transparency of the polymer material, the better the transmittance and quality of the formed LCD panel. For example, BCB (Dow chemical), PC403 (JSR), etc., with a thickness of about 1 to 5 μm. Since the dielectric constant of the polymer material will affect the capacitance of the cross capacitor, the larger the dielectric constant of the polymer material, the larger the capacitance of the cross capacitor will be. As mentioned above, the larger the capacitance of the AC capacitor, the longer the delay time of the LCD panel. That is, the dielectric constant of the polymer material affects the delay time of the LCD panel. After the planarization layer 505, a via hole 506, 507 is formed. For example, lithography and etching are used to form via holes 506, 507 to the source / drain s / D, as shown in FIG. 5B. Of course, the photoresist material 'required to form the vias 506 and 507 by using the lithography and the remaining method may be a positive photoresist or a negative photoresist. For example, when a positive photoresist is used, the lithography process can be used to directly pattern the positive photoresist. Thereafter, as shown in FIG. 5C, a metal layer is deposited to fill the via holes 506, 507, and the source / drain metal wires 508, 509 are defined. The next step is to form a passivating layer 510 over the flattening layer 505 and cover the source / drain metal wires 508 and 509 at the same time. Finally, a conductive layer 511 is formed to connect the source / drain metal wires.

Page 10.445651 Jade 'invention description (8) 5 0 9 For example, 疋 defines an opening to the source / drain metal wire 509 on the protective layer 5 10, and then fills in a conductive material to form a conductive layer 511, as The data line of the LCD panel 'this conductive material is, for example, indium tin oxide (Indiuin T i η χ X ide, IT 0). [Effects of the Invention] One of the characteristics of the TFT element structure disclosed in the above embodiments of the present invention is that a planarization layer is formed on the dielectric layer. By thus planarizing the layer, the present invention does not need to etch the edges of the underlying (ie, scan line layer, or gate layer) metal into a tape, thereby reducing different metal layers (scan line layer and data line layer) Probability of short circuit between. In addition, by appropriately selecting the polymer material of the planarization layer, the present invention can also reduce the intersection and capacitance values between the scanning lines and the data lines. In this way, the delay time of the LCD panel can be reduced and the speed can be increased. In addition, the gate electrode G can also be placed under the data line layer (ie, the conductive layer 5 丨 1) to increase the aperture ratio of the LCD panel. ’This will not increase the chance of short circuits between different metals. Knowing the above, 'Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various changes without departing from the spirit and scope of the present invention. And retouching, so the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims (1)

445 65 1 Six 'application patent scope1 · A thin film transistor structure including: a silicon substrate; a first source / drain located on the silicon substrate; a first source and drain located on the broken substrate Top; an active layer is located between the first source / drain and the second source / drain of the silicon substrate. A gate insulating layer 'covers the first source / drain, the second source / drain and the active layer; a gate on the gate insulating layer; a dielectric layer on the gate insulating layer And a gate electrode; a planarization layer on the dielectric layer; a first source / dead metal wire above the planarization layer and connected to the first source / drain electrode below; A second source / drain metal wire is positioned above the planarization layer and is connected to the second source / drain electrode below; a protective layer is formed over the planarization layer and covers the first source / A drain metal wire and the second source / drain metal wire; and a conductive layer on the protection layer and connected to the first source / drain metal wire below. 2. The thin film transistor structure described in item 1 of the patent application scope, wherein the silicon substrate is a polycrystalline silicon substrate. 3. The thin film transistor structure described in item 1 of the patent application scope, wherein the silicon substrate is an amorphous silicon substrate. 4. The thin film transistor element junction as described in item 1 of the scope of patent application Page 12 445651 The 6 'patent application structure further includes: a buffer layer located between the silicon substrate and the first source / drain, the second source / drain and the active layer. 5. The thin film transistor device structure described in item 1 of the patent application scope, wherein the gate insulating layer is formed of silicon oxide. 6. The thin film transistor device structure described in item 1 of the patent application scope, wherein the gate insulating layer is formed of silicon nitride. 7. The thin film transistor structure according to item 1 of the scope of the patent application, wherein the dielectric layer is formed by silicon oxide via plasma chemical vapor deposition (PECVD). 8. The thin film transistor element structure described in item 1 of the scope of patent application, wherein the planarization layer is formed of a polymer compound D 9. The thin film transistor element structure described in item 1 of the scope of patent application, wherein The conductive layer is an indium tin oxide layer. 10. A manufacturing method for forming a thin film transistor structure, comprising: providing a silicon substrate; forming a first source / drain and a second source / drain; forming a gate insulating layer; forming a gate Forming a dielectric layer: forming a planarizing layer; forming a first via hole and a second via hole, the first via hole and the second via hole passing through the planarizing layer and the dielectric Layer to the first source / drain Page 13 445 65 1 6. The scope of patent application and the second source / drain; deposit a metal layer and define the metal to be a first source / dead metal wire and a second source / drain metal conductor / And the polar metal passes through the protective layer to the first forming a protective layer defining an opening, a wire; and a manufacturing method, wherein the manufacturing method, wherein the manufacturing method further comprises forming a conductive layer. 11. The silicon substrate described in item 10 of the scope of patent application is a polycrystalline silicon substrate. 12. The silicon substrate is an amorphous silicon substrate as described in item 10 of the scope of the patent application. 13. As described in item 10 of the scope of the patent application: includes a buffer layer between the silicon substrate and the source / Between drains. 14. The manufacturing method as described in item 10 of the scope of the patent application, wherein the gate insulating layer is formed of a stone evening oxide. 15. The manufacturing method as described in item 10 of the scope of the patent application, wherein the step of forming the gate insulating layer is formed by crushed gaseous substances through plasma chemical vapor deposition (PECVD). 16. The manufacturing method as described in item 10 of the scope of patent application, wherein the step of forming the flattening layer is a polymer compound formed by a coating method. 17. The manufacturing method according to item 16 of the patent application, wherein the dielectric constant of the polymer compound is approximately 5 ° 18. The manufacturing method according to item 16 of the patent application, wherein the Page 14 445651 6. Scope of patent application The polymer compound is BCB. 19. The manufacturing method according to item 16 of the scope of patent application, wherein the polymer compound is PC403. 20. The manufacturing method according to item 11 of the scope of patent application, wherein the conductive layer is an indium tin oxide layer. ΙΙΙΙΗ!