TW442976B - Etching procedure for fabricating floating gate in flash memory - Google Patents

Abstract

A kind of method for fabricating floating gate in flash memory is disclosed in this invention and is used to enhance the contact characteristics in between the floating gate and the erase gates. This method includes the formations of the followings: a tunnel oxide layer, a polysilicon layer and an interpoly insulating layer. For these formed layers, two-step dry etching procedure is used to complete the definition of floating gate. In the first step, the interpoly insulating layer is etched in an oxidation reaction-chamber so as to form a wide-up narrow-bottom opening. In the second step, polysilicon layer and tunnel oxide layer are sequentially etched and opened in a poly reaction chamber by using the manner of switching the etching gas and following the formed opening as stated above. By using two-step dry etching procedure in this invention, we have discovered that floating gate can be made to have good contact outline so as to be advantageous for the deposition of the following oxide layer and the filling of contact window. Additionally, this two-step etching procedure substantially simplifies the process operation of floating gate so as to effectively reduce the production cost of flash memory.

Description

, 4429 7 6 I. "-. V. Invention Regulations (1) 5-1 Field of Invention: The present invention relates to the production of a kind of flash memory (flash memory) elements, especially to the production of flash memory. A method of forming floating gates in the body to increase contact reliability. 5-2 Background of the Invention:

Field effect transistors with floating gates have been widely used in non-volatile semiconductor memory. The electrons in the transistor's memory cell are programmed or erased by entering or removing the floating gate. The programming state of such a transistor's memory cell is generally obtained by applying a voltage across the source-drain region, and then measuring the current flowing in between.

The charge used to set the program can be stored in the floating gate for a long time, ideally an infinite time. The general memory arrays of such transistor cells include resettable program-only memory (PROM), erasable and resettable program-only memory (EPROM), and electrically erasable And reset program read-only memory (EEPR0M), and flash electrically erasable and reset program read-only memory (flash EEPR0M). Among them, flash memory (f 1 ash EEPR0M) is currently used in high-volume non-volatile memory because of its small size and high reliability. It is used to insert or use it in drive memory systems.

Page 5 d429 7 6 V. Description of the invention (2) Basically, this type of semi-conductor is combined, and each of them is recorded as the source of the integrated electrical erasing and resetting chip program. The source of the unique memory is formed. The inter-drain gate group is a chip formed by the source ». One side and the two ends extend these source and drain electrodes to the adjacent source and gate electrodes, and a control gate) word lines) are placed on these floating rows. The body memory system consists of many integrated circuits. In addition to the various controls and operations provided by the Crystal Memory system, it also has an array of readable cells (EEPROM cells) in a two-dimensional array. The array chip includes a source and a drain area separated and formed on a substrate. , Bit lines of memory. On each channel area of the bit, one is suspended into a two-dimensional array. And each of the arrays has long vertical control gates (the control gates form the character lines of the memory) (there is an electrically erasable and reset program read-only memory (EEPR0M) = pieces Also = the application of erase gates. Erase gates are usually adjacent to floating gates, and a thin layer of dielectric is sandwiched between the two gates. When a suitable voltage is input, The electrons can be transferred from the floating gate to the erasure gate f. In the flash memory system, the erasure gate is often used as a barrier in the unit cell, so that the erasure of the program can be completed at the instant of the flash.

Since the development of high-density memory cell arrays is a trend, we try to use self-aligned technology in the process. When applied to the fabrication of erased gates, one method of self-alignment is to deposit the erased closed electrodes between adjacent rows of the formed recording cell array.

Page 6

For a fast-memory cell region (not with compound 2 0 (extending beyond this β and suspended base 10 surface tunnel vertical 4 0 is used to connect between the rows and the two sides of the floating gate β, the first pin is the needle The relevant descriptions of some related parts of the flash memory cell are formed. This is formed on a half of the base of the guide vessel (a long parallel source liquid electrode is shown). Firstly, it is implanted in the base 10 and the base 10 has field oxygen. field oxide), doped polycrystalline silicon strips 30 (polycrystalline η is a field oxide 20 ′, these polycrystalline silicon strips 30 are separated into floating suspension gates and the channel portion of the memory substrate 10 are formed in a layer on the surface The gate oxide layer 22 (commonly referred to as tunnel oxide) is separated from the polycrystalline silicon strip 30 and the source and drain in the direction of the doped polycrystalline silicon strip 40 (polycrystalline 2). Magic bar control gate. A polycrystalline interlayer dielectric layer 32 is also formed on the suspension gate to isolate the suspension gate from the control gate. In addition, an oxidation strip 42 is formed on the top of the control closed electrode to insulate the gate. Suspension The gate and control gate sidewalls are protected by oxide layers 34 and 44, respectively. The doped polycrystalline silicon strips 50 (polycrystalline 3) filled in between the spaces are electrically isolated. These polycrystalline silicon strips 50 form an erasing idler electrode and are connected to the floating gate 30 through the oxide layer 34. The second A The two-D circle sequentially highlights a traditional manufacturing process of the above-mentioned suspended gate. Referring to the second A diagram, the gate oxide layer 22 is first grown on the substrate 10 by thermal oxidation. Then, a polycrystalline layer 30 is formed, and then Then, the polycrystalline dielectric layer 32 is deposited. In order to define the structure of the floating gate and provide contact with the erased gate 50, an etching process is performed to etch through the polycrystalline dielectric layer 32 and the polycrystalline silicon layer. Crystal 1 layer 30 does not etch a part (without etching) of the tunnel oxide layer 22 to form a vertical contact opening. The etching process is performed using multiple reactions.

4429 7 6 V. Description of the invention (4) The etching machine of the chamber, each layer of the etching is selected from its type reaction chamber. Therefore, to etch the three layers (32, 30, 22), the wafers need to be transferred between different reaction chambers. For example, the polycrystalline interlayer dielectric layer 32 and the oxide layer are usually etched using fluoride as an etchant (such as CF Θ 漭) and are usually performed in a gaseous reaction chamber. Etching requires the use of an etchant such as HBrO 漭, and is mostly performed in a polycrystalline reaction chamber. And because the etching process needs to go through the conversion process of the reaction chamber twice (after the polycrystalline interlayer dielectric layer 32 is engraved in the oxide reaction chamber, it is 'converted to the polycrystalline reaction chamber and etched the polycrystalline silicon layer 30' and then switched to the oxide reaction chamber. Channel oxide layer 22), so the definition of suspended gate can be completed in three steps (second B to second D 圊). At the same time, the above-mentioned Du engraving step is generally carried out by using the reactive ion etching (RIE) procedure. This is because the ion reactive etching is a dry process that can etch clean vertical and high aspect ratio openings. Applicable to this process. However, although there is a suitable dry etching technique, since the formation of the contact opening needs to be completed in the conversion room of the reaction chamber, we found that the etched opening surface often has depressions at the junction of the polycrystalline layer 1 and the tunnel oxide layer 22 The copy appears' for example, the depression 33 in the second C figure. The occurrence of defects is mainly due to the differences in the conditions of the reaction chambers, and the effect of pressure is most obvious. For example, the 'oxide reaction chamber is generally equipped with a higher operating pressure than the polycrystalline reaction chamber. Therefore, when the etching of poly 1 is completed, and the crystal garden is transferred from the poly reaction chamber to the gaseous reaction chamber for etching the oxide layer, the wafer is the first to be exposed to the sudden increase in etching pressure.

4 W7 6-'丨 _ V. Description of the invention (5) Over-etching of the etched part from the vertical plane will occur' and a recessed area 33 in the circle will appear. And because the surface defects of the contact window appear here often lead to the phenomenon that the regional oxide layer is weak when the subsequent oxide layer 34 is formed, j further causes the reverse voltage between poly 1 and poly 3 to be worsened. A method to improve the contact surface will certainly improve the electronic i characteristics of the flash shame body. 5-3 Purpose and summary of the invention: In view of the above-mentioned background of the invention, the traditional engraving procedure of the floating gate | many shortcomings produced by the invention 'The present invention proposes an improved method to improve the contact between the floating gate and the erase gate characteristic. ^ Another object of the present invention is to propose an etching procedure to improve the sidewall profile of the suspension electrode to reduce the phenomenon of weak oxides on the surface of the suspension gate. Program to improve the rumor 4429 7 6 V. Description of the invention (6) Another object of the present invention is to improve the structure of the contact window so as to facilitate the filling of the closed electrode layer β According to the above-mentioned object, the present invention provides a The method for making a flash memory suspension gate includes the following steps in the embodiment: forming a tunnel oxide layer on a substrate, forming a polycrystalline silicon layer (polycrystalline 1) on the tunnelizing layer, and forming an insulation on the polycrystalline silicon layer Layers, and a two-step etching process is used to etch through these layers to form a contact opening. The two steps of the β-etching process are performed in different reaction chambers. The first step is to place the crystal S] into an oxide reaction chamber 4 The insulation layer is etched through to form an opening that is wide at the top and narrow at the bottom. The second step is to transfer the crystals to a polycrystalline reaction chamber. The polycrystalline silicon layer and the tunnel oxide layer are sequentially etched along the opening formed in the first step by switching the etching gas shock to form a vertical and smooth contact window. surface. We have found that the two-step dry etching process of the present invention can greatly improve the contact profile of the floating gate electrode compared to the conventional three-step etch process. With a smoother contact surface, the subsequent forming of the oxide layer can obtain a better and uniform deposition quality, and the wide and narrow shape on the top of the contact window is more conducive to the subsequent filling of the conductive body. In addition, this two-step etching process substantially simplifies the manufacturing process of the floating gate (simplified from three steps to two steps) ', which can effectively reduce the production cost of flash memory. After the definition of the contact window is completed, an oxide layer is deposited on the surface of the wafer in order to protect and insulate the polycrystalline silicon portion exposed in the contact window. After that, the gasification layer on the surface of the wafer can be subjected to ΝΗ / Ν 2 plasma treatment, and a rapid thermal tempering process can be added to achieve the function of strengthening the surface oxide layer structure β

4429 7 6 V. Description of the invention (7) 5-4 Detailed description of the invention: The third A to C circles show the process of making a microelectronic structure according to the present invention. The following embodiments are specifically directed to the production of flashing humiliation body suspension gates. Of course, those skilled in the art will understand that the present invention is not limited to the application of impoverished embodiments, and it can also be applied to the manufacture of other microelectronic structures. Referring to FIG. 3A, a semiconductor substrate 2 ', which is preferably made of silicon material, is first provided, in which active regions and passive field regions (not shown) have been defined. On the substrate 2, a tunnel oxide layer 4 is first formed. The tunnel oxide layer 4 can be manufactured by a thermal oxidation process or a low-pressure (or atmospheric) chemical vapor deposition method. Secondly, a polycrystalline silicon layer 6 (polycrystalline 1) is formed on the tunnelization layer 4 by a chemical vapor deposition method or other suitable procedures. Above the polycrystalline silicon layer 6, an insulating layer 8 is formed. The insulating layer 8 contains an oxide, and the forming can be performed by a chemical vapor deposition method or other suitable procedures. Then 'the traditional curtain curtain technology (such as light group pattern transfer or alignment of other structures) defines the pattern of the floating gate β. To form the closed loop electrode, you need to go through an etching process. The present invention uses two steps Etching 'etching technology is reactive ion dry name method. In the first etching step, the wafer is first placed in a π 氡 etching reaction chamber. The reaction chamber is passed into an etching vessel such as CHF〆CF Jun, and the insulating layer 8 is etched until the polycrystalline silicon layer 6 is exposed.

442976 V. Description of the invention (8), and form an opening with a wide upper and a narrow lower, as shown in the circle. This shape with a wide top and a narrow bottom makes the subsequent filling of poly 3 (erasing the gate) easier. After the first etching step is completed, the wafer is transferred to a polycrystalline etching reaction chamber, and the etching in the second step is performed. The structure etched in the second step is preferably a vertical profile. It should be noted that the etching process should not expose the wafer to the atmosphere during the transfer between reaction chambers. When performing the second etching step, first pass in an etching gas such as c 2F, and etch through the polycrystalline silicon layer 6 », and then switch the etching gas to an oxide etchant of C12, HBr to remove a small portion of the tunnel oxide layer 4, A contact window is formed as in the third example. Since the removal of the tunnel oxide layer 4 is mainly to provide a more reliable contact substrate for the forming contact window, only a small part of the oxide needs to be removed, so the etching time does not need to be too long. In this way, the oxide etchant The time spent in the reaction chamber is short, and its impact on the reaction test pipeline is very limited. In addition, the father crystal layer 6 and the channel. Gasification Can 4 are combined into the same reaction chamber, and the engraving can provide an etching environment similar to that of traditional sub-chamber etching. Therefore, a smoother contact profile is etched, and the traditional process is etched. The occurrence of the depression of the gate surface (at the junction of the two layers) has been greatly improved. In addition, because the present invention simplifies the etching step from the traditional three-step scale to a two-step scale, the number of transfers in the reaction chamber is relatively reduced, and the production cost of flash memory is also reduced accordingly. Referring again to the third 'a wide protective oxide layer 9 is then formed on the entire wafer surface' to form an insulating effect on the polycrystalline silicon 6 exposed in the contact window. The 9-inch oxide layer is made by chemical vapor deposition or other suitable procedures. 111 ^ ¾ * 12 X --- 4429 7 6 V. Description of the invention (9) After the oxide layer 9 is deposited, it may be further subjected to a chemical treatment to strengthen the protective structure. In the embodiment, the N / NH3 plasma program is used for gasification treatment to improve the electrical property of the oxide. • A rapid thermal annealing (RTA) treatment can be added afterwards, and the rapid thermal annealing of Oxidation Can 9 Fire preference is performed in an N 2O environment. Since N 2 0 can be split into nitrogen and oxygen reactive atoms at the high temperature of tempering, the oxygen reactive atoms can penetrate into the oxide layer to repair the effect of the oxide layer gap, making the oxide layer defective. The situation of density and current leakage is greatly reduced. The above description is only a preferred embodiment of the present invention. It is not intended to limit the scope of the patent application of the present invention: all other things that are completed without departing from the spirit disclosed by the present invention, etc. Changes or modifications should be included in the scope of patent application described below.

"29 7 6 The round type simply explains the related structure of a conventional flash memory in the first side view: The second A to D section shows the traditional three-step etching process for making a floating gate; the third A to three C The cross section of the figure shows the process of making a floating gate according to an embodiment of the present invention. Representative symbols of the main parts:

2 Semiconductor substrate 4 Tunnel oxide layer 6 Polycrystalline silicon layer 8 Polycrystalline insulating layer 9 Protective oxide layer 10 Semiconductor substrate 20 Field oxide 22 Tunnel oxide layer 30 Suspension gate 32 Intercrystalline insulating layer oxide layer 34 Suspension gate sidewall oxide layer 40 control gate 42 control gate oxide layer 44 control gate sidewall oxide layer 50 erase gate

Claims (1)

4429 76 Six's patent application method for making a gate structure in a flash memory element includes at least: providing a semiconductor substrate on which a first insulating layer, a A conductive layer, and a second insulating layer; 'etching part of the second insulating layer to the conductive layer exposed in a first reaction chamber to form a first opening; and etching the part in a second reaction chamber The conductive layer and a part of the first insulating layer are formed by digging the first opening to form a second opening. 2. The method according to item 1 of the patent application scope, further comprising depositing a third insulating layer over the semiconductor substrate after the second opening is formed. 3_ The method according to item 2 of the patent application, wherein the third insulating layer mentioned above contains an oxide "4. The method according to item 2 of the patent application, further comprising performing a plasma treatment on the third insulating layer. 5. The method according to item 4 of the patent application, wherein the above-mentioned electro-excitation treatment includes N2 / NΗ3 plasma treatment β 6_ The method according to item 2 of the patent application range further includes when the third insulation layer is formed, Perform a rapid thermal tempering procedure. Page 15 _ 4429 7 6__ VI. Application scope of patent 7. The method of applying for the first paragraph of the patent application, wherein the above-mentioned conductive layer includes polycrystalline silicon. 8. The method according to item 1 of the scope of patent application, wherein said first insulating layer includes an oxide. 9. The method according to item 1 of the patent application park, wherein the above-mentioned second insulating layer includes an oxide.玉 〇. The method of applying for the first item of the patented patent garden, wherein the shape of the first opening is 11mm wide and 11mm narrow. * A method for making a plurality of gate structures in a flash memory device. Method 'at least includes: providing a base substrate, forming an insulating layer on the silicon substrate; forming a polycrystalline silicon layer on the insulating layer; forming a polycrystalline insulating layer on the polycrystalline silicon layer to form a stacked structure'the The stacked structure includes the insulating layer, the polycrystalline silicon layer, and the intercrystalline insulating layer; The two strip-shaped structures are separated by two dry etching steps, wherein the two steps and a second cooking step, the two identical reaction chambers: and the stack of Φ structures define a plurality of parallel dry etching steps including one The first etching step and the 14-etching step are performed on two different steps, respectively. Dedicated office Please apply as if. Line 2 1 6. Application for patent Fanyuan deposit a gate oxide layer on the silicon substrate to isolate the strip structure. The method of item 11 further includes the oxide layer of the gate 13. The method of item 12 in the scope of patent application, wherein the above-mentioned plasma treatment includes N2 / NH3 plasma treatment. 14. The method of claim 11 in the scope of patent application further includes performing a rapid thermal tempering procedure after the gate oxide layer is formed. 15. The method of claim 11 in which the above-mentioned insulating layer contains an oxide. 16. The method according to item 11 of the scope of patent application, which makes the above-mentioned polycrystalline insulating layer contain an oxide. 17. The method according to item 11 of the application, wherein the first etching step described above etches through the polycrystalline insulating layer. 18. The method according to item 17 of the scope of patent application, wherein the etching of the polycrystalline interlayer insulating layer described above forms an opening with a wide width and a narrow width. Page 4429 76 VI. Patent Application Park 19 · If the scope of the patent application is to step through the polycrystalline silicon layer and etch the method of item 11, the above mentioned ## part of the insulation is wide. 20.— Contains a method for making a suspended gate in flash memory, forming a small package, forming a polycrystalline layer with subsequent oxidation, and forming an etching layer including oxidation on an oxide on a substrate; On the oxide layer of the tunnel; the insulating layer of the object on the polycrystalline silicon layer; in the reaction chamber, the insulating part is etched as far as the crystalline silicon layer is exposed to form a first opening, the first lower narrow shape; on a polycrystalline An anti-corrosive oxide layer is etched to form a vertical π; a protective oxidation is performed, and a plasma treatment is performed to open the opening in a wide chamber. A portion of the polycrystalline silicon layer is etched and a portion of the first opening is dug deep to form a second opening. Layer over the substrate; and nitride the protective oxide layer. 21. The method of claim 20 in the scope of patent application, further comprising performing a rapid thermal tempering process after the plasma treatment is completed.