、4429 634429 63
五、發明說明（/ ) 經濟部智慧財產局員工消费合作社印製 本發明是有關於--種半導體元件之製造方法，且特別是 有關於一種動態隨機存取記憶體（D R A Μ)之電容器下電極 的製造方法。 -般電容器的結構，包括兩個電極及兩個電極之間的介 電層。爲了提高電容器的電容値，必須減少電極間介電層 的厚度，增加介電層的介電常數値，或者增加電極的表面 積。 其中，一種增加電極表面積的方法，係在電極的表面形 成具有選擇性半球狀砂晶粒（Se 1 ec t i ve Hemi sphe r 1 ca 1 Grain ; Selective-HSG)之結構，作爲電容器之下電極， 此係由於選擇性半球狀矽晶粒具有凹凸不平的特徵，可增 加下電極的表面積，以提高電容値。 目前半導體製造過程中，大多以多晶矽做爲電容器之下 電極所使用的材質，然而，選擇性半球狀矽晶粒在多晶矽 的表面上，因多晶矽會抑制選擇性半球狀矽晶粒的形成， 使得選擇性半球狀矽晶粒所形成的結構不佳，甚至不會形 成，因此，通常會在做爲電容器下電極之多晶矽的表面， 先形成摻雜非晶砂（doped amorphous silicon; D-a-Si) 層 '然後在於此摻雜非晶矽層的表面上形成選擇性半球狀 矽晶粒，如此，選擇性半球狀矽晶粒將具有較佳之結構。 第1A圖至第1D圖繪示習知一種下電極的製造流程剖面 圖。 首先，請參照第1A圖，提供一基底100，基底100上已 形成有介電層102,其中介電層102具有開口 104暴露出 3 本紙張尺度遡用中國g家標準（CNS)A4规格（210 X 297公藿〉 — — — — — — — Ί — · — I I I I — —^^* — — 11 — — — —^^ ^1 {請先閱讀背面之注意事項再填寫本頁) 4429 63 A7V. Description of the Invention (/) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs This invention is related to a method for manufacturing a semiconductor device, and in particular, to a capacitor of a dynamic random access memory (DRA M) Method for manufacturing electrodes. A general capacitor structure including two electrodes and a dielectric layer between the two electrodes. In order to increase the capacitance 电容器 of the capacitor, it is necessary to reduce the thickness of the dielectric layer between the electrodes, increase the dielectric constant 値 of the dielectric layer, or increase the surface area of the electrode. Among them, a method for increasing the surface area of an electrode is to form a structure with selective hemispherical sand grains (Se 1 ec ti ve Hemi sphe r 1 ca 1 Grain; Selective-HSG) on the surface of the electrode as the lower electrode of the capacitor. This is because the selective hemispherical silicon grains have uneven features, which can increase the surface area of the lower electrode to increase the capacitance. At present, in the semiconductor manufacturing process, polycrystalline silicon is mostly used as the material for the lower electrode of the capacitor. However, the selective hemispherical silicon grains on the surface of the polycrystalline silicon, because the polycrystalline silicon can inhibit the formation of the selective hemispherical silicon grains, making The structure formed by the selective hemispherical silicon grains is not good, and even does not form. Therefore, doped amorphous silicon (Da-Si) is usually formed on the surface of the polycrystalline silicon used as the lower electrode of the capacitor. The layer 'then forms selective hemispherical silicon crystal grains on the surface of the doped amorphous silicon layer. Thus, the selective hemispherical silicon crystal grains will have a better structure. 1A to 1D are cross-sectional views showing a conventional manufacturing process of a lower electrode. First, referring to FIG. 1A, a substrate 100 is provided. A dielectric layer 102 has been formed on the substrate 100, and the dielectric layer 102 has an opening 104 to expose three paper sizes. The Chinese paper standard (CNS) A4 specification ( 210 X 297 Gong> — — — — — — — — — — — IIII — — ^^ * — — 11 — — — — ^^ ^ 1 {Please read the notes on the back before filling this page) 4429 63 A7
經濟部智慧財產局貝工消费合作社印製 五、發明說明（2 ) 基底100。 續之，於基底100上形成摻雜非晶矽層Γ06，並塡滿開 U 104。然而，在介電層102與開口 1〇4所裸露之部分基 底100表面具有雜質，做爲形成多晶矽結晶的晶核，因此 在摻雜非晶矽層106的形成過程之熱預算下，會導致在摻 雜非晶矽層106中，形成多晶矽結晶108，且多晶矽結晶 108之大小會隨著摻雜非晶矽層106之厚度增大而越來越 大。 接著，請參照第1B圖，定義介電層102上的摻雜非晶 矽層106，以在對應開口 104的上方，形成具有多晶矽結 晶108與摻雜非晶矽材質106b之非晶矽層l〇6a，並且裸 露部分多晶砂結晶108。 其後，請參照第1C圖，於介電層102上的摻雜非晶矽 層106a之表面形成選擇性半球狀矽晶粒層11〇,以增加後 續完成的下電極之表面積。 但是，由於摻雜非晶矽層106a所裸露之表面，有一部 份是多晶矽結晶108,而具有較佳結構之選擇性半球狀矽 晶粒層110,僅會形成在表面是非晶矽的摻雜非晶矽材質 106b上’因此，摻雜非晶矽層i〇6a所裸露之表面，並不 會全部都形成選擇性半球狀矽晶粒，導致無法有效增加下 電極之表面積，進而無法有效增進電容器之電容儲存能 力。 續之’請參照第1D圖，進行一全面性回火步驟，使摻 雜非晶矽層106a之摻雜離子，得以擴散至選擇性半球狀 4 本紙張尺度適用中國國家標準（CNSM4規格<210 X 297公sn — — — — — — —1 I I T ^ — — — — — — II · I I I I I I — ^ 4 <請先閱讀背面之注意事項再填寫本頁) 4429 6 3 經濟部智慧財產局員工消費合作社印製 Λ7 Β7 五、發明說明（幺） 砂晶粒層i i 0中，增加選擇性半球狀砂晶粒層Π 0之導電 性’進而降低電容器之電容缺乏效應。此外，在回火步驟 中’摻雜非晶矽材質106b經由高溫結晶，而摻雜非晶砂 層1〇6ϋ則轉換成爲具有多晶矽結晶1〇8(請參照第1C圖） 之ί爹維多晶砂層1 〇6c。 此時，選擇性半球狀矽晶粒層110，與因回火步驟而由 摻雜非晶矽層106a轉換爲具有多晶矽結晶1〇8(請參照第 1C圖）之摻雜多晶矽層i〇6c，共同組成一電容下電極1丨2。 由於在形成摻雜非晶矽層106之熱預算影響下，介電層 1Q2與開口 104所裸露之基底100表面若有雜質存在，則 此些雜質在形成摻雜非晶矽層106的過程中，將成爲形成 多晶矽的晶核，導致摻雜非晶矽層106形成後，摻雜非晶 矽層106中將形成許多多晶矽結晶108。 而在定義摻雜非晶砂層106之後，所形成之摻雜非晶砂 層106a的大部分表面裸露多晶矽結晶1〇8,因爲多晶矽結 晶108會抑制選擇性半球狀矽晶粒之形成，因此選擇性半 球狀矽晶粒層110僅會少量的形成在摻雜非晶矽層！06a 之表面上’而其所能提尚下電極表面積的能力有限。 習知爲解決在形成摻雜非晶矽層時，因製程之熱預算影 響’造成在摻雜非晶矽層中形成大量多晶矽結晶，導致於 後續製程中抑制選擇性半球狀矽晶粒層之形成，因此，請 參照第2圖，在基底200上方形成一層較薄的摻雜非晶矽 層206a，接著，於爐管（furnace)中，在摻雜非晶矽層206a 上形成一層很薄的氧化層207。 本紙張尺度適用+國0家標準（CNS)A4規格（210 X 297公 ---I--—Ί — I 1 j )裝 - - ---- - 訂 i — — — — — — —^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製 4429 63 -i 4 S 2 i \s Γ du c / 0 06 五、發明說明（4) 續之在氧化層207上，形成一層摻雜非晶矽層206b 於 形成摻雜非晶矽層206a時，同樣的在熱預算的影脊下， 會在摻雜非晶矽層206a中形成大量的多晶矽結晶208a， 而多晶矽結晶208a之成長會受到氧化層207之抑制，且 在氧化層207上所形成之摻雜非晶矽層206b中，因熱預 算所形成之多晶矽結晶的量將稍微減少，但是還是會以氧 化層207的雜質（如原生氧化層）爲晶核，生長出許多多晶 矽結晶208b。如此一來，在後續於圖案化之摻雜非晶矽層 上所形成選擇性半球狀矽晶粒之量仍不曾有效提高，因此 所能增加的表面積仍受到限制。 因此本發明就是在提供一種下電極之製造方法，其方法 簡述如下：首先提供一基底，於基底上形成有具有裸露出 基底之開口的一層介電層，接著，於基底上方，形成一層 第一摻雜非晶矽層，並塡滿開口。續之，對於第一摻雜非 晶矽層之一表面，進行一淸潔步驟。繼之，於第一摻雜非 晶矽層上形成一第二摻雜非晶矽層，其中第一與第二摻雜 非晶矽層之間的介面具有抑制第一摻雜非晶矽層中之複 數個多晶矽結晶之成長的功能.。之後，定義第一與第二摻 雜非晶矽層以分別形成第三摻雜非晶矽層與第四摻雜非 晶矽層。接著，於第三與第四摻雜非晶矽層上，形成一層 選擇性半球狀矽晶粒層，最後，進行一回火步驟，以將選 擇性半球狀矽晶粒層、第三與第四摻雜非晶矽層轉換成電 容下電極。 依照本發明的一較佳實施例，其中第一摻雜非晶矽層之 本紙張尺度適用中國國家標準（CNS>A4規格（2〗0 X 297公釐） — — — — — - I [ I I I I J »11 — — — — — · ^ (請先閱讀背面之注意事項再填寫本頁) 4429 63 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明說明（f) 厚度小於第二摻雜非晶矽層之厚度《由於先在基底上方形 成-層厚度較薄的第一摻雜非晶矽層，因此在此摻攀非晶 矽層中所形成之多晶矽結晶之數量較少，且尺寸較小。 再者，於形成第一摻雜非晶矽餍之後，以一淸潔步驟去 除此第一摻雜非晶矽層上之原生氧化層以及雜質，並接著 於基底上方形成一層第二摻雜非晶矽層，因此在第二與第 一摻雜非晶砂層之間的介面上，並沒有可供形成多晶矽結 晶之晶核。 此外介面會抑制第一摻雜非晶矽層中多晶矽結晶的繼 續生長，因此在第二摻雜非晶矽層中，並不會因爲形成摻 雜非晶矽層之熱預算而導致在第二摻雜非晶矽層中形成 多晶矽結晶。所以，在定義形成第三與第四摻雜非晶矽層 後，幾乎所有的第三與第四摻雜非晶矽層表面上，都可形 成選擇性半球狀矽晶粒層，因此可以大大提高所欲形成之 電容下電極之表面積，進而提高電容器之電容値。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂’下文特舉一較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1A圖至第1D圖繪示習知一種下電極的製造流程剖面 圖； 第2圖係顯示習知一種形成摻雜非晶矽之剖面圖；以及 第3A圖至第3E圖所示，爲根據本發明一較佳實施例之 --種下電極之製造方法流程剖面簡圖。 7 本紙張尺度適用中Η B家標準（CNS)A4規格（2〗0 X 297公爱） I I [ I I I J — I — 1 ^^* *--I--II »11111!1 {請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消費合作社印製 4429 63 A7 B7 五、發明說明（6) 其中，各圖標號與構件名稱之關係如下： 100，200，300 •基底 — 102，202，302 :介電層 104，204，304 :開口 106，106a，206a，206b，306，316，318 :摻雜非晶石夕層 106b，306a，316a，318a :多晶石夕層 108 ' 208ϋ，208b ’ 308 .多晶砂結晶 110，320 :選擇性半球狀矽晶粒層 112，322 :下電極 2 0 7 :氧化砂層 314 :介面 實施例 第3A圖至第3E圖所示，爲根據本發明一較佳實施例之 一種下電極之製造方法流程剖面簡圖。 請參照第3A圖，首先提供一基底300，基底300上巳形 成有半導體元件（未繪示）。接著，於基底300上形成一層 介電層302，此介電層302包括以化學氣相沉積法所形成 之氧化砂層。 續之，圖案化介電層302 ’以在介電層302中形成一裸 露出基底300中之元件（未繪示）的開口 304。繼之，於基 底300上方形成一層厚度較薄之摻雜非晶矽層306，並塡 滿開[J 304，此摻雜非晶矽層306之厚度可視後續所欲形 成之下電極的高度而改變。其中，摻雜非晶矽層306之摻 8 本紙張尺度適用中困0家標準（CNS)A4規格（210 X 297公釐〉 II ：-----.---1' 贫--------訂---------炊 V (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消費合作社印製 4 A29 63 Λ7 ί 山κ· UtKi —__Β7____ 五、發明說明（〇 ) 雜離子例如是砷離子或磷離子，用以增加摻雜非晶矽層 306的導電性。較佳的非晶矽層306的形成方法例以化 學氣相沈積法於基底300上形成一層非晶矽層，並同時進 行一離子植入製程。 由於形成摻雜非晶矽層306之熱預算之影響，因此在摻 雜非晶矽層306中會形成多晶矽結晶308，而因爲摻雜非 晶矽層306之厚度較薄，因此在其中形成之多晶砂結晶的 量較小，且其尺寸也較小。 接著’請參照第3Β圖，進行一淸潔步驟，以去除摻雜 非晶矽層306上之原生氧化層（未繪示）以及雜質（未繪 示）。其中，淸潔步驟包括以氟化氫去除摻雜非晶矽層306 上之原生氧化層以及雜質。續之，於摻雜非晶矽層306上， 形成一層摻雜非晶砂層316，此摻雜非晶砂層316之厚度 大於摻雜非晶矽層306之厚度。其中，摻雜非晶矽層316 之摻雜離子例如是砷離子或磷離子，其係用以增加摻雜非 晶矽層316的導電性。較佳的非晶矽層316的形成方法例 如以化學氣相沈積法於摻雜非晶矽層306上形成一層非晶 石夕層，並同時進行一離子植入製程= 由於摻雜非晶矽層306與316之間的介面314係經過一 去除其上原生氧化層之淸潔步驟，因此此介面314將抑制 在摻雜非晶矽層306中的多晶矽結晶的繼續生長。再者， 由於在形成摻雜非晶矽層316之前，進行一淸潔步驟，因 此在介面314上沒有原生氧化層或是雜質可做爲後續形成 摻雜非晶矽層316時多晶矽結晶之晶核，所以在摻雜非晶 9 冬紙張尺度適用中國因家棵準（CNS)A4規格(210 * 297公；* ) — !liJ—— —^裝------ -- ^ · I I------^) (請先閱讀背面之注意事項再填寫本頁) 广 Λ429 63 五、發明說明（y ) 矽層3 1 6中，並沒有形成多晶矽結晶。 續之，請參照第3C圖，圖案化摻雜非晶矽層306與316， 使留下的非晶矽層306與106對應在開口 304的上方，爲 簡化敘述，係將圖案化之摻雜非晶矽層316與306合稱爲 摻雜非晶砂層3 1 8 ϋ由於摻雜非晶砂層306之厚度較薄， 加上介面314抑制多晶矽結晶308之成長，所以在摻雜非 晶矽層306中因形成摻雜非晶矽306之熱預算所形成之多 晶矽結晶308之量較少，且尺寸也較小，而在摻雜非晶矽 層316中亦沒有形成多晶矽結晶，因此在圖案化形成摻雜 非晶矽層318時，僅裸露出少部分的多晶矽結晶308，甚 至沒有裸露出來。 繼之，請參照第3D圖，於介電層302上的摻雜非晶矽 層318之表面形成選擇性半球狀矽晶粒層320，以增加後 續完成的下電極之表面積。由於摻雜非晶矽層318，僅裸 露出少部分的多晶矽結晶308,甚至沒有將多晶矽結晶308 裸露出來，因此幾乎所有的摻雜多晶矽層318表面上都形 成有選擇性半球狀矽晶粒層320，因此可以有效提高後續 所形成之電容下電極之表面積。 之後，請參照第3Ε圖，進行一全面性回火步驟，使摻 雜非晶矽層318之摻雜離子，得以擴散至選擇性半球狀矽 晶粒層320中，增加選擇性半球狀矽晶粒層320之導電 • 性5進而降低電容器之電容缺乏效應。此外，在回火步驟 中，摻雜非晶矽層318中的摻雜非晶矽材質經由高溫結 晶，而摻雜非晶矽層318則轉換爲之多晶矽層318a(其係 本紙張尺度適用中國國家標準（CNSXA4規格（210 X 297公簸> (請先閱讀背面之注意事項再填寫本頁) > J— L. 1 n ii n ^0，· n n nPrinted by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the Invention (2) Base 100. Continuing, a doped amorphous silicon layer Γ06 is formed on the substrate 100, and U104 is filled. However, there are impurities on the surface of the dielectric layer 102 and a portion of the substrate 100 exposed by the opening 104 as the nuclei for forming polycrystalline silicon crystals. Therefore, under the thermal budget of the formation process of the doped amorphous silicon layer 106, it will cause In the doped amorphous silicon layer 106, a polycrystalline silicon crystal 108 is formed, and the size of the polycrystalline silicon crystal 108 will increase as the thickness of the doped amorphous silicon layer 106 increases. Next, referring to FIG. 1B, the doped amorphous silicon layer 106 on the dielectric layer 102 is defined to form an amorphous silicon layer having a polycrystalline silicon crystal 108 and a doped amorphous silicon material 106b over the corresponding opening 104. 〇6a, and exposed part of the polycrystalline sand crystal 108. Thereafter, referring to FIG. 1C, a selective hemispherical silicon grain layer 110 is formed on the surface of the doped amorphous silicon layer 106a on the dielectric layer 102 to increase the surface area of the lower electrode that is subsequently completed. However, since the exposed surface of the doped amorphous silicon layer 106a is partially polycrystalline silicon crystal 108, the selective hemispherical silicon grain layer 110 with a better structure will only be formed on the surface of the doped amorphous silicon layer. On the amorphous silicon material 106b, therefore, the exposed surface of the doped amorphous silicon layer i06a does not all form selective hemispherical silicon crystal grains, resulting in an inability to effectively increase the surface area of the lower electrode, and thus cannot effectively improve Capacitor storage capacity. Continued 'Please refer to FIG. 1D to perform a comprehensive tempering step so that the doped ions of the doped amorphous silicon layer 106a can diffuse into the selective hemispherical shape. 4 This paper size is applicable to Chinese national standards (CNSM4 specifications < 210 X 297 male sn — — — — — — — — 1 IIT ^ — — — — — — II · IIIIII — ^ 4 < Please read the notes on the back before filling out this page) 4429 6 3 Employees of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the consumer cooperative Λ7 B7 V. Description of the invention (i) In the sand grain layer ii 0, the conductivity of the selective hemispherical sand grain layer Π 0 is increased, thereby reducing the lack of capacitance of the capacitor. In addition, in the tempering step, the doped amorphous silicon material 106b is crystallized at a high temperature, and the doped amorphous sand layer 106 is converted into a polycrystalline silicon having a polycrystalline silicon crystal 108 (see FIG. 1C). Sand layer 1 06c. At this time, the selective hemispherical silicon crystal layer 110 is converted from the doped amorphous silicon layer 106a to a doped polycrystalline silicon layer 108 having a polycrystalline silicon crystal 108 (see FIG. 1C) due to the tempering step. , Together form a capacitor lower electrode 1 丨 2. Due to the influence of the thermal budget of forming the doped amorphous silicon layer 106, if there are impurities on the surface of the substrate 100 exposed by the dielectric layer 1Q2 and the opening 104, these impurities are in the process of forming the doped amorphous silicon layer 106. It will become a nucleus for forming polycrystalline silicon. After the doped amorphous silicon layer 106 is formed, many polycrystalline silicon crystals 108 will be formed in the doped amorphous silicon layer 106. After the doped amorphous sand layer 106 is defined, most of the surface of the formed doped amorphous sand layer 106a is exposed with polycrystalline silicon crystals 108, because the polycrystalline silicon crystals 108 can inhibit the formation of selective hemispherical silicon grains, so the selectivity The hemispherical silicon grain layer 110 is only formed in a small amount on the doped amorphous silicon layer! 06a on the surface 'and its ability to improve the surface area of the lower electrode is limited. Conventionally, in order to solve the problem of forming a doped amorphous silicon layer, a large number of polycrystalline silicon crystals are formed in the doped amorphous silicon layer due to the influence of the thermal budget of the manufacturing process, resulting in the suppression of the selective hemispherical silicon grain layer in subsequent processes. Is formed, therefore, please refer to FIG. 2, a thin layer of doped amorphous silicon layer 206 a is formed on the substrate 200, and then a thin layer of doped amorphous silicon layer 206 a is formed in a furnace tube Of the oxide layer 207. This paper size is applicable to + China National Standard (CNS) A4 specification (210 X 297 male --- I ---- Ί-I 1 j) installed-------order i — — — — — — — ^ (Please read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4429 63 -i 4 S 2 i \ s Γ du c / 0 06 V. Description of the invention (4) Continued on oxidation On the layer 207, a doped amorphous silicon layer 206b is formed. When the doped amorphous silicon layer 206a is formed, a large amount of polycrystalline silicon crystals 208a will be formed in the doped amorphous silicon layer 206a under the shadow of the thermal budget. The growth of polycrystalline silicon crystal 208a will be inhibited by the oxide layer 207, and in the doped amorphous silicon layer 206b formed on the oxide layer 207, the amount of polycrystalline silicon crystal formed due to the thermal budget will be slightly reduced, but it will still be A plurality of polycrystalline silicon crystals 208b are grown using impurities (such as a native oxide layer) of the oxide layer 207 as crystal nuclei. As a result, the amount of selective hemispherical silicon crystal grains formed on the patterned doped amorphous silicon layer has not been effectively increased, so the surface area that can be increased is still limited. Therefore, the present invention is to provide a method for manufacturing a lower electrode. The method is briefly described as follows: firstly, a substrate is provided with a dielectric layer having an opening exposing the substrate on the substrate, and then a layer of a first layer is formed on the substrate. A doped amorphous silicon layer fills the opening. Continuing, a cleaning step is performed on one surface of the first doped amorphous silicon layer. Next, a second doped amorphous silicon layer is formed on the first doped amorphous silicon layer, and an interface between the first and second doped amorphous silicon layers has a suppression effect on the first doped amorphous silicon layer. The function of the growth of a plurality of polycrystalline silicon crystals. After that, the first and second doped amorphous silicon layers are defined to form a third doped amorphous silicon layer and a fourth doped amorphous silicon layer, respectively. Next, a selective hemispherical silicon grain layer is formed on the third and fourth doped amorphous silicon layers. Finally, a tempering step is performed to convert the selective hemispherical silicon grain layer, the third and the first The four-doped amorphous silicon layer is converted into a capacitor lower electrode. According to a preferred embodiment of the present invention, the paper size of the first doped amorphous silicon layer conforms to the Chinese national standard (CNS > A4 specification (2) 0 X 297 mm) — — — — —-I [IIIIJ »11 — — — — — · ^ (Please read the notes on the back before filling this page) 4429 63 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (f) The thickness is less than the second doped non Thickness of crystalline silicon layer "Since the first doped amorphous silicon layer with a thinner layer is formed first on the substrate, the number of polycrystalline silicon crystals formed in this doped amorphous silicon layer is smaller and the size is smaller than Furthermore, after the first doped amorphous silicon is formed, the primary oxide layer and impurities on the first doped amorphous silicon layer are removed in a cleaning step, and then a second doped layer is formed over the substrate. The hetero-amorphous silicon layer has no nucleus for forming polycrystalline silicon crystals on the interface between the second and first doped amorphous sand layers. In addition, the interface will inhibit polycrystalline silicon crystals in the first doped amorphous silicon layer Continued to grow, so in the second In the hetero-amorphous silicon layer, polycrystalline silicon crystals are not formed in the second doped amorphous silicon layer due to the thermal budget of the doped amorphous silicon layer. Therefore, the third and fourth doped non-crystalline silicon layers are defined by definition. After the crystalline silicon layer, almost all the third and fourth doped amorphous silicon layers can form a selective hemispherical silicon grain layer on the surface, so the surface area of the lower electrode of the capacitor to be formed can be greatly increased, thereby further increasing Capacitance of a capacitor. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below and described in detail with the accompanying drawings as follows: The simplicity of the drawings Note: FIGS. 1A to 1D are cross-sectional views showing a conventional manufacturing process of a lower electrode; FIG. 2 is a cross-sectional view showing a conventional formation of doped amorphous silicon; and FIGS. 3A to 3E show , Which is a simplified cross-sectional view of a method for manufacturing a lower electrode according to a preferred embodiment of the present invention. 7 This paper size is applicable to ChinaΗ B family standard (CNS) A4 specification (2〗 0 0 297 public love) II [ IIIJ — I — 1 ^^ * *-I--II »11111! 1 { Please read the notes on the back before filling this page) 4429 63 A7 B7 printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (6) Among them, the relationship between each icon number and component name is as follows: 100, 200, 300 • Substrates — 102, 202, 302: dielectric layers 104, 204, 304: openings 106, 106a, 206a, 206b, 306, 316, 318: doped amorphous stone layers 106b, 306a, 316a, 318a: polycrystalline Shi Xi layer 108 '208ϋ, 208b' 308. Polycrystalline sand crystal 110, 320: Selective hemispherical silicon grain layer 112, 322: Lower electrode 207: Oxidized sand layer 314: Interface example 3A to 3E The figure shows a schematic cross-sectional view of a method for manufacturing a lower electrode according to a preferred embodiment of the present invention. Referring to FIG. 3A, a substrate 300 is first provided, and a semiconductor element (not shown) is formed on the substrate 300. Next, a dielectric layer 302 is formed on the substrate 300. The dielectric layer 302 includes an oxide sand layer formed by a chemical vapor deposition method. Continuing, the dielectric layer 302 'is patterned to form an opening 304 in the dielectric layer 302 to expose components (not shown) in the substrate 300. Next, a thinner doped amorphous silicon layer 306 is formed over the substrate 300, and is fully filled [J 304. The thickness of the doped amorphous silicon layer 306 may be determined by the height of the lower electrode to be formed subsequently. change. Among them, the doped amorphous silicon layer 306 is doped with 8 papers. The paper size is applicable to the standard of CNS A4 (210 X 297 mm) II: -----.--- 1 'poor --- ----- Order --------- Cook V (Please read the notes on the back before filling out this page) Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs 4 A29 63 Λ7 ί · κ · UtKi —__ Β7 ____ 5. Description of the invention (0) The hetero ions are, for example, arsenic ions or phosphorus ions, to increase the conductivity of the doped amorphous silicon layer 306. A preferred method for forming the amorphous silicon layer 306 is chemical vapor deposition. An amorphous silicon layer is formed on the substrate 300 and an ion implantation process is simultaneously performed. Due to the influence of the thermal budget of forming the doped amorphous silicon layer 306, polycrystalline silicon crystals are formed in the doped amorphous silicon layer 306 308, and because the thickness of the doped amorphous silicon layer 306 is thinner, the amount of polycrystalline sand crystals formed therein is smaller and its size is smaller. Then, please refer to FIG. 3B for a cleaning step To remove the native oxide layer (not shown) and impurities (not shown) on the doped amorphous silicon layer 306. The cleaning step includes Hydrogen fluoride is used to remove the native oxide layer and impurities on the doped amorphous silicon layer 306. Next, a doped amorphous sand layer 316 is formed on the doped amorphous silicon layer 306, and the thickness of the doped amorphous sand layer 316 is greater than The thickness of the doped amorphous silicon layer 306. The doped ions of the doped amorphous silicon layer 316 are, for example, arsenic ions or phosphorus ions, which are used to increase the conductivity of the doped amorphous silicon layer 316. The method for forming the amorphous silicon layer 316 is, for example, chemical vapor deposition to form an amorphous stone layer on the doped amorphous silicon layer 306, and an ion implantation process is simultaneously performed. The interface 314 between 316 undergoes a cleaning step to remove the native oxide layer thereon, so this interface 314 will inhibit the continued growth of polycrystalline silicon crystals in the doped amorphous silicon layer 306. Furthermore, since the doping is being formed, Before the amorphous silicon layer 316, a cleaning step is performed. Therefore, there is no native oxide layer or impurities on the interface 314 as the nuclei of polycrystalline silicon crystals when the doped amorphous silicon layer 316 is subsequently formed. 9 Winter paper scales apply to Chinese family standards ( CNS) A4 specification (210 * 297 males; *) —! LiJ—— — ^ equipment -------^ · I I ------ ^) (Please read the notes on the back before filling (This page) Guang Λ429 63 V. Description of the invention (y) In the silicon layer 3 1 6, no polycrystalline silicon crystal is formed. Continuing, please refer to FIG. 3C, patterning the doped amorphous silicon layers 306 and 316 so that the remaining amorphous silicon layers 306 and 106 correspond above the opening 304. To simplify the description, the patterned doped The amorphous silicon layers 316 and 306 are collectively referred to as a doped amorphous sand layer 3 1 8 ϋ Because the thickness of the doped amorphous sand layer 306 is thin, and the interface 314 inhibits the growth of polycrystalline silicon crystal 308, the doped amorphous silicon layer The number of polycrystalline silicon crystals 308 formed in 306 due to the thermal budget of the doped amorphous silicon 306 is small and the size is small, and no polycrystalline silicon crystals are formed in the doped amorphous silicon layer 316, so patterning When the doped amorphous silicon layer 318 is formed, only a small portion of the polycrystalline silicon crystal 308 is exposed, not even exposed. Next, referring to FIG. 3D, a selective hemispherical silicon grain layer 320 is formed on the surface of the doped amorphous silicon layer 318 on the dielectric layer 302 to increase the surface area of the lower electrode that is subsequently completed. Due to the doped amorphous silicon layer 318, only a small part of the polycrystalline silicon crystal 308 is exposed, and even the polycrystalline silicon crystal 308 is not exposed. Therefore, a selective hemispherical silicon grain layer is formed on the surface of almost all the doped polycrystalline silicon layer 318. 320, which can effectively increase the surface area of the lower electrode of the capacitor formed later. Then, referring to FIG. 3E, a comprehensive tempering step is performed, so that the doped ions of the doped amorphous silicon layer 318 can be diffused into the selective hemispherical silicon crystal layer 320, and the selective hemispherical silicon crystal is increased. The conductivity of the granular layer 3205 further reduces the lack of capacitance effect of the capacitor. In addition, in the tempering step, the doped amorphous silicon material in the doped amorphous silicon layer 318 is crystallized through high temperature, and the doped amorphous silicon layer 318 is converted into a polycrystalline silicon layer 318a (which is a paper scale applicable to China) National Standards (CNSXA4 specifications (210 X 297 mm)> (Please read the precautions on the back before filling out this page) > J— L. 1 n ii n ^ 0, · nnn
绂V 經濟部智慧財羞局員工消费合作社印製 經濟部智慧財產局員工消费合作社印製 4429 6 3 Λ7 r OOfi B7 五、發明說明（q ) 包括多品砂層3 1 ό a與3 0 6 a )’並且與選擇性半球狀砂晶粒 層320共同組成一電容下電極322。 由於先在基底300上方形成一層厚度較薄的摻雜非晶矽 層306，因此在此摻雜非晶矽層306中所形成之多晶矽結 晶308之數量較少，且尺寸較小。 再者，於形成摻雜非晶矽層之後，以一淸潔步驟去除此 摻雜非晶矽層306上之原生氧化層以及雜質，並接著於基 底300上方形成一層摻雜非晶矽層316，因此在摻雜非晶 矽層316與306之間的介面314上，並沒有可供形成多晶 砂結晶之晶核。 此外介面314會抑制多晶矽結晶308的繼續生長，因此 在摻雜非晶矽層316中，並不會因爲形成摻雜非晶矽層之 熱預算而導致在摻雜非晶矽層3丨6中形成多晶矽結晶。所 以，在圖案化形成摻雜非晶矽層318時，摻雜非晶矽層318 之表面今裸露少部分的多晶砂結晶’甚至沒有裸露出多晶 矽結晶。 如此一來，幾乎所有的慘雜多晶砂層318表面上，都可 形成選擇性半球狀矽晶粒層320，因此可以大大提高所欲 形成之電容下電極之表面積，進而提高電容器之電容値。 本發明之較佳實施例係以形成一柱狀（c y丨i n d 1： i C a 1 > 結構電容之下電極爲例，其於實際應用上，本發明亦可應 用於雙堆疊（double-stacked)、翼型結構（fin-structured) 、 樹枝狀堆疊 （spread-stacked) 和盒狀結構 (box-structured)等電容器下電極之製程，以高電容下電 本紙張尺度適用中國國家標芈（CNSXA4規格（210x297公釐> ------] i _丨丨丨丨丨訂·-----*梭 (請先閱讀背面之注意事項再填寫本頁) (M)( A7 B7 五、發明說明（Λ)) 極之表面積，進而提高電容器之儲存電荷量。 雖然本發明已以一較佳實施例揭露如上，然其並用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾’因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 ------I- I--ί)裝----- 訂·！ 1!*^^ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局貝工消费合作社印製 本紙張尺度適用中Β困家株準（CNS)A4規格<210x297公釐）绂 V Printed by the Consumer Cooperative of the Wisdom and Wealth Bureau of the Ministry of Economic Affairs Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed 4429 6 3 Λ7 r OOfi B7 V. Description of the invention (q) Including multi-product sand layers 3 1 ό a and 3 0 6 a ) 'And together with the selective hemispherical sand grain layer 320 form a capacitor lower electrode 322. Since a thinner doped amorphous silicon layer 306 is formed above the substrate 300, the number of polycrystalline silicon crystals 308 formed in the doped amorphous silicon layer 306 is smaller and the size is smaller. Furthermore, after the doped amorphous silicon layer is formed, the primary oxide layer and impurities on the doped amorphous silicon layer 306 are removed by a cleaning step, and then a doped amorphous silicon layer 316 is formed over the substrate 300. Therefore, on the interface 314 between the doped amorphous silicon layers 316 and 306, there is no nucleus for forming polycrystalline sand crystals. In addition, the interface 314 inhibits the continued growth of the polycrystalline silicon crystal 308. Therefore, in the doped amorphous silicon layer 316, the doped amorphous silicon layer 3 does not result in the doped amorphous silicon layer 3 丨 6. Polycrystalline silicon crystals are formed. Therefore, when the doped amorphous silicon layer 318 is patterned, a small portion of the polycrystalline sand crystals on the surface of the doped amorphous silicon layer 318 are not even exposed. In this way, the selective hemispherical silicon grain layer 320 can be formed on the surface of almost all the miscellaneous polycrystalline sand layer 318, so the surface area of the lower electrode of the capacitor to be formed can be greatly increased, and the capacitance of the capacitor can be increased. A preferred embodiment of the present invention is to form a columnar (cy 丨 ind 1: i C a 1 > structure capacitor lower electrode as an example). In practical applications, the present invention can also be applied to a double-stack (double- Stacked, fin-structured, spread-stacked, and box-structured capacitors are used in the lower electrode process of capacitors. Powering down with high capacitance. This paper applies Chinese national standards ( CNSXA4 Specifications (210x297 mm > ------] i _ 丨 丨 丨 丨 丨 Order · ----- * Shuttle (Please read the precautions on the back before filling this page) (M) (A7 B7 V. Description of the invention (Λ)) The surface area of the electrode is increased, which further increases the stored charge of the capacitor. Although the present invention has been disclosed above with a preferred embodiment, it is also used to limit the present invention. Anyone skilled in this art will not depart from Within the spirit and scope of the present invention, various modifications and retouching can be made. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application. ------ I- I--ί) ----- Order · 1! * ^^ (Please read the precautions on the back before filling in this page) Property Office HIGHLAND consumer cooperatives printed in this paper quasi Β sleepy family strains (CNS) A4 size scale applicable < 210x297 mm)