TW442898B - Method of using shallow trench to increase isolation capability - Google Patents

Abstract

This invention is about the method of increasing isolation capability. Shallow trench is formed in the semiconductor device of a chip, in which this chip is provided with a semiconductor substrate. In addition, the first gate oxide layer is formed on this semiconductor substrate and a silicon nitride layer is formed on this gate oxide layer. This method includes the following procedures. At first, a deep well is formed in the semiconductor substrate. Gate oxide layer and silicon nitride layer are then defined. After that, trench is formed. Based on the patterns of gate oxide layer and silicon nitride layer, parts of the gate oxide layer and silicon nitride layer are etched. After that, the first doping process is performed to form two device cells in the deep well of semiconductor substrate. These two device cells are annealed. The whole silicon nitride layer is removed. The second doping is conducted onto device cell and the third doping is performed onto device cell. The first gate oxide layer is removed. The second gate oxide layer, a polysilicon layer and a layer of tungsten silicide are sequentially deposited. A polysilicon gate is defined. Polysilicon gate is etched, in which this polysilicon gate is contacted with these two memory cells. A cell isolation structure under the trench is undergone with a doping process, in which the cell isolation structure is located in between two device cells. An annealing process is performed onto device cell and cell isolation structure. A conformal silicon oxide layer is deposited to fill up the trench. After that, a planarization process is conducted onto the surface of silicon oxide layer.

Description

442898-^-§8109874 ^ Modification on the fifth day of the invention Description of the invention (1) '~ ~ 5-1 Field of the invention: The present invention relates to a method for increasing the isolation ability, and in particular, it relates to the species in BN + R Method for forming shallow trenches in adjacent areas between M cells 5 ~ 2 Background of the invention The main function of the conventional 4 δ Read Only Memory (ROM) is to read data. Because the data will not be lost due to the power supply interruption. This is also called non-volatile memory (N ο η-V ο 1 ati 1 e Memory) ° Figure A is a traditional read-only memory crystal The top view of the cell '^ two implanted regions in the figure] 〇2 and two polycrystalline silicon regions 丨 丨 〇 The area surrounded by the cell isolation region i 〇3 D implantation region 丨 〇2 is generally a high concentration of God It is formed by being implanted into a p-type silicon substrate, and is usually labeled as M + (Buried N +). Its function is generally the source or the drain of a metal-oxide semiconductor transistor. The polycrystalline silicon region 110 generally functions as a gate of a metal-oxide semiconductor, and deposits a polycrystalline silicon layer on a silicon oxide layer on the surface of a silicon substrate. The unit cell isolation region 1 0 3 ′ is conventionally formed by ion implantation—the isolation region. The first diagram B is a cross-sectional view of the read-only memory cell of the first diagram A. The implantation region 102 is formed in the silicon substrate 101, and the cell isolation region 103 is in the implantation region 102. intermediate. The ideal memory is low cost, high performance, high density, and low power consumption.

Page 4 2000. 12.06.005 4428 9 8 _ Case No. 88109874 _ Month and Day __ V. Description of the invention (2) Can be 'random access, non-volatile, easy to test, high reliability and standardization of all processes . Moreover, better cell isolation lines are expected to increase anti-punch through strength. Unfortunately, these memory technologies are repeatedly challenged and fail to provide the benefits of foot fishing. Therefore, how to obtain better cell isolation is an urgent matter. 5-3 Purpose and Summary of the Invention: In view of the above-mentioned background of the invention, there are many shortcomings caused by traditional manufacturing. The present invention therefore proposes a method for forming shallow trenches to substantially increase the isolation capability. In one embodiment, a shallow trench is formed in a semiconductor device of a wafer. The wafer has a semiconductor substrate, and the semiconductor substrate

Page 5 2000. 12.06.006 442δ98 Case No. 88109874 Amendment V. Description of the Invention (3) There is a nitride formed on the bottom Gate oxidation This method package. Then determine the deep well at the bottom of the gate oxide layer. Under the second electrode oxide layer, the tungsten silicide layer is below the crystalline silicon gate. The oxide layer was siliconized for the first time, and then the tempered cell was deposited to deposit one more than two separate structures. The siliconized layer is deep in the subsequent elements. The element cell layer, a moment of polycrystalline silicon, a cell spacer, an oxide stone, a semiconductor, a trench, and a nitride are formed in half of the entire nitrogen. Removed polysilicon gates from the structure. The back layer is filled with a first Shixi layer. In the base. According to the layer and the gate conductor, the silicon-based layer is the first gate layer and one, which is more than the trench fire treatment trench. Layer to include the subsequent gate layer and nitrogen. After Then doped element. In order. Definition: Contact with vesicular septum cells to isolate oxygenated oxygen. First, doped with the argonized pattern. The two and third spar crystals are located on the surface layer of the deposition system. Dream layer. The ascaris engraved to form a two-element cell doped polar oxide. #. The 5-4 diagram of doping one of the two elements is briefly explained in order to make the above and other objects of the present invention easy to understand, and the following materials will be performed by β, "" The attack and advantages can be more clearly explained; Jiaguan cooperated with the attached drawings to make detailed ^ == one 8 is a schematic diagram of the traditional Γ read memory cell. The first A to the second [the figures show the present invention ~ not intended. The representative symbols of the main parts : 1 1 base

Page 5-1 2000.12.06.007 12 '1 2A Gate oxide layer 442898-~ Rev. V. Description of invention (4) 13 Nitride stone layer 14 P-type well area 15 BN + ROM cell 17 Polycrystalline sand layer 18 Shi Xihua Yan layer 101 Substrate 102 Implantation area 103 Isolation area 110 Polycrystalline silicon 5-5 Detailed description of the invention: Firstly, the structure of the invention will be specifically described—representing some changes and structures of the invention] to describe the invention. This will be followed. In addition, the second point is discussed next. Then, discuss the changes in the process of the better manufacturer. The conventional embodiment and the manufacturing of this embodiment are also called

However, this is not intended to illustrate the fact that there are several ROM cell elements. Therefore, this is not a schematic diagram to limit the scope and applicability of the present invention. Listed structure. These devices limit the semiconductor device of the present invention to all practical and applicability. It is used to prove the preferred embodiment of the present invention. Referring to the figure-A, the first heterotitanium silicon (SiN) layer 13 is formed on a substrate "privately supplies a gate oxide layer 12 and a nitrogen system to form a P Type well area 丨. Then, as shown in the second β diagram, to output a BN + ROM cell 15. Then the P side is 'as shown in the second C diagram', and I w 卿 / υ is deleted 1. ~ As shown in Figure 2D,

Page 6 2000.12.06.008 442898-Case No. 88109874 Che month day_correction 5 'Explanation of the invention (5) SiN layer 13 ′ is then performed in a conventional manner by the doping step of BN + ^ cell ^. Subsequently, the second E graph shows that the tempered BN + region is processed, and the gate oxide layer 12 of the BN + ROM cell 15 will become larger, while the bn + ί? 〇Μ cell 15 will shrink due to consumption, so the second The BN + r0m cell 15 of the E picture is smaller than the second D picture. Moreover, the thickness of the gate oxide layer 12 of the BN + ROM cell 15 is higher than that of the isolation region. Then 'as shown in the second F, remove the si N layer 1 3 a. Then, the implantation step of adjusting the starting voltage and the implantation step of NMOS resistance to breakdown are performed. Since the second picture is a read-only memory cell A cross-sectional view of this ion implantation step cannot be shown in the illustration. Di Er's G picture shows that the gate oxide layer is immersed, but a portion of the gate oxide layer with a thickness of several angstroms remains. Subsequently, as shown in the second n, after the above steps, a gate oxide layer 2A, a polycrystalline silicon layer 17 and a tungsten silicide layer 18 are sequentially deposited. Then, after the polysilicon gate is defined, the polycrystalline silicon layer 7 and the tungsten silicide layer 8 are then removed using a conventional dry etching method, as shown in the second figure I, and as shown in the second figure J. The dry etching method removes the excess oxide layer 12A, and the gate oxide layer 12A has been formed on the BN + ROM cell 15 ′. At the same time as in the second K diagram, the trench 19 is formed by a conventional etching method. This traditional etching method has different selectivity for silicon and silicon oxide systems. In addition, the ditch 19 will be formed from one BN + read cell 15 to another broken ROM cell 15 m. The second L picture shows the implantation step of the cell isolation structure 2 (). Among them, the defect between βN + surface cells ^ 5 and the isolation structure can be reduced by using the tungsten tungsten tempering method. Finally, referring to the second L diagram, a conformal SiO2 layer is deposited using PECVD or APCVD, and an etch-back (or CMP) step is performed. This process can achieve better isolation results. _The above description is only a preferred embodiment of the present invention ^, and is not intended to be limited.

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Claims (1)

4 428 9 8 6. Scope of patent application 1. A semiconductor element on a wafer has a semiconductor substrate, a body substrate, and a nitride layer. The method includes: deep-welling the first gate oxide layer of the semiconductor substrate The step in which the wafer is formed in the semiconductor to define the plurality of trenches has a first well in the step according to the engraved part; tempering should remove the entire second cell; removing the first gate oxidation Layer and the nitride layer and the first group of process variables; doped to form two elements and two element cells; a plurality of the silicon nitride; doped in the two element cells to form a shallow trench Method, and a first gate oxide layer forming a silicon layer is formed in the gate oxygen; a silicon nitride layer is then formed to define the step of forming a nitride nitride layer, an interlayer oxide layer, wherein the etching A second gate oxide layer of the two meta-layers is deposited in the deep substrate of the semiconductor substrate for the second time; a second gate oxide layer, a polycrystalline stone layer and a stone chemical layer are sequentially deposited. Polysilicon gate Describe the polysilicon gate, between the cells; the spar gate is in contact with the two elements, and a cell isolation structure is below the plurality of trenches, wherein the cell isolation structure is located between the two elements Between cells Page 9 442898 "Six, the patent application Fanyuan tempered the two element cell and the cell isolation structure;> one of the conformal oxide layer fills the plurality of groove rods; and flatten the oxide dream layer Surface >> 2. The method according to item 1 of the patent application, wherein the step of removing part of the silicon nitride layer includes a plasma etching process. 3. The method according to item 1 of the patent application, wherein the first method is etched. The step of the gate oxide layer includes the use of a plasma etching process. 4_ The method of the first scope of the patent application, wherein the deep well includes-pfa well 0 where the two element cells include 5. The method of item 2 includes two BN + ROM cells. 6. For the method of item 丄 of the patent application range, wherein the second step of doping the two element cells includes the initial voltage adjustment doping. 7. For the patent application range The method of item i, wherein the step of doping the two element cells for the third time includes NMOS anti-breakdown doping. The first gate oxygen is removed therein. The method layer as described in the first item of the patent application scope Methods include soaking. Page 10 442898 VI. Application scope of patent 9 · If the method of applying for the first item of patent scope, the step of tempering the isolation structure of the two element cells from the cell includes silicidation of silicon. 10. The method according to item 1 of the scope of patent application, wherein the method for forming the conformal gasification layer includes PECVD and APCVD. 1 1 · The method according to item 1 of the scope of patent application, wherein the method of planarizing the surface of the silicon oxide layer is selected from the group consisting of etch-back and CMP. 12. 12. A kind of ROM device on one chip Forming a friend of a shallow trench, wherein the wafer has a semiconductor substrate, and a first gate oxide layer is formed on the semiconductor substrate, and a silicon nitride layer is formed on the gate oxide layer. The method includes: forming a deep well in the semiconductor substrate; defining the first gate oxide layer and the silicon nitride layer, and thereafter forming a plurality of trenches; according to the first gate oxide layer and the silicon nitride layer The defining step is to etch the silicon nitride layer and the first gate oxide layer, wherein the #etching step has a set of process variables; the first doping to form two element cells on the semiconductor substrate In the manhole; soil-tempering the two element cells; removing the entire nitrided dream layer; Page 11 442898 6. Application scope S ---- Doping the two element cells for the second time; Doping the two element cells for the third time; Removing the first gate oxide layer; Depositing one in order A second gate oxide layer, a polycrystalline silicon layer, and a tungsten silicide layer; a polycrystalline silicon interlayer; etching the polycrystalline silicon gate, the polycrystalline silicon gate contacting between the two element cells; a doped cell The isolation structure is below the plurality of trenches, wherein the cell isolation structure is located between the two element cells; 'tempering the two element cells and the cell isolation structure; depositing a conformal silicon oxide layer to fill the cell A plurality of trenches; and planarizing the surface of the oxide layer β 13. The method of claim 12 in which the step of removing a portion of the vaporized silicon layer includes using a plasma etching process. 14. The method of claim 12 in the scope of patent application, wherein the step of etching the first-gate oxide layer includes using a plasma etching process. 15. The method of claim 12 in the patent application range, wherein the deep well includes a -ρ well. 16. The method according to item 12 of the patent application, wherein the two elements are encapsulated Page 12 44289 8 VI. Application scope of patents-including two M + ROM cells "If the method of applying for the item 12 of the patent scope, the second step of replacing the two 70 cells includes Initial voltage adjustment is complicated. 18. The method of claim 12 in which the third step of doping the two element cells includes NMOS anti-breakdown doping. 19, such as the method of item 12 of the patent scope, wherein the method of removing the first gate oxide layer includes the immersion method "| 20. The method of item 12 of the patent scope, wherein the element cell and the element are tempered The step of the cell isolation structure includes doping tungsten silicide. Among them, the oxygen which is conformal is formed. 21. The method according to item 12 of the patent application method of forming a layer includes PECVD and APCVD. 22. The method according to item 12 of the scope of patent application, wherein the method of flattening the surface of the layer is selected from the group consisting of the etch-back method and the CMP-to form the silicon oxide ν, and the city is close to the group. Page 13