TW441084B - Semiconductor apparatus - Google Patents

Semiconductor apparatus Download PDF

Info

Publication number
TW441084B
TW441084B TW089104256A TW89104256A TW441084B TW 441084 B TW441084 B TW 441084B TW 089104256 A TW089104256 A TW 089104256A TW 89104256 A TW89104256 A TW 89104256A TW 441084 B TW441084 B TW 441084B
Authority
TW
Taiwan
Prior art keywords
resistor
resistance
circuit
semiconductor device
protection
Prior art date
Application number
TW089104256A
Other languages
Chinese (zh)
Inventor
Tadao Seto
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of TW441084B publication Critical patent/TW441084B/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

This invention is to achieve sufficient resistance against electrostatic breakdown without reducing circuit speed in an electrostatic breakdown protection circuit that is provided at an input part. A protection resistance part 13-2 consisting of a protection resistor R1, a resistor R2 that is connected in parallel with the protection resistor R1, and a switch S1 that is connected in series with the resistor R2 is provided, for example, between an input pad 11 and an input circuit 12, that is connected to it as an electrostatic breakdown protection circuit 13 via a protection element part 13-1. Then, in an operation mode, the switch S1 is turned on by a control signal for reducing the resistance of the protection resistance part 13-2, where as in a non-operation mode, the switch S1 is turned off by the control signal for increasing the resistance of the protection resistance part 13-2, thus switching resistance according to the conditions.

Description

4410^4 . Λ/δ Λ] η« / __έ. 經濟部智慧財產局員工消費合作社印*''Λ 五、發明說明（1 ) <發明所屬之技術領域> 本發明係關於半導體装置、特別是關於具備用以防止輸 出/入電路之靜電破壞之靜電破壞保護電路之半導體裝 置。 <習知技術> 以往用以防止輸出/入電路之靜電破壞之靜電破壞保護 電路係顧慮對靜電破壞之耐受性，而決定保護電阻之大小 (電阻値）。 圖9表示將習知之靜電破壞保護電路之概略構造用於半 導體裝置之輸入部之情況之例。 於該情況下，爲了保護構成輸入電路101之輸入段之 CMOS反相器之p通道MOS電晶體101 a及η通道MOS電晶體 101b之各間氧化暎免受靜電破壞，在該輸入電路丨〇1及輸 入墊（pad) 102之間設置靜電破壞保護電路103。 靜電破壞保護電路103係具有由例如設於電源VDD與輸 入墊102之間之p通道MOS電晶體1 〇3a，及設於接地GND 與輸入墊102之間之η通道MOS電晶體i〇3b所成之保證元 件103-1及保護電阻103-2而構成。 於此種構造之靜電破壞保護電路103中，藉由使保護電 路1〇3-2變大，可使其對靜電破壞具有充分之耐受性。 惟’若使保護電阻103-2變大’則會有不僅面積増大。 輸入信號延遲等影響輸入信號之傳達速度之問題。 <發明欲解決之問題> 如上所述’習知技術藉由使保護電阻變大使其對靜電破 t I 1 Γ — — — — — — I— 裝·--I I I I 1 * I I I I I I 1 I ) c請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X _297公t ) A7 4 41 08 4 -----B7 五、發明說明（2 ) 壞具有充分之耐受性，但卻有造成因保護電阻變大而使電 路動作速度降低之問題s 本發明於此便以提供一不會造成電路動作速度降低且可 對靜電破壞具充分之耐受性之半導體裝置 <解決課題之手段> 爲達成上述目的，本發明之半導體裝置係包含：外部端 子；連接於該外部端子之内部電路；以及設於該内部電路 與前述外部端予之間，具有被控制成在通常動作時電阻値 下降’在非動作時電阻値上升之電阻部之靜電破壞保護電 路。 依本發明之半導體裝置’可因應狀況切換控制電阻値。 藉此’可得到在動作時及非動作時各最適宜之電阻値。 <發明之實施形態> 以下參照圖面說明本發明之實施形態。 (第1實施形態） 、圖1係本發明之第一實施形態之半導體裝置之概略構 造此處係表不將靜電破壞保護電路使用於輸入部之例。 Ρ旧輸入部係於例如輸入墊（外部端子）1 1、與其相連 、輸電路（内部電路）12之間，設置靜電破壞保護電路 13 = 靜電破壞保護電路13具有例如：設於上述輸入整Η側之 a —牛部13-1，及設於上述輸入電路〗2侧，被控制成在 2動作換式時電阻値下降，在非動 上升 護電阻部13-2。 本紙張尺⑭祕⑵-- t I^--------訂--------—線 r (請先閱讀背面之注意事項再填寫本頁> 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 4 41 0 8 4 Λ7 ______B7___ 五、發明說明（3 ) 於該情況下，保護元件部13-1具有設於電源VDD與上述 輸入墊1 1之間之p通道MOS電晶體13a ;及設於接地GND 與上述輸入墊1 1之間之η通道MOS電晶體13b。 保護電阻部1 3 - 2係包含例如：保護電阻（第1電阻）R 1 ; 與該保護電阻R 1並聯之電阻（第2電阻）R 2 ;以及與該電 阻R2串聯之開關（SW)S1。 於該情況下，保護電阻R1爲了保護構成上述輸入電路 12之輸入段之CMOS反相器之p通道MOS電晶體12a及η通 道MOS電晶體12b之各閘氧化膜免於靜電保護，具有對該 靜電破壞充足之耐受性（電阻値）。 另一方面，電阻R 2之値係爲可使合成電阻値（Ri . R2/ (R1+R2))成爲適於電路速度之電阻値。 於此構造中，例如將使晶片内部成爲動作狀態/非動作 狀態之致能信號作爲控制信號，在非動作模式時，使上述 開關S 1爲“關”。藉此，保護電阻部1 3 - 2之總輸入電阻可 被做成對保護電阻；所造成之靜電破壞具備充足的耐受性 者。 於是在非動作換式時，可保護構成輸入電阻12之輸入 段之CMOS反相器之p通道MOS電晶體12a及^通道河03電 晶體12b之各閘氧化膜免受靜電破壞。 相對於此，在動作模式時’依控制信號使上述開關s i 爲開。藉此，保護電阻邵13-2之總輸入電阻可依保護電 阻R1與電阻R2並聯而成之合成電阻，被做成比保護電阻 R1小而適於電路動作速度者。 -6' 木纸張又度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----11I1I—I1 裝.I — 丨 I 1 I !訂!丨 — — 丨丨· 丨 (請先閱讀背面之注意事項再填寫本頁) 4 41 08 4 A7 137 經濟部智慧財產局員工消費合作社印製 五、發明說明（ 故，在動作模式時，因可排除輸入信號延遲等對輸入信 號之傳達速度造成之影響’故可達成適宜之電路動作速 度。 (第2實施形態） 圖2爲本發明之第2實施例之半導體裝置之概略構造 圖。此處係顯示將靜電破壞保護電路用於輸入部之例。 於該情況下，上述輸入墊11及上述輸入電路12之間所 設之靜電破壞保護電路13之電阻部設有保護電阻13-21， 其係具有：保護電阻（第1電阻）R 1 ;各與該保護電阻R !並 聯之複數之％阻（第2電阻）R2a、R_2b.,,;與各電阻R2a、 R2b…串聯之各開關Sla、Sib...。 於此構造中，例如藉由控制信號選擇性的使上述開關 Sla、Sib··.成爲“開”/“關”，可獲得與上述第i實施形 態略相同之效果’並且特別是在動作模式時，可將電阻値 更精細的予以切換控制。 (第3實施例） 圖3爲本發明之第3實施例之丰導體裝置之概略構造。 此處表示將靜電保護破壞電路用於輸入部之情况之例。 於4情況下’設於上述輸入整11與上述輸入電路12之 間之靜電破壞保護電路13之電阻部係有保護電阻部13_ 22，其係由例如以下構件並聯而成；保護電阻（第1電 阻）R 1 ;與該保護電阻R 1串聯’由第1控制信號控制之開 關（弟1開關）Sla ’·電阻（第2電阻）R2 ;與該電阻R2串 聯’由第2控制信號控制之開關（第2開關）Slb。（惟，R1 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公笼） (請先閱讀背面之注意事項再填寫本頁) -------訂--II--1 — ·線 4 4 1 0 8 4 A7 B7 五、發明說明（5 SR2)。 於該構造中，與上述弟施形態略相同，例如在命第 丄控制信號僅使上述開關Sla爲“開，，之情況（非動作模式 時），可選擇性的得到能充分承受保護電阻及1所造成之靜 電破壞之電阻値；又在由第2控制信號僅使上述開關slb 爲“開”之情況（動作模式時）可選擇性的得到適於電阻R2 所造成之電路動作速度之電阻値。 (第4實施形態） 圖4爲本發明之第4實施形態之半導體裝置之概略構 造。此處表示將靜電破壞保護電路用於輸入部之情況之 例。 於該情況下’設於上述輸入墊11與上述輸入電路12之 間之靜電破壞保護電路1 3之電阻部係設有保護電阻部i 3 · 2 3，其係由例如以下構件並聯而成；保護電阻（第j電 [5· ) R 1 ;與該保護電阻R 1串聯，由控制信號反轉控制開 關（第1開關）SI a ;電阻（第2電阻）R2 ;與該電阻R2串 聯' 由上述控制信號非反轉控制之開關（第2開關）s 1 b。 (惟 R1 ^R2)。 於該構造中，與上述第3實施形態之情況略相同，例 如，藉由以控制信號選擇性的使上述開關S 1 a、S 1 b ‘‘開” / “關”，在非動作模式時可得到能充分承受保護電阻 R1所造成之靜電破壞之電阻値；又在動作模式時可得到 適於電阻R2所造成之電路動作速度之電阻値。 (第5實施形態） -8 - 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公餐） f請先閱讀背面之注意事項再填寫本頁) 裝---------訂-------丨線 經濟部智慧財產局員工消費合作社印製 Λ41 08 4 Λ7 ---— Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 ) 圖5爲本發明之第5實施形態之半導體裝置之概略構造 圖。此處表示將靜電破壞保護電路用於輸入部之情況之例。 於該情沉下，設於上述輸入墊11與上述輸入電路12之 間之靜電破壞保護電路13之電阻部設有由例如可變電阻尺 所成之保護電阻部13_24。 於該構造中，例如，由基於外部指示之控制信號切換上 述可變電阻R之電阻値，在非動作模式時可得到能充分承 受靜電破壞之電阻値，又，在動作模式時可得到能適於電 路動作速度之電阻值。 (第6實施形態） 圖6爲本發明之第$實施形態之半導體裝置之概略構 造。此處表示將靜電破壞保護電路用於輸入部之情況之 例。 於該情形下’設於上述輸入塾11與上述輸入電路12之 間之靜電破壞保護電路i 3之電阻部設有由例如保護電阻 (第1電阻）R1、與之串聯之電阻（第2電阻）r2、及使上述 保遵電阻R 1之兩端短路之開關S 1所成之保護電阻部13 -25。 於該構造中，與上述第5實施形態之情況略相同，藉由 以控制信號使上述開關S 1成爲“開’，/ “關”，在非動作模式 時可得到能充分承受保護電阻R 1及電阻R 2串聯所造成之 靜電破壞之電阻値，又在動作模式時能得到可適於電阻造 成之電路動作速度之電阻値。 如上述，可因應狀況切換控制電阻値α -9 - (請先閱讀背面之注意事項再填寫本頁) 裝------II訂·--------線 本纸張尺度適用t國國家標準（CNS)A4規格（210x297公釐） 4 4 10 8 4 經濟部智慧財產局員工消費合作社印製 五、發明說明（7 ) 即，在非動作模式時可設定成能充分承受靜電破壞之電 阻値，又在動作模式時可設定成能適於電路動作速度之電 阻値。藉此，在動作模式及非動作模式皆爲可得到最適當 之電阻値。故，靜電破壞保護電阻不會造成電路動作速度 降低，且可充分承受靜電破壞。 於上述本發明之各實施形態中，皆係説明使用於輸入部 之例，不限於此，例如圖7所示，亦可用作爲在輸出入整 21上所連接之輸出電路22之輸出部之靜電破壞保護電路 13。 即，在用於輸出部之情況下，可保護構成輸出電路22 之輸出段之CMOS反相器之n通道MOS電晶體22a及通道 MOS電晶體22b之各閘氧化膜免受靜電破壞。 又，例如圖8所示，亦可用於作爲輸出入墊31連接之輸 入電路12及輸出電路22之輸出/入部之靜電破壞保護電路 13; 即在用於輸出/入部之情況下，例如構成輸入電路12之 輸入段之CMOS反相部之p通道MOS電晶體12a及η通道 MOS電晶體12b之各問氧化膜；以及構成輸出電路22之 輸出段之CMOS反相器之η通道MOS電晶趙22a及p通道 MOS電晶體22b之各閘氧化膜，皆可受到保護免受靜電 破壞。 其他在不改變本發明之範圍下，可有各種變形實施。 <發明之效果> 以上，依上述之本發明可提供一半導體裝置，其不會造 -10- —--^· I —-----1τ·---I---_ — (請先閱讀背面之注意事項再填寫本頁) 本纸張尺度適用令國國家標準（CNS)A4規格（210 X 297公t ) 經濟部智慧財產局員工消費合作社印製 ” Cl 8 t A7 _B7_五、發明說明（8 ) 成電路動作速度降低，且可充分承受靜電破壞。 <圖面之簡單説明> [圖1 ] 本發明之第1實施形態之半導體裝置構造之輸入部概略 表示。 [圖2] 本發明之第2實施形態之半導體裝置構造之輸入部概略 表示圖。 [圖3] 本發明之第3實施形態之半導體裝置構造之輸入部概略 表示圖。 [圖4] 本發明之第4實施形態之半導體裝置構造之輸入部概略 表示圖。 [圖5] 本發明之第5實施形態之半導體裝置構造之輸入部概略 表示圖。[圖6] 本發明之第6實施形態之半導體裝置構造之輸入部概略 表示圖。 [圖7] 本發明之丰導體裝置構造之輸出部概略表示圖。 [圖8] 本發明之半導體裝置構造之輸出/入部概略表示圖。 -11 - (請先閱讀背面之注意事項再填寫本頁) 裝·--- 訂---------線 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印制^ 441 08 4 A7 _B7_五、發明說明（9)[圖9] 用以説明習知技術及其問題點之半導體裝置之輸入部概 略構成圖。[符號説明] 1 1...輸入墊 1 2 ...輸入電路 12a...p通道MOS電晶體 12b., .η通道MOS電晶體 13...靜電破壞保護電路 1 3 - 1 ...保護元件部 13-2，13-21，13-22，13-23，13-24，13-25 ...保護電阻部 13a...p通道MOS電晶體 13b.…η通道MOS電晶體 2 1 ...輸出墊 22 ...輸出電路 22a.,.η通道MOS電晶體 22b...ρ通道MOS電晶體 3 1 ...輸出入墊 R 1 ...保護電阻 R2，R2a，R2b，〜...電阻 R...可變電阻 S 1，S 1 a，S 1 b，〜_ 開關 V D D ...電源 GND ...接地 -12- .----— — — — —--.. *-------訂--------- <請先閱讀背面之注意事項再填寫本I) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公S )4410 ^ 4. Λ / δ Λ] η «/ __έ. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs * '' Λ V. Description of the invention (1) < Technical field to which the invention belongs > The present invention relates to semiconductor devices, In particular, the present invention relates to a semiconductor device having an electrostatic destruction protection circuit for preventing electrostatic destruction of an input / output circuit. < Known Technology > Conventional electrostatic damage protection circuits to prevent electrostatic damage to output / input circuits are concerned about the resistance to electrostatic damage and determine the size of the protection resistor (resistance 値). Fig. 9 shows an example of a case where a schematic structure of a conventional electrostatic discharge protection circuit is applied to an input portion of a semiconductor device. In this case, in order to protect the p-channel MOS transistor 101a and the n-channel MOS transistor 101b of the CMOS inverter constituting the input section of the input circuit 101 from oxidation damage, the input circuit An electrostatic damage protection circuit 103 is provided between the 1 and the input pad 102. The ESD protection circuit 103 has, for example, a p-channel MOS transistor 10a provided between the power supply VDD and the input pad 102, and an n-channel MOS transistor i03b provided between the ground GND and the input pad 102. It consists of a guaranteed element 103-1 and a protective resistor 103-2. In the electrostatic destruction protection circuit 103 having such a structure, by making the protection circuit 10-3-2 larger, it is possible to make it sufficiently resistant to electrostatic destruction. However, if "the protection resistor 103-2 is made larger", there is a large area. Issues such as input signal delay that affect the speed at which input signals are transmitted. < Problems to be Solved by the Invention > As described above, the conventional technique increases the protection resistance to break static electricity. cPlease read the notes on the back before filling this page) This paper size is applicable to China National Standard (CNS) A4 (210 X _297g t) A7 4 41 08 4 ----- B7 V. Description of the invention (2) It has sufficient resistance, but it causes the problem that the operating speed of the circuit is reduced due to the increase of the protective resistance. The present invention is here to provide a circuit that does not cause a decrease in the operating speed of the circuit and has sufficient resistance to electrostatic damage. Acceptable semiconductor device < means for solving the problem > In order to achieve the above object, the semiconductor device of the present invention includes: an external terminal; an internal circuit connected to the external terminal; and an internal circuit provided between the internal circuit and the aforementioned external terminal. At the same time, there is an electrostatic destruction protection circuit in a resistance portion which is controlled to have a resistance 値 drop during normal operation and a resistance 値 increase during non-operation. According to the semiconductor device of the present invention, the control resistor 値 can be switched depending on the situation. By this, 'the optimum resistance 値 can be obtained during operation and non-operation. < Embodiment of the invention > An embodiment of the present invention will be described below with reference to the drawings. (First Embodiment) Fig. 1 is a schematic configuration of a semiconductor device according to a first embodiment of the present invention. Here, an example in which an electrostatic discharge protection circuit is used for an input section is shown. The old input section is connected to, for example, an input pad (external terminal) 1 1. It is connected between it and an output circuit (internal circuit) 12 and an electrostatic discharge protection circuit 13 is provided. 13 = The electrostatic discharge protection circuit 13 has, for example: On the side a—the cow part 13-1, and the two sides provided on the input circuit are controlled so that the resistance 値 drops during the two-action switching type, and the protection part 13-2 is raised in the non-moving state. Secret of this paper rule-t I ^ -------- Order ---------- line r (Please read the notes on the back before filling out this page> Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the employee's consumer cooperative, printed by the Intellectual Property Bureau of the Ministry of Economic Affairs 4 41 0 8 4 Λ7 ______B7___ 5. Description of the invention (3) In this case, the protection element section 13-1 has a power supply VDD and the above-mentioned input pad 1 P-channel MOS transistor 13a between 1; and n-channel MOS transistor 13b provided between ground GND and the above-mentioned input pad 1 1. The protective resistor section 1 3-2 includes, for example, a protective resistor (first resistor) R 1; a resistor (second resistor) R 2 connected in parallel with the protection resistor R 1; and a switch (SW) S1 connected in series with the resistor R 2. In this case, the protection resistor R 1 protects the input constituting the input circuit 12 described above. The gate oxide films of the p-channel MOS transistor 12a and the n-channel MOS transistor 12b of the segmented CMOS inverter are protected from static electricity and have sufficient resistance to resistance to static electricity (resistance 値). On the other hand, resistance R 2 is to make the combined resistance (Ri. R2 / (R1 + R2)) a resistance suitable for the circuit speed. In this structure, for example, an enable signal for making the inside of the wafer into an operating state / non-acting state is used as a control signal, and in the non-operation mode, the above-mentioned switch S 1 is turned "OFF". As a result, the protective resistor 1 3- The total input resistance of 2 can be made to protect the resistance; the electrostatic damage caused by it has sufficient resistance. Therefore, in the non-action mode, it can protect the p of the CMOS inverter that constitutes the input section of the input resistance 12. The gate oxide films of the channel MOS transistor 12a and the channel transistor 03b are protected from electrostatic damage. In contrast, in the operation mode, the above-mentioned switch si is turned on according to the control signal. Thus, the protection resistor 13- The total input resistance of 2 can be made according to the combined resistance of the protective resistor R1 and the resistor R2 in parallel, which is made smaller than the protective resistor R1 and suitable for the circuit operation speed. -6 'wood paper is also applicable to the Chinese national standard (CNS ) A4 specification (210 X 297 mm) ---- 11I1I—I1 pack. I — 丨 I 1 I! Order! 丨 — — 丨 丨 · 丨 (Please read the precautions on the back before filling this page) 4 41 08 4 A7 137 Consumer Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printing 5. Description of the invention (Therefore, in the operation mode, the influence of the input signal delay on the transmission speed of the input signal can be eliminated. Therefore, an appropriate circuit operation speed can be achieved. (Second Embodiment) Fig. 2 shows this A schematic diagram of a semiconductor device according to a second embodiment of the invention. Here is an example of using an electrostatic destruction protection circuit for the input section. In this case, the static electricity provided between the input pad 11 and the input circuit 12 The resistance portion of the damage protection circuit 13 is provided with a protection resistor 13-21, which includes: a protection resistor (first resistor) R 1; a plurality of% resistances (second resistors) R2a, R_2b each connected in parallel with the protection resistor R! . ,,; Each switch Sla, Sib ... connected in series with each resistor R2a, R2b .... In this structure, for example, by selectively controlling the switches Sla, Sib, ... to "on" / "off" by the control signal, the same effect as that of the i-th embodiment described above can be obtained ', and especially in the operation mode In this case, the resistor 値 can be fine-tuned for switching control. (Third Embodiment) Fig. 3 is a schematic structure of a abundant conductor device according to a third embodiment of the present invention. Here is an example of a case where an electrostatic protection destruction circuit is used for the input section. In 4 cases, the resistance portion of the electrostatic destruction protection circuit 13 provided between the above-mentioned input unit 11 and the above-mentioned input circuit 12 is a protection resistance portion 13_22, which is formed by, for example, paralleling the following components; the protection resistance (the first Resistor) R 1; in series with the protective resistor R 1 'a switch controlled by the first control signal (brother 1 switch) Sla' · resistor (second resistor) R2; in series with the resistor R2 'controlled by the second control signal Switch (second switch) Slb. (However, the paper size of R1 is applicable to China National Standard (CNS) A4 specification (210 x 297 male cage) (Please read the precautions on the back before filling out this page) ------- Order--II--1 — · Line 4 4 1 0 8 4 A7 B7 V. Description of the invention (5 SR2). In this structure, it is slightly the same as the above-mentioned configuration. For example, when the first control signal is set to ON, In the case (non-operation mode), a resistance 値 that can fully withstand the protection resistance and the electrostatic damage caused by 1 can be selectively obtained; and when the above-mentioned switch slb is "on" by the second control signal (action In the mode), a resistor 适于 suitable for the operating speed of the circuit caused by the resistor R2 can be selectively obtained. (Fourth Embodiment) FIG. 4 is a schematic structure of a semiconductor device according to a fourth embodiment of the present invention. An example of the case where the damage protection circuit is used for the input portion. In this case, the resistance portion of the electrostatic damage protection circuit 1 3 provided between the above-mentioned input pad 11 and the above-mentioned input circuit 12 is provided with a protection resistance portion i 3 · 2 3, which is formed by, for example, the following components connected in parallel; protection Resistance (jth electrical [5 ·) R 1; in series with the protection resistance R 1, the control signal (first switch) SI a is reversed by the control signal; resistance (second resistance) R 2; in series with the resistance R 2 ' The above-mentioned control signal is a switch (second switch) s 1 b. (But R1 ^ R2). In this structure, it is slightly the same as that in the third embodiment. For example, by using the control signal selectivity When the above-mentioned switches S 1 a and S 1 b are turned “on” / “off”, a resistance 能 that can fully withstand the electrostatic damage caused by the protective resistor R1 can be obtained in the non-operation mode; and an appropriate resistance can be obtained in the operation mode. The resistance 动作 caused by the resistance of the circuit R2 caused by the resistance R2. (Fifth embodiment) -8-This paper size applies to China National Standard (CNS) A4 (210 X 297 meals) f Please read the precautions on the back before reading (Fill in this page) Install --------- Order ------- 丨 Printed by the Intellectual Property Bureau Employee Consumption Cooperative of the Ministry of Economic Affairs Λ41 08 4 Λ7 ----- Β7 Employee Consumption of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the cooperative V. Explanation of the invention (6) FIG. 5 is a schematic diagram of a semiconductor device according to a fifth embodiment of the present invention structure map. Here is an example of a case where an electrostatic discharge protection circuit is used for the input section. In this case, the resistance portion of the electrostatic destruction protection circuit 13 provided between the input pad 11 and the input circuit 12 is provided with a protective resistance portion 13_24 made of, for example, a variable resistance scale. In this structure, for example, the resistance 値 of the variable resistor R is switched by a control signal based on an external instruction. In the non-operation mode, a resistance 充分 which can sufficiently withstand the damage of static electricity can be obtained, and in the operation mode, a suitable resistance 得到The resistance value depends on the circuit operating speed. (Sixth Embodiment) Fig. 6 is a schematic configuration of a semiconductor device according to a sixth embodiment of the present invention. This example shows the case where an electrostatic discharge protection circuit is used for the input section. In this case, the resistance portion of the electrostatic destruction protection circuit i 3 provided between the input 塾 11 and the input circuit 12 is provided with, for example, a protective resistor (first resistor) R1 and a resistor (second resistor) connected in series therewith. ) R2, and the protection resistors 13 to 25 formed by the switch S 1 which short-circuits both ends of the above-mentioned compliance resistor R 1. In this structure, it is slightly the same as the case of the above-mentioned fifth embodiment. By using the control signal to make the switch S 1 "ON", "OFF", it is possible to obtain sufficient protection resistance R 1 in the non-operation mode. The resistance 破坏 caused by the static electricity damage caused by the series connection of the resistor R 2 and the resistance 适于 suitable for the circuit operation speed caused by the resistance 动作 in the operation mode. As mentioned above, the control resistance 値 α -9-(Please Read the precautions on the back before filling in this page.) -------- Order II · -------- The size of the thread paper is applicable to the national standard (CNS) A4 (210x297 mm) 4 4 10 8 4 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (7) That is, in the non-operation mode, it can be set to a resistance that can fully withstand static electricity damage. In the operation mode, it can be set to be suitable. The resistance 电路 at the operating speed of the circuit. Therefore, the most suitable resistance 可 can be obtained in both the operating mode and the non-operating mode. Therefore, the electrostatic damage protection resistor will not cause the circuit to operate at a reduced speed, and can fully withstand the electrostatic damage. The above hair In each of the embodiments, the examples are used for the input part, and it is not limited to this. For example, as shown in FIG. 7, it can also be used as the electrostatic damage protection circuit 13 of the output part of the output circuit 22 connected to the input / output unit 21. That is, when used in the output section, the gate oxide films of the n-channel MOS transistor 22a and the channel MOS transistor 22b of the CMOS inverter constituting the output section of the output circuit 22 can be protected from electrostatic damage. For example, as shown in FIG. 8, it can also be used as the input circuit 12 connected to the input / output pad 31 and the electrostatic damage protection circuit 13 in the output / input part of the output circuit 22; that is, in the case of the input / output part, for example, the input circuit is constituted. The oxide film of the p-channel MOS transistor 12a and the n-channel MOS transistor 12b of the CMOS inverting part of the input section of 12; and the n-channel MOS transistor of the CMOS inverter constituting the output section of the output circuit 22 Each gate oxide film of the p-channel MOS transistor 22b can be protected from being damaged by static electricity. Others can be implemented with various modifications without changing the scope of the present invention. ≪ Effects of the invention > The hair Can provide a semiconductor device, which will not make -10- —-- ^ · I —----- 1τ · --- I ---_ — (Please read the precautions on the back before filling this page) The paper size applies the national standard (CNS) A4 specification (210 X 297 gt) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Cl 8 t A7 _B7_ V. Description of the invention (8) The speed of the circuit is reduced. And can fully withstand electrostatic damage. < Brief description of drawings > [Fig. 1] An input portion of a semiconductor device structure according to a first embodiment of the present invention is schematically shown. [Fig. 2] A schematic illustration of an input section of a semiconductor device structure according to a second embodiment of the present invention. [Fig. 3] A schematic illustration of an input section of a semiconductor device structure according to a third embodiment of the present invention. [Fig. 4] A schematic illustration of an input section of a semiconductor device structure according to a fourth embodiment of the present invention. [FIG. 5] A schematic diagram showing an input portion of a semiconductor device structure according to a fifth embodiment of the present invention. [Fig. 6] A schematic illustration of an input section of a semiconductor device structure according to a sixth embodiment of the present invention. [Fig. 7] A schematic diagram showing an output section of the Feng conductor device structure of the present invention. [FIG. 8] A schematic illustration of an input / output section of a semiconductor device structure according to the present invention. -11-(Please read the precautions on the back before filling in this page) Loading · --- Ordering --------- The size of thread paper is applicable to China National Standard (CNS) A4 (210 X 297) (%) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 441 08 4 A7 _B7_ V. Description of Invention (9) [Figure 9] A schematic diagram of the input section of a semiconductor device used to explain the conventional technology and its problems. [Symbol description] 1 1 ... input pad 1 2 ... input circuit 12a ... p-channel MOS transistor 12b., .Η-channel MOS transistor 13 ... electrostatic destruction protection circuit 1 3-1 .. .Protection element section 13-2, 13-21, 13-22, 13-23, 13-24, 13-25 ... Protection resistor section 13a ... p-channel MOS transistor 13b .... n-channel MOS transistor 2 1 ... output pad 22 ... output circuit 22a.,. Η channel MOS transistor 22b ... ρ channel MOS transistor 3 1 ... output input pad R 1 ... protection resistors R2, R2a, R2b, ~ ... resistance R ... variable resistors S1, S1a, S1b, ~ _ Switch VDD ... Power GND ... Ground -12- .----— — — — —-- .. * ------- Order --------- < Please read the notes on the back before filling in this I) This paper size applies to China National Standard (CNS) A4 specifications ( 210 X 297 male S)

Claims (1)

^41 084 A8 B8 C8 '—_____ —__D8 六、申請專利U" " ' '~ 1.—種半挲體裝置，其特徵在於：具備 外部端子； 内部電路，其與該外部端子連接；及 靜電破壞保護電路，其具有電阻部，其係設於該内部 電路與前述外部端子之間，其係被控制成在通常動作時 電阻値下降，而在非動作時電阻値上升。 2‘如申請專利範圍第1項之半導體裝置，其中前述靜電破 壞保護電路更具有保護元件，其係由設於電源與前述外 部端子之間之P通道M0S電晶體或設於接地與前述外部 端子之間之n通道MOS電晶體之至少任一者所成者。 3. 如申請專利範圍第^項之半導體裝置，其中前述電阻部 係由：第1電阻、與該第1電阻並聯之第2電阻、及與該 第2電阻串聯之開關所成者。 4. 如申請專利範圍第3項之半導體裝置，其中前述第^電 阻及前述開關係由：各與前述第1電阻並聯之複數之電 阻、及與各電阻事聯之開關所成者。 經濟部智慧財產局員工消費合作社印製 .. ft-------袈------訂 (請先閲讀背面之注意事項再填寫本頁) 5. 如申請專利範圍第i項之半導體裝置，其中前述電阻部 係由下述元件並聯而成·第1電阻、串聯於該第i電阻之 第1開關、第2電阻、及串聯於該第2電p且之第2開關。 6_如申請專利範園第1項之半導體装置，其中前述電p且部 係由可變電阻構成。 7.如申請專利範圍第1項之半導體裝置，其中前述電p且部 至少係由：串聯之第1電阻與第2電阻、及爲了使前述第 1、第2電阻之任一者短路而設置之開闞所構成。 -13- 本紙張尺度適用中困國家樣率（CNS ) A4規格（21〇X297公釐）^ 41 084 A8 B8 C8 '—_____ —__ D8 VI. Patent application U " "' ~~ 1. A half-body device characterized by having external terminals; an internal circuit connected to the external terminals; and The electrostatic destruction protection circuit has a resistance portion provided between the internal circuit and the external terminal, and is controlled such that the resistance 値 decreases during normal operation and the resistance 値 increases during non-operation. 2 'The semiconductor device according to item 1 of the scope of patent application, wherein the aforementioned electrostatic destruction protection circuit further has a protection element, which is composed of a P channel M0S transistor provided between the power source and the external terminal or provided between the ground and the external terminal Between at least any one of the n-channel MOS transistors. 3. The semiconductor device according to item ^ of the scope of patent application, wherein the aforementioned resistance portion is formed by a first resistor, a second resistor connected in parallel with the first resistor, and a switch connected in series with the second resistor. 4. For the semiconductor device according to item 3 of the scope of patent application, the aforementioned resistor ^ and the aforementioned open relationship are formed by a plurality of resistors each connected in parallel with the aforementioned first resistor, and a switch associated with each resistor. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs: ft ------- 袈 ------ Order (please read the precautions on the back before filling this page) 5. If you apply for a patent scope item i In the semiconductor device, the resistance portion is formed by connecting the following elements in parallel: a first resistor, a first switch connected in series with the i-th resistor, a second resistor, and a second switch connected in series with the second electric p. 6_ The semiconductor device according to item 1 of the patent application park, wherein the aforementioned electric p and the part are composed of a variable resistor. 7. The semiconductor device according to item 1 of the scope of the patent application, wherein the electrical resistor is provided at least by: a first resistor connected in series with a second resistor, and provided to short-circuit any of the first resistor and the second resistor. It consists of the openings. -13- This paper size applies to the sample rate of CNS A4 (21 × 297 mm)
TW089104256A 1999-03-12 2000-03-09 Semiconductor apparatus TW441084B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11066301A JP2000260948A (en) 1999-03-12 1999-03-12 Semiconductor device

Publications (1)

Publication Number Publication Date
TW441084B true TW441084B (en) 2001-06-16

Family

ID=13311863

Family Applications (1)

Application Number Title Priority Date Filing Date
TW089104256A TW441084B (en) 1999-03-12 2000-03-09 Semiconductor apparatus

Country Status (3)

Country Link
JP (1) JP2000260948A (en)
KR (1) KR20000076814A (en)
TW (1) TW441084B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108933574A (en) * 2017-05-23 2018-12-04 株式会社村田制作所 Power amplification circuit

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004260139A (en) * 2003-02-06 2004-09-16 Sanyo Electric Co Ltd Semiconductor device
JP2009182123A (en) 2008-01-30 2009-08-13 Toshiba Corp Semiconductor device
JP5187150B2 (en) * 2008-11-13 2013-04-24 セイコーエプソン株式会社 Integrated circuit device, electro-optical device and electronic apparatus
JP5288479B2 (en) 2009-04-27 2013-09-11 ルネサスエレクトロニクス株式会社 Display panel driver
JP2012129570A (en) * 2012-04-03 2012-07-05 Megica Corp Method of manufacturing chip
JP5752657B2 (en) * 2012-09-10 2015-07-22 株式会社東芝 Semiconductor device
KR102140734B1 (en) 2014-05-14 2020-08-04 삼성전자주식회사 Semiconductor device including electrostatic discharge circuit and operation method thereof
JP2021027056A (en) * 2019-07-31 2021-02-22 ラピスセミコンダクタ株式会社 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108933574A (en) * 2017-05-23 2018-12-04 株式会社村田制作所 Power amplification circuit
CN108933574B (en) * 2017-05-23 2023-10-24 株式会社村田制作所 Power amplifying circuit

Also Published As

Publication number Publication date
KR20000076814A (en) 2000-12-26
JP2000260948A (en) 2000-09-22

Similar Documents

Publication Publication Date Title
US5617283A (en) Self-referencing modulation circuit for CMOS integrated circuit electrostatic discharge protection clamps
TWI440273B (en) Cascoded input-output device for protection and method applied thereon
US5726589A (en) Off-chip driver circuit with reduced hot-electron degradation
US10535647B2 (en) Electrostatic discharge (ESD) protection circuit
JP3808026B2 (en) Semiconductor device
TW441084B (en) Semiconductor apparatus
US7430100B2 (en) Buffer circuit with enhanced overvoltage protection
US9541583B2 (en) Voltage detector with high voltage protection
JP4723505B2 (en) Active protection circuit device
US6188243B1 (en) Input/output circuit with high input/output voltage tolerance
TW321803B (en)
JP2010183168A (en) Integrated circuit device and electronic apparatus
JP2918821B2 (en) Off-chip driver circuit
CN112910448A (en) Overvoltage protection circuit for PMOS-based switches
US20060018064A1 (en) High voltage tolerant I/O circuit
US20100149704A1 (en) Esd protection circuit
TW201021411A (en) Pad circuit for the programming and I/O operations
EP2430657A1 (en) Integrated circuit and integrated circuit package
JP5257526B2 (en) Reset circuit and system
JP3808090B2 (en) Semiconductor device
US6150844A (en) High voltage tolerance output stage
JPH118928A (en) Short-circuit preventing circuit
US11728642B2 (en) Semiconductor device and protection circuit
TWI718846B (en) High-voltage and low-voltage signaling output driver
TWI391030B (en) Method for enhancing esd protection in an integrated circuit and related device and integrated circuit

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees