4 4 Ί 〇 d 8 5826twf.doc/008 A? _ B7 五、發明説明（p 本發明是有關於一種電子元件的封裝方法及其結構， 且特別是有關於一種積體電路晶片（Integrated Circuit Chip；) 的封裝方法及其結構，將封膠步驟（Molding)後、位於流道 (Mold Runner)之封裝材料移除時，不會損害封裝件 (Package)。 在半導體產業中’積體電路之封裝係用以提供晶片 (Die)與印刷電路板(Printed Circuit Board, PCB)或其他適當 元件之間電性連接的媒介、並用以保護晶片，是製作積體 電路成品的最後步驟。一般積體電路係包覆於封裝件之 中’然後再將封裝件焊接至印刷電路板或其他基板上。 在封裝過程中，常使用兩件式模具(Two-Piece M(>iding Equipment)以及封裝材料’對諸如積體電路晶片等電子元 件進行封膠步驟。一般是將載有晶片之基板置入模具的模 穴（Cavity)中’再由模具中的流道將封裝材料導入模穴以 包覆晶片，待封裝材料固化後》再將封裝件脫模。然而， 此時封裝件仍和位於流道且固化之封裝材料連接，必須將 此多餘的部份移除，進行所謂的去除步驟(Degate)，以完 成封裝件之製作。 經濟部智慧財產局員工消費合作社印製 ---------装------訂 (請先閲讀背面之注意事項再填寫本頁) 然而，由於位在流道的封裝材料與基板之間接合力的 緣故’在折斷多餘的封裝材料、進行去除步驟時會扭曲基 板，導致基板表面的防焊罩(Solder Mask)破損、導電跡線 (Trace)斷裂，封裝材料、防焊罩、導電跡線、晶片與基板 之間脫層(Delamination)產生縫隙。而水氣將由上述縫隙侵 入封裝件內’導致在後續步驟中因加熱而使水氣迅速膨 3 本紙張尺度逋用中國國家揉準（CNS ) 格（2Ϊ0Χ297公釐> ---- A7 A7 經濟部智慧財產局員工消費合作社印製 5826twf.doc/0084 4 〇 〇d 8 5826twf.doc / 008 A? _ B7 V. Description of the invention (p The present invention relates to a packaging method and structure of an electronic component, and in particular to an integrated circuit chip ;) Packaging method and structure, after removing the sealing step (Molding), the packaging material located in the runner (Mold Runner) will not damage the package (Package). In the semiconductor industry, 'Integrated Circuits' Packaging is used to provide a medium for the electrical connection between a die and a printed circuit board (PCB) or other appropriate components, and to protect the chip. It is the final step in the production of integrated circuit products. The circuit is enclosed in a package and then the package is soldered to a printed circuit board or other substrate. In the packaging process, two-Piece M (> iding equipment) and packaging materials are often used 'The sealing step of electronic components such as integrated circuit wafers. Generally, the substrate carrying the wafer is placed in the cavity of the mold (Cavity)' Then the packaging material is introduced into the cavity through the flow channel in the mold. Wrap the wafer and wait for the curing of the packaging material to release the package. However, at this time, the package is still connected to the cured packaging material located in the flow channel. This excess must be removed and a so-called removal step is performed. (Degate) to complete the production of the package. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs --------- Installation ----- Order (Please read the precautions on the back before filling this page ) However, due to the bonding force between the packaging material located on the flow path and the substrate, the substrate will be distorted when the excess packaging material is broken and the removal step is performed, resulting in damage to the solder mask on the surface of the substrate and conductive traces. (Trace) fracture, packaging materials, solder masks, conductive traces, delamination between the wafer and the substrate to create a gap. And the moisture will invade the package through the above gaps, resulting in water in the subsequent steps due to heating Fast inflation 3 This paper size is in Chinese National Standard (CNS) format (2Ϊ0 × 297mm > ---- A7 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5826twf.doc / 008
D I |_ 五、發明説明（v) 脹，產生爆米花效應（Popcorn Effect)，使得封裝件毁損。 請參照第1圖，其所繪示的是一種習知封裝基板的俯 視圖，此爲Amkor與Anam兩家公司於1994年提出之美 國專利第5,635,671號，其係於基板100上流道104所在 位置形成材質爲金或鈀（Palladium，Pd)的去除區（Degating Region)102，而且此一去除區102的寬度大於流道1〇4的 寬度。由於封裝材料對金質去除區1〇2的接合力小於其對 基板100之接合力，因此在折斷流道位置之多餘封裝材料 時，不會破壞封裝件之結構。但是金質去除區102會佔用 基板100上可供佈線的面積，而且製作金質去除區102 , 會增加封裝件的生產成本。 其次，請參照第2圖，其所繪示的是一種習知移除多 餘封裝材料之方法的示意圖，此爲Motorola公司在i99l 年提出之美國專利第5,542,171號，其方法是對基板2〇〇 進行濺鍍蝕刻（Sputter Etching)，以增加後續步驟中封裝材 料與基板間的接合力。然後，在基板200上對應於流道21〇 通往待封裝之半導體晶片202的閘道(Gate)204位置塗％ 油性墨水或聚合物206，以降低此區域中封裝材料208跑 基板2〇〇的接合力，因此在折斷流道位置之多餘封裝材料 208a時，不會損及封裝件。然而，此種方法在以油性璺水 或聚合物塗污特定區域之製程複雜且困難，不僅增加了_ 造成本，而且此種塗污作業常會有損及產品品質之顧慮。 因此本發明提供一種電子元件的封裝方法及其結構， 於封裝基板上之特定區域形成疏水性含氟材料層，不影_ 4 本紙張尺度逋用中國國家標牟（CNS ) A4規格（210X297公釐） ----^ . - - . ^^^1 - — ~ - _ I^11 I I m n ίeJ f靖先閱讀背面之注意事项再填寫本耳j A7 B7D I | _ 5. Description of the invention (v) Expansion, resulting in a popcorn effect, causing damage to the package. Please refer to FIG. 1, which shows a top view of a conventional package substrate. This is US Patent No. 5,635,671 filed by Amkor and Anam in 1994. It is formed at the position of the flow channel 104 on the substrate 100. The material is a gold or palladium (Palladium, Pd) removal region (Degating Region) 102, and the width of this removal region 102 is greater than the width of the runner 104. Since the bonding force of the packaging material to the gold removal region 102 is smaller than its bonding force to the substrate 100, the structure of the package will not be damaged when the excess packaging material at the flow path location is broken. However, the gold-removed area 102 occupies an area available for wiring on the substrate 100, and manufacturing the gold-removed area 102 will increase the production cost of the package. Secondly, please refer to FIG. 2, which shows a schematic diagram of a conventional method for removing excess packaging materials. This is a US Pat. No. 5,542,171 filed by Motorola in i99l. Sputter Etching is performed to increase the bonding force between the packaging material and the substrate in the subsequent steps. Then, apply% oil-based ink or polymer 206 on the substrate 200 at the position of the gate 204 corresponding to the flow channel 21 to the semiconductor wafer 202 to be packaged, so as to reduce the encapsulation material 208 running on the substrate 200 in this area. Therefore, when the excess packaging material 208a at the flow path position is broken, the package will not be damaged. However, this method has a complicated and difficult process of staining certain areas with oily water or polymer, which not only increases the cost, but also often causes concerns about the quality of the product. Therefore, the present invention provides a method for packaging electronic components and a structure thereof. A hydrophobic fluorine-containing material layer is formed in a specific area on a packaging substrate, without affecting the _ 4 paper size used in China National Standards (CNS) A4 specification (210X297) ^) ---- ^.--. ^^^ 1-— ~-_ I ^ 11 II mn eJ f Jing first read the precautions on the back before filling in this ear j A7 B7
^ S 5 S26twf.doc/0〇8 五、發明説明（》） 基板上可供佈線的面積’並可降低位於流道之封裝材料對 基板之接合力，在進行去除步驟時不會損害封裝件。其中， 疏水性含氟材料層和封裝基板的接合力大於其與封裝材料 間的接合力，而且可以保護封裝件，防止水氣滲入封裝件 內產生爆米花效應。 根據本發明之上述及其他目的，提出一種電子元件的 封裝方法，首先提供封裝所需之基板，其具有承載面與鑲 嵌面，而承載面又分爲元件配置區與元件周緣區。再於基 板的兀件周緣區上形成疏水性含氟材料層。接著，將電子 兀件固疋於基板上的元件配置區內，並使電子元件與基板 電性連接。其次，以封裝材料將電子元件密封包覆，再將 位於疏水性含氟材料層上的多餘封裝材料移除。 此外’根據本發明之上述及其他目的，又提出一種電 子元件封裝件，其中包括具有承載面的基板、疏水性含氣 材料層、電子元件及封裝材料。在基板的承載面上具有元 件配置區與元件周緣區，疏水性含氟材料層則是覆蓋於元 件周緣區上。而電子元件固定於元件配置區內，且與基板 電性連接。封裝材料配置於元件配置區上’將電子元件密 封包覆，且疏水性含氟材料層與封裝材料的接合力小於封 裝材料與基板及/或電子元件的接合力。 、 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉較佳實施例，並配合所式’ 說明如下： @ 圖式之簡單說明： 本紙張尺度適用中國國家標準（c叫入4胁（21〇χ297公着） I 1:1 - - - - - I I. 1 11 I - - - X J*s f靖先閲讀背面之iit事項4填寫本頁j 濟 部 智 慧 財 產 局 貝 工 消 費 合 作 社 印 製 經濟部智慧財產局員工消費合作社印製 441048 A7 5826twf.doc/008 五 '發明説明) 第1圖所繪示爲一種習知封裝基板的俯視圖； 第2圖所繪示爲另一種習知移除多餘封裝材料之方法 的示意圖； 第3圖所繪示爲依照本發明之較佳實施例，一種電子 元件的封裝方法之流程圖； 第4A圖至第4E圖所繪示爲依照本發明之較佳實施 例，一種電子元件的封裝製程示意圖；以及 第5圖所繪示爲依照本發明之較佳實施例，一種電子 元件的封裝方法，形成疏水性含氟材料層之示意圖。 圖式之標記說明： 100、200、400 :基板 102 :金質去除區 104、210 :流道 202 :半導體晶片 204 :閘道 206 :油性墨水或聚合物 208、208a、416 :封裝材料 300〜308 :電子元件之封裝步驟 402 :承載面 404 :鑲嵌面 406 :元件配置區 408 :元件周緣區 410 :疏水性含氟材料層 412 :電子元件 6 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） 4 41 04 8 5 826twf. doc/008 ^ ________B7 五、發明説明（ζ) 414 :導線 418 :封裝件 500 :反應室 502 :管線 504 :罩幕層 實施例 請參照第3圖，其所繪示的是依照本發明之較佳實施 例，一種電子元件的封裝方法之流程圖。第4A圖至第4E 圖，其所繪示的是依照本發明之較佳實施例，一種電子元 件的封裝方法，其製作流程的示意圖。而第3圖中之步驟 300〜308分別與第4A圖至第4E圖相對應。 如第3圖中之步驟300所示’並請參照第4A圖，首 先提供進行封裝所需的基板400。在封裝基板400上具有 用以承載元件之承載面402與鑲嵌面（Mounting Surface)404，其中承載面402例如是承載半導體晶片的晶 片貼附面（Die Attach Surface)。 第4A圖中包括封裝基板400部份區域之俯視圖及剖 面示意圖，其中承載面402上具有與其他元件電性連接所 需的導電跡線(Trace)(未顯示於圖中）。此外，在承載面402 上又可劃分爲元件配置區406,以及位於元件配置區406 周圍的元件周緣區408，而鑲嵌面404則具有與其他元件 或基板電性連接所需之焊墊（Solder Pad)(未顯示於圖中）。 其次，請同時參照第3圖中之步驟3〇2與第4B圖’ 在基板400之承載面402的元件周緣區4〇8上形成表面具 7 (請先聞讀背面之注意事項再填寫本頁) 裝-^ S 5 S26twf.doc / 0〇8 5. Description of the invention (") The area available for wiring on the substrate 'and can reduce the bonding force of the packaging material located on the flow path to the substrate, and will not damage the package during the removal step . Among them, the bonding force between the hydrophobic fluorine-containing material layer and the packaging substrate is greater than the bonding force between the hydrophobic fluorinated material layer and the packaging material, and it can protect the package and prevent water vapor from penetrating into the package to produce a popcorn effect. According to the above and other objects of the present invention, a method for packaging electronic components is provided. First, a substrate required for packaging is provided, which has a bearing surface and an embedded surface, and the bearing surface is further divided into a component configuration area and a component peripheral area. A hydrophobic fluorine-containing material layer is formed on the peripheral edge region of the element of the substrate. Next, the electronic components are fixed in the component arrangement area on the substrate, and the electronic components are electrically connected to the substrate. Second, the electronic components are hermetically sealed with a packaging material, and then the excess packaging material located on the hydrophobic fluorine-containing material layer is removed. In addition, according to the above and other objects of the present invention, an electronic component package is further provided, which includes a substrate having a bearing surface, a hydrophobic gas-containing material layer, an electronic component, and a packaging material. There is a component arrangement area and a component peripheral area on the bearing surface of the substrate, and a hydrophobic fluorine-containing material layer covers the component peripheral area. The electronic component is fixed in the component arrangement area and is electrically connected to the substrate. The packaging material is disposed on the component disposition area, and the electronic component is sealed and covered, and the bonding force between the hydrophobic fluorine-containing material layer and the packaging material is smaller than the bonding force between the packaging material and the substrate and / or the electronic component. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following exemplifies the preferred embodiments and the following formulas: The description is as follows: @ 图 的 的 说明 ： This paper scale applies to China Standard (c is called 4 threats (21〇χ297) I 1: 1-----I I. 1 11 I---XJ * sf Read the iit item on the back 4 Fill out this page Printed by the Bureau of Industrial Property and Consumer Cooperatives Printed by the Consumers 'Cooperative of the Intellectual Property Bureau of the Ministry of Economics and printed 441048 A7 5826twf.doc / 008 Five' Invention Description) Figure 1 shows a top view of a conventional package substrate; Figure 2 shows FIG. 3 is a schematic diagram of another conventional method for removing redundant packaging materials. FIG. 3 is a flowchart of a method for packaging electronic components according to a preferred embodiment of the present invention. FIGS. 4A to 4E FIG. 5 is a schematic diagram of an electronic component packaging process according to a preferred embodiment of the present invention; and FIG. 5 is a schematic view of an electronic component packaging method according to a preferred embodiment of the present invention to form a hydrophobic fluorine-containing material. Layer of Intentions. Description of drawing symbols: 100, 200, 400: substrate 102: gold removal area 104, 210: runner 202: semiconductor wafer 204: gate 206: oily ink or polymer 208, 208a, 416: packaging material 300 ~ 308: Packaging steps for electronic components 402: Bearing surface 404: Mosaic surface 406: Component configuration area 408: Component peripheral area 410: Hydrophobic fluorine-containing material layer 412: Electronic component 6 (Please read the precautions on the back before filling this page ) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) 4 41 04 8 5 826twf. Doc / 008 ^ ________B7 V. Description of the invention (ζ) 414: Wire 418: Package 500: Reaction chamber 502: Pipeline 504: Please refer to FIG. 3 for an embodiment of a mask layer, which shows a flowchart of a method for packaging electronic components according to a preferred embodiment of the present invention. 4A to 4E are schematic diagrams illustrating a method for packaging an electronic component and a manufacturing process thereof according to a preferred embodiment of the present invention. Steps 300 to 308 in Figure 3 correspond to Figures 4A to 4E, respectively. As shown in step 300 in FIG. 3 and referring to FIG. 4A, a substrate 400 required for packaging is first provided. The package substrate 400 has a bearing surface 402 and a mounting surface 404 for carrying components. The bearing surface 402 is, for example, a die attach surface for carrying a semiconductor wafer. FIG. 4A includes a top view and a schematic cross-sectional view of a part of the package substrate 400. The carrying surface 402 has conductive traces (not shown) necessary for electrical connection with other components. In addition, the bearing surface 402 can be divided into a component configuration area 406 and a component peripheral area 408 located around the component configuration area 406, and the damascene surface 404 has solder pads (Solder) required for electrical connection with other components or substrates. Pad) (not shown). Secondly, please refer to steps 3202 and 4B in FIG. 3 at the same time to form the surface 7 on the component peripheral region 408 of the bearing surface 402 of the substrate 400 (please read the precautions on the back before filling in this Page)
、1T 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家榡準（CNS) Α4規格（2丨〇><297公釐） 441 04 8 π — 8 _B7 五、發明説明（〔） — 有疏水性質(Hydrophobic)之含氟材料層41〇，其厚度約爲 10埃（Angstrom, A)至1000埃。形成此一疏水性含氟材料 層的方法包括化學热相沈積（Chemical Vapor Deposition CVD)，例如電漿化學氣相沈積（Plasma Enhenced chemieai Vapor Deposition, PECVD)。 請配合參照第5圖，其所繪示的是依照本發明之較佳 實施例’一種電子元件的封裝方法，形成疏水性含氟材料 層之示意圖，其中與第4A及4B圖中相同之構件係採用 相同之標號。將基板400置於反應室500中，以罩幕層 (Mask)504遮蓋基板400上的元件配置區406與鑲嵌面 404，再將電漿氣體源由管線5〇2導入反應室500中，進 行電漿化學氣相沈積，於基板4〇〇上形成疏水性含氟材料 層410 ’以覆蓋元件周緣區408及基板400之側壁部份 經濟部智慧財產局員工消費合作社印製 , .·1 I ^n, ^^^1 _- - ^^^1 n ι^ϋ t HI ^^^1 Ύ—ν Γ靖先聞讀背面之逢意事if再嗔寫本頁j 進行電漿化學氣相沈積時，其所使用的電漿氣體源包 括碳氟化合物（Carbon-Fluoro Compound)，例如過氟碳化 物（Perfluoro-Carbon Compound) ’諸如烷類化合物及/或烯 類化合物等。而形成疏水性含氟材料層410所使用之烷類 化合物包括六氟乙烷(Hexafluoro-Ethane, C2F6)等，烯類化 合物則包括四氟乙烯（Tetrafluoro-Ethylene)等。 接著，請參照第3圖中之步驟304與第4C圖，將電 子元件412固定於基板400之元件配置區406內，並在電 子元件412與基板400之間形成電性連接。其中電子元件 412包括半導體元件，例如積體電路晶片等，使電子元件 412固定於元件配置區406內，可以採用例如絕緣膠、導 8 本紙張尺度適用中國國家標準（CNS ) A4规格（21〇><297公釐） B7 441 048 5826twf.doc/008 五、發明説明（，） 電膠或貼帶等接著材料（未顯示於圖中），將電子元件412 黏貼固定於基板400表面。電子元件412與基板400之間 的電性連接’則可以採用例如打線接合（Wire Bonding, W/B) 的方式，在電子元件412的焊墊(未顯示於圖中）與基板400 上的導電跡線之間形成導線414。 第4A圖、第4B圖中之元件配置區406與第5圖中 之罩幕層5〇4略呈正方形，在本實施例中係以此種構型進 行說明’然而元件配置區406與罩幕層504可以是其他不 同的形狀’故前述圖中所示的元件配置區及覃幕層形狀並 非用以限制本發明之範圍。而以打線接合方式形成導線 414，電性連接電子元件412與基板4〇〇，係舉例說明本實 施例，並非用以限制本發明之範圍，故亦可採用諸如捲帶 自動接合（Tape Automated Bonding, TAB)或覆晶接合（Flip， 1T Printed by the Intellectual Property Bureau of the Ministry of Economy ’s Consumer Cooperatives. The paper size is applicable to China National Standards (CNS) A4 specifications (2 丨 〇 > < 297 mm) 441 04 8 π — 8 _B7 V. Description of the invention ([ ) — Hydrophobic fluorine-containing material layer 410, with a thickness of about 10 Angstroms (Angstrom, A) to 1000 Angstroms. The method for forming the hydrophobic fluorine-containing material layer includes Chemical Vapor Deposition CVD, such as Plasma Enhenced chemieai Vapor Deposition (PECVD). Please refer to FIG. 5, which shows a schematic diagram of a method for packaging an electronic component to form a hydrophobic fluorine-containing material layer according to a preferred embodiment of the present invention. The same components as those in FIGS. 4A and 4B are shown. The same reference numerals are used. The substrate 400 is placed in the reaction chamber 500, and the component arrangement area 406 and the mosaic surface 404 on the substrate 400 are covered with a mask layer 504, and the plasma gas source is introduced into the reaction chamber 500 through the line 502 to perform Plasma chemical vapor deposition forms a hydrophobic fluorinated material layer 410 'on the substrate 400 to cover the peripheral edge area 408 of the element and the side wall of the substrate 400. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, .1 I ^ n, ^^^ 1 _--^^^ 1 n ι ^ ϋ t HI ^^^ 1 Ύ—ν Γ Jing first read the meanings on the back if and then wrote this page j for plasma chemical vapor phase During deposition, the plasma gas source used includes carbon-fluoro compounds, such as Perfluoro-Carbon Compounds, such as alkane compounds and / or olefin compounds. The alkane compounds used to form the hydrophobic fluorine-containing material layer 410 include Hexafluoro-Ethane (C2F6), and the olefin compounds include Tetrafluoro-Ethylene. Next, referring to steps 304 and 4C in FIG. 3, the electronic component 412 is fixed in the component arrangement area 406 of the substrate 400, and an electrical connection is formed between the electronic component 412 and the substrate 400. The electronic component 412 includes a semiconductor component, such as a integrated circuit wafer, etc., so that the electronic component 412 is fixed in the component configuration area 406. For example, an insulating adhesive and a guide can be used. > < 297 mm) B7 441 048 5826twf.doc / 008 V. Description of the invention (,) Adhesive materials such as electro-adhesives or tapes (not shown in the figure), the electronic component 412 is adhered and fixed on the surface of the substrate 400. The electrical connection between the electronic component 412 and the substrate 400 can be performed by, for example, wire bonding (W / B). The bonding pads (not shown) of the electronic component 412 and the substrate 400 are electrically conductive. A lead 414 is formed between the traces. The component arrangement area 406 in FIG. 4A and FIG. 4B and the mask layer 500 in FIG. 5 are slightly square. In this embodiment, this configuration is used for description. However, the component arrangement area 406 and the cover The curtain layer 504 may have other different shapes. Therefore, the component arrangement area and the shape of the curtain layer shown in the foregoing figures are not intended to limit the scope of the present invention. The wire 414 is formed by wire bonding, and the electronic component 412 and the substrate 400 are electrically connected. This example illustrates this embodiment and is not intended to limit the scope of the present invention. Therefore, such as tape auto bonding (Tape Automated Bonding) , TAB) or flip-chip bonding (Flip
Chip FC)等方式進行電性連接。 然後，再參照第3圖中之步驟306和第4D圖，對已 完成元件貼附之基板400進行封膠，在基板4〇〇之承載面 402上形成封裝材料416，將電子元件412密封包覆。封 膠步驟之進行，例如是使用兩件式模具，將基板置於其中 的模穴內’再以轉移成型（Transfer Molding)或射出成型 (Injection_Moldlng)方式，將封裝材料由流道引入模穴以g 覆其中的元件，待封裝材料固化再進行脫模，將封裝件與 模具分離。而所使用的封裝材料416包麵固性環氧樹脂 (Thermosetting Epoxy Resin)等，疏水性含氟材料層之材 的選擇與封裝材料和基板有關’亦即必須使封裝材料與疏 本纸張尺度適用中國國家標率（CNS ) A4規格（2!0x297公嫠） ^^^1 1-1 ί—- I nn ^^^1 ^—1 ^—^1· i Hal ^^^^1 、一-6J (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消费合作社印製Chip FC). Then, referring to step 306 in FIG. 3 and FIG. 4D, the substrate 400 to which the components have been attached is sealed, a packaging material 416 is formed on the bearing surface 402 of the substrate 400, and the electronic component 412 is sealed. cover. The sealing step is performed, for example, by using a two-piece mold and placing the substrate in the cavity therein, and then using a transfer molding or injection molding method to introduce the packaging material from the flow channel into the mold cavity to g Cover the components, and release the mold after the packaging material is cured to separate the package from the mold. The sealing material used is 416, such as Thermosetting Epoxy Resin. The choice of the material of the hydrophobic fluorine-containing material layer is related to the packaging material and the substrate. That is, the packaging material must be in accordance with the paper size. Applicable to China National Standards (CNS) A4 specification (2! 0x297 male) ^^^ 1 1-1 ί—- I nn ^^^ 1 ^ —1 ^ — ^ 1 · i Hal ^^^^ 1, one -6J (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs
4 41 04 B A7 B7 5826twf.doc/〇〇8 五、發明説明（ 材料層之間的接合力小於封裝材料難&_ ^^^1· ^—^1 ^^^1 I 41¾ n 1^1 ^^^1 c請先閱讀背面之注意事項再填寫本頁) 再請參照第3圖中之步驟谓以及第祁圖 除步驟’將位於流道且固化、與封裝件418連接的 移除。由於封裝材料與疏水性含氟材料二 接口力小h封裝材料與基板的接合力，因此將位於流 多餘封裝材料使其類裝件主體分_4 41 04 B A7 B7 5826twf.doc / 〇〇8 V. Description of the invention (the joint force between the material layers is less than the encapsulation material & _ ^^^ 1 · ^ — ^ 1 ^^^ 1 I 41¾ n 1 ^ 1 ^^^ 1 c Please read the precautions on the back before filling out this page.) Please refer to the steps in Figure 3 and the removal step in Figure 3. 'The removal will be located in the runner and solidified, and connected to the package 418 . Due to the small interface force between the packaging material and the hydrophobic fluorine-containing material and the bonding force between the packaging material and the substrate, the excess packaging material will be located to separate the main body of the package.
地將多餘的封裝材料從疏水性含氟材料層分離，使封裝J 上f有多餘的封裝材料，以利後續其他自動化製程步驟之 進行。而且進行去除步驟時，不會扭曲基板與損害封裝件， 防止封裝件中的封裝材料因去除步驟而與電子元件或基板 間產生裂縫。難在元件周緣區賊疏水性含氣材料層， 在完成封裝件後，可抑制水氣滲入封裝件內，避免產生爆 米花效應。 由上述本發明較佳實施例可知，應用本發明具有下列 優點： 經濟部智慧財產局員工消費合作社印製 一 1，本發明之電子元件的封裝方法及其結構，係在基板 的兀件周緣區上形成含氟材料層，可以降低元件周緣區中 的多餘封裝材料對基板的接合力。而且封膠時的流道位置 係在元件周緣區之中’因此在移除位於流道且固化之多餘 封裝材料時’將多餘封裝材料折斷’使其與封裝件主體分 離，並不會對封裝件主體造成損害，可提高封裝件的良率， 延長其使用壽命。 2_再者’本發明之電子元件的封裝方法及其結構，係 10 本紙張尺度適用中國國家標準（CNS } μ規格（210X297公餐） A7 B7 ；:Ο 4 ： 5826twf.doc/008 五、發明説明（ 在基板的兀棒周緣區上形成表面具有疏水性質之含氣材 層:當電子元件完成封裝後，藉由此疏水性含氟材料層的 fe離，可以抑制水氣滲入封裝件內，提高封裝件抗爆米花 效應的能力，防止其產生爆米花效應，延長封裝件的 壽命。 3·由於疏水性含氟材料層是覆於基板表面上，不會佔 用基板上可供佈線的區域，因此可適用於具有高佈線密度 之封裝基板，而且不會限制基板的可佈線性。 4.此外，本發明之電子元件的封裝方法，可以使用目 則被廣泛運用於封裝製程的兩件式模具，不需重新設計及 Sc作模具’或使用複雜的三件式模具(Three-Piece Mold)、 改良型兩件式模具（Modified Two-Piece Mold)，可以降低 生產成本。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。Separate the excess packaging material from the hydrophobic fluorine-containing material layer, so that there is excess packaging material on the package J, so as to facilitate subsequent automatic processing steps. Moreover, the removal step does not distort the substrate and damage the package, and prevents cracks between the packaging material in the package and the electronic component or the substrate due to the removal step. It is difficult to thief the hydrophobic gas-containing material layer in the peripheral region of the component. After the package is completed, it can inhibit water vapor from penetrating into the package and avoid the popcorn effect. It can be known from the above-mentioned preferred embodiments of the present invention that the application of the present invention has the following advantages: 1. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. The packaging method and structure of the electronic components of the present invention are in the peripheral area of the substrate. Forming a fluorine-containing material layer thereon can reduce the bonding force of the excess packaging material to the substrate in the peripheral region of the element. Moreover, the position of the flow channel during sealing is in the peripheral area of the component. Therefore, when the excess packaging material located in the flow channel is cured, it will 'break off the excess packaging material' and separate it from the package body, which will not affect the package. Damage to the body of the component can increase the yield of the package and extend its service life. 2_Furthermore, the packaging method and structure of the electronic component of the present invention are 10 paper sizes applicable to Chinese national standards (CNS) μ specifications (210X297 meals) A7 B7 ;: 〇4: 5826twf.doc / 008 V. [Explanation of the invention] (A gas-containing material layer having a hydrophobic property is formed on the peripheral edge region of the substrate of the substrate: after the electronic component is packaged, by the separation of the hydrophobic fluorine-containing material layer, moisture can be prevented from penetrating into the package. To improve the ability of the package to resist the popcorn effect, prevent it from producing a popcorn effect, and extend the life of the package. 3. Since the hydrophobic fluorine-containing material layer covers the surface of the substrate, it will not occupy the area available for wiring on the substrate Therefore, it can be applied to packaging substrates with high wiring density, and does not limit the wiring of the substrate. 4. In addition, the packaging method for electronic components of the present invention can be used in a two-piece package that is widely used in packaging processes. Mold, no need to redesign and Sc for mold 'or use of complicated Three-Piece Mold, Modified Two-Piece Mold, can reduce production Cost. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be determined by the scope of the attached patent application.
- n n - n In -- I. n - - la m —— T 3 、T i請先聞讀背面之注意事項再填寫本頁J 經濟部智慧財產局員工消費合作社印製 本紙張尺度逋用十國國家榡率（CNS) M规格（210X297公釐）-nn-n In-I. n--la m —— T 3, T i Please read the notes on the back before filling out this page. National Standard Rate (CNS) M Specifications (210X297 mm)