4 40993 A7 B7 五、發明說明（） 發明領域： (請先閱讀背面之注意事項再填寫本頁) 本發明係有關於一種多層電路梅之 及其，特別是有關於在属^篆層^^^^^以氧狀丨及接 層（ground plane)之間內建電容器之設計。 潑明背景= 近年來，不只是積體電路（1C)包括主動元件如電晶 體或者被動元件如電容、電阻等都要求輕、薄、短、小 以降低成本，用以惠之印刷電路板（printed, circuit b〇ard;PCB)也同時朝向H板計，以因應 曰益增加之電子元件的數量，此外，一般而言，最基本 的系由一層的観和一層的構成’而 多層板（mu It i pie iayer)則是上述之導電層和絕緣層，依 成。最上層的板子主要設計以 备，其它之邁i元件（包括霭遞、戴溶及連為』^·)、边 及他，而以下之各層已I.窗LgU泉之^線 層則吊-接最上層承戴之一Ιϋί'·.、片及慕件，氯藏 層導線屢l篇層再以Hi (或稱)紘私鼻遽。 經濟部智慧財產局員Η消費合作社印製 如圖一所示，爲減少訊號傳輸時彼此干擾。通常， 多層板之各導體圖案層設計也會將有關Ci^E®(signal plane layer)· φ 和電壓層（pow '*νφ·Κ：·*Τ - · 1 層（g c ο Li η d ΡI a ri知切，分開，邋4驢^或稱之 間則係iT介電，晨4Τ_· ί|Γί©例如玻璃纖維，FR4、環 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）4 40993 A7 B7 V. Description of the invention () Field of invention: (Please read the precautions on the back before filling out this page) The present invention relates to a multi-layer circuit plum, and in particular to the subordinate layer ^^ ^^^ The design of the built-in capacitor between the oxygen shape and the ground plane. Bright background = In recent years, not only integrated circuits (1C) including active components such as transistors or passive components such as capacitors and resistors have been required to be light, thin, short and small to reduce costs in order to benefit printed circuit boards ( printed, circuit b〇ard; PCB) are also facing the H board at the same time, in order to respond to the increase in the number of electronic components, in addition, in general, the most basic is composed of a layer of 一层 and a layer 'and a multilayer board ( mu It i pie iayer) is the above-mentioned conductive layer and insulating layer. The top layer of the board is mainly designed for preparation, other Mi i components (including 霭 delivery, Dai Rong and Lianwei "^,), side and other, and the following layers have been I. window LgU spring ^ line layer is hanging- Connect one of the top layers to wear Ιϋί '.. piece, and pieces. The chlorine reservoir wire is repeatedly layered, and then Hi (or called) private nose. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and the Consumer Cooperative, as shown in Figure 1, to reduce interference with each other during signal transmission. In general, the design of each conductor pattern layer of a multilayer board will also involve Ci ^ E® (signal plane layer) · φ and voltage layer (pow '* νφ · Κ: · * Τ-· 1 layer (gc ο Li η d PI a ri knows to cut, separate, i4 dielectric or iD dielectric between, 晨 4Τ_ ί | Γί © For example, glass fiber, FR4, the size of this paper is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm)
經濟部智慧財產局員工消費合作社印製 五、發明說明（） 氧樹脂等隔離，然而」即使如此__，多餍基板之rc操作 ' 時，包括開關等動作時，將導致電壓層20及接地層'30 之間電位差的高頻振遣（high frequency fluctuations) 或接地電壓的反彈波（ground bouncing)的問題，特別是 ' 元件速度要求愈來愈快時，問就愈嚴重。爲^少上述 問題所導致電壓不穩所產生之雜訊，傳統的做法是將最 上層之訊號層上形成一電力環（power ring)40與一接地 環（ground ring)35,並以一外加旁路電容連接，上述之 電力環及接地環分別以一導孔（via)連接至電壓層20及 接地層3 0。 上述跨接一電容器，需要增加組裝製程（assembly process)的一額外步驟，因此增加了整體製程的週期時 間（cycle time)，同時也有可靠度的問題，特別是高頻 表現極差，但以目前之1C設計而言，特別是用於電腦 之主機板而言，電壓層之電流，一般都會有超高頻帶（高 於20 0 Μ Hz)範圍操作的問題。另一種傳統方法是利用電 壓層20及接地層30之間的介電材料層25的厚度調整 電容量，這種方法於需要較大的電容時，就減少介電材 料層25的厚度，配合以介電層上金屬平行板面積，或 增加另一組電壓層20及接地層30。這種方法雖也可解 決組裝的週期時間，然而由於介電材料層25的厚度需 要特別調整，或者增加另一組電壓層及接地層（未圖 示），以增加所需要的電容量。 此外，爲了增加數位訊號的時脈速度和在更小的空 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） -1, -I ^---- —裝--------訂--------線 (諳先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員Η消費合作社印製 4 40993 A7 _ B7 _ 五、發明說明（） 間內裝入更多的功能，單一晶片封裝的元件數量也急遽增 多，也因此’装引獨 .:多’例如钍)能容納超過又0(Γ; 倜韵弓j腳，以因應大量增加之內連線數目。除此之外，更 有覆晶構裝技術（<iiP cj)jj package technique)及球腳格 狀陣列技術（ball grid array ; 等等，以因應高 高霱求 ° 而這些元 件由於速度切換極快，訊號傳輸時的問題將E ，其承載晶片的基板更迫切需要的電容器\ 然而就目Jfcp· ’由於空間有限’ ！ 插電容器相形較一般pcmi板固靡，因此有待二虞,，明 " ·_ >ApVl r- 圓··》^^*· ........- t- . 以解決題。 … 爲此’本發明將提供一<£ι^且€2¾^.，.量 以解決上藏μ。 發明目的及槪沭： 本發明之一目的係提供一種(擊路之方 法。 本發明之另一目的係用以解決傳統方法部 ηψΈκ^ΜΜ> μmmMMM：^ 本發明係一種具有之l屋.鶴構’該多 層基板結構至少包含：一具有上_訊邏層/_一箩一介置層/ 费地.，層·Χ—、第；；介電層/二電力層/—!三介電層/五谭 _號_層之組裝*-霉.路板，組裝電路板並具有複數個連接洞； 本紙張尺度適用中國國家標準（CNS>A4規格（2〗0 X 297公釐） ------^-------ί ill---1 訂----------線 . (請先閱讀背面之注意事項再填寫本頁) 440993 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（） 且第二介氧層內具有至少一個已遇^ 乂麗靈，耍 霉電塞，以形成電容< 器’電容塡充介電材料比第一介電層之介電常數明顯"': 高，約大兩個數量級，且上訊號層至少包含一接地環及 一電力環並分別有導孔連接至接地層及電力層，本發明 並提供私戚減。當然，電力層及 接地層內之第二介電層’內也可以具有塡入第二或第三 種電容塡充介電材料以形成不同電容量的電容器。本發 明並提供具內建電容之多層基板結構的方法。 圖式簡單說昍： 本發明的較佳實施例將於往後之說明文字中輔以 下列圖形做更詳細的闡述： 圖一顯示傳統方法之多層印刷電路扳以旁路電容 跨接於電力環與接地環之間之示意圖。. 圖二顯示依據本發明之方法所形成具有內建電容 多層基板板之示意圖。 圖三顯示依據本發明之方法，彤成導孔於多層基板 之各層介電層的示意圖。 圖四顯示依據本發明之方法，形成內建電容於多層 基板之電壓層及接地層之間的示意圖β 圖五顯示依據本發明之方法，最後所形成具有內建 電容多層基板之示意圖。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 、取--------訂--------—線 A7 B7 經濟部智慧財產局員工消費合作社印制^ 五、發明說明（） 發明詳細說明： 有鑑於如發明背景所述，多層基板爲電子元件開關 等動作時’導致電壓層犮接地層之間的或 翁round bouncing)的問題，特別是高速元 件所造成的問題，需要外加旁路電容連接電力環（power ring)與接地環（ground ring)，或者額外設計電壓層和電 壓層之間介電層厚度產生電容以濾除電壓不穩定所造 成雜訊的問題。但如此將需額外的步驟安裝，徒增製程 時間，同時調整之彈性也不大。特別是球腳格狀陣列 BGA或覆晶封裝基板由於空間限制要加入電容於最上 層訊號層就更形困難，本發明提供之方法將可有效解決 •上述問題 τ 爲方便起見本發明之一實施例係以四層基板，各層 之間和發明背景所述相同，以做爲說明，但這並不代表 限制本發明之範圍，凡熟悉該項技藝之人士當可運用本 發明之精神做修飾或修改，都應屬於本發明之範圍。 濾信號脈衝壓， 訊。本發明提供之多層_板結構係如圖二所示之四層板 示意圖，由'言·_!分別爲下訊號層120A (signal plane)、電壓層 1 3 0 A (p o we r p j a n e)、接地層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------!-1--rk-----I--訂---------線 ϊ (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消貲合作社印製 440993 A7 ______B7___ 五、發明說明（） 140A(ground plane)及上訊號層150A。最上層之導線 層’即上訊號層1 50A，孫用以承載丨C晶片，及其它電 子元件。或單一晶片，就BGA的承載'基板而言， 片之)透晶is藏接， 而IC晶片之接地接腳則和接地環丄。接地環i 55 和電力環1 60則由導孔162,1 64分別和接地層140A及 電壓層130A之及各層導線連接。此外，^5„杂;.態,層,^3*6 I董麗外....的..導孔以。這些額外的_躉._孔可塡 入不同i雳,常數,.之材料.二.磁费里里.量.之熏1値..〜。......电於 P c B ^ R - 4 氧.常數數僅.，爲j., A屋丄4之胤.而.已，因此若以傳統之製 造方法，即應甩麗藤跪麗黑纖,暴氣處黑美鐵遞板，就必 須將其中電鼠麗氣麗息獯4|&鳳黑麗屬^氣基^例 如0.0015英寸或更小，配合調整電壓層和接地層金屬 面積，而如果利用本發明之方法，則只需在既有之導孔 ft.,® 的電容値。並™氣各麗.，電..路之麗患3諷息越應 得“新《霉激電谷’因此可以，克服各®〶凰二，局..速，麗流.應。.換.., 慎’當然本發明之內建電容也可以除 變換介電層材料外，再利用電壓層和接地層之距離做調 整。 ？ 本發明之过„建„霍容.忠灸„層基板中之方法，描述如下_· 請參考圖三的示意圖。首先將預定組裝之多層基板疊合 並進行鑽孔以形成複數個洞105於多層基板之中，複數 個洞105係預留以做爲多層基板的連接洞，接著，將上 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） \1fjy · --------_---κ:^--------訂---------線 , (請先閒讀背面之注意事項再填寫本頁) A7 4 4 0 9 9 3 ____B7_ 五、發明說明（） 述已鑽孔之多層基板分開，以分開處理，另外再視需要 鑽一個或以上的孔108於第二介電層135中以供形成內 建電容之用。在此所稱之多層基板至少包含一第二介電' 層135* —第一介電層145及一第三介電層125，第二 介電層通常爲低介電常數之BT環氧樹脂且上下兩面各 具有第二導體層130及140以預做爲電壓層及一接地 層，而第一介電層145上則有導體層150例如銅箔以保 留做爲上訊號層，同時第三介電層125上則也有銅箔 120以保留做爲下訊號層。以一較佳的實施例而言，BT 基板約厚0.25-0.6mm,而複數個洞105之孔徑約爲 200-250μΓη。 接著，請參考圖四，將上述已鑽孔之多層基板分開 以分開處理。首先，將第二介電層1 3 5中需要形成電容 .之貫，.孔l〇S,..以_網板迦亂败.方篇 里材赳丄38，此時不需孽.形成j建...電.容之氣遲...,..,,1.05 π是/被、蓋.，.住的。電容塡充介電材料138，例如爲粉末狀的 JaTiQ二通:存趱教盒體，之後’再以^膜 蓋爲慕二介篇邏J 35之所.,.1.要.，鑑應服.區域，葬蝕JE1所有 属之部，.分_二..在氣屣,;去除夕後，亩以鍍銅.處理，以形成 兩導體層139於第二介電層135上、下導體層14 0A， 13 0A上’用以封住已塡入電容塡充介電材料138的導 孔以形成平行板電容器，以上述之BT基板，第二介電 層1 3 5而言、.若.入.、.的1:‘秦罨·:帶,ί數. -〇^4疋^5^數4^,.名,屬.容。 請參考圖五，將一第一導體1 5 0/該第一介電層145/ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐〉 (請先閱讀背面之注意事項再填寫本頁) 裝------ 訂---------線 ！ 經濟部智慧財產局員工消費合作社印製 A7 440993 B7____ 五、發明說明（） 具有接地層圖案140A及電壓層圖案130A之第二介電 層135/該第三介電層125/—第三導體層120熱壓合後 以形成多層基板雛型。隨後，再分別圖案化該第一導體· 150’第三導體層120以形成上、下訊號層圖案1 50 A 及12 0A，並至少在150A及120A的其中之一形成至少 一接地環155及一電力環160,最後再施以貫孔電鍍鍍 上導體，銅層164及16‘2,以連接電力環160與電壓層 圖案130A及接地環155與接地層圖案140A結果請參 考圖五。 本發明具有之優點： (1) 以本發明提供之多層基板內建電容方式相較 於傳統方法而言非常簡單，且可使得設計工程師 更加有彈性及效率。 (2) 本發明之內建電容可以依電容量需求調整電 容介電層材料，同時也可以容許不同導孔位置塡 入不同介電常數之材料，當然也可以同時調整電 壓層與接地層之間介電層厚度。 ' 本發明僅以較佳實施例說明如上，並非用以限定本 發明之申請範圍；凡熟習該項技藝人士，在未脫離本發 明之精神下，當可作些許改變或修飾，其專利保護範圍 均應包含在下述之申請專利範圍內。 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ------1--^----r _ ^ ----------------. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention () Oxygen resin and other isolation, but "even so __, RC operation of the multi-substrate substrate," including switching and other actions, will cause the voltage layer 20 and the connection. The problem of high frequency fluctuations or ground bouncing of the potential difference between the formations '30, especially when the component speed requirements are getting faster, the problem becomes more serious. In order to reduce the noise caused by the voltage instability caused by the above problems, the traditional method is to form a power ring 40 and a ground ring 35 on the top signal layer, and add an additional The bypass capacitor is connected. The power ring and the ground ring are connected to the voltage layer 20 and the ground layer 30 through a via, respectively. The above-mentioned connection of a capacitor requires an additional step of the assembly process, and therefore increases the cycle time of the overall process. At the same time, there is also a problem of reliability, especially the high frequency performance is very poor. In terms of 1C design, especially for motherboards used in computers, the current in the voltage layer generally has problems of operation in the ultra-high frequency band (higher than 20 MHz). Another conventional method is to adjust the capacitance by using the thickness of the dielectric material layer 25 between the voltage layer 20 and the ground layer 30. This method reduces the thickness of the dielectric material layer 25 when a larger capacitance is required, and cooperates with The area of the metal parallel plate on the dielectric layer, or another set of voltage layer 20 and ground layer 30 may be added. Although this method can also solve the cycle time of the assembly, the thickness of the dielectric material layer 25 needs to be specially adjusted, or another set of voltage layers and ground layers (not shown) are added to increase the required capacitance. In addition, in order to increase the clock speed of digital signals and apply the Chinese national standard (CNS > A4 specification (210 X 297 mm)) at a smaller paper size, -1, -I ^ ---- --install --- ----- Order -------- line (谙 Read the notes on the back before filling in this page) Member of the Intellectual Property Bureau of the Ministry of Economic AffairsΗPrinted by Consumer Cooperatives 4 40993 A7 _ B7 _ V. Description of Invention () There are more functions installed in the room, and the number of components on a single chip package has also increased sharply. Therefore, 'installation alone .: more', such as 钍) can accommodate more than 0 (Γ; In addition, the number of interconnects. In addition, there are flip chip packaging technology (& iiP cj) jj package technique) and ball grid array technology (ball grid array; etc.) Since these components switch extremely fast, the problem of signal transmission will be E, and the substrate on which the wafer is carried is more urgently needed. \ However, Jfcp · "due to limited space"! Plug capacitors are more stable than ordinary pcmi boards, so To be waited for two years, Ming " · _ > ApVl r- circle ·· ^^ * · ........- t-. The problem ... To this end, the present invention will provide an amount of < £ ι ^ and € 2¾ ^., ... to solve the above-mentioned μ. Purpose of the invention and 槪 沭: One of the objectives of the present invention is to provide a method of hitting the road Another object of the present invention is to solve the traditional method ηψΈκ ^ MM > μmmMMM: ^ The present invention is a kind of housing. Crane structure 'The multi-layer substrate structure includes at least:箩 One interlayer / fee., Layer · X—, first; Dielectric layer / Second power layer / —! Three dielectric layer / Wutan _ No. _Assembly of assembly * -Mold. Road board, assembled circuit board And has a plurality of connection holes; this paper size applies to Chinese national standards (CNS > A4 specification (2〗 0 X 297 mm) ------ ^ ------- ill --- 1 order- --------- line. (Please read the notes on the back before filling this page) 440993 Α7 Β7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention () and within the second oxygen layer Have at least one 遇 Li Ling, a fungus plug to form a capacitor < capacitor " the dielectric material of the charge is significantly higher than the dielectric constant of the first dielectric layer " ': high, about two larger Order, and the upper signal layer includes at least a ground ring and a power ring and has vias connected to the ground layer and the power layer, respectively. The present invention provides a private reduction. Of course, the second dielectric in the power layer and the ground layer Layers may also have capacitors filled with a second or third type of capacitor / dielectric material to form different capacitances. The invention also provides a method for a multilayer substrate structure with a built-in capacitor. The diagram is briefly explained: The preferred embodiment of the present invention will be explained in more detail in the following explanatory text with the following figures: Figure 1 shows the traditional method of a multilayer printed circuit with a bypass capacitor across the power loop And ground ring. Figure 2 shows a schematic diagram of a multilayer substrate with built-in capacitors formed according to the method of the present invention. FIG. 3 is a schematic diagram showing the formation of vias in the dielectric layers of the multilayer substrate according to the method of the present invention. Fig. 4 shows a method for forming a built-in capacitor between a voltage layer and a ground layer of a multilayer substrate according to the method of the present invention. Fig. 5 shows a method for forming a multi-layer substrate with a built-in capacitor at the end according to the method of the present invention. This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling this page), take -------- Order ------- --- Line A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ V. Description of the invention () Detailed description of the invention: In view of the background of the invention, when the multi-layer substrate is an electronic component switch, etc., it will cause a voltage layer and a ground layer (Or round bouncing) problems, especially problems caused by high-speed components, need to add a bypass capacitor to connect the power ring and the ground ring, or an additional design between the voltage layer and the voltage layer The thickness of the dielectric layer generates capacitance to filter out noise caused by voltage instability. But this will require additional steps to install, increase the process time, and the flexibility of adjustment is not great. Especially for ball-foot grid array BGA or flip-chip package substrates, it is more difficult to add capacitors to the uppermost signal layer due to space constraints. The method provided by the present invention can effectively solve the problem described above. For example, a four-layer substrate is used. The description of each layer is the same as that described in the background of the invention, but it does not mean to limit the scope of the present invention. Those who are familiar with the technology can use the spirit of the present invention to make modifications or Modifications should fall within the scope of the invention. Filter signal pulse pressure. The multi-layer board structure provided by the present invention is a schematic diagram of a four-layer board as shown in Fig. 2. The words "__!" Are the lower signal layer 120A (signal plane), the voltage layer 130 A (po we rpjane), and The paper size of the stratum applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------!-1--rk ----- I--order ------- --Lines (Please read the notes on the back before filling this page) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 440993 A7 ______B7___ 5. Description of the invention () 140A (ground plane) and the upper signal layer 150A. The uppermost wire layer is the upper signal layer 150A, which is used to carry the C chip and other electronic components. Or a single chip, as far as the BGA carrier substrate is concerned, the chip is hidden through the crystal, and the ground pin of the IC chip is connected to the ground ring. The ground ring i 55 and the power ring 160 are connected to the ground layer 140A and the voltage layer 130A and the wires through the via holes 162 and 164, respectively. In addition, ^ 5 „Miscellaneous; state, layer, ^ 3 * 6 I Dong Li outside .... of the pilot hole. These additional _ 趸 ._ holes can be inserted into different i, constants, ... Material. Two. Magnetic Ferry. Quantity. Smoked 1 値 .. ~ ............ Electric P c B ^ R-4 Oxygen. Constant number is only. It is j., A House 4而 .And so, if you use the traditional manufacturing method, you should throw the black rattan black fiber of Li Teng Li, the black American iron delivery board in the violent place, you must put the electric mouse Li Li Li Xi 獯 4 | & Feng Hei For example, if it is 0.0015 inch or less, the metal area of the voltage layer and the ground layer can be adjusted in coordination with the metal layer. If the method of the present invention is used, only the capacitance of the existing via ft., ® is required. Qigeli., Electricity .. Lu Zhili suffering 3 deserves the sorrow "The new" Mold stimulates the valley of electricity "so you can overcome each 〶 〶 Phoenix II, Bureau .. Speed, Liliu. Should. ..., Caution. Of course, the built-in capacitor of the present invention can also adjust the distance between the voltage layer and the ground layer in addition to changing the dielectric layer material. ? The method of constructing a layer substrate in the present invention is described as follows. Please refer to the schematic diagram of FIG. 3. First, stack a plurality of substrates to be assembled and drill holes to form a plurality of holes 105 in multiple layers. In the substrate, a plurality of holes 105 are reserved as connection holes for the multilayer substrate. Then, the above paper size is applied to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) \ 1fjy · ---- ----_--- κ: ^ -------- Order --------- line, (please read the precautions on the back before filling this page) A7 4 4 0 9 9 3 ____B7_ 5. Description of the invention () The drilled multilayer substrate is separated for separate processing, and one or more holes 108 are drilled in the second dielectric layer 135 as needed to form a built-in capacitor. The multilayer substrate referred to herein includes at least a second dielectric layer 135 * —a first dielectric layer 145 and a third dielectric layer 125. The second dielectric layer is usually a BT epoxy resin with a low dielectric constant. Moreover, the upper and lower sides each have second conductor layers 130 and 140 to be used as a voltage layer and a ground layer in advance, and a conductor layer 150 such as copper foil on the first dielectric layer 145 to retain As the upper signal layer, there is also a copper foil 120 on the third dielectric layer 125 to be reserved as the lower signal layer. In a preferred embodiment, the BT substrate is about 0.25-0.6 mm thick, and a plurality of holes 105 The hole diameter is about 200-250μΓη. Then, please refer to Figure 4 to separate the above-mentioned drilled multilayer substrate for separate processing. First, a capacitor needs to be formed in the second dielectric layer 1 3 5. 〇S, .. with _ net board Jia chaotic defeat. Fang Li 赳 丄 38, at this time does not need evil. Form j Jian ... electricity. Rong Zhiqi is late ..., .. ,, 1.05 π is / Quilt, cover., .. Capacitor / chargeable dielectric material 138, such as powdered JaTiQ two-pass: storage box, and then use ^ film cover as Mu Erjie chapter logic J 35 .,. 1. To., Serving. Area, to bury all the affiliated parts of JE1, _2 .. In the air, after removing the acres, the acres are treated with copper plating to form two conductor layers. 139 On the second dielectric layer 135, the upper and lower conductor layers 14 0A and 13 0A are used to seal the via holes that have been inserted into the capacitor and the charging dielectric material 138 to form a parallel plate capacitor. In terms of dielectric layer 1 3 5 ·: Belt, digits. -〇 ^ 4 疋 ^ 5 ^ number 4 ^ ,. name, genus. Capacity. Please refer to Figure 5, a first conductor 1 5 0 / the first dielectric layer 145 / this paper Standards are applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page) Installation -------- Order --------- line! Economy Printed by the Consumer Cooperatives of the Ministry of Intellectual Property Bureau A7 440993 B7____ 5. Description of the Invention () The second dielectric layer 135 / the third dielectric layer 125 / the third conductor layer 120 with the ground layer pattern 140A and the voltage layer pattern 130A After thermocompression, a multilayer substrate prototype is formed. Subsequently, the first conductor 150 'and the third conductor layer 120 are respectively patterned to form upper and lower signal layer patterns 1 50 A and 12 0A, and at least one ground ring 155 and at least one of 150A and 120A are formed. A power ring 160 is finally plated with a through-hole electroplating conductor, copper layers 164 and 16'2 to connect the power ring 160 and the voltage layer pattern 130A and the ground ring 155 and the ground layer pattern 140A. Please refer to FIG. 5 for the results. The invention has the following advantages: (1) Compared with the traditional method, the built-in capacitor method of the multilayer substrate provided by the invention is very simple, and can make the design engineer more flexible and efficient. (2) The built-in capacitor of the present invention can adjust the material of the capacitor dielectric layer according to the capacitance requirement, and also allow different positions of the vias to enter materials with different dielectric constants. Of course, it is also possible to adjust the voltage layer and the ground layer at the same time. Dielectric layer thickness. '' The present invention is described above only with a preferred embodiment, and is not intended to limit the scope of application of the present invention. Those skilled in the art can make some changes or modifications without departing from the spirit of the present invention, and the scope of patent protection All should be included in the scope of patent application described below. This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ------ 1-^ ---- r _ ^ -------------- -. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs