19Iltwfl.doc/002 A7 B7 經濟部中央標準局貝工消費合作社印裝 五、發明説明（丨） 本發明係有關於一種半導體元件金屬內連線的製造 方法，特別是有關於一種具有大型著陸墊的導電插塞的製 造方法。 在追求積體電路元件微小型化的過程中，個體元件已 被製造的非常小，且這些元件也被緊密的構裝。在致力於 元件尺寸縮小的同時，如何利用最少的製程步驟，生產較 小型高密度的電容器與連接基底的連線，是隨之而來的一 連串的挑戰。比如在過去幾年中，以二微米的線寬可製造 出具有五十萬個電晶體的積體電路，但在目前，生產具有 幾百萬個電晶體的積體電路已非難事。爲維持整個積體電 路晶片的小型化，導電線寬的寬度已縮減爲0.5微米之 下，所以可想而知，未來高積集度的積體電路將會需要更 小的金屬線寬和連線。 小型化過程在微影對準與基底接觸窗的製作過程中產 生一些難題。通常在製造高積集度的半導體元件，例如動 態隨機存取記憶器（DRAM)單元時，因爲不同的微影罩幕 需要精確的對準，所以連接矽基底之儲存電極的製作乃成 爲一個困難的過程。當線寬降低，積體電路的製程在對準 一微影形狀至另一微影形狀與公差的控制有很多困難。例 如底電極的基部（比如插塞）與覆蓋金屬層或柱狀電極（底 電極）的對準是很重要的。爲降低錯誤對準的誤差和產量的 損失’對準公差應被提高。 關於金屬內連線的其他問題亦倍受重視，並努力硏究 其解決方案。例如US5,374,591專利案(Haswgawa等人)提 (請先閱讀背面之注意事項再填寫本頁) -:° 本紙張尺度適用中國囤家榡準（CMS ) A4規格（210X297公蝥） 19lltwf|.doc/002 A7 B7 五、發明説明（2 ) 出一金屬插塞的製造方法，其中介層孔周圍的附著層已被 去除。US5,459，100專利案(Choi)提出在不同深度的孔中製 作金屬插塞的方法，此專利使用兩種不同的氧化層，並蝕 刻淸除部份上位氧化層。US5,567,270專利案（Liu)則提出 一具有較大型上表面之插塞接觸窗的製作方法。 然而，如何以一有效率的製造方法製備一具有大型著 陸墊區的插塞依然是十分需要的。 有鑑於此，本發明的主要目的，係在提供一插塞(或金 屬內連線）的製造方法’此插塞具有釘狀的著陸墊，其可用 來與基底或下方的導電層接觸。 本發明的另一目的’在提供一具有大型著陸墊的插塞 之製造方法，該著陸墊可用來與上方的導電層接觸，藉以 減少錯誤對準的發生。 本發明的目的，亦在提供一具有大型著陸墊的插塞之 製造方法’藉以提高上層導電層對插塞著陸墊的對準公差 (overlay derivation) 〇 爲達上述之目的，本發明提供二個較佳實施例，說明 著陸墊之釘狀插塞的製造方法。第一實施例(第1A-4C圖） 利用兩種不同蝕刻速率蝕刻二絕緣層，上位絕緣層24的 側面被飩刻形成一鑄模，以形成平面大型的著陸墊36。第 二實施例(第5_8圖）利用二種蝕刻方法蝕刻一絕緣層_(1) 等向性蝕刻以及(2 )非等向性蝕刻。等向性蝕刻形成一半球 形的孔（例如碗形），此孔用於製作圓形的釘狀著陸墊58的 圓形頭部。 b 本紙張尺度逋用中國國家標準（CNS ) Λ4規格（210X297公趁} (請先閱讀背而之注意事項再填寫本頁) Γ 經濟部中央標嗥局貝工消費合作社印製 19! ltwfl.doc/002 A7 經淆部中央標卑局员τ_消贽合作私印來 五、發明説明（,） 第一實施例係爲一具有大型著陸墊的釘狀插塞之製造 方法，其中包括： (a) ,(請參考第1圖）在一半導體結構之接觸窗區上方， 形成一第一絕緣層2 0，該絕緣層係爲一氧化層； (b) 在第一絕緣層20上形成一第二絕緣層24，該絕緣 層係爲一氧化層； (c) 在第二絕緣層24上；沉積一第一光阻層28 ;此第 一光阻層28在接觸窗上方具有一第一開口； · (d) 利用選擇性的等向性蝕刻，蝕刻第二絕緣層24，控 制第二絕緣層24與第一絕緣層20之蝕刻選擇比約 在2:1與20:1之間；等向性蝕刻在第二絕緣層之第 一光阻開口 28A上，蝕刻一寬度25，範圍在0.05 與0.3微米之間； (e) 利用一乾蝕刻，蝕刻第一絕緣層20，用以暴露出基 底10的表面； (0去除第一光阻層28 ; (g) 在基底表面沉積一導電層34,該導電層係一多晶矽 層或一金屬層；以及 (h) 利用回蝕或化學機械硏磨法平坦化該導電層34，藉 以形成一釘狀導電插塞36。 本發明的第二實施例，係利用一兩步驟蝕刻法，製造 一圓形的釘狀插塞。其中包括： (請參考第5圖）在一半導體結構上，形成一第一絕緣層 40，該絕緣層係一氧化層； Ί (請先閱讀背面之注意事項再填寫本頁) 丁 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） A7 B7 191 Itwfl .doc/002 五、發明说明（f) 在第一絕緣層40上形成一第一光阻層44;該第一光阻 層44在接觸窗上方具有一第一開口； 利用一等向性蝕刻對第一絕緣層40進行一第一蝕刻； 利用一非等向性蝕刻對第一絕緣層40進行一第二蝕 刻，用以暴露出基底10的表面；第二蝕刻形成一圓形的 釘狀接觸孔26 ; (請參考第6圖）去除第一光阻層44 ; (請參考第7圖）沉積一導電層54，較佳是以多晶矽免 塡圓形的釘狀接觸孔50(46+48); 利用化學機械硏磨法或一回蝕過程平坦化該導電層， 藉以形成一圓形的釘狀導電插塞58。 本發明提供二實施例，說明一具有大型著陸墊區的釘 狀著陸墊的製造方法。此大型著陸墊區增加了上位的金屬 接觸窗之錯誤對準的公差。本發明的兩個實施例，不僅容 易製造且花費低。本發明可作爲任何兩個導電層（或基底) 間的連線，並具有寬鬆的對準公差。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第ΙΑ、2A、3A及4A圖所示，爲根據本發明之第一實 施例，一種著陸墊之釘狀插塞的製造方法剖面圖。 第IB、2B、3B及4B圖所示，爲根據本發明之第一實 施例，一種釘狀著陸墊複插塞的製造方法，該圖式分別爲 本紙乐尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (诗先閲讀背面之注意事項再填寫本頁) 訂 ^部中"標準局貝工消贽合竹社印聚 經漭部中次榡準局貝-T消f合作社印^ -4 3 92 4 9 19Utwfl.doc/002 A7 B7 五、發明説明（y ) 第ΙΑ、2A、3A及4A剖面圖的製造步驟流程圖。 第4C圖所示/爲根據本發明之實施例，一種插塞的釘 狀著陸墊與上位導電層接觸的製造方法剖面圖。 第4D圖所示，爲根據本發明之實施例，一種具有著陸 墊之釘狀插塞的製造方法剖面圖，其中二插塞爲垂直堆 疊° 第4Ε圖係顯示本發明之一著陸墊的俯瞰圖，表示本發 明之對準公差的增加。 ^ 第5圖至第8圖所示，爲根據本發明之第二實施例， 一種圓形的釘狀著陸墊複插塞的製造方法。 第9Α、9Β圖係顯示根據本發明之第一與第二實施例 之釘狀插塞的俯瞰圖。 實施例 本發明將以圖式詳細說明之。本發明提供一半導體元 件的釘型插塞的製造方法，本發明可作爲任何兩導電層間 的接觸窗，例如兩個金屬層或金屬層與基底之間。本發明 將以下面兩個實施例說明之。 第一實施例 第1Α至4C圖所示，爲本發明之第一實施例的製造方 法。如第一圖所示爲在半導體結構10上，形成一第一絕 緣層20,該半導體結構由形成於基底上之不同層件與元件 所組成。該半導體結構可包括半導體元件，例如由閘極 12，閘極絕緣層14，間隙壁16，閘極介電層18等元件所 組成的場效電晶體（FETs)。基底在主動區的上方有一接觸 (锖先閱讀背面之注意事項再填寫本頁)19Iltwfl.doc / 002 A7 B7 Printed by the Central Bureau of Standards, Ministry of Economic Affairs, Shellfish Consumer Cooperative, V. Description of the Invention (丨) The present invention relates to a method for manufacturing a metal interconnect of a semiconductor element, and more particularly to a method having a large landing pad Manufacturing method of conductive plug. In the pursuit of miniaturization of integrated circuit components, individual components have been made very small, and these components have also been closely packed. While working to reduce the size of the components, how to use the smallest number of process steps to produce smaller and high-density capacitors connected to the connection substrate is a series of challenges. For example, in the past few years, an integrated circuit with 500,000 transistors can be manufactured with a line width of two microns, but at present, it is not difficult to produce an integrated circuit with millions of transistors. In order to maintain the miniaturization of the integrated circuit chip, the width of the conductive line width has been reduced to less than 0.5 micrometers, so it is conceivable that in the future, integrated circuits with high accumulation levels will require smaller metal line widths and connections. line. The miniaturization process creates some difficulties during the fabrication of the lithographic alignment and substrate contact windows. Generally, when manufacturing semiconductor elements with high accumulation levels, such as dynamic random access memory (DRAM) units, the fabrication of storage electrodes connected to a silicon substrate becomes difficult because different lithographic masks require precise alignment. the process of. When the line width is reduced, the manufacturing process of the integrated circuit has many difficulties in aligning one lithographic shape to another lithographic shape and controlling the tolerance. For example, the alignment of the base of the bottom electrode (such as a plug) with the cover metal or columnar electrode (bottom electrode) is important. To reduce the misalignment error and loss of yield 'the alignment tolerance should be increased. Other issues regarding metal interconnects are also valued and efforts are being made to explore their solutions. For example, US Pat. No. 5,374,591 (Haswgawa et al.) Proposes (please read the precautions on the back before filling out this page)-: ° This paper size is applicable to China Storehouse Standard (CMS) A4 specification (210X297 cm) 19lltwf |. doc / 002 A7 B7 V. Description of the invention (2) A method for manufacturing a metal plug, in which the adhesive layer around the via hole has been removed. US Patent 5,459,100 (Choi) proposes a method for making metal plugs in holes of different depths. This patent uses two different oxide layers and etches away some of the upper oxide layers. US Patent No. 5,567,270 (Liu) proposes a method for manufacturing a plug contact window with a larger upper surface. However, how to prepare a plug with a large land area by an efficient manufacturing method is still very much needed. In view of this, the main object of the present invention is to provide a method for manufacturing a plug (or metal interconnect). The plug has a nail-like land pad which can be used to contact the substrate or the underlying conductive layer. Another object of the present invention is to provide a method for manufacturing a plug having a large landing pad, which can be used to contact the conductive layer above to reduce the occurrence of misalignment. The object of the present invention is also to provide a method for manufacturing a plug having a large landing pad, thereby increasing the overlay derivation of the upper conductive layer to the plug landing pad. To achieve the above-mentioned object, the present invention provides two A preferred embodiment illustrates a method for manufacturing a nail plug of a landing pad. The first embodiment (FIGS. 1A-4C) uses two different etching rates to etch the two insulating layers. The side of the upper insulating layer 24 is etched to form a mold to form a large planar landing pad 36. The second embodiment (FIGS. 5-8) uses two etching methods to etch an insulating layer_ (1) isotropic etching and (2) anisotropic etching. Isotropic etching forms a hemispherical hole (e.g., a bowl shape), which is used to make the round head of the round pin-shaped landing pad 58. b This paper size is in accordance with Chinese National Standard (CNS) Λ4 specification (210X297). (Please read the precautions before filling out this page) Γ Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 19 ltwfl. doc / 002 A7 Member of the Central Standards Bureau of the Ministry of Confusion, τ_elimination cooperation, private printing, 5. Description of the Invention (,) The first embodiment is a method for manufacturing a nail plug with a large landing pad, including: (a), (refer to FIG. 1), a first insulating layer 20 is formed above a contact window area of a semiconductor structure, and the insulating layer is an oxide layer; (b) is formed on the first insulating layer 20 A second insulating layer 24, which is an oxide layer; (c) on the second insulating layer 24; depositing a first photoresist layer 28; the first photoresist layer 28 has a first An opening; (d) using selective isotropic etching to etch the second insulating layer 24 to control the etching selection ratio of the second insulating layer 24 and the first insulating layer 20 to be between about 2: 1 and 20: 1 ; Isotropically etch on the first photoresist opening 28A of the second insulating layer, and etch a width of 25, ranging between 0.05 and 0.3 microns (e) using a dry etch to etch the first insulating layer 20 to expose the surface of the substrate 10; (0 to remove the first photoresist layer 28; (g) depositing a conductive layer 34 on the surface of the substrate, the conductive layer is a A polycrystalline silicon layer or a metal layer; and (h) planarizing the conductive layer 34 by etch back or chemical mechanical honing to form a pin-shaped conductive plug 36. The second embodiment of the present invention uses one or two steps An etching method is used to make a round pin-shaped plug, which includes: (refer to FIG. 5) forming a first insulating layer 40 on a semiconductor structure, the insulating layer being an oxide layer; Ί (Please read first Note on the back, please fill in this page again.) The paper size of this paper is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) A7 B7 191 Itwfl .doc / 002 5. Description of the invention (f) On the first insulating layer 40 Forming a first photoresist layer 44; the first photoresist layer 44 has a first opening above the contact window; performing a first etching on the first insulating layer 40 by using an isotropic etching; using an anisotropy Performing a second etch on the first insulating layer 40 to expose The surface of the bottom 10; the second etching forms a round pin-shaped contact hole 26; (please refer to FIG. 6) remove the first photoresist layer 44; (please refer to FIG. 7) deposit a conductive layer 54, preferably Polycrystalline silicon is used to avoid round pin-shaped contact holes 50 (46 + 48); the conductive layer is planarized by chemical mechanical honing or an etch-back process, thereby forming a round pin-shaped conductive plug 58. The present invention Two embodiments are provided to illustrate a method for manufacturing a nailed landing pad with a large landing pad area. This large landing pad area increases the misalignment tolerance of the upper metal contact window. The two embodiments of the present invention are not only easy to manufacture but also low in cost. The invention can be used as a connection line between any two conductive layers (or substrates) and has loose alignment tolerances. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: 2A, 3A, and 4A are cross-sectional views of a method for manufacturing a nail-shaped plug for a landing pad according to a first embodiment of the present invention. Figures IB, 2B, 3B, and 4B show a method for manufacturing a multi-plug for a nailed landing pad according to the first embodiment of the present invention. The drawings are applicable to the Chinese National Standard (CNS) A4 for the paper scale. Specifications (210X297 mm) (Read the notes on the back of the poem before filling out this page) Order ^ in the Ministry of Standards " Standard Bureau Bei Gong Xiaohe Zhuzhu Printing Department of the Ministry of Economy and Social Affairs quasi bureau Bei T-f cooperative印 ^-4 3 92 4 9 19Utwfl.doc / 002 A7 B7 V. Description of the invention (y) Flow chart of manufacturing steps of section IA, 2A, 3A and 4A. FIG. 4C shows / is a cross-sectional view of a method for manufacturing a pin-shaped landing pad of a plug in contact with an upper conductive layer according to an embodiment of the present invention. FIG. 4D is a sectional view of a method for manufacturing a nail plug with a landing pad according to an embodiment of the present invention, in which two plugs are vertically stacked. The figure shows an increase in the alignment tolerance of the present invention. ^ Figures 5 to 8 show a method for manufacturing a round nail-shaped landing pad complex plug according to a second embodiment of the present invention. Figures 9A and 9B are bird's-eye views showing nail plugs according to the first and second embodiments of the present invention. Examples The present invention will be described in detail with reference to the drawings. The present invention provides a method for manufacturing a pin plug of a semiconductor device. The present invention can be used as a contact window between any two conductive layers, such as between two metal layers or between a metal layer and a substrate. The invention is illustrated by the following two examples. First Embodiment Figs. 1A to 4C show a manufacturing method according to a first embodiment of the present invention. As shown in the first figure, a first insulating layer 20 is formed on the semiconductor structure 10, and the semiconductor structure is composed of different layers and elements formed on a substrate. The semiconductor structure may include semiconductor elements, such as field effect transistors (FETs) composed of gate 12, gate insulating layer 14, spacer 16, gate dielectric 18 and other elements. The substrate has a contact above the active area (锖 Read the precautions on the back before filling this page)
本紙張尺度適用中國國家標準（CNS ) A4規格（2ί〇Χ297公釐} »— -ί ο »— -ί ο 1911twfl,doc/002 第二絕緣層24。第 A7 B7 五、發明説明（厶） 窗區η ’插塞36將形成與接觸窗區η接觸。 第一絕緣層20係爲一氧化層或一四乙基正砂酸鹽 (TEOS)氧化物’其中以TEOS氧化物爲較佳。第一絕緣層 20的較佳厚度約在1〇〇〇至20000Α之間。 接著，在第一絕緣層20上 二絕緣層24與第一絕緣層20之蝕刻選擇比以控制在約2:1 以及20:1之間較好，而以約1〇:1的蝕刻選擇比最佳。第 二絕緣層24較佳爲一氧化層，例如以電漿化學氣相沉檀 法製造之氧化層（ΡΕ-氧化層）、硼磷矽玻璃(BPSG)或磷矽玻 璃(PSG)，而以PE-氧化層製成最佳。 表一顯示第一與第二絕緣層配合等向性飩刻的較佳組 (請先閱讀背面之注意事項再填寫本頁} "0 ΓThis paper size applies the Chinese National Standard (CNS) A4 specification (2ί〇Χ297mm) »— -ί ο» — -ί ο 1911twfl, doc / 002 Second insulation layer 24. Article A7 B7 V. Description of the invention (厶) The window region η ′ plug 36 will be in contact with the contact window region η. The first insulating layer 20 is an oxide layer or a tetraethyl ortho-saltate (TEOS) oxide. Among them, TEOS oxide is preferred. The preferred thickness of the first insulating layer 20 is between about 1000 and 20000 A. Then, the etching selection ratio of the two insulating layers 24 to the first insulating layer 20 on the first insulating layer 20 is controlled to about 2: 1. And 20: 1 is better, and an etching selection ratio of about 10: 1 is the best. The second insulating layer 24 is preferably an oxide layer, such as an oxide layer manufactured by a plasma chemical vapor deposition method ( PE-oxide layer), borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), and the PE-oxide layer is the best. Best Group (Please read the notes on the back before filling out this page} " 0 Γ
合。 表1 :本發明的較佳組合 組合類型 第一絕緣層2 0 第二絕緣層24 等向性蝕刻 1 TEOS BPSG BOE 2 TEOS PE-Oxide BOE or DHF 3 TEOS PSG BOE or DHF 好鴻部中决禕卑局負h消费合作社印製 請參考第1A圖，在第二絕緣層24上形成一第一光阻 層28，第一光阻層較好在接觸窗11的上方有一第—光阻 開口，第一光阻開口之開口大小(例如直徑）約在0.15至2.0 微米之間較佳，最好在0.15和0.5微米以內第一光阻開 口可有任何形狀，例如圓形 '矩形、正方形或三角形，而 以圓形較佳。 如第2A圖所不，第一絕緣層24是利用第二絕緣層24 |σ 本紙张尺度適用中國國家標準{ CNS ) A4規格（2丨0X 297公釐） A7 B7 1911t\vfl.doc/002 五、發明説明（q ) 與第一絕緣層20約2:1至20:1的蝕刻選擇比’等向性蝕 刻鑿穿第一光阻的開口。第二絕緣層的等向性蝕刻以緩衝 氧化物蝕刻(BOE)或稀釋的氫氟酸(DHF)進行，而等向性蝕 亥0,蝕刻第二絕緣層之寬度25約在0·05至0.3微米之間。 .等向性蝕刻形成一圓盤形開口 26Α(例如上位開口或著陸 墊開口），此開口是作爲插塞36之大型著陸墊的模型（例如 鑄模）。 再利用乾蝕亥ίί(例如一種非等向性蝕刻），蝕刻第一絕fe 層20，暴露出基底10的表面。此蝕刻形成一下位開口 26B。上位開口 26A與下位開口 26B共同形成一釘狀開口 26，此開口將形成一釘狀插塞。接著再去除第一光阻層 28 ° 如第3A圖所示，沉積一導電層34。導電層34較好由 一多晶矽或多晶矽與矽化鎢所組成，導電層34的較佳厚 度約在1000至10000A之間。本發明可用於製造鎢、鎢合 金、多晶矽或任何導電物質的插塞。 請參考第4A圖，平坦化導電層34，藉以形成一釘狀 導電插塞36。導電層34可藉由化學機械硏磨(CMP)過程或 一回蝕過程平坦化，而以回鈾過程平坦化較佳。 如第4E圖所示，插塞36的著陸墊最好有一頂面關鍵 尺寸（Critical dimension)67(例如中心孔）’其具有一對準公 差67A，範圍約在0.05與0.3微米間，而以在0.08與0.12 微米之間最佳。請參照第4E圖，第4E圖爲插塞36的俯 瞰圖。 (請先閱讀背面之注意事項再填寫本頁) 訂 本紙乐尺度適用中國國家摞準（CNS ) Μ規格（210X297公釐） 191 Itwf! -doc/002 A7 B7 五、發明説明（δ ) 如第4C圖所示，在本發明大型圓形的釘狀著陸墊36 的上方Υ形成—金屬接觸/金屬層37。在第二絕緣層24 的上方=成〜介電層21 ’格式化此界電層。使金屬層37 與大型著^陸墊插塞36相接觸，金屬層亦被格式化。如第 4D圖所不，上位的導電層37形成本發明之另一個釘狀著 陸墊38。 第二實施例 本發明之第二實施例乃是—半導體元件之圓形的釘狀 插塞58之製造方法。第5圖到第8圖顯示第二實施例的 製造步驟。 i靑參考第5圖，在半導體結構上形成一第一絕緣層 4〇 °此半導體結構1〇被製造在矽基底之上d第一絕緣層 4〇較好由一氧化層(BPSG或未摻雜的矽玻璃(USG))所組 成’而以棚磷矽玻璃最佳。一插塞與基底接觸的接觸區最 好被定義在基底之主動區的上方，此接觸插塞58可被製 造在基底或其他導電層之上。 如第5圖所示’在第一絕緣層40上，形成一第一光阻 層44 °第〜光阻層44在接觸區上方具有一第一光阻開口 44A。第—光阻開口可爲任何形狀，而以圓形或矩形較佳， 但以圓形最好。 請參考第5圖，利用等向性蝕刻在第一光阻層4〇執行 一第—蝕刻。等向性蝕刻以BOE或DHF較佳。第一蝕刻 在第一絕緣層40(第一開口 46)上蝕刻一半徑47，半徑範 圍約在0.05與〇.3微米之間較佳。此蝕刻形成一半碗形的 ,___ a 本紙張尺度適;fH gjgj家構準（cns )⑽桃（2丨加公们 (请先聞讀背面之注意事項再填寫本頁)Together. Table 1: The preferred combination type of the present invention The first insulation layer 2 0 The second insulation layer 24 Isotropic etching 1 TEOS BPSG BOE 2 TEOS PE-Oxide BOE or DHF 3 TEOS PSG BOE or DHF Printed by the humble negative consumer cooperative, please refer to FIG. 1A. A first photoresist layer 28 is formed on the second insulating layer 24. The first photoresist layer preferably has a first photoresist opening above the contact window 11, The opening size (eg, diameter) of the first photoresistive opening is preferably between 0.15 and 2.0 microns, and most preferably within 0.15 and 0.5 microns. The first photoresistive opening may have any shape, such as a circle, rectangle, square, or triangle. It is better to use a circle. As shown in Figure 2A, the first insulating layer 24 uses the second insulating layer 24 | σ This paper size applies the Chinese national standard {CNS) A4 specification (2 丨 0X 297 mm) A7 B7 1911t \ vfl.doc / 002 5. Description of the invention (q) An etching selection ratio of about 2: 1 to 20: 1 and the first insulating layer 20 is isotropically etched through the opening of the first photoresist. The isotropic etching of the second insulating layer is performed by buffer oxide etching (BOE) or diluted hydrofluoric acid (DHF), while the isotropic etching is 0, and the width 25 of the second insulating layer is about 0.05 to 0.3 micron. Isotropic etching forms a disc-shaped opening 26A (such as an upper opening or a landing pad opening), which is a model (such as a casting mold) of a large landing pad serving as the plug 36. Then, dry etching (for example, anisotropic etching) is used to etch the first insulating layer 20 to expose the surface of the substrate 10. This etching forms the lower opening 26B. The upper opening 26A and the lower opening 26B together form a nail-shaped opening 26, and this opening will form a nail-shaped plug. Then, the first photoresist layer is removed by 28 °. As shown in FIG. 3A, a conductive layer 34 is deposited. The conductive layer 34 is preferably composed of a polycrystalline silicon or polycrystalline silicon and tungsten silicide. The preferred thickness of the conductive layer 34 is between about 1000 and 10,000 A. The invention can be used to make plugs of tungsten, tungsten alloys, polycrystalline silicon, or any conductive material. Referring to FIG. 4A, the conductive layer 34 is planarized to form a nail-shaped conductive plug 36. The conductive layer 34 may be planarized by a chemical mechanical honing (CMP) process or an etch-back process, and is preferably planarized by a uranium etch-back process. As shown in FIG. 4E, the landing pad of the plug 36 preferably has a top critical dimension 67 (such as a central hole), which has an alignment tolerance 67A, ranging from about 0.05 to 0.3 micrometers. Best between 0.08 and 0.12 microns. Please refer to FIG. 4E, which is a top view of the plug 36. (Please read the notes on the back before filling this page) The size of the paper scale is applicable to China National Standards (CNS) M specifications (210X297 mm) 191 Itwf! -Doc / 002 A7 B7 V. Description of the invention (δ) As shown in FIG. 4C, a metal contact / metal layer 37 is formed on the large circular nail-shaped landing pad 36 of the present invention. Above the second insulating layer 24 = the dielectric layer 21 'is used to format this boundary electrical layer. The metal layer 37 is brought into contact with the large landing pad plug 36, and the metal layer is also formatted. As shown in FIG. 4D, the upper conductive layer 37 forms another nail-like land pad 38 of the present invention. Second Embodiment A second embodiment of the present invention is a method for manufacturing a circular pin-shaped plug 58 for a semiconductor device. 5 to 8 show manufacturing steps of the second embodiment. i. Referring to FIG. 5, a first insulating layer 40 is formed on a semiconductor structure. This semiconductor structure 10 is fabricated on a silicon substrate. The first insulating layer 40 is preferably made of an oxide layer (BPSG or undoped). Silicate glass (USG) is the best choice. A contact area where a plug contacts the substrate is preferably defined above the active area of the substrate. The contact plug 58 can be fabricated on the substrate or other conductive layer. As shown in FIG. 5 ', a first photoresist layer 44 is formed on the first insulating layer 40. The first to photoresist layers 44 have a first photoresist opening 44A above the contact area. The first photoresist opening can be of any shape, but a circle or rectangle is preferred, but a circle is best. Referring to FIG. 5, a first-etch is performed on the first photoresist layer 40 by using isotropic etching. For isotropic etching, BOE or DHF is preferred. First etching A radius 47 is etched on the first insulating layer 40 (the first opening 46), and the radius is preferably between about 0.05 and 0.3 micrometers. This etching forms a half-bowl shape, ___ a The paper size is appropriate; fH gjgj family structure (cns) Peach (2 丨 Canadians (please read the precautions on the back before filling this page)
*1T 枝漭部中"標枣局員^-消先合作社印聚 A7 1911twfl.doc/002 嫂湞部中央標準局員工消费合作社印絮 B7_ 五、發明説明（今） 孔，此孔用於定義圓形釘狀插塞的著陸墊。 第5圖指出利用非等向性蝕刻在第一絕緣層40上執行 一第二蝕刻。非等向性蝕刻暴露出基底10的表面，形成 一下位開口 48。第二蝕刻形成一圓形的釘狀接觸孔 50(46+48)，此孔由一上位碗形開口 46與下位開口 48共同 組成。 如第6圖所不，移除第一光阻層44。 請參考第6圖，在表面沉積一導電層54，塡滿圓形&勺 釘狀接觸孔50(46+48)。導電層54以多晶矽、鎢、鋁或鈦 /氮化鈦所組成較佳。 請參考第七圖，導電層54最好被平坦化，藉以形成一 圓形的釘狀導電插塞58。導電層54的平坦化最好藉由化 學機械硏磨或可利用回蝕法完成。 接著，如第8圖所示，在本發明插塞58的大型著陸墊 上，形成一導電層（例如金屬接觸窗/金屬層）64。在第一 絕緣層40之上，形成一介電層62，微影触刻(pattern)此介 電層。在大型著陸墊插塞58上，形成一金屬層64，亦微 影蝕刻此金屬層。 第9A與9B圖表示出第一與第二實施例的俯瞰圖。第 9A圖顯示一圓形插塞65(36或58)，而第9B圖顯示一矩 形插塞65(36或58)。虛線表示下位開口 48(或26B)。此插 塞可爲任何形狀，但以圓形、正方形或矩形較佳。 本發明提供二實施例，說明一具有大型著陸墊區的釘 狀著陸墊之製造方法。此大型著陸墊區增加上層金屬接觸 13 本紙張尺度適用中國囤家標準（CNS ) A4規格（210X297公釐） (請先閱讀背面之注意事項再填寫本頁) - ^43 92 4 9 A7 19™02_B7__ 五、發明説明（卬） 窗錯誤對準的公差。本發明的兩個實施例，不僅容易製造 且花費低廉。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 (諳先閱讀背面之注意事項再填寫本頁) J=e 經湞部中决標卒局負JX消费合作牡印髮 本紙張尺度適用中國國家標隼{ CNS ) A4規格（2丨0X 297公釐）* 1T Member of the Ministry of Standards " Biao Jujube Bureau ^ -Xiaoxian Cooperative Co., Ltd. A7 1911twfl.doc / 002 Ministry of Standards Bureau Staff Consumer Cooperative Co., Ltd. Print B7_ 5. Description of the invention (present) hole, this hole is used to define Landing pad with round spike plug. FIG. 5 indicates that a second etching is performed on the first insulating layer 40 using anisotropic etching. The anisotropic etching exposes the surface of the substrate 10 to form a lower opening 48. The second etching forms a circular pin-shaped contact hole 50 (46 + 48). This hole is composed of an upper bowl opening 46 and a lower opening 48 together. As shown in FIG. 6, the first photoresist layer 44 is removed. Referring to Fig. 6, a conductive layer 54 is deposited on the surface, and the circular & spoon-shaped contact hole 50 (46 + 48) is filled. The conductive layer 54 is preferably composed of polycrystalline silicon, tungsten, aluminum, or titanium / titanium nitride. Referring to the seventh figure, the conductive layer 54 is preferably planarized to form a round pin-shaped conductive plug 58. The planarization of the conductive layer 54 is preferably performed by chemical mechanical honing or by an etch-back method. Next, as shown in FIG. 8, a conductive layer (such as a metal contact window / metal layer) 64 is formed on the large-scale landing pad of the plug 58 of the present invention. On top of the first insulating layer 40, a dielectric layer 62 is formed, and the lithography patterned the dielectric layer. On the large landing pad plug 58, a metal layer 64 is formed, and this metal layer is lithographically etched. 9A and 9B are diagrams showing bird's-eye views of the first and second embodiments. Figure 9A shows a round plug 65 (36 or 58), and Figure 9B shows a rectangular plug 65 (36 or 58). The dotted line indicates the lower opening 48 (or 26B). This plug can be of any shape, but is preferably circular, square or rectangular. The present invention provides two embodiments, illustrating a method for manufacturing a nail-like landing pad having a large landing pad area. This large landing pad area increases the upper metal contact 13 This paper size is applicable to the Chinese standard (CNS) A4 size (210X297 mm) (Please read the precautions on the back before filling this page)-^ 43 92 4 9 A7 19 ™ 02_B7__ 5. Description of the invention (卬) Tolerance of window misalignment. The two embodiments of the present invention are easy to manufacture and inexpensive. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling this page) J = e The final bid of the Ministry of Economic Affairs and the negative JX consumer cooperation printed and issued on this paper are applicable to Chinese national standards {CNS) A4 size (2 丨 0X 297 public %)