2 2 9 3 4 A7 B7 五 、發明説明（ 詳細說明： 技術領域： 本發明係關於一種形成靴帶式電路之升壓節點的方 法’特別是關於一種具高崩潰電壓及低漏電流之升壓節點 的製作方法。 發明背景： 積體電路的種類主要有兩種：分別是邏輯(Logic)和記 憶體(Memory)。前者主要是執行邏輯的運算，如個人電腦 的心臟微處理器；後者則如各種的唯讀及隨機存取記憶 體，用來儲存所輸入的資料或數據。整個記憶體的結構除 了有數以億計的記憶胞(Memory cell)之外，尚且包含將記 憶胞的位址加以解碼以決定其位置的位址解碼器，以及其 他與記憶體的操作相關的周邊電路。其中記憶胞在記憶體 内係以陣列的方式排列，每一個行與列的組合代表一個特 定的記憶體位址。在記憶胞陣列中，位於同行或者同列的 的記憶胞再以相同的導線加以串接，其中左右横向的導線 與棱列上的§己憶胞相接，稱為字元漆(仰Line);而上下 縱向的導線與縱列上的記憶胞相接，稱為位元線(Bjt Line)。 首先以動態隨機存取記憶體（DRAM)為例，說明位 元線和字元線運作的型態，請參考圖一，為一個DRAm記 憶胞連接位元線和字元線的電路示意圖。所述記憶 胞10係位於陣列中的第三列第五行，其包含一個M〇s電晶 體11和一個電容器12，其中MOS電晶體11的閘極彳彳彳連接 本紙張尺度適用中國國家標準（C^s } A4規格（2〖0X2.97公釐） ——II—af— (祷先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 [!H 3 π 〜·Μ ； Α7 _____Β7____ 五、發明説明（> ) 至字元線13，MOS電晶體11的源極112連接至位元線14， MOS電晶體11的汲極113連接至電容器12，而該電容器12 的另一端則接地。當DRAM記憶體的操作要在該記憶胞 上讀或寫0或1時，該字元線13必須Hi」入r個高乎位的突波-以啟動該MOS電晶體11，而讀寫0或1的訊號則由位元鎳 14來傳輸。其中所述高準位的突波係由圖上的字元線驅動 電路(Word Une Driver) 15所控制。所述字元線驅動器係 一種勒：帶式電路(Boot Strap Circuit)。 業界已有許多論文和專利揭露出使用於半導體記憶裝 置的勒：帶式電路，例如Mao; Robert S. of Etron Techno丨ogy，|nc·，在美國專利uS51f^467中所揭露之” Bootstrap circuit for word line driver in semiconductor memory” ，以及 Sugibayashi; Tadahiko of NEC Corporation，在美國專利US5184035中所揭露之” Bootstrap circuit incorporated in semiconductor memory device for driving word lines”。圖二係顯示目前業界所普 遍使用的字元線驅動器的電路圖，包含有第一電晶體31、 第二電晶體32、和第三電晶體33等三個電晶體。其中第一 電晶體31的汲極311連接至第一切換開關S1，其閘極312 連接至第—切換開關S2 ’而其源極313連接至第二電晶體 32的閘極322。所述第二電晶體32的汲極321連接至第一電 壓源V1，其閘極322在節點B連接至第一電晶體31的源極 313 ’而其源極323經由郎點A連接至字元線μ。所述第二 電晶體33的及極331連接至節點A，其閘極332連接至第二 —1 ____ _ 本紙張尺度適用中國國家標準（CNS ) A4規格（210>?297公整) ------ (#先聞讀背面之注意事項再^寫本頁) 訂 經濟部智慧財產局員工消费合作社印製 A7 B7 五、發明説明（2) 切換開關S3，而其源極333則接地。所述第三切換開關S3 係第一切換開關S1的反相。其中第一切換開關別、第二切 換開關S2、和第三切換開關S3係做為啟動字元線M的選擇 開關。當要將字元線的電位提昇至高準位時，第一切換開 關S1和第二切換開關S2都輪出高準位Vcc使第一電晶體31 和第二電晶體32皆導通，而第三切換開關S3則輸出低準位 使第二電晶體33關閉。相反地，當要將字元線的電位降至 低準位時，第一切換開關51和第二切換開關52都輸出低準 位使第一電晶體31和第二電晶體32皆關閉，而第三切換開 關S3則輸出高準位使第三電晶體33導通而接地。 當苐一電晶體31導通時，節點B (亦即第二電晶體32 的閘極322 )的電位提昇至Vcc-Vth(T1)，使得第二電晶體 32得以形成反轉層（丨nversjon |_ayer)而導通。其中Vcc代表 工作電壓’而Vth(T1)代表第一電晶體31的啟始電麗 (Threshold Vo丨tage)。此時第一電壓源V1開啟至高電壓 Vh ’因第一電晶體32的向電容輕合而使節點b的電位提昇 至Vcc-Vth(T1)+K* Vh (其中K代表電長耦合比率 (Capacitor Coupling Ratio)，為一個接近 1 的常數）。此時 節點B的電位已提昇到至少比Vh高出一個Vth(T1)，因此第 二電晶體32得以完全導通，而使節點A (亦即字元線）的 電位提昇至Vh的高電位，得以進行資料的讀和寫。 然而’若是節點B有漏電流而無法將電荷儲存足釣長 的時間，第二電晶體32的閘極便無法長久維持比Vh高出_ 個Vth(T1)的電位，也因此字元線Μ的局電位便無法維持。 本紙張尺度適用中國國家標準（CpS ) Α4規格（210>^97公釐] 〜 ---一 ---II -^--I I 壯衣I I 訂 I I - I I . · ' . Γ.,ι 、 (請先聞讀背面之注意事項再填寫本頁) i4 3 92 2 1 A7 五、發明説明（0 ) 巧節點B的漏電流會使字元線M的電位降低，而導致 .續讀寫動侧錯誤。其中，節點B的漏電流主要係來自接 面漏電流(Junction Leakage)。 發明概述： =發_主要目的為提供—種在半導體基板上形成鞋 帶式電路之升壓節點的方法。 本發明的次要目的為提供一種具高崩潰電壓及低漏電 流之升壓節點的製作方法。 .本發明的再—目的為提供一種使字元線維持高電位的 時間大幅提高的方法。 經濟部智慧財產局員工消費合作社印製 本發明揭露-種在半導體基板上形成使用於字元線驅 動器之靴帶式電路中升壓節點的方法，在一半導體基板上 形成- n型金氧半場效電晶體’以其源極做為所述ς帶式 電路之升壓節點’其步驟包括有：首先在所述半導體基板 上陸續形成ρ型井區和絕緣隔離，所述Ν型金氧半場效電 晶體將形成在該ρ型井區内。接下來形成金氧半場效電晶 體之閑極結構’所述電晶體之閘極結構包含有閘極介電 =、閘極導電層、以聽化_蓋。後續形成Ν型接雜之 淡摻雜源極/祕區，在所述祕結構_猶彡成氮化石夕間 隙壁’並利用Ν型換雜離子佈植技術纽極區進行濃播 雜’而源極區則不進行濃摻雜。陸續沉積一層氣化石夕層及 一層氧化妙層，利用傳統的微影與非均向性银刻技術，在 所述氧化石夕層上開啟么自動對準的插塞窗口，再利用祕 刻技術將位於插塞窗口内的氮化石夕層去除。最後再形成複2 2 9 3 4 A7 B7 V. Description of the invention (Detailed description: Technical field: The present invention relates to a method for forming a boost node of a shoelaced circuit ', especially to a boost with high breakdown voltage and low leakage current Method for making nodes. Background of the Invention: There are two main types of integrated circuits: logic and memory. The former mainly performs logical operations, such as the heart microprocessor of a personal computer; the latter is Such as various read-only and random access memory, used to store the input data or data. In addition to hundreds of millions of memory cells, the entire memory structure also contains the address of the memory cell An address decoder that decodes to determine its position, and other peripheral circuits related to the operation of the memory. The memory cells are arranged in an array in the memory, and each combination of rows and columns represents a specific memory Body address. In the memory cell array, memory cells located in the same row or in the same row are connected in series by the same wire, of which the left and right lateral wires and the prism The § self-memory cell is connected, which is called the character lacquer (Yang Line); and the upper and lower vertical wires are connected with the memory cells on the column, which is called the Bjt Line. First, dynamic random access memory is used. DRAM is used as an example to explain the operation mode of bit lines and word lines. Please refer to Figure 1 for a circuit diagram of a DRAm memory cell connecting bit lines and word lines. The memory cell 10 is located in an array. The third column in the fifth row contains a Mos transistor 11 and a capacitor 12, where the gate of the MOS transistor 11 is connected to this paper. The Chinese standard (C ^ s} A4 specification (2 〖0X2.97mm） ——II—af— (Please read the notes on the back before filling this page) Order printed by the Intellectual Property Bureau employee consumption cooperative printed by the Ministry of Economic Affairs Intellectual Property Bureau printed by the consumer consumption cooperative printed [! H 3 π ~ · Μ; Α7 _____ Β7 ____ 5. Description of the Invention (>) to word line 13, the source 112 of MOS transistor 11 is connected to bit line 14, the drain 113 of MOS transistor 11 is connected to capacitor 12, The other end of the capacitor 12 is grounded. When the DRAM memory is operated in this memory When reading or writing 0 or 1 on the memory cell, the word line 13 must be Hi ”into r high-level surges-to activate the MOS transistor 11, and the signal to read or write 0 or 1 is bit nickel 14 for transmission. The high-level surge is controlled by the word line driver circuit (Word Une Driver) 15. The word line driver is a type of Boot Strap Circuit. There are many papers and patents in the industry exposing the use of semiconductor memory devices such as: band circuits, such as Mao; Robert S. of Etron Techno | ogy, | nc ·, disclosed in US patent uS51f ^ 467 "Bootstrap "circuit for word line driver in semiconductor memory", and "Bootstrap circuit incorporated in semiconductor memory device for driving word lines" as disclosed in Sugibayashi; Tadahiko of NEC Corporation, in US patent US5184035. Figure 2 is a circuit diagram of a word line driver commonly used in the industry, including three transistors including a first transistor 31, a second transistor 32, and a third transistor 33. The drain 311 of the first transistor 31 is connected to the first switch S1, the gate 312 thereof is connected to the first switch S2 ', and the source 313 thereof is connected to the gate 322 of the second transistor 32. The drain 321 of the second transistor 32 is connected to the first voltage source V1, and its gate 322 is connected to the source 313 'of the first transistor 31 at the node B, and its source 323 is connected to the word via the Lang point A. Element line μ. The sum electrode 331 of the second transistor 33 is connected to the node A, and the gate electrode 332 of the second transistor 33 is connected to the second—1 ____ _ This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 >? 297 mm)- ---- (#First read the notes on the back, and then ^ write this page) Order the A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (2) Switch S3, and its source 333 is grounded . The third changeover switch S3 is an inversion of the first changeover switch S1. The first changeover switch type, the second changeover switch S2, and the third changeover switch S3 are selected switches for activating the word line M. When the potential of the word line is to be raised to a high level, both the first switch S1 and the second switch S2 turn out a high level Vcc to turn on the first transistor 31 and the second transistor 32, and the third transistor The switch S3 outputs a low level to turn the second transistor 33 off. Conversely, when the potential of the word line is to be lowered to a low level, both the first switch 51 and the second switch 52 output a low level so that both the first transistor 31 and the second transistor 32 are turned off, and The third changeover switch S3 outputs a high level to make the third transistor 33 conductive and grounded. When the first transistor 31 is turned on, the potential of the node B (that is, the gate 322 of the second transistor 32) is raised to Vcc-Vth (T1), so that the second transistor 32 can form an inversion layer (nversjon | _ayer) and turn on. Where Vcc represents the working voltage 'and Vth (T1) represents the threshold voltage of the first transistor 31. At this time, the first voltage source V1 is turned on to a high voltage Vh ', and the potential of the node b is increased to Vcc-Vth (T1) + K * Vh (where K represents the electric length coupling ratio ( Capacitor Coupling Ratio), which is a constant close to 1.) At this time, the potential of the node B has been raised to at least one Vth (T1) higher than Vh, so the second transistor 32 can be completely turned on, and the potential of the node A (that is, the word line) is raised to a high potential of Vh. Be able to read and write data. However, if the node B has a leakage current and cannot store the charge for a long time, the gate of the second transistor 32 cannot maintain a potential higher than Vh by _Vth (T1) for a long time, and therefore the word line M The local potential cannot be maintained. This paper size applies Chinese National Standard (CpS) Α4 specification (210 > ^ 97mm) ~ -------- II-^-II Zhuang Yi II Order II-II. · '. Γ., Ι, (Please read the precautions on the back before filling this page) i4 3 92 2 1 A7 V. Description of the Invention (0) The leakage current of the smart node B will reduce the potential of the word line M, resulting in continued reading and writing. Side error. Among them, the leakage current of node B mainly comes from junction leakage current. Summary of the invention: The main purpose is to provide a method for forming a boost node of a shoelaced circuit on a semiconductor substrate. A secondary object of the present invention is to provide a method for manufacturing a boost node with high breakdown voltage and low leakage current. Another object of the present invention is to provide a method for greatly increasing the time during which a word line maintains a high potential. Economy Printed by the Consumer Cooperative of the Ministry of Intellectual Property, the invention discloses a method for forming a boost node on a semiconductor substrate for a shoe-line circuit used for a word line driver, and forming an n-type metal-oxide half field effect on a semiconductor substrate. Transistor 'with its source as described The step of the boosting node of the type circuit includes: firstly forming a p-type well region and insulation isolation on the semiconductor substrate, and the N-type metal-oxygen half field effect transistor will be formed in the p-type well region. Next, the free-electrode structure of the metal-oxide half-field effect transistor is formed. The gate structure of the transistor includes a gate dielectric layer, a gate conductive layer, and a lid. The subsequent formation of an N-type doped light doping The source / secret region is formed in the secret structure _ to form a nitrided nitride gap wall 'and the N-type exchange ion implantation technology is used to perform the doping in the new electrode region, while the source region is not to be doped. A layer of gasified stone layer and a layer of oxide layer are successively deposited. Using conventional lithography and anisotropic silver engraving technology, a plug window for automatic alignment is opened on the oxide stone layer, and then the secret engraving technology is used. The nitrided layer located in the plug window is removed. Finally, a complex is formed.
A7 -_B7 五、發明^ " 晶石夕揚塞。 本發明運用：1)在節點B處不進行濃摻雜、2)利用 一層氮化矽層以做為開啟複晶矽插塞窗口的蝕刻保護層等 :種方法，其分別都可以降低節點B的漏電流，提高I說 π式電路所控制的字元線得以維持高電位的時間。本發明 將兩者&運用在字元線驅動電路的製程上’更可發揮相乘 的功效’使字元線維持高電位的時間大幅提高，可以確保 5己憶體讀和寫的動作之正確性和可靠度。 圖式的簡要說明： 圖一為一個DRAM記憶胞連接位元線和字元線的電路示意 圖。 圖二顯示目前業界所普遍使用的字元線驅動電路的電路 圖。 圖三是本發明之實施例中在一半導體基板上形成P型井 區、絕緣隔離和淡摻雜源極/汲極區的剖面示意圖。 圖四是本發明之實施例中形成介電質間隙壁的剖面示意 圖。 圖五是本發明之實施例中形成濃摻雜汲極區的剖面示意 圖。 圖六是本發明之實施例中沉積一層氮化矽層及一層第一氧 化矽層的剖面示意圖。 圖七是本發明之實施例中利用傳統的微影與非均向性蝕刻 技術在所述第一氡化矽層上開啟插塞窗口的剖面示意 本紙乐尺度適用中國國家標芈（qis ) A4規格（210#297公釐） (請先聞讀背面之注$項再填寫本頁) .π 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（心） 圖。 (請先聞讀背面之注意事項再填寫本頁) 圖八是本發明之實施例中利用濕軸彳技術將位於插塞窗口 内的氮化石夕層去除的剖面示意圖。 圖九是本發明之實施例中在所述插塞窗口内形成第一複晶 矽插塞的剖面示意圖。 圖十是本發明之實施例中形成第二複晶石夕插塞和區域内連 線的剖面示意圖。 圖號說明 1〇_ DRAM記憶胞 11- MOS電晶體 111-M0S電晶體之閘極 112- MOS電晶體之源極 113-MOS電晶體之汲極 12- 電容器 13-字元線 14- 位元線 15-字元線驅動電路 31-第一電晶體 311- 第一電晶體之汲極 312-第一電晶體之閘極 313- 第一電晶體之源極 32-第二電晶體 321- 第二電晶體之没極 322-第一電晶體之閘極 323-第二電晶體之源極 33-第三電晶體 331 _ 第三電晶體之汲極 332-第三電晶體之閘極 333-第三電晶體之源極 40-半導體基板 41- P型井區 42-絕緣隔離 43- 閘極結構 431-閘極介電層 、 432- 閘極導電層 433-氮化矽頂蓋 44- 淡摻雜源/沒極區 本紙張尺度適用中國國家標举（CNS ) A4規格（210殳297公釐） 46- 介電質間隙壁 48- 濃推雜ί及極區 50- 氮化發層 52- 光阻 54-第一複晶矽插塞 56-弟-一複晶破插塞 A7 _____ B7 五、發明説明（，） 45-砷或磷離子 47-光阻 49-砷或磷離子 51-第一氧化發層 53-插塞窗口 55-第二氧化矽層 57-區域内連線 ^發明係個在半導縣板上形絲帶式電路之 升壓節點的方法’所形成之升壓節點的PN接面具有低漏 ，流和高崩潰電壓·暴數^得由黎轴爷或 子元線付以將兩電位維持足夠長的時間。本發明可適用於 動態隨機存取記紐、雜賊縣記紐、以及任何型 態之記憶體之字元線驅動電路。此外’為避免說明過於冗 長並避免圖示過於複雜，實施例的說明以及圖示，都將集 中在製造所述升壓節點（亦即背景說明中的節點巳）的製 程步驟及其結構，而圖三至圖十所顯示的電晶體係背景說 明圖二中之第一電晶體31，而所述升壓節點（節點B)係 位於其源極處。 清參考圖三’首先利用習知標準的微影及離子佈植製 程在一半導體基板40上形成P型井區41，再藉由習知的 技術形成絕緣隔離42 ’並因而定義出主動元件區。所述絕 緣隔離42可以是傳統的區域氧化矽層（LOCOS)，也可 以是淺渠溝隔離(Shallow Trench Isolation)，其作用是將每 本紙張尺度適用中國國篆標率（CNS〉A4規格（210>g297公釐） ' ! ' (請先閱讀背面之注意事項再填良本頁〕 .裝. 經濟部智慧財產局員工消費合作社印製 A7 ____B7______ 五、發明説明（f ) I----Γ---装II - f (請先閣讀背面之注意事項再填寫本頁) 一個主動元件區隔離開。接著利用習知的製程技術形成金 氧半場效電晶體之閘極結構43，其包含有閘極介電層 (Gate Dielectric)431、閘極導電層432、以及氮化矽頂蓋 (Nitride Cap)433。 其中所述閘極介電層431係以熱氧化法(Thermal Oxidation)所形成之氧化矽層，其厚度在30至8〇A_之間。 在形成所述閘極介電層41之前或之後，通常加入一道啟 始電壓調整的離子佈植製程（圖上未顯示）。所述閘極導 電層432係以低壓化學氣相沉積法（l〇w Pressure Chemical Vapor Deposition;以後皆簡稱為 LPCVD)或其他 經濟部智慧財產局員工消費合作社印製 之化學氣相沉積法形成之一層複晶矽層，其厚度介於800 至4000人之間。所述複晶矽層的摻雜有兩種方法，其中之 一係以碎或鱗摻入反應氣體石夕烧(S丨lane)中，使珅或磷與碎 同步沉積；另一方法係先沉積一本質複晶矽層，再以離子 佈植的技術將砷或磷摻雜入該複晶矽層内。隨後，以 LPCVD或电漿增強式化學氣相沉積法Enhanced Chemica丨Vapor Deposition;以後皆簡稱為PECVD)技術沉 積一氮化矽層，其厚度在500至3〇〇〇A之間。接著利用 傳統的微影和非等向反應性離子蚀刻技術，以％為反應 氣體來勤m氮切層，翻C|2献應氣體來侧複晶 石夕層’以形成具氮化㈣蓋433的_結構。接著以氧 氣電漿灰化法和濕式去光阻法剝除掉用以定義閑極結構的 光阻。此外，若欲得到電阻較低的間極導電層432，亦可 在所述複晶矽層上沉積一層矽化金屬層（snidde 本紙張尺度適用中國(c^s)从胁（别处97公缝1-- 陷4 3 9 2 2 1 A7 — B7 五、發明説明（1 )A7 -_B7 V. Invention ^ " The present invention uses: 1) no thick doping at the node B, 2) using a silicon nitride layer as an etching protection layer for opening the polycrystalline silicon plug window, etc .: each method can reduce the node B The leakage current increases the time that the word line controlled by the I-type π circuit can maintain a high potential. The present invention uses both & in the process of the word line driving circuit to 'more multiply effect', so that the time for which the word line maintains a high potential is greatly improved, and the reading and writing actions of the 5th memory body can be ensured. Correctness and reliability. Brief description of the figure: Figure 1 is a schematic circuit diagram of a DRAM memory cell connecting bit lines and word lines. Figure 2 shows a circuit diagram of a word line driving circuit commonly used in the industry. FIG. 3 is a schematic cross-sectional view of forming a P-type well region, insulating isolation, and a lightly doped source / drain region on a semiconductor substrate according to an embodiment of the present invention. Fig. 4 is a schematic cross-sectional view of a dielectric spacer formed in an embodiment of the present invention. FIG. 5 is a schematic cross-sectional view of forming a heavily doped drain region in an embodiment of the present invention. FIG. 6 is a schematic cross-sectional view of a silicon nitride layer and a first silicon oxide layer deposited in an embodiment of the present invention. FIG. 7 is a cross-sectional view showing that a plug window is opened on the first siliconized silicon layer by using conventional lithography and anisotropic etching techniques in the embodiment of the present invention. The paper scale is applicable to the Chinese national standard (qis) A4. Specifications (210 # 297mm) (Please read the note on the back before filling in this page.) .Π Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of invention (heart). (Please read the precautions on the back before filling out this page.) Figure 8 is a schematic cross-sectional view of removing the nitrided nitride layer located in the plug window using the wet shaft technology in the embodiment of the present invention. Fig. 9 is a schematic cross-sectional view of forming a first polycrystalline silicon plug in the plug window according to an embodiment of the present invention. Fig. 10 is a schematic cross-sectional view showing the formation of a second polycrystalline spar plug and an interconnect in the region in the embodiment of the present invention. Description of drawing number 1〇_ DRAM memory cell 11- MOS transistor 111-M0S transistor gate 112- MOS transistor source 113-MOS transistor drain 12- capacitor 13-word line 14-bit Line 15-Word line driving circuit 31-First transistor 311-Drain of first transistor 312-Gate of first transistor 313-Source of first transistor 32-Second transistor 321- The second transistor 322-the first transistor 323-the second transistor 33-the third transistor 331 _ the third transistor's drain 332-the third transistor's gate 333- Source of the third transistor 40-Semiconductor substrate 41-P-well region 42-Insulation 43-Gate structure 431-Gate dielectric layer 432-Gate conductive layer 433-Silicon nitride cap 44-Light Doped source / non-polar area This paper size is applicable to China National Standards (CNS) A4 specification (210 殳 297 mm) 46- Dielectric bulkhead 48- Concentrated dopant 50-Nitride layer 52 -Photoresistor 54-first polycrystalline silicon plug 56-brother-one polycrystalline broken plug A7 _____ B7 V. Description of the invention (,) 45-arsenic or phosphorus ion 47-photoresist 49-arsenic or phosphorus ion 51- the first Chemical layer 53-plug window 55-second silicon oxide layer 57-area connection ^ Invention is a PN of the step-up node formed by a method of step-up of a ribbon-shaped circuit on a semiconductor board The interface has low leakage, high current, and high breakdown voltage. The number of bursts must be paid by Li Shaye or Ziyuan to maintain the two potentials for a sufficient time. The present invention can be applied to dynamic random access memory buttons, miscellaneous county memory buttons, and character line drive circuits of any type of memory. In addition, 'in order to avoid the description being too long and the illustration too complicated, the description of the embodiment and the illustration will focus on the process steps and structure of manufacturing the boost node (ie node 巳 in the background description), and The transistor system shown in FIG. 3 to FIG. 10 illustrates the first transistor 31 in FIG. 2, and the boost node (node B) is located at its source. Refer to FIG. 3 'Firstly, a conventional standard lithography and ion implantation process is used to form a P-type well region 41 on a semiconductor substrate 40, and then a conventional technique is used to form an insulation isolation 42' and thus define an active device region . The insulation isolation 42 may be a traditional local silicon oxide layer (LOCOS) or a shallow trench isolation (Shallow Trench Isolation), and its function is to apply each paper size to the Chinese national standard (CNS> A4 specification ( 210 > g297 mm) '!' (Please read the precautions on the back before filling out this page]. Packing. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 ____B7______ V. Description of Invention (f) I ---- Γ --- install II-f (please read the precautions on the back before filling out this page) An active device area is isolated. Then, the gate structure 43 of the metal-oxide half field-effect transistor is formed by the conventional process technology. The gate dielectric layer (Gate Dielectric) 431, the gate conductive layer 432, and the silicon nitride cap (Nitride Cap) 433. The gate dielectric layer 431 is a thermal oxidation method (Thermal Oxidation). The formed silicon oxide layer has a thickness of 30 to 80 Å. Before or after the gate dielectric layer 41 is formed, an ion implantation process (not shown in the figure) is usually added to start the voltage adjustment. The gate conductive layer 432 is deposited by low pressure chemical vapor deposition (10w Pressure Chemical Vapor Deposition; hereafter referred to as LPCVD) or other chemical vapor deposition methods printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs to form a layer of polycrystalline silicon layer with a thickness of 800 to 4000 people There are two methods for doping the polycrystalline silicon layer, one of which is doped with scale or scale into the reactive gas Sine Lan, so that thorium or phosphorus is simultaneously deposited with the broken; The method is to deposit an intrinsic polycrystalline silicon layer, and then dope arsenic or phosphorus into the polycrystalline silicon layer by ion implantation technology. Then, LPCVD or plasma enhanced chemical vapor deposition method Enhanced Chemica 丨 Vapor Deposition; hereafter abbreviated as PECVD) technology to deposit a silicon nitride layer with a thickness between 500 and 3000 A. Then use the traditional lithography and anisotropic reactive ion etching technology, with% as the reactive gas Laiqin m nitrogen-cutting layer, flipping C | 2 donating gas to the side of the polycrystalline spar layer to form a structure with a nitrided lid 433. Then stripping with oxygen plasma ashing method and wet photoresist removal method Remove the photoresistor that defines the structure of the idler electrode. In addition, if you want to get the resistance Low interpolar conductive layer 432, or a layer of silicidated metal can be deposited on the polycrystalline silicon layer 2 1 A7 — B7 V. Description of the invention (1)
Layer) 〇 接下來請繼續參考圖三，在主動元件區形成N型摻雜 之淡摻雜源極/汲極區44 (NLDD)。所述淡摻雜源極/汲 極區44，係以能量介於20至80 KeV的砷或磷離子45進 行離子佈植所形成，其摻雜濃度介於1E12到5E13原子/ 平方公分之間。所述淡摻雜源極/汲極區44的作用是減低 熱電子效應(Hot曰ectron Effect)。 接下來請參考圖四，在所述閘極結構的側壁形成介電 質間隙壁46(Dielectric Spacer)。所述介電質間隙壁46的 製程，是先用LPCVD或是PECVD技術形成一層厚度介 於1000至3000人的氮化矽層’再以Cf4做為反應氣體藉 由非等向反應性離子蝕刻法進行回蝕刻而成。此時所述閘 極結構已整個被氮化矽所包覆，包括其氮化矽頂蓋433和 其側壁的介電質間隙壁46，以利後續自動對準接觸窗 (Self-aiigned Contact)製程的進行。當然本發明亦可選擇 非自動對準接觸窗的製程，則介電質間隙壁選用氮化矽或 氡化矽皆可，而上述氮化矽頂蓋433也非必須。 經濟部智慧財產局員工消費合作社印製 接下來請參相五’在絲元件_成濃摻衡及極區 奶。特別重要的是，在對所述第一電晶體（亦即圖 3 31 )進行源極/汲極之離子佈猶，僅針^ 二Γ對源極和汲極都進行佈植的製程 二 摻雜汲極區48的师^ 佈 層先阻47 ’利用微影技術保留覆蓋在源極上 ，以做為後續離子佈植時的保護層。接下來進行離子 本紙張尺家轉（〒 經濟部智慧財產局員工消費合作杜印製 腿43922彳 A7 _______B7 五、發明説明（丨〇 ) 植’以能量介於30至100 KeV的砷或磷離子49進行離子 佈植形成濃摻雜ϊ：及極區48，其摻雜濃度介於1E14到 5E16原子/平方公分之間。 此步驟係本發明之重點所在。有別於習知技藝對源極 和汲極都進行佈植，本發明僅針對汲極進行離子佈植，而 對節點B所在的源極則以光阻47做為保護層而不進行離 子佈植。此舉的原因在於’以理論上說，一個PN接面的 崩潰電壓(Breakdown Vo丨tage)與其離子摻雜濃度成反比; 在實際所形成的元件上，崩潰電壓則約略與與其離子摻雜 ?辰度的二分之一次方成反比（請詳見Richard S. Muller &Theodo「e 丨_ Kamins 所著 Device Electronics ForLayer) 〇 Next, please continue to refer to FIG. 3 to form an N-doped lightly doped source / drain region 44 (NLDD) in the active device region. The lightly doped source / drain region 44 is formed by ion implantation with arsenic or phosphorus ions 45 having an energy between 20 and 80 KeV, and its doping concentration is between 1E12 and 5E13 atoms / cm 2. . The role of the lightly doped source / drain region 44 is to reduce the hot electron effect. Next, referring to FIG. 4, a dielectric spacer 46 (Dielectric Spacer) is formed on a sidewall of the gate structure. In the process of forming the dielectric spacer 46, a silicon nitride layer having a thickness of 1,000 to 3,000 people is first formed by using LPCVD or PECVD technology, and then Cf4 is used as a reactive gas for etching by anisotropic reactive ions It is etched back. At this point, the gate structure has been completely covered with silicon nitride, including its silicon nitride top cover 433 and the dielectric spacer 46 on its side wall to facilitate subsequent automatic alignment of the self-aiigned contact. The progress of the process. Of course, the present invention can also choose a process of non-automatically aligning the contact window. The dielectric spacers can be made of silicon nitride or silicon halide, and the silicon nitride top cover 433 is not necessary. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. It is particularly important that during the source / drain ion implantation of the first transistor (ie, FIG. 3 31), only the process of implanting both the source and the drain is performed. The first layer of the miscellaneous drain region 48 is the first resist layer 47 '. The lithography technique is used to retain the source electrode, which serves as a protective layer for subsequent ion implantation. Next, transfer the paper ruler (〒 The consumer cooperation of the Intellectual Property Bureau of the Ministry of Economic Affairs Du printed leg 43922 彳 A7 _______B7 V. Description of the invention (丨 〇) Plant arsenic or phosphorus ions with an energy between 30 and 100 KeV 49 ion implantation to form heavily doped ytterbium: and polar region 48, whose doping concentration is between 1E14 to 5E16 atoms / cm 2. This step is the focus of the present invention. It is different from the conventional technique for the source. Both the drain and the drain are implanted. The present invention only performs ion implantation for the drain, and the source where the node B is located uses photoresist 47 as a protective layer without ion implantation. The reason for this is that Theoretically, the breakdown voltage (Breakdown Votage) of a PN junction is inversely proportional to its ion doping concentration; on the actual formed element, the breakdown voltage is about one-half the degree of doping with its ions. The power is inversely proportional (see Richard S. Muller & Theodo "e 丨 _ Kamins Device Electronics For
Integrated Circuits-Second Edition 一書中第 197 頁之說明 以及第198頁之圖4.13所示）。因此本發明在節點β處 不开>成濃#雜之源極的離子佈植’〒提高該處PN接面之 崩潰電壓’也因此減低該接漏電疏，提高由勒:帶式電 路所控制的字元線得以維持高電位的時間。 接下來請參考圖六，首先將光阻47去除之後，再陸 續沉積一層氮化矽層50及一層第一氧化矽層51。所述氮 化矽層50係利用LPCVD或是PECVD技術所形成，其厚 度介於200至Ί500Α之間。所述第一氧化石夕層5<|係做為 層間介電層’其厚度介於2000至8000A之間，後續將形 成一穿透该第一氧化矽層51的複晶矽插塞(p〇丨ysj|jc〇n P丨ug)。所述氮化石夕層50亦可以氮氧化矽層（〇xynitride Layer)來取代。 本紙張尺度適用中國國家標率（> Μ規格（210)}^97公楚） -----—r ^^ - 、1T (請先閲讀背面之注$項再填^本頁)The Integrated Circuits-Second Edition book is described on page 197 and shown in Figure 4.13 on page 198). Therefore, the present invention does not open at the node β > 成 浓 # impurity source ion implantation 'increasing the breakdown voltage of the PN junction there, thereby reducing the leakage current, and improving the by-pass: The controlled word line is maintained at a high potential for a time. Please refer to FIG. 6. After removing the photoresist 47, a silicon nitride layer 50 and a first silicon oxide layer 51 are successively deposited. The silicon nitride layer 50 is formed by using LPCVD or PECVD technology, and has a thickness between 200 and 500 A. The first oxide layer 5 < | is used as an interlayer dielectric layer, and its thickness is between 2000 and 8000 A. A polycrystalline silicon plug (p) penetrating the first silicon oxide layer 51 will be formed subsequently (p 〇 ysj | jcon P ugug). The nitride nitride layer 50 may be replaced by a silicon oxynitride layer. This paper size is applicable to China's national standard (> M specification (210)} ^ 97gongchu) -----— r ^^-, 1T (please read the note $ on the back and fill in ^ page)
五、發明説明（"） ~~ 接下來請參考圖七，首先塗伟上-層光阻52 ’再利用 傳統的微雜_向性_技術，在所述第-氧化砂層Η 上開啟插塞固π 53。所述非均向性银刻技術係屬於離子 侧’因有氮化發層50做為银刻保護層，因此不會 點B所在的半導體基板40造成損害。 接^來請參考圖八’利用濕餘刻技術將位於插塞窗口 I 53内的氮化砍層5〇去除。所述濕银刻係利用力。熱的鱗酸 來進行’紐點是可以達職高之氮鮮職切的飯刻 選擇比’並且不會對半導體基板4G造成财，因此可二 降低節點B的漏電流’提高由W式電路所控制的字元線 得以維持高電位的時間。 ' 由上述圖五至圖八的描述可知，本發明運用：1)在 節點B處不進行錄雜' 2) ·—層氮化妙層以做為開 啟複晶矽插塞窗口的蝕刻保謹層等兩種方法，其分別都可 以降低節點B的漏電流，提高由每帶式霞政所控制的字元 線得以維持高纽⑽間。本發縣兩者转用在字元線 驅動電路的製程上，更可發揮相乘的功效’使字元線維持 面電位的時間大幅提高，可以確保記憶體讀和寫的動 正確性和可靠度。 接下來請參考圖九，在所述插塞窗口 53内形成第一 複晶石夕插塞(P_icon P_54。形成所述第一複晶石夕插 塞54 ’，以LPCVD形成-複晶石夕屬，其厚度介於聊 至6000A之間。所述複晶矽層的摻雜有兩種方法，1中之 -係以碎_摻人反應鍾梦財，料或磷射同步沉 本紙張尺皮適用中國國家襟準（，）A4規格2耐297公釐} - (諳先閲讀背面之注意事項再填寫本頁) 裝. 訂 經濟部智慧財產局員工消費合作社印製 A7 ^-——_67 — 五 '發明説明（丨>) 另—方法係先沉積一本質複晶矽層，再以離子佈植的 技術將坤或磷播雜入該複晶。再來以CMp技術進行 一化製％，將位於第一氧化矽層51上方的複晶矽層磨 去’以形成第一複晶矽插塞54。 接下來請參考圖十’形成第二複晶矽插塞56和區域 内，線(Local |nterconnection)57，以將節點B連接至第二 電晶體的閘極（未顯示在圖上，請參見圖二之電路圖）。 首先形成一層第二氧化矽層55,並在該第二氧化矽層55 開啟一個插塞窗口。接著以LPCVD形成一複晶矽層，其 厚度介於2000至5000A之間，目的在於將該插塞窗口填 滿。該複晶矽層的摻雜係採用同步摻雜，在沉積複晶矽的 同時在矽烷環境中加入砷或磷而得。接下來使用CMP技 =將第二氧化矽層55表面上的複晶矽層磨去，而在插塞 岛口形成第二複晶石夕插塞56。第二複晶石夕插塞56係位於 第一複晶矽插塞54的上方，並連接第一複晶矽插塞54。 接下來再形成一層摻雜的複晶矽層或矽化金屬層，利用習 知的微影與蝕刻步騍形成區域内連線57。另，本發明實施 例中的苐一複晶妙插塞54和第二複晶石夕插塞56亦可以金 屬插塞來取代。本發明所述形成靴帶式電路之升壓節點的 方法於焉完成。 以上實施例係將本發明之技術應用在以N型金氧半場 效電晶體做為靴帶式電路元件的製作。當然本發明亦可運 用在以N型金氧半場效電晶體做為靴帶式電路元件的製作 上’僅要將上述實施例中的p和N對調即可，為免說明書 本紙張尺度適用中國國家榡準（)入4規格（210i3297公釐） (請先閱讀背面之注意事項再填寫本頁) ο1 裝· -訂 陷4392 2 j A7 B7 五、發明説明（"） 過於冗長不再贅述。 以上所述係利用較佳實施例詳細m明本發明，而非限 本發明的範園’而且熟知此技藝的人士亦能明瞭，適當 而作些微的改變與調整，仍將不失本發明之要義所在，亦 不脫離本發明之精神和範圍。 經濟部智慧財產局員工消費合作社印製 C (請先聞讀背面之注意事項再填寫本頁)V. Description of the invention (~) Please refer to Figure VII below. First, apply the upper Wei-layer photoresist 52 'and then use the traditional micro-heterotropic_orientation technique to open the plug on the first oxide sand layer Η.塞 固 π53. The anisotropic silver engraving technique belongs to the ion side. Since the nitrided hair layer 50 is used as the protective layer for the silver engraving, the semiconductor substrate 40 at the point B is not damaged. Next, please refer to FIG. 8 'using a wet-etching technique to remove the nitride cutting layer 50 located in the plug window I53. The wet silver engraving uses force. The hot glutamic acid is used to carry out the "knot point is the choice ratio of nitrogen that can reach the high-level nitrogen cutting position" and does not cause wealth to the semiconductor substrate 4G. Therefore, the leakage current at the node B can be reduced, and the W-type circuit can be improved. The time during which the controlled word line is maintained at a high potential. 'From the above description of Fig. 5 to Fig. 8, it can be known that the present invention uses: 1) no impurity recording is performed at the node B' 2)-a layer of nitrided nitride is used as an etching guarantee to open the polycrystalline silicon plug window Two methods, such as layer, can reduce the leakage current of node B and increase the word line controlled by each band Xiazheng. The two states of the county are transferred to the manufacturing process of the word line drive circuit, which can play a multiplier effect. 'The time for the word line to maintain the surface potential is greatly improved, which can ensure the correctness and reliability of the reading and writing of the memory. degree. Next, referring to FIG. 9, a first polycrystalline stone plug (P_icon P_54 is formed in the plug window 53. The first polycrystalline stone plug 54 ′ is formed to form a polycrystalline stone by LPCVD. The thickness of the metal is between 6000 and 6000A. There are two methods for doping the polycrystalline silicon layer, one of which is to use the broken _ doped reaction Zhong Mengcai, material or phosphorous to simultaneously sink the paper ruler. China National Standard (,) A4 size 2 resistant to 297 mm}-(谙 Read the precautions on the back before filling out this page) Pack. Order A7 printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ -——_ 67 — 5 'Explanation of the invention (丨 >) Another method is to first deposit an intrinsic polycrystalline silicon layer, and then implant Kun or phosphorus into the compound by ion implantation technology. Then use CMP technology to perform chemical conversion. The polycrystalline silicon layer above the first silicon oxide layer 51 is ground away to form a first polycrystalline silicon plug 54. Next, please refer to FIG. 10 to form a second polycrystalline silicon plug 56 and the area, the line ( Local | nterconnection) 57 to connect Node B to the gate of the second transistor (not shown on the figure, see Figure 2 for power Figure). First, a second silicon oxide layer 55 is formed, and a plug window is opened in the second silicon oxide layer 55. Then, a polycrystalline silicon layer is formed by LPCVD with a thickness between 2000 and 5000A, the purpose is to Fill the plug window. The doped system of the polycrystalline silicon layer is synchronously doped, and is obtained by adding arsenic or phosphorus in a silane environment while depositing the polycrystalline silicon. The next step is to use the CMP technique = second oxidation The polycrystalline silicon layer on the surface of the silicon layer 55 is polished away, and a second polycrystalline silicon plug 56 is formed at the island of the plug. The second polycrystalline silicon plug 56 is located on the first polycrystalline silicon plug 54. Above, and is connected to the first polycrystalline silicon plug 54. Next, a doped polycrystalline silicon layer or a silicided metal layer is formed, and the area interconnect 57 is formed by the conventional lithography and etching steps. In the embodiment of the present invention, the first and second polycrystalline plugs 54 and 56 can also be replaced by metal plugs. The method for forming a boost node of a shoelaced circuit according to the present invention is completed in 焉. The above embodiments apply the technology of the present invention to an N-type metal-oxide half-field-effect transistor as a shoelaced type. Production of circuit components. Of course, the present invention can also be used to make N-type metal-oxide-semiconductor field-effect transistors as shoe-laced circuit components. The size of this paper is applicable to China's national standard (4) (210i3297 mm) (Please read the precautions on the back before filling out this page) ο1 Packing · -Setting 4392 2 j A7 B7 V. Description of the invention (") It is too verbose to repeat it. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention ', and those skilled in the art will also understand that appropriate changes and adjustments will be made. Without departing from the spirit of the invention, and without departing from the spirit and scope of the invention. Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs (Please read the notes on the back before filling out this page)
適 度 ^ i張 氏 β 準 標 I家 國 Μ I釐 公Moderate ^ i Zhang's β quasi standard I country M I centimeter