TW436923B - Method and apparatus for etch rate stabilization - Google Patents

Method and apparatus for etch rate stabilization Download PDF

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Publication number
TW436923B
TW436923B TW88121794A TW88121794A TW436923B TW 436923 B TW436923 B TW 436923B TW 88121794 A TW88121794 A TW 88121794A TW 88121794 A TW88121794 A TW 88121794A TW 436923 B TW436923 B TW 436923B
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Taiwan
Prior art keywords
etching
chamber
substrate
gas
flow rate
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TW88121794A
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Chinese (zh)
Inventor
Norman Williams
Scott K Baldwin Jr
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Lam Res Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32917Plasma diagnostics
    • H01J37/32935Monitoring and controlling tubes by information coming from the object and/or discharge
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32009Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
    • H01J37/32082Radio frequency generated discharge
    • H01J37/321Radio frequency generated discharge the radio frequency energy being inductively coupled to the plasma
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J37/00Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
    • H01J37/32Gas-filled discharge tubes
    • H01J37/32431Constructional details of the reactor
    • H01J37/32733Means for moving the material to be treated
    • H01J37/32743Means for moving the material to be treated for introducing the material into processing chamber
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/18Vacuum control means
    • H01J2237/182Obtaining or maintaining desired pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J2237/00Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
    • H01J2237/18Vacuum control means
    • H01J2237/186Valves

Abstract

A method of consecutively processing a series of semiconductor substrates with minimal etch rate variation. The method includes steps of (a) placing a semicondcutor substrate on a substrate support in a plasma etching chamber, (b) maintaining a vacuum in the chamber, (c) etching an exposed surface of the substrate by supplying an etching gas to the chamber and energizing the etching gas to form a plasma in the chamber, (d) removing the substrate from the chamber; and (e) consecutively etching additional substrates in the chamber by repeating steps (a-d), the etching step being carried out by maintaining an amount of reactive gas in contact with an exposed surface of the substrate at a level sufficient to obtain a repeatable rate of etching for each of the substrates processed during repeated step (c). An apparatus useful for carrying out the method includes a plasma etching chamber having a substrate support in an interior thereof and a dielectric member facing the substrate support, a gas supply supplying etching gas into the interior of the chamber, an antenna passing RF energy through the dielectric member, a vacuum pump separated from the interior of the chamber by an adjustable gate valve, and a controller maintaining an anount of reactive gas in contact with an exposed surface of the substrate at a level sufficient to obtain a repeatable rate of etching for each substrate processed in the chamber during consecutive single substrate etching of batch of substrates.

Description

經濟部智慧財產局員工消費合作社印製 43692 34. A7 ___B7_____ 五、發明說明(1 ) 發明範疇 本發明與電漿處理室中的改良處有關,也與基體(如半 導體晶圓)上的電漿蝕刻金屬、多晶矽或電介質層的方 有關。 發明背景 %漿處理系統,其中天線耦合到射頻(RF)源並使氣體通 電進入處理至中的電漿狀態,已揭示於美國專利案號 4,948,458 ; 5,198,718 ; 5,241,245 ; 5,304,279 : 5,401,350 ; ^ 5,571,366。於該等系統中,天線位於處理室的外部且提供 傳遞能量給RF通過電介質牆或窗進入處理室中。此等處 理系統可運用於各種半導體處理應用如蝕刻、淤積、抗剥 離等等。g此等系統用於電漿蚀刻一批連續處理的半導體 基體時,蝕刻率可能於蝕刻該批基體過程中產生變化。蝕 刻率的此等變動是不理想的,因爲已蝕刻進基體的特徵可 能會落在可接受的產品參數範圍外。 因此,有必要於電漿處理室及電漿蝕刻方法的技藝中, 使連續處理的半導體基體可使用控制更佳的蝕刻率來處 理。 發明總結 本發明提供一種以最低蝕刻率變動來連續處理連串半導 體基體的方法。該方法包括數種步驟:(a)於電漿妙刻室 中’將半導體基體放在基體支撑上;(b)保持蝕刻室的眞 芝;(c)藉由將蚀刻氣禮供應到姑刻室及使蚀刻氣體通電以 岭蚀刻室中形成電漿的方式處理基體;(d)將基體從蚀刻 I:-------------------訂-----I-- (請先閱讀背面之注意事項再填寫本頁) -4 -Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 43692 34. A7 ___B7_____ V. Description of the invention (1) The scope of the invention The invention relates to the improvement in the plasma processing chamber, and also to the plasma on the substrate (such as a semiconductor wafer) Etching metal, polycrystalline silicon, or dielectric layers. BACKGROUND OF THE INVENTION A plasma processing system in which an antenna is coupled to a radio frequency (RF) source and energizes a gas into a plasma state being processed is disclosed in U.S. Patent Nos. 4,948,458; 5,198,718; 5,241,245; 5,304,279: 5,401,350; ^ 5,571,366 . In these systems, the antenna is located outside the processing chamber and provides the transfer energy to the RF into the processing chamber through a dielectric wall or window. These processing systems can be used in a variety of semiconductor processing applications such as etching, deposition, peel resistance, and more. g When these systems are used to plasma etch a batch of semiconductor substrates that are continuously processed, the etch rate may change during the etching of the batch of substrates. These variations in etch rate are not ideal because features that have been etched into the substrate may fall outside acceptable product parameter ranges. Therefore, it is necessary to use a technique of a plasma processing chamber and a plasma etching method so that a semiconductor substrate that is continuously processed can be processed with a better controlled etching rate. Summary of the Invention The present invention provides a method for continuously processing a series of semiconductor substrates with a minimum change in etching rate. The method includes several steps: (a) 'putting a semiconductor substrate on a substrate support in a plasma etching chamber; (b) holding a chitin in an etching chamber; (c) supplying an etching gas to an engraving Chamber and energize the etching gas to process the substrate in the manner of forming a plasma in the ridge etching chamber; (d) removing the substrate from the etching --- I-- (Please read the notes on the back before filling this page) -4-

經濟部智慧財產局員工消費合作社印製 4 3咖 34 λζ »· I----------B7____ 五、發明說明(2 ) 室移除:以及(e)重複步驟(a_d)於蝕刻室中連續處理額外的 基體,其中處理步驟的實施係藉由保持某數量的活性氣體 接觸基體的暴露面争個基體獲 得可重複的姓刻率的程度。 根據本發明的一項較佳特點,半導體基體可包括多晶矽 層,其中多晶矽是在步驟(c)中及蝕刻室於步驟(c)中維持 在低於100 mTorr的眞空壓力下,以HBr及Cl2蚀刻。較佳的 疋’蚀刻皇係利用眞空菜浦形成眞空,其中眞空系浦係藉 由調整閘閥而與蝕刻室内部分開,而調整閘閥在步驟(c)中 會保持在固定位置。在步驟(c)中,RF偏頻可由基體支撑 施加到基體上及/或當重複步驟(c)時,蚀刻氣體的至少— 個組成的流率會增加。例如,在步驟(c)中,蝕刻室内部的 蝕刻氣體的至少一個组成的流率可被調整保持在固定壓力 及/或在步驟(c)中’蚀刻氣體的至少一個組成的流率可根 據蚀刻室内部的一個或多個物質的即時分析來調整。 在較佳的具體實施例中,鉋工或非鉋工天線會使蝕刻氣 體通電進入電紫狀態,其中天線由電介質部件與蚀刻室内 部分開’電介質部件至少會與基體支撑共同擴張,而基體 支撑具有約600 pF或以下的接地電容。更佳的是,電介質 部件包括聚四氟乙烯塗層面向基體支律,而基體支撑具有 約200 pF或以下的接地電容。Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 3 coffee 34 λζ »· I ---------- B7____ V. Description of the Invention (2) Room removal: and (e) Repeat steps (a_d) in The additional substrate is continuously processed in the etching chamber, wherein the processing step is performed by maintaining a certain amount of reactive gas in contact with the exposed surface of the substrate to obtain a repeatable degree of survivability of the substrate. According to a preferred feature of the present invention, the semiconductor substrate may include a polycrystalline silicon layer, wherein the polycrystalline silicon is maintained in the step (c) and the etching chamber in the step (c) under a hollow pressure of less than 100 mTorr with HBr and Cl2 Etching. The better 疋 'etching line uses 眞 empty Caipu to form emptiness, wherein the 眞 empty system is opened from the etching chamber part by adjusting the gate valve, and the adjusting gate valve will be kept in a fixed position in step (c). In step (c), the RF offset frequency may be applied to the substrate by the substrate support and / or when step (c) is repeated, the flow rate of at least one composition of the etching gas may increase. For example, in step (c), the flow rate of at least one composition of the etching gas inside the etching chamber may be adjusted to be maintained at a fixed pressure and / or the flow rate of at least one composition of the etching gas in step (c) may be based on Real-time analysis of one or more substances inside the etch chamber to adjust. In a preferred embodiment, the planer or non-planer antenna will energize the etching gas into the electric purple state, wherein the antenna is partially opened by the dielectric member and the etching chamber. The dielectric member will at least co-expand with the substrate support, and the substrate support Has a ground capacitance of approximately 600 pF or less. Even better, the dielectric part includes a Teflon coating facing the substrate support, and the substrate support has a ground capacitance of about 200 pF or less.

本發明也提供一種電漿蝕刻裝置,包括處理室,其内部 有基質-專-#面-向基.體支罈、氣體供應用於將 -杜'妹给—直— 理-..室主報.」.....天-線.1殄#埤能量终RF -5- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) — — — — — — — — — - JIJ — ΙΪΙ -------1 f請先閱讀背面之注意事項再填寫本頁) A7 43 692 3 4 B7___ 五、發明說明(3 ) 通過電介質部件並使蝕刻氣體通電進入電漿狀態、眞空泵 浦部眞空並使用調整閘閥與4理室—内可隱 離、以及控制器用以保持某一數量的活性氣體接觸基體暴 露面於足以使連續單一基體蝕刻一批基體時處理室所處理 的每個基體獲得可重複的蚀刻率的程度。 根據本裝置的較佳具體實施例,控制器會連續調整蝕刻 氣體的至少一個组成的處理室内部流率及/或控制器會在 處理室内處理每個基體蝕刻時使閘閥保持在固定位置。基 體支撑可包括電極用提供RF偏頻,而控制器會在連續單 一基體蝕刻一批基體時隨之調整至每個基體的RF偏頻。 例如,控制器可調整蝕刻氣體的一個或一個以上的组成的 流率爲比先前基體群爲高的流率以用於後來的基體群。 根據本發明的一個較佳具體實施例,控制器會調整蚀刻 氣體的一個或一個以上的組成的流率,以於基體蝕刻期間 提供處理室内部固走的眞空壓力。例如,控制器可根據基 體蚀刻期間處理室内部的一個或多個活性物質的即時分析 來賙整蚀刻氣體的一個或多個組成的流率。在蚀刻具有多 晶矽層的個別基體時,其中多晶矽層係由以可調整的流率 供應至處理室内部的HBr及Cl2所蝕刻,控制器可控制眞空 泵浦保持固定的泵送速度,控制閘閥保持固定位置、控制 氣體供應保持HBr流率於恆定速率' 以及控制氣體供應改 變足量的(:12流率以補償蝕刻氣體的活定物質對處理室内 部牆壁的吸附作用。 圖式簡軍説明 -6 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 x 297公釐) -1-----------裝-------- 訂----------線 I (諝先r讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消费合作社印製 3 6 ·9 2 參.5 ’ Α7 -------Β7____ 五、發明說明(4 ) 本發明將參照所附圖式以更詳細地説明之,其中: 圖1表示用於實施本發明之方法的電漿蝕刻室簡要截面 視圖; 圖2爲關於電漿蝕刻室内處理連串1 8個晶圓調整閘閥位 置與晶圓數量之關係圖; 圖3爲於LAM 9400SETM電漿蝕刻室操作壓力10 mTorr、 天線功率 350瓦、夾盤 1〇〇 瓦、ci2 20 seem、HBr 100 seem 以 及卡盤溫度60°C下蝕刻多晶矽過程中,端點信號與時間之 關係圖。 圖4爲LAM 9400TM處理室配置相較於lam 9600TM處理室 配置之效率與負荷阻力之關係圖; 圖5爲處理連串1 2個晶圓期間<:12流率與晶圓數量的關係 圖; 圖6爲處理室内部操作壓力1〇 mTorr、天線350瓦功率、 卡盤100瓦、Cl;;變動流率與HBr 100 seem下蝕刻多晶矽時, 多晶硬蚀刻率與Cl2流率之關係圖; 圖7爲處理連串12個晶圓時,其中HBr與Cl2之總量會以 HBr與Cl;j之固定5:1的比率而改變,電壓 '功率及HBr與ci2 之流率與晶圓數量之關係圖; 圖8爲以比例5:1供應變動流率之HBr&ci2蝕刻多晶矽 時,多晶矽蝕刻率與晶圓數量之關係圖。 圖9爲處理連串12個晶圓時,其中ci2保持固定流率2〇 seem而Hbr流率爲變動,電壓、功率及HBr與Cl2之流率與晶 圓數量之關係圖; 本紙張又度適用中國國家標翠(CNS)A4規格(21〇 X 297公爱) I I I I---^ i ! i ---^---— II---^ I (請先閱璜背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明(5 ) 圖1 〇爲以HBr變動流率而Cl2保持固定流率20 seem蝕刻 多晶碎時,多晶矽蝕刻率與晶圓數量之關係圖; 圖1 1爲處理連串1 2個晶圓時,其中Cl2流率變動而HBr 固定流率100 sCCIn,電壓、功率及HBr與Cl2之流率與晶圓 數量之關係圖; 圖1 2爲以ci2變動流率而HBr固定流率1〇〇 seem蝕刻多晶 碎時’多晶矽蝕刻率與晶圓數量之關係圖; 圖1 3爲處理連串i 2個晶圓時,其中在cl2流率爲變動而 HBr固疋流率100 seem且菜送速度増加,電壓、功率、及 HBr與Cl2流率與晶圓數量之關係圖: 圖1 4爲以ci2變動流率、HBr固定流率1〇〇 seem且泵送速 度增加之下蝕刻多晶矽時,多晶矽蝕刻率與晶圓數量之關 係圖; 圖1 5爲處理連串1 2個晶圓時’其中Cl2流率變動而HBr 不供應給處理室,電壓、功率、及ci2流率與晶圓數量之 關係圖; 圖1 6爲以變動Cl2且無HBr蝕刻多晶梦時,多晶矽蝕刻率 與晶圓數量之關係圖; 圖1 7爲處理矽調節晶圓時,其中Cl2流率變動、HBr固定 流率100 seem且泵送速度增加,室壓與氣氣流率與時間之 關係圖; 圖1 8爲處理光敏抗蚀劑塗層晶圓時,其令ci2流率變 動、HBr流率固定在1〇〇 sccm且泵送速度增加,室壓及氣 氣流率與時間之關係圖; -8- 本紙張尺度適用中國國家標準(CNS)A4規格(210x297公《 ) ,I ------------ I II (請先f讀背面之注意事項再填寫本頁) 訂------.——線 經濟部智慧財產局員工消費合作杜印製 A7 B7 五、發明說明(β ) 圖1 9爲處理連串1 2個晶圓時,其中Cl2流率變動、HBr 流率固定在100 sccm且泵送速度增加,氣氣流率與晶圓數 量之關係圖; 圖20爲於處理室内部操作壓力1〇 mTorr、天線350瓦功 率、卡盤100瓦功率且Cl2 1〇〇 sccin下蚀刻裸矽晶圓時的光 學放射光譜(optical emission spectrum ; OES); 圖21爲於處理室内部操作壓力1〇 mT〇rr、天線350瓦功 率、卡盤100瓦功率且ΗΒγ 100 seem下蝕刻裸矽晶圓時的光 學放射光譜(optical emission spectrum ; OES);以及 圖22爲於處理室内部操作壓力1〇 mT〇rr、天線35〇瓦功 率、卡盤100瓦功率、ci2 20 seem且HBr 100 seem下姓刻多 碎塗層日日圓時的光學放射光譜(〇pHcai emission spectrum ; OES)。 較佳具體實施例之詳細説明 本發明提供一種改良的電漿處理反應器及電漿蝕刻方 法’能在蚀刻一批連續處理的半導體基體時提供更可重複 之結果。特別是在蚀刻一批半導體晶圓過程中,已經發現 轴刻率的變化可能有突然增加或減少高達3〇%的性質或有 發生達數小時的緩慢變化之性質。蝕刻率的改變似乎與電 漿姓刻室的歷史有關’且尤其是與先前已處理的基體類型 有關。 一種常運用來穩定膜片蝕刻率之方法是先處理25(或以 上)個假晶圓(dummy wafer)(純矽)後再處理眞正的產品晶 圓。雖然此技術確實在開始時有穩定的效果,但由於會處 -9- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------I 1 ί 1 ϊ Ϊ 11111--^ — — — — — — — — — (請先閱讀背面之注音ί事項再填寫本頁)The invention also provides a plasma etching device, including a processing chamber, which has a substrate-specific- # 面-向 基. Body support, gas supply for the -Du '妹 给-直-理-.. "........ Tian-line.1 殄 # 埤 能 终 RF -5- This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) — — — — — — — — — -JIJ — ΙΪΙ ------- 1 f Please read the notes on the back before filling in this page) A7 43 692 3 4 B7___ V. Description of the invention (3) Pass the dielectric part and energize the etching gas into the plasma state The emptying pump part is empty and the adjusting gate valve and the 4 chamber are used. The interior can be hidden, and the controller is used to keep a certain amount of active gas in contact with the exposed surface of the substrate, which is sufficient for the continuous single substrate to etch a batch of substrates. The degree to which each substrate obtains a repeatable etch rate. According to a preferred embodiment of the device, the controller continuously adjusts the flow rate inside the processing chamber of at least one composition of the etching gas and / or the controller keeps the gate valve in a fixed position while processing each substrate etching in the processing chamber. The substrate support can include electrodes that provide RF offset frequencies, and the controller adjusts to the RF offset frequency of each substrate as a single substrate is etched in succession. For example, the controller may adjust the flow rate of one or more components of the etching gas to be higher than the previous matrix group for later matrix groups. According to a preferred embodiment of the present invention, the controller adjusts the flow rate of one or more components of the etching gas to provide a hollowing-out pressure that is fixed inside the processing chamber during substrate etching. For example, the controller may trim the flow rate of one or more components of the etching gas based on the instant analysis of one or more active materials inside the processing chamber during substrate etching. When etching an individual substrate with a polycrystalline silicon layer, where the polycrystalline silicon layer is etched by HBr and Cl2 supplied to the interior of the processing chamber at an adjustable flow rate, the controller can control the aerial pump to maintain a fixed pumping speed and control the gate valve to maintain Fixed position, control gas supply to maintain HBr flow rate at a constant rate ', and control gas supply to change a sufficient amount (: 12 flow rate to compensate for the adsorption of living materials of the etching gas on the interior wall of the processing chamber. Schematic brief description- 6-This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) -1 --------------------------- Order ---- Line I (I read the precautions on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs Printed by the Employee Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 6 · 9 2 cf. 5 'Α7 ------- B7____ V. Description of the invention (4) The present invention will be described in more detail with reference to the attached drawings, in which: FIG. 1 shows a schematic cross-sectional view of a plasma etching chamber for implementing the method of the present invention. ; Figure 2 is a series of 18 wafer adjustment gate valves for plasma etching chamber processing The relationship between the number of wafers and the number of wafers; Figure 3 shows the operating pressure of 10 mTorr, antenna power of 350 watts, 100 watts of chuck, ci2 20 seem, HBr 100 seem, and chuck temperature of 60 ° C in the LAM 9400SETM plasma etching chamber. Figure 4 shows the relationship between the endpoint signal and time during the etching of polycrystalline silicon. Figure 4 shows the relationship between the efficiency and load resistance of the configuration of the LAM 9400TM processing chamber compared to the configuration of the lam 9600TM processing chamber. Figure 5 shows the processing of a series of 12 crystals. The relationship between the flow rate and the number of wafers during the circle period; Figure 6 is the operating pressure inside the processing chamber 10mTorr, the antenna 350 watts power, chuck 100 watts, Cl; the variable flow rate and HBr 100 seem to etch For polycrystalline silicon, the relationship between the polycrystalline hard etching rate and the flow rate of Cl2; Figure 7 shows the total amount of HBr and Cl2 when processing a series of 12 wafers with a fixed 5: 1 ratio of HBr and Cl; Relationship between voltage, power, flow rate of HBr and ci2 and number of wafers; Figure 8 shows the relationship between polysilicon etch rate and number of wafers when HBr & ci2 is used to etch polycrystalline silicon at a ratio of 5: 1 Figure 9 shows that ci2 remains fixed when processing a series of 12 wafers The rate is 20seem and the flow rate of Hbr varies, the voltage, power, and the relationship between the flow rate of HBr and Cl2 and the number of wafers; this paper is also applicable to China National Standard Cui (CNS) A4 specification (21〇X 297) ) III I --- ^ i! I --- ^ ---— II --- ^ I (Please read the precautions on the back of the page before filling out this page) Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs Α7 Β7 V. Description of the invention (5) Figure 10 is the relationship between the polysilicon etch rate and the number of wafers when polycrystalline silicon fragments are etched at a constant flow rate of HBr while Cl2 is maintained at 20 seem. Figure 1 1 is a processing series 1 2 For each wafer, the flow rate of Cl2 fluctuates and the fixed flow rate of HBr is 100 sCCIn. The relationship between voltage, power, and the flow rate of HBr and Cl2 and the number of wafers; The relationship between the etching rate of polycrystalline silicon and the number of wafers when the polycrystalline chip is etched at 100 mm. Figure 13 shows the variation in the flow rate of cl2 and the fixed flow rate of HBr at 100 seem when processing a series of i 2 wafers. And the food delivery speed increases, the voltage, power, and the relationship between the flow rate of HBr and Cl2 and the number of wafers: Figure 14 is a ci2 variable flow rate, HBr fixed The relationship between polycrystalline silicon etch rate and the number of wafers when polycrystalline silicon is etched at a rate of 100seem and the pumping speed is increased; Figure 15 is the processing of a series of 12 wafers, where the Cl2 flow rate changes and HBr is not supplied For the processing chamber, the relationship between voltage, power, and ci2 flow rate and the number of wafers; Figure 16 is the relationship between the polysilicon etching rate and the number of wafers when the polycrystalline dream is etched with varying Cl2 without HBr; Figure 1 7 The relationship between the flow rate of Cl2, the fixed flow rate of HBr at 100 seem, and the increase of pumping speed, and the relationship between chamber pressure and air flow rate and time when processing silicon-adjusted wafers; Figure 18 shows the processing of photoresist-coated crystals. When it is round, it makes the ci2 flow rate change, the HBr flow rate fixed at 100 sccm, and the pumping speed increases, and the relationship between the chamber pressure and air flow rate and time; -8- This paper size applies the Chinese National Standard (CNS) A4 specifications (210x297 male "", I ------------ I II (please read the precautions on the back before filling out this page) Order ------.---- Ministry of Economics Intellectual Property Bureau employee consumption cooperation Du printed A7 B7 V. Description of invention (β) Figure 19 shows the processing of a series of 12 wafers, of which Cl2 Rate change, HBr flow rate fixed at 100 sccm and pumping speed increased, the relationship between the air flow rate and the number of wafers; Figure 20 shows the operating pressure inside the processing chamber 10mTorr, the antenna 350 watts power, and the chuck 100 watts power And the optical emission spectrum (OES) when etching bare silicon wafers under Cl2 100sccin; Figure 21 shows the operating pressure inside the processing chamber 10mTrr, 350W antenna power, 100W power chuck Moreover, the optical emission spectrum (OES) when a bare silicon wafer is etched under γΒγ 100 seem; and FIG. 22 shows the operating pressure inside the processing chamber 10 mT0rr, the antenna 35 watt power, and the chuck 100 watt power Optical emission spectrum (〇pHcai emission spectrum; OES) at the time of Japanese Yen with ci2 20 seem and HBr 100 seem carved with multiple broken coatings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention provides an improved plasma processing reactor and plasma etching method 'which can provide more repeatable results when etching a batch of continuously processed semiconductor substrates. Especially in the process of etching a batch of semiconductor wafers, it has been found that the change in the axial etch rate may have a property of sudden increase or decrease of up to 30% or a property of slow change that occurs for several hours. The change in etch rate appears to be related to the history of the plasma chamber, and especially to the type of substrate that has been previously processed. One method often used to stabilize the etch rate of a diaphragm is to process 25 (or more) dummy wafers (pure silicon) before processing the normal product wafers. Although this technology does have a stable effect at the beginning, because it will be -9- this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------ I 1 ί 1 ϊ Ϊ 11111-^ — — — — — — — — — (Please read the note on the back before filling in this page)

4 3 6923 ( A7 五、發明說明(7 ) 理各種類型的產品晶圓,蝕刻率很快便變得十分不穩定。 此外,以此方法處理假晶圓不但耗時且導致工具的持有成 本増加。在生產環境下,電漿蝕刻工具的使用者均希望工 具具有穩定且再生性的性能,如此更可確保所有的處理步 驟均位於指定處理的窗口範圍内。 以CL或CVHBr氣體蝕刻多晶矽在處理有光敏抗蝕劑塗 層的晶圓之後,顯示了明顯的蚀刻率下降。此蝕刻率的降 低可多達原來速率的20-30%。在蝕刻二氧化矽塗層的晶圓 之後’多晶矽蝕刻率通常會增加了數個百分點。而在另一 個情況下,蝕刻多個調節晶圓需要恢復蚀刻率,如此導致 浪費工具時間及降低晶圓的產出。 實驗已經由設計與標準化以便量化這些效應。典型的處 理順序包括蝕刻五個(或以上)的純矽調節晶圓、—個多晶 矽塗層晶圓 '五個光敏抗蚀劑塗層的晶圓及再一個多晶矽 塗層晶圓。最初多晶矽塗層晶圓相較於最後的多晶矽塗層 晶圓的蝕刻率的差異可以看出,並可用於測量處理的變 動。最理想的是蝕刻率保持不變。在後續的測試時,在基 體支撑上(即具機械式或靜電式夹緊的卡盤)較低的RF偏 頻配合網路具有無線電頻率探針用於測量處理室的電I、 電流與RF信號相位。這些測量用於計算負荷(處理室加上 電漿)阻抗及輸送至處理室的負荷功率。其他評估以辨識 蚀刻率變化來源的變數是由電漿發射出的光學信號(兩個 波長)及閘閥(例如瑞士 VAT所製造之可變閘閥,其簡稱爲 “V AT閥”)位置所表示的處理室泵送速度’其中閘閥位於增 -10- 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) » u n II 1 ^1 ^1 ϋ^-5、· . .線! 經濟部智慧財產局員工消費合作社印製 A7 B7 43692 3 五、發明說明(8 ) 壓泵浦與處理室之間。 本發明之方法及裝置可在任何合適的電漿蝕刻反應器内 實施,其中個別的基體係,經連續處理。較㈣冑衆蚀刻反 應器是如圖1所7F之電感耦合式電漿反應器。根據本發 明,電漿蝕刻反應器經修正包括控制器,適用於批次處理 個別半導體基體時達到蝕刻率穩定。此反應器可包括任何 合適的來源以於處理室内產生電漿及任何合適的氣體供應 用於將姓刻氣體送到處理室内(例如氣環、喷麗頭、氣體 噴嘴固定安裝於延伸通過電介質窗的開口等等)。 在圖1所示之具體實施例中,眞空處理室1〇包括一基體 固疋座12用於提供靜電夾緊力給基體13與1117偏頻給基體 支撑及一中心環14用於限制電漿在^6回冷的同時於基體 上方的區域内。用於保持高密度(例如1〇n_1〇12 i〇ns/cm3) 電漿於處理室内的能量來源如由合適rF來源提供電力的 鉋工天線1 8及相關的R F阻抗配合電路1 9電感耦合r f能 量到處理室10内’如此以提供高密度的電漿。處理室包 括合適的眞空泵浦裝置,其中眞空泵浦裝置包括可調閘閥 (無顯示)連接至出口 15用以保持處理室内部於所需的壓 力(例如’ 50mTorr以下,典型是l-2〇mTorr)。 圖1所示反應器包括一本質上爲飽工的均勻厚度電介質 窗20介於天線18與處理室1〇内部之間。但是,也可使用 其他天綠及/或窗配置如非鉋工天線及/或非鉋工電介質 窗。再者,在可使用任何合適的氣體供應機構的同時,在 顯示氣體分配環2 2包圍中心環1 4的具體實施例中包括多 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之生意事項再填寫本頁) -----I--訂--- i -----! 經濟部智慧財產局員工消費合作社印製 43692 3 A7 B7 五、發明說明(9 )4 3 6923 (A7 V. Description of the invention (7) Etching of various types of product wafers, the etching rate quickly becomes very unstable. In addition, processing fake wafers in this way is not only time consuming and leads to tool holding costs In the production environment, users of plasma etching tools hope that the tools have stable and reproducible performance, so that they can ensure that all processing steps are within the specified processing window. CL or CVHBr gas is used to etch polycrystalline silicon. After processing a photoresist-coated wafer, a significant decrease in etch rate was shown. This etch rate can be reduced by as much as 20-30% of the original rate. After the silicon dioxide-coated wafer is etched, 'polycrystalline silicon' Etching rates typically increase by several percentage points. In another case, etching multiple tuned wafers requires restoration of the etch rate, which results in wasted tool time and reduced wafer yield. Experiments have been designed and standardized to quantify these The typical processing sequence includes etching five (or more) pure silicon-regulated wafers, one polycrystalline silicon-coated wafer, and five photoresist-coated wafers. Wafer and another polycrystalline silicon coated wafer. The difference in etch rate between the initial polycrystalline silicon coated wafer and the final polycrystalline silicon coated wafer can be seen and can be used to measure process variations. The most ideal is the etch rate Keep the same. In the subsequent test, the lower RF offset frequency on the substrate support (ie, the chuck with mechanical or electrostatic clamping) has a radio frequency probe to measure the electrical I of the processing chamber. , Current and RF signal phase. These measurements are used to calculate the load (processing chamber plus plasma) impedance and the load power delivered to the processing chamber. Other evaluations to identify the source of changes in etching rate are the optical signals emitted by the plasma (Two wavelengths) and gate valve (such as the variable gate valve manufactured by VAT in Switzerland, which is referred to as "V AT valve") position of the pumping speed of the processing chamber ', where the gate valve is located at -10- Standard (CNS) A4 specification (21〇X 297 mm) (Please read the notes on the back before filling out this page) »un II 1 ^ 1 ^ 1 ϋ ^ -5,... Line! Intellectual Property Bureau, Ministry of Economic Affairs Employee consumption cooperation Print A7 B7 43692 3 V. Description of the invention (8) Between the pump and the processing chamber. The method and device of the present invention can be implemented in any suitable plasma etching reactor, in which individual base systems are continuously processed. The relatively common etching reactor is an inductively coupled plasma reactor as shown in Figure 7F. According to the present invention, the plasma etching reactor is modified to include a controller, which is suitable for batch processing of individual semiconductor substrates to achieve an etching rate. Stable. This reactor can include any suitable source to generate plasma in the processing chamber and any suitable gas supply for sending the gas to the processing chamber (such as air ring, spray head, gas nozzle fixedly installed to extend through The opening of the dielectric window, etc.). In the specific embodiment shown in FIG. 1, the emptying processing chamber 10 includes a base fixing seat 12 for providing electrostatic clamping force to the base 13 and 1117 offset frequency to the base support and a The central ring 14 is used to limit the plasma in the area above the substrate while cooling back to 6 times. For maintaining high density (for example, 10n_1012 iOns / cm3) The energy source of the plasma in the processing room, such as a planer antenna powered by a suitable rF source, and related RF impedance matching circuits, 1 9 inductive coupling The rf energy is introduced into the processing chamber 10 'so as to provide a high density plasma. The processing chamber includes a suitable vacuum pumping device, wherein the vacuum pumping device includes an adjustable gate valve (not shown) connected to the outlet 15 to maintain the required pressure inside the processing chamber (for example, below 50 mTorr, typically l-2. mTorr). The reactor shown in FIG. 1 includes a dielectric layer 20 of substantially uniform thickness which is interposed between the antenna 18 and the interior of the processing chamber 10. However, other sky green and / or window configurations such as non-planer antennas and / or non-planer dielectric windows may be used. Furthermore, while any suitable gas supply mechanism can be used, the specific embodiment showing the gas distribution ring 2 2 surrounding the center ring 14 includes multiple paper sizes that are applicable to China National Standard (CNS) A4 specifications (210 X 297 (Mm) (Please read the business matters on the back before filling out this page) ----- I--Order --- i -----! Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 43692 3 A7 B7 5 Description of the invention (9)

個氣體出口(例如1 8個環繞隔開的出口)如圓形孔(未顯示) 用於將氣體供應23所供應之處理氣體送到處理室丨〇。基 體固定座12可包括數個傳統的特徵如升桿機構(未顯示) 用於升高基體1 3。 在一般操作條件下,氣體流動到處理室是固定的,且處 理室的壓力會在電腦控制下不斷調整VAT閥的開啓而保持 固定(典型約10 mTorr)。例如,在處理4 〇個調節晶圓時, 已可觀察到多晶矽蝕刻率緩慢增加而VAT閥也緩慢開啓。 圖2表示在調節前面1 〇個調節晶圓與第一個多晶矽塗層晶 圓期間,VAT閥緩慢開啓〇但是當光敏抗蝕劑塗層晶圓被 触刻時’ VAT閥迅速關閉且多晶妙蚀刻率降低。表格^彙 整了於兩個不同的處理室配置(即LAM 9400™與LAM 9600TM)中處理五個光敏抗蝕劑塗層晶圓之後多晶矽蝕刻 率的下降。 表格I ί請先閱讀背面之注意事項再填寫本頁) 裝 經濟部智慧財產局員工消費合作社印製 在處理五個光敏抗蝕劑塗層晶圓之後 多晶矽蝕刻率與傳送RF雷力的狻化 處理室與操作條件 蝕刻率變化% 傳送功率變化 % 9400/氣體流率固定/可調 VAT/P=10 mTorr -22.5% ~ -15% 9600/氣體流率固定/可調 VAT/P=10 mTorr -12.8% -2.3% 9400/VAT固定疋12流率變動 /P= 10 mTorr -12.9% ~ -15% 9600/VAT固定/Cl2流率變動 /P=10 mTorr + 1.1% -4% ‘張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公釐 I ---訂- --------線 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明(1〇 ) 這些實驗的分析已產生下列有關多晶矽蝕刻率變動之解 釋。在處理抗蝕劑塗層晶圓之後蝕刻率的下降是肇因於處 理室牆壁正覆蓋已蚀刻的光敏抗蚀劑碎塊。此種覆蓋接著 會吸收大量進入的氣體直到牆壁完全鈍化。如此意味著蝕 刻晶圓的可用氣氣減少,並造成處理室壓力降低。這又表 示多晶矽蝕刻率下降且VAT閥關閉以多少保持固定的處理 室壓力。已蝕刻的矽物質的光學信號也明顯降低,如圖3 所示。然後氣氣與其他分子殘留的後續吸收可達數小時, 即使已不再處理抗蝕劑塗層的晶圓β如果已混雜的處理室 經過過夜的泵送作用,牆壁便會解吸許多的蝕刻氣體,當 再度開始處理時,牆壁上的殘留便會再度強力吸收蝕刻氣 體,蚀刻率便再度下降。如果以氣氣蝕刻表面氧化的晶圓 時’碎可说會以SiCl4的形態脱離並釋出氧氣。氧氣會活潑 地清除處理室牆壁的光敏抗蝕劑碎塊,如此牆壁便不會與 氣氣嚴重鈍化,而後續的多晶矽蝕刻率會較高。 用來評估這些效應的一個方法是考慮使處理室具有三個 泵浦與三個氣體來源。這些泵浦相當於增壓泵浦、晶圓與 處理室牆壁。而這些氣體來源相當於入口物質流動控制 器、晶圓與處理室牆壁。當各種泵浦機構以不同的速度消 耗氣體時,Mathcad模型便沿著這些線路發展以計算部分 壓力與蚀刻率。結果顯示當牆壁覆蓋抗蚀劑殘留,但分子 殘留解吸作用以相當低的速度發生時,大量進入的氣體均 被處理室牆壁“排空,,了。如此產生牆壁的淨泵浦效應,而 爲了補償,VAT閥便會關閉。當處理氧化表面的晶圓時, -13- 本紙張尺度適用中國國家標準(CNS〉A4規格(21〇 x 297公釐) -------------^---- (請先閱讀背面之注意事項再填寫本頁) 訂------:---線 ! A7 B7 4 3 892 3 五、發明說明(11 ) 檣壁上的沉澱物會釋出,發生氣態產物的淨產生。於此情 況下,可觀察到在處理晶圓時,VAT閥會稍微開啓。 上述化學與泵浦效應只是部分的蚀刻率問題。使用[AM 9400TM工具,且將矽晶圓的基體改成抗蝕劑塗層的晶圓 時,觀察到負%阻力與負荷功率(無法精準測量,因此特 定處理室爲大電容設計)下降。負荷阻力下降導因於處理 罜内的化學要素随蝕刻光敏抗蝕劑而變化。此下降造成操 作點降到功率效率曲線之下,且輸送功率下降。如此造成 多晶矽蝕刻率進一步下降,在幅度上可與上述的化學與泵 浦效應相比。LAM 9600TM工具的功率下降較少,因爲其 處理至電谷較低’操作點稍高於效率曲線,在負荷阻力上 的負荷功率的阻抗較低。圖4顯示效率曲線上的相對位置 與負荷阻力與傳送功率上的光敏抗蝕劑塗層晶圓的效應。 如表格I所示,兩個處理室配置之傳送功率下降。 第三個效應是處理室溫度可能在處理過程中的升高效 應。但是溫度效應被認爲是遠小於化學與RF電力效應。 爲試圖排除化學與RF效用已經進行了數種實驗。第一 種實驗(在LAM 9400™工具上進行)從調整VAT閥位置以固 疋乳體入口流率保持固定壓力而改變祠服迴路。在新迴路 中,VAT閥的位置固定,並藉由改變氣氣流率補償處理室 牆壁的泵送作用來保持處理室内的壓力固定。如表格I所 示’如此導致處理五個抗蝕劑塗層晶圓之後,多晶珍蝕刻 率有12.9%的變化(標準伺服迴路爲22.5%),但仍伴隨傳送 功率下降~ 15% »這樣的結果顯示化學效應已經補償但r ρ -14- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------------裳!!--訂---II----線 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 43β92 五、發明說明(彳2 )A gas outlet (for example, 18 spaced-apart outlets) such as a circular hole (not shown) is used to send the processing gas supplied by the gas supply 23 to the processing chamber. The base fixing seat 12 may include several conventional features such as a lever raising mechanism (not shown) for raising the base 13. Under normal operating conditions, the flow of gas to the processing chamber is fixed, and the pressure in the processing chamber is constantly adjusted by the computer control to keep the VAT valve open (typically about 10 mTorr). For example, when processing 40 conditioning wafers, it has been observed that the polysilicon etch rate slowly increases and the VAT valve opens slowly. Figure 2 shows that during the adjustment of the first 10 adjustment wafers and the first polycrystalline silicon-coated wafer, the VAT valve slowly opens. But when the photoresist-coated wafer is etched, the VAT valve closes quickly and the polycrystalline silicon Reduced etching rate. Table ^ summarizes the reduction in polysilicon etch rate after processing five photoresist-coated wafers in two different processing chamber configurations (ie, LAM 9400 ™ and LAM 9600TM). Form I (Please read the notes on the back before filling this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed on the polysilicon etching rate and the transmission of RF lightning force after processing five photoresist-coated wafers Processing room and operating conditions Etching rate change% Transmission power change% 9400 / Gas flow rate fixed / adjustable VAT / P = 10 mTorr -22.5% ~ -15% 9600 / Gas flow rate fixed / adjustable VAT / P = 10 mTorr -12.8% -2.3% 9400 / VAT fixed 疋 12 flow rate change / P = 10 mTorr -12.9% ~ -15% 9600 / VAT fixed / Cl2 flow rate change / P = 10 mTorr + 1.1% -4% Applicable to China National Standard (CNS) A4 specifications (21 × X 297 mm I --- Order--------- Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economics A7 B7 V. Invention Description (1〇 ) The analysis of these experiments has resulted in the following explanation of the variation in the etch rate of polycrystalline silicon. The decrease in etch rate after processing a resist-coated wafer is due to the process chamber walls being covered with etched photoresist fragments. This This covering then absorbs a large amount of the incoming gas until the wall is completely passivated. This means etching the crystals The available gas is reduced and the pressure in the processing chamber is reduced. This in turn means that the polysilicon etch rate is reduced and the VAT valve is closed to maintain the fixed processing chamber pressure. The optical signal of the etched silicon material is also significantly reduced, as shown in Figure 3. Then the subsequent absorption of gas and other molecular residues can reach several hours, even if the resist-coated wafer is no longer processed. If the mixed processing chamber is pumped overnight, many walls will desorb many etchings. Gas, when the processing is started again, the residue on the wall will strongly absorb the etching gas again, and the etching rate will decrease again. If the surface oxidized wafer is etched with gas, the chip will be separated and released in the form of SiCl4. Oxygen is emitted. Oxygen will actively remove the photoresist fragments on the walls of the processing chamber, so that the walls will not be severely passivated with gas, and the subsequent polysilicon etching rate will be higher. One method to evaluate these effects is to consider The processing chamber has three pumps and three gas sources. These pumps are equivalent to booster pumps, wafers and processing chamber walls. And these gas sources When it comes to the inlet material flow controller, wafer and processing chamber wall. When various pumping mechanisms consume gas at different speeds, Mathcad models are developed along these lines to calculate partial pressure and etch rate. The results show that When the etchant remains, but the molecular residual desorption occurs at a relatively low speed, a large amount of the entered gas is "emptied" by the wall of the processing chamber. This produces a net pumping effect on the wall, and to compensate, the VAT valve will Close. When processing wafers with an oxidized surface, -13- This paper size applies to Chinese National Standards (CNS> A4 specification (21 × x297 mm) ------------- ^- -(Please read the notes on the back before filling this page) Order ------: --- line! A7 B7 4 3 892 3 V. Description of the invention (11) The deposits on the wall will be released and the net production of gaseous products will occur. In this case, it can be observed that the VAT valve opens slightly when processing the wafer. The above chemistry and pumping effects are only part of the problem of etch rate. When using the [AM 9400TM tool and changing the substrate of a silicon wafer to a wafer with a resist coating, negative resistance and load power were not observed (precise measurement is not possible, so the specific processing room is designed for large capacitance). The decrease in the load resistance is due to the fact that the chemical elements in the processing bath change with the etching of the photoresist. This decrease causes the operating point to fall below the power efficiency curve and the transmission power to fall. This results in a further reduction in the polysilicon etch rate, which is comparable in magnitude to the chemical and pumping effects described above. The power reduction of the LAM 9600TM tool is less, because it is processed to a lower valley, the operating point is slightly higher than the efficiency curve, and the impedance of the load power on the load resistance is lower. Figure 4 shows the relative position on the efficiency curve and the effect of photoresist-coated wafers on load resistance and transfer power. As shown in Table I, the transmission power of the two processing chamber configurations decreased. The third effect is that the temperature of the processing chamber may increase during processing. But the temperature effect is considered to be much smaller than the chemical and RF power effects. Several experiments have been performed in an attempt to rule out chemical and RF utility. The first experiment (performed on the LAM 9400 ™ tool) altered the shroud circuit by adjusting the position of the VAT valve to maintain a constant pressure at the breast inlet flow rate. In the new circuit, the position of the VAT valve is fixed, and the pressure in the processing chamber is kept constant by changing the gas flow rate to compensate for the pumping effect of the wall of the processing chamber. As shown in Table I, 'This resulted in a 12.9% change in polysilicon etch rate after processing five resist-coated wafers (22.5% for a standard servo loop), but still with a reduction in transmission power ~ 15% »This The results show that the chemical effect has been compensated, but r ρ -14- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------ Shang! !! --Order --- II ---- line (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 43β92 V. Description of Invention (彳 2)

效應則無。然後處理室配置改爲處理室電容較小(爲 200pF » LAM 94〇〇τμ^ ^ ^ '600pF) ^ LAM 9600SE™X X _ 以試囷使RF電力的下降達到最小。重複該實驗顯 理五個&敍劑塗層晶圓之後.傳送功率下降约4 %, =晶碎姓刻率小幅上升u%。這表示化學與阳支應兩者 眭已大Γ補償。圖5表示在保持HBr流率®定在100 _ ,氣氣流率是處理光敏抗_塗層晶圓時的兩倍以上。 氣^流率的增加相當於全部氣體流率約增加21%。 前述測試顯示晶圓僅呈現了整個㈣處理中的極小部分 (於上述條件下)’爲了解所發生的幾種效應,必須全面地 觀察處理室。測試數據顯示敍刻再生性的改良處是可以達 到的’且功奉成本持有可藉由計入處理室踏壁上成分組成 的吸收效應修改蝕刻處理而降低。 經濟部智慧財產局員工消費合作社印製 過去進行幾種實驗調查在蚀刻多晶梦時,控制α與撕 兩者流率作爲改善蝕刻率再生性的裝置之可行性。蝕刻率 再生性的改良處的實現可使用根據本發明計人㈣處理時 所,生的各種處理室狀況之方法。以純A與脑氣體及這 些氣體混合的流率蝕刻矽與光敏抗蝕劑時,已經分析了光 學放射光譜(OES)。12個晶圓的標準化順序是用來量化處 理四個碎塗層調節晶圓前後以及處理五個光敏抗蝕劑塗層 晶圓前後的触刻率差異。纟氣禮流率目《而處理室菜浦速 度老動以保持壓力固定的傳統控制條件下,在MM 940〇ΡΤΧ™工具處理光敏抗蝕劑塗層晶圓之後,多晶矽蝕 刻率下降了 15%。但是如在接地電容約2〇〇pF(例如於lam -15- 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 x 297公釐) 43692 3 A7 ----- B7 五、發明說明(13 ) 9600SETM工具下處理而不在接地電容~6〇〇 pF之9400工具下 處理)的處理室内處理時,此百分比的下降可減爲一半。 之所以如此原因是在處理光敏抗蝕劑塗層晶圓之後,送至 處理室的RF電力在9400TXtmX具中下降了〜15%,但在 96003丑"^處理室中僅下降0至4%。功率下降的發生是因爲 電漿電阻增加導致負荷阻力下降。電漿電阻增加可能肇因 於在處理光敏抗蝕劑晶圓時電漿的化學變化及可能電子溫 度下降。 在LAM工具上所做的測量有石英Ί'CPTM视窗與環繞靜電 卡盤的陶瓷氣環《卡盤的接地電容是~2〇〇pf。對於每個實 驗’均執行相同的晶圓順序並測量多晶矽蝕刻率。表格工工 表示順序與所做測量之基線處理參數β在每次執行之前, 處理室會使用SFe及&饋入氣體清除電漿至端點。在三種 蝕刻率晶圓的每一種上多晶矽的開始厚度是使用Pr〇metrix FT-650來決定。在處理了】2個晶圓後,測量多晶矽剩下的 厚度並決定蝕刻率。 至負%的RF電力並非主動地由來自rj?探針的回饋迴路 所控制’其中RF探針位於RF偏頻配合網路内。實驗是以 低處理室電容爲基礎,以避免功率效率隨負荷阻力結果變 化而產生過大的下降。每次實驗時,VAT閥均保持在固定 位置而一個或多個饋入氣體的流率則會變化以保持固定的 處理室壓力10 mTorr。在打開RF之前及蝕刻每個晶圓時, 紀綠氣體的流率》同時也紀錄來自RJ?探針的RF參數(電 壓、電流、相位、傳送功率、負荷阻力及負荷電抗)。在 -16- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝--------訂---------線 經濟部智慧財產局員工消費合作社印製 A7 43S923 五、發明說明(μ ) 打開R F電力後,通常氣體流率一開始會下降,在光敏抗 蝕劑塗層晶圓的情況下’剩餘的蝕刻率會接著穩定増加。 氣體流率値與R F參數相對於約蝕刻—半時間,也就是打 開R F電力後約3 0秒。 五種測試的進行方法是改變一個或兩個饋入氣體的流 率’同時保持處理室固定壓力10 mTorr。這五種測試如下: (i) 以5:1的比例同時改變HBr與Cl2的流率 (Π)只改變HBr的流率,(:12保持流率20 seem (iii) 只改變Cl2的流率,HBr保持流率1 〇〇 sccm (iv) 以更高的泵浦速度重複第三個測試 (v) 只改變(:12的流率,HBr保持流率0 seem 在上述測試進行之前,多晶砂蚀刻率的測量乃是被當作 在類似處理條件下,除了改變泵浦速度來保持處理室壓力 於lOmTorr外’清潔處理室内<:12流率(加上1〇〇 sccn^HBr) 功说。結果如圖6所示。多晶梦蚀刻率從純HBr的1750 A/min提高到加入5〇 seem的Cl2時的~2650 A/min。只使用 Clz的餘刻率約是只使用HBr的兩倍。這些蝕刻率在闡述測 試⑴至(V)的結果時非常有用。 表格III彙整這五個實驗的結果β前面兩個測試結果類 似’因爲以5:1的比例改變兩種氣體會導致Cl2流率產生極 小的變化,因此只有HBr的流率一直在改變。在四個碎調 節晶圓前後,當HBr流率改變時,多晶矽蝕刻率非常相近 (0.5%之内)。但是蝕刻五個光敏抗蝕劑塗層晶圓會導致蝕 刻率下降至1 2到15%。此情況可與第三個實驗Cl2流率改 -17- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) <請先閱讀背面之注意事項再填寫本頁) 裝 訂-------------線 經濟部智慧財產局員工消費合作社印制衣 A7 B7 43 692 3 五、發明說明(15 ) 變而HBr流率固定在100 sccin做比較β於此發生了相反的 效應。在處理調節晶圓後蚀刻率下降約丨2 %,但蝕刻光敏 抗蝕劑塗層晶圓後卻約保持固定(+3 5〇/。)。這顯示處理室牆 壁與晶圓條件是當調節晶圓正在钱刻時,HBr(即Η,Br)子 產物優先耗用,以及當蝕刻抗蝕劑塗層晶圓時,來自 ClJCl)的產物會優先耗用。在打開rf電力之前,總氣體 流率在整個1 2次晶圓順序中約保持固定。此表示流率與 處理室牆壁無關,且幾乎無或極少發生化學現象直到發生 分子分解爲止。同樣地,這就像處理室調節中Br2及112的 角色極小。 第三個實驗以更高的泵浦速度(VAT閥260次與230次)重 複一遍,因爲繼四個調節晶圓之後Cl2流率非常低。在此 情況下(測試(iv)),Cl:流率以55 seem開始因爲大量的HBr 正流失到處理室牆壁與泵浦。Cl2的大流率導致頗高的多 晶矽蝕刻率2500 A/min。當處理室牆壁充滿HBr產物時, Cla流率下降至13 seem來補償,多晶矽蝕刻率則下降 2 1 %。相反的,在蝕刻光敏抗蚀劑塗層晶圓時,主要是 Clz產物被耗用而C12流率再度增加至42 seem。多晶碎钱刻 率中度增加5%。蝕刻率的過度補償可能是因爲某些ηβγ產 物在光敏抗蝕劑蝕刻期間及之後馬上耗用,並由快速蚀刻 的氣氣來補償。藉由增加氣氣流率(可能伴隨HBr流率小幅 增加)補償耗盡的蝕刻產物可能提供一種可行的蝕刻率穩 定技術於某操作範圍上,但這不是普遍的解決方案,因爲 調節晶圓後蝕刻率顯示變化。同時,選擇泵浦速度也應謹 -18- 本紙張尺度適用中國國家標準<CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) -I 裝·!-- 訂------------線 經濟部智慧財產局員工消費合作社印製 43692 3 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(π ) 愼決定,因爲較高泵浦速度時會發生蝕刻率的過度補償。 由於晶圓與不同速率的主要物質的處理室牆壁泵浦子產物 似乎取決於晶圓類型或處理室條件,精確的補償應可藉由 即時測量處理室的氣態内容物來取得。例如,藉由合適分 析技術(例如OES光譜)的測量應可用於此目的。使用不同 策送的RGA也可達到所需的結果但是會増加生產過程中的 成本。就經濟面而言,補償CL流率可能是最低價且最容 易實施於生產過程中β 第五個實驗是只使用氣氣來進行的。這對於生產可能不 疋一個可行的選擇但是完成後可使流率補償的測試更完 整。使用單一氣體的情況應簡單明瞭,因爲随產物的耗 用,其流率會增加以補償損失。從表格III中可看出多晶碎 蚀刻率在調節晶圓後增加1.8% ’並在光敏抗姓劑晶圓後下 降0.8%。氣氣流率的微小變化與前面的實驗相比結果令人 驚訏。當同時使用HBr與Cl2時,流率改變1 〇至sccm, 但只有氣氣時,低於10 seem的變化便足以補償蚀刻率。 在這五個實驗中,蝕刻的均一性非常良好,與標準僅偏 差約2.5%。橫過蝕刻的多晶矽晶圓的蝕刻輪廓在前面三個 測試中邊緣蝕刻稍快,而測試(iv)特別均一,可能是因爲 氣體流率較高。測試(v)則中央蝕刻稍快。 値得注意的是比較已分解分子的密度與電漿中現存離子 的密度。於10 mTorr時,每1 cm3約有1014個原子與分子。 如果電子密度爲〜5x 101°,則2000中只有一個粒子會被離 子化。因分解與衍生的流率變化導致之氣體壓力變化顯示 19 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) I.--ml------ 裝-----丨丨訂--I I ----線 (請先閱讀背面之注急事項再填寫本頁) ^3 692 3 A7 經濟部智慧財產局員工消費合作社印製 B7 五、發明說明(17 ) 兩者中的一個粒子爲已分解的碎塊。已分解原子的強烈反 應會導致快速耗用及流率的明顯變化’。 圖7顯示測試⑴的負荷電恩、負荷電力、ci2流率及HBr 流率變化。已蚀刻多晶梦晶圓的蚀刻率如圖8所示。其可 看出負荷電歷對多晶矽之蚀刻率的控制具有較低的影響, 而負荷電壓對較多實際製程如氣氣蝕刻Si〇2或光敏抗蝕劑 的蝕刻率控制具有較多的影響。其他測試的類似曲線顯示 於圖9-16用來圖解説明所述之效應。 在處理晶圓時,氣氣流率範園可能明顯改變。圖I 7表示 第三個晶圓測試作爲蝕刻時間功能的氣氣流率與處理室壓 力。在左侧’固定HBr流率提供處理室壓力8 mTorr,並在 3秒後’打開氣氣讓壓力增加爲mTorr。12秒後打開 A F,壓力先增而後降回1 〇 mT〇rr。氣氣流率持續下降且不 完全穩定即使在蝕刻終了時。前面的調節晶圓具有甚至更 緩慢的流率下降,而後續的調節晶圓以更快的速度穩定流 率。流率的降低可與第一個光敏抗蝕劑晶圓(測試(^)第7 個)比較,如圖1 8所示。在此,在流率相當迅速穩定之 後,後者於整個蝕刻中增加並經過所有的後續光敏抗蝕劑 晶圓β此過程只有將晶圓從光敏抗蝕劑改爲矽晶圓才能相 反改變。圖1 9表示RF打開之前的氣氣流率及測試(iv)的每 個晶圓的氣氣流率範圍(壓力穩定後)。這些會改變流率點 並使耗用機構及處理室對蚀刻過程的重要性複雜化。 根據本發明的一個具體實施例,ΗΒγ& /或ci2的流率必 須根據處理室條件與晶圓類型來控制。爲控制一個或多個 -20- 本纸張尺度適用中國國突樘遂^riuc、λ ^日从/Τι_Λ。μ,.、妨 s / y < υ 1 ώ έ * c ο > 1 ^--------訂--------線 (請先閱讀背面之注意事項再填寫本頁) 43692 3 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明(18 ) 處理氣體的流率以獲得蝕刻穩定,根據本發明,光學放射 光譜可提供有關處理室的氣態要素之必要資訊。在評估監 視此放射信號之技術時,使用僅氣氣、僅HBr及5:1比例的 HBr/Cl2混合波長範圍240-850 mm的光譜。圖20表示在以 氣氣蝕刻一裸矽晶圓時,採取的光譜。波長位置所有的大 於700 nm的線是導因於原子氣氣,而介於300-400 nm及 500-600 nm的線與帶可能導因於氣化矽蝕刻產物。當只使 用HBr時,可獲得圖2 1所示之光譜,其中可確認所有線與 原子溴有關。歸因於氫的線並未出現,因爲其會在能量中 大量分離。圖22表示使用Cl2與HBr之混合可獲得的光譜。 可再次看到來自矽晶圓的蝕刻產物,但可能除圖2 〇純氣 氣光譜中明顯用圖表示的837.6 nm線之外,並沒有原子氣 氣線。即使進入處理室的HBr:Cl2比例是5:1,原子氣氣的 光學發射似乎受到抑制。對於此結果可能的一個解釋是被 排空的已吸取Η與B r可能在處理室牆壁上耗用了 Ci2。雖 然測試顯示在HBr/Cl2混合中沒有(:12線,如此使得此處所 述之OES技術不適用於測量Br/Cl的比例,但是估計其他適 用於即時蝕刻基體時取得组成氣體之氣體比例的測量技術 可根據本發明之方法來使用,以便於批次處理連續蝕刻晶 圓時,獲得蚀刻率變化的降低。 當蚀刻光敏抗蝕劑晶圓時,唯一可觀察到的光譜線是原 子溴。但是在蝕刻五個晶圓後,這些線的強度下降四倍。 這可能是因爲電漿中抗姑劑蚀刻產物出現造成電子溫度下 降所致。預計這些大量的碎塊有許多低能量狀態,將阻止 -21 - t...氏張尺度適用中國國家標準(CNS)A4規格咖〆观公爱) (諝先閱讀背面之注意事項再填寫本頁)No effect. Then the processing chamber configuration was changed to a smaller processing chamber capacitance (200pF »LAM 94〇〇τμ ^ ^ ^ '600pF) ^ LAM 9600SE ™ X X _ Try to minimize the decline in RF power. After repeating the experiment, it was shown that after five & agent-coated wafers, the transmission power decreased by about 4%, which means that the chipping rate increased slightly by u%. This means that both chemistry and yang branch have large compensation. Figure 5 shows that while maintaining the HBr flow rate® at 100 °, the gas flow rate is more than double that when processing photosensitive anti-coated wafers. The increase in gas flow rate is equivalent to an overall gas flow rate increase of about 21%. The foregoing tests show that the wafer only shows a very small portion of the entire plutonium process (under the above conditions) 'To understand the several effects that occur, you must fully observe the processing chamber. The test data shows that the improvement of the reproducibility can be achieved, and the cost of holding can be reduced by modifying the etching treatment by taking into account the absorption effect of the composition of the components on the tread wall of the processing chamber. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. Several experiments have been conducted in the past to investigate the feasibility of controlling the flow rate of α and tear as a device to improve the reproducibility of the etching rate when etching polycrystalline dreams. The improvement of the etch rate and reproducibility can be achieved by the method of calculating the conditions of various processing chambers generated during the process of the present invention. Optical Emission Spectroscopy (OES) has been analyzed when silicon and photoresist are etched at a flow rate of pure A with brain gases and these gases. The standardized order of 12 wafers is used to quantify the difference in etch rate before and after processing four broken coating adjustment wafers and before and after processing five photoresist coated wafers. The rate of air flow is low, and under the traditional control conditions that the processing room Caipu speed is kept constant to maintain the pressure, after the photoresist-coated wafer is processed by the MM 940IPOT ™ tool, the polysilicon etch rate is reduced by 15%. . However, if the grounding capacitance is about 200pF (for example, lam -15- this paper size applies the Chinese National Standard (CNS) A4 specification (21 × 297 mm) 43692 3 A7 ----- B7 V. Description of the invention (13) When processing under the 9600SETM tool but not in the processing chamber with a ground capacitance of ~ 600pF (9400 tool), this percentage reduction can be reduced to half. The reason for this is that after processing the photoresist-coated wafer, the RF power sent to the processing chamber dropped by ~ 15% in the 9400TXtmX tool, but only decreased by 0 to 4% in the 96003 ugly processing chamber. . The decrease in power occurs because the increase in plasma resistance results in a decrease in load resistance. The increase in plasma resistance may be due to the chemical changes in the plasma while processing the photoresist wafer and the possible decrease in electron temperature. Measurements made on the LAM tool include a quartz Ί'CPTM window and a ceramic air ring surrounding the electrostatic chuck. The grounding capacitance of the chuck is ~ 200pf. The same wafer sequence was performed for each experiment 'and the polysilicon etch rate was measured. Table workers represent the sequence and baseline measurements of the measurements made. Before each execution, the processing chamber will use SFe and & feed gas to remove the plasma to the endpoint. The starting thickness of polycrystalline silicon on each of the three etch rate wafers was determined using Prometrix FT-650. After processing two wafers, the remaining thickness of polycrystalline silicon was measured and the etch rate was determined. The RF power to negative% is not actively controlled by the feedback loop from the rj? Probe, where the RF probe is located in the RF offset frequency matching network. The experiment is based on a low process chamber capacitance to avoid excessive reductions in power efficiency as load resistance results change. During each experiment, the VAT valve was held in a fixed position and the flow rate of one or more feed gases was changed to maintain a fixed process chamber pressure of 10 mTorr. Before turning on the RF and etching each wafer, the flow rate of the green gas also recorded the RF parameters (voltage, current, phase, transmission power, load resistance, and load reactance) from the RJ? Probe. In -16- this paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) ----- Printed by A7 43S923, Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs V. Description of the Invention (μ) After RF power is turned on, the gas flow rate will usually decrease at first. In the case of photoresist-coated wafers The remaining etch rate will then increase steadily. The gas flow rate 値 and R F parameters are relative to the etching-half time, which is about 30 seconds after the R F power is turned on. Five tests were performed by changing the flow rate of one or both of the feed gases' while maintaining a fixed pressure of 10 mTorr in the processing chamber. The five tests are as follows: (i) Change the flow rate of HBr and Cl2 simultaneously at a ratio of 5: 1 (Π) only change the flow rate of HBr, (: 12 maintain the flow rate 20 seem (iii) change only the flow rate of Cl2 HBr maintains a flow rate of 100 sccm (iv) Repeats the third test at a higher pumping speed (v) only changes (: a flow rate of 12 and HBr maintains a flow rate of 0 seem The measurement of sand etch rate is considered to be under similar processing conditions, except that the pump speed is changed to maintain the processing chamber pressure at 10 mTorr. 'Clean processing chamber <: 12 flow rate (plus 100 sccn ^ HBr) function Said. The results are shown in Figure 6. The polycrystalline dream etching rate increased from 1750 A / min for pure HBr to ~ 2650 A / min when Cl2 was added at 50 Seem. The remaining rate using only Clz was about using only HBr These etching rates are very useful in interpreting the results of the tests ⑴ to (V). Table III summarizes the results of these five experiments. The results of the previous two tests are similar. 'Because changing the two gases at a ratio of 5: 1 will Resulting in a very small change in the Cl2 flow rate, so only the flow rate of HBr has been changing. When the HBr flow rate is changed, the polysilicon etch rate is very similar (within 0.5%). However, etching five photoresist-coated wafers will cause the etch rate to drop to 12 to 15%. This situation can be compared with the third experiment Cl2 flow rate change -17- This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) < Please read the precautions on the back before filling this page) Binding --------- ---- Printed clothing A7 B7 43 692 3 of the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention description (15) The HBr flow rate was fixed at 100 sccin for comparison. The opposite effect occurred here. After adjusting the wafer, the etching rate decreased by about 2%, but the photoresist-coated wafer remained approximately fixed after etching (+3 50 /.). This shows that the conditions of the processing room wall and wafer are when the wafer is adjusted When the money is engraved, the HBr (ie, hafnium, Br) sub-products are preferentially consumed, and when the resist-coated wafer is etched, the products from ClJCl are preferentially consumed. Before the rf power was turned on, the total gas flow rate remained approximately constant throughout the 12 wafer sequences. This means that the flow rate has nothing to do with the walls of the processing chamber, and there is little or no chemical phenomenon until molecular decomposition occurs. Again, this is like the minimal role of Br2 and 112 in process room conditioning. The third experiment was repeated at higher pumping speeds (260 and 230 VAT valves) because the Cl2 flow rate was very low after four adjustment wafers. In this case (test (iv)), the Cl: flow rate starts at 55 seem because a large amount of HBr is being lost to the walls of the processing chamber and the pump. The high flow rate of Cl2 results in a fairly high polysilicon etch rate of 2500 A / min. When the wall of the processing chamber is filled with HBr products, the Cla flow rate drops to 13 seem to compensate, and the polysilicon etch rate decreases by 21%. In contrast, when photoresist-coated wafers were etched, mainly the Clz product was consumed and the C12 flow rate increased again to 42 seem. The polycrystalline coin-cut rate increased moderately by 5%. The excessive compensation of the etch rate may be because some ηβγ products are consumed during and immediately after the photoresist is etched, and are compensated by the rapid etching gas. Compensating for depleted etch products by increasing the gas flow rate (which may be accompanied by a small increase in HBr flow rate) may provide a viable etch rate stabilization technique over a certain operating range, but this is not a universal solution because the post-wafer etch is adjusted The rate display changes. At the same time, the pump speed should be selected. -18- This paper size applies to the Chinese National Standard < CNS) A4 size (210 X 297 mm) (Please read the precautions on the back before filling out this page) -I Loading ·! -Ordered by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 43692 3 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of Invention (π) 愼 Decision, This is because over-compensation of the etch rate occurs at higher pump speeds. Since the processing chamber wall pumping products of the wafer and the main substance at different rates seem to depend on the type of wafer or the processing chamber conditions, accurate compensation should be obtained by measuring the gaseous contents of the processing chamber in real time. For example, measurements with appropriate analytical techniques (such as OES spectroscopy) should be used for this purpose. RGAs with different strategies can also achieve the desired results but increase costs in the production process. In terms of economics, compensating the CL flow rate is probably the lowest price and the easiest to implement in the production process. The fifth experiment was performed using only gas. This may not be a viable option for production, but will complete the flow rate compensation test when complete. The use of a single gas should be straightforward, as the flow rate increases as the product is consumed to compensate for losses. From Table III, it can be seen that the polycrystalline etch rate increased by 1.8% after adjusting the wafer, and decreased by 0.8% after the photoresist wafer. The small changes in airflow rate are surprising compared to previous experiments. When using HBr and Cl2 at the same time, the flow rate changes from 10 to sccm, but when only gas is used, a change below 10 seem is sufficient to compensate the etching rate. In these five experiments, the uniformity of the etch was very good, deviating from the standard by only about 2.5%. The etch profile across the etched polycrystalline silicon wafer etched the edge slightly faster in the previous three tests, and test (iv) was particularly uniform, probably due to the higher gas flow rate. In test (v), the center etch is slightly faster. It is important to compare the density of the decomposed molecules with the density of existing ions in the plasma. At 10 mTorr, there are about 1014 atoms and molecules per 1 cm3. If the electron density is ~ 5x 101 °, only one particle in 2000 will be ionized. Changes in gas pressure due to decomposition and derivative flow rate changes 19-This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) I .-- ml ------ Pack --- -丨 丨 Order--II ---- line (please read the urgent matters on the back before filling this page) ^ 3 692 3 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs B7 V. Invention Description (17) One of the particles is a decomposed fragment. The strong reaction of the decomposed atoms will result in rapid depletion and significant changes in flow rate '. Figure 7 shows the changes of load power, load power, ci2 flow rate, and HBr flow rate of the test puppet. The etching rate of the etched polycrystalline wafer is shown in FIG. 8. It can be seen that the load ephemeris has a lower influence on the control of the etch rate of polycrystalline silicon, and the load voltage has more influence on the etch rate control of more practical processes such as gas-etched Si02 or photoresist. Similar curves for other tests are shown in Figures 9-16 to illustrate the effects described. When processing wafers, the airflow rate range may change significantly. Figure I 7 shows the gas flow rate and process chamber pressure as a function of etch time for the third wafer test. On the left side, the fixed HBr flow rate provided the processing chamber pressure of 8 mTorr, and after 3 seconds, the gas was turned on to increase the pressure to mTorr. After 12 seconds, the A F was opened, and the pressure first increased and then decreased back to 10 mTorr. The gas flow rate continued to decrease and was not completely stable even at the end of the etching. The previous conditioning wafers have even slower flow rate drops, while the subsequent conditioning wafers stabilize the flow rate at a faster rate. The reduction in flow rate can be compared with the first photoresist wafer (test (^) 7th), as shown in Figure 18. Here, after the flow rate stabilizes fairly quickly, the latter increases throughout the etch and passes through all subsequent photoresist wafers. This process can be reversed only by changing the wafer from a photoresist to a silicon wafer. Figure 19 shows the airflow rate before RF is turned on and the range of airflow rate (after pressure stabilization) per wafer for test (iv). These change the flow rate points and complicate the importance of the consuming mechanism and processing chamber to the etching process. According to a specific embodiment of the present invention, the flow rate of Ηγ and / or ci2 must be controlled according to the conditions of the processing chamber and the type of wafer. In order to control one or more -20- this paper size is applicable to China's national crisis ririuc, λ ^ day from / Τι_Λ. μ ,. 、 may s / y < υ 1 hisft * c ο > 1 ^ -------- Order -------- line (please read the precautions on the back before filling in this Page) 43692 3 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (18) Process gas flow rate to obtain etching stability. According to the present invention, the optical emission spectrum can provide the necessary gaseous elements of the processing chamber. Information. When assessing the technology for monitoring this radiation signal, a gas-only spectrum, only HBr, and a 5: 1 ratio HBr / Cl2 mixed wavelength range 240-850 mm were used. FIG. 20 shows a spectrum taken when a bare silicon wafer is etched with gas. All lines greater than 700 nm at the wavelength position are due to atomic gas, while lines and bands between 300-400 nm and 500-600 nm may be due to vaporized silicon etching products. When only HBr was used, the spectrum shown in Fig. 21 was obtained, and it was confirmed that all lines were related to atomic bromine. The line attributed to hydrogen does not appear because it is largely separated in energy. Figure 22 shows the spectrum obtainable using a mixture of Cl2 and HBr. The etching products from the silicon wafer can be seen again, but there may be no atomic gas lines except the 837.6 nm line which is clearly shown in the pure gas spectrum in Figure 20. Even if the HBr: Cl2 ratio entering the processing chamber is 5: 1, the optical emission of atomic gas seems to be suppressed. A possible explanation for this result is that the evacuated aspirated plutonium and B r may have consumed Ci2 on the walls of the processing chamber. Although the test shows that there is no (: 12 line in the HBr / Cl2 mixture, this makes the OES technology described here not suitable for measuring the ratio of Br / Cl, but it is estimated that other suitable for obtaining the proportion of the gas composition gas when the substrate is etched immediately The measurement technique can be used in accordance with the method of the present invention in order to obtain a reduction in the change in etching rate when batch-etching a continuous etching wafer. When etching a photoresist wafer, the only observable spectral line is atomic bromine. However, after five wafers were etched, the strength of these lines decreased fourfold. This may be due to the decrease in electron temperature caused by the appearance of anti-etching products in the plasma. These large fragments are expected to have many low-energy states, which will Stop -21-t ... Zhang scales are applicable to Chinese National Standard (CNS) A4 specifications. (〆Please read the precautions on the back before filling this page)

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^ 3 592 3 - 五、發明說明(19 ) 電衆電子獲得大量的.能量。如此,視配備與實際㈣處理 過程而定,OES可能不提供所需的電漿要素監視的程度。 處理室牆壁(例如側牆壁、嵌入件、噴灑頭、電介質窗 等)對姓刻率變化的效應影響已藉由在處理室牆壁上塗上 處理鈍化物質的方式完成調查研究。例如,處理室的塗層 可使用各種物質如陶瓷或有機物質。雖然陶瓷物質已發現 對穩定多晶矽蝕刻率沒什麼助益,但是有機物質如聚四氟 乙烯(即特氟隆TEFLONT,已發現提供令人驚訝的良好結 果。根據本發明,爲蝕刻率穩定目的結合控制一個或多個 處理氣體流率時,連續蝕刻數批丨〇個或以上的晶圓(例如 光敏抗蝕劑、氧化表面、多晶矽及假晶圓)的蝕刻率變化 可以降低至5 %以下,更佳的是降至2 %以下。此等的蝕刻 率穩定相當於比傳統處理過程在順序上改良5P% ^不論有 無穩定塗層,蝕刻率穩定也可改善,方式是使用500奸以 下,較佳是300 pF以下,更佳的是200 pF以下的低處理室 電容之處理室配置。有了根據本發明可獲得之改良處,蚀 刻處理過程預期可以執行而不需要在開始執行產品晶圓生 產之前,執行矽調節晶圓通過電漿室。 (請先閱讀背面之注意事項再填寫本頁) 裝-------訂---------線 ! 經濟部智慧財產局員工消費合作社印製 -22- 本紙張尺度迺用中_家標準(CNS)A4規格⑽χ 297公楚) 4 3692 3 A7 五 ---------- 發明說明(2〇 ) 表格II 晶S 順序 晶圓數量 晶圓類型 1 多晶珍飯刻率 2 坏矽/調節 3 調節 4 - 調節 5 調節 6 多晶梦飯刻率 7 光敏抗蝕劑塗層 8 光敏抗钱劑 9 光敏抗蚀劑 10 光敏抗蚀劑 11 光敏抗蚀劑 12 多晶矽蝕刻率 處理參數包括以下:總壓力10 mTorr、TCPTM電力350瓦、 偏頻電力 100 瓦、HBr流率 1〇〇 seem、012流率 20 seem、ESC 8Torr Helium、60°C、# 刻持續時間 60秒。 J I--^. —------訂-----I-- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 -23- 本紙張尺度適用中國困家標準(CNS)A4規格(210 X 297公釐) 43 692 3 B7 A7 經濟部智慧財產局員工消費合作社印製 五 、發明說明(21 ) 表格III 第一個 蝕刻率 第二個 蝕刻率 第三個 多晶矽 變化% 多晶碎 變化% 多晶砂 蚀刻率 蚀刻率 蝕刻率 晶圓 晶圓 晶圓 (#1) (#6) (#12) 標準開放式迴路參數 多晶矽蝕刻率(A/min) 未測量 2127 -12.80% 1854 RF之前總氣體流率 (seem) 120 蝕刻時HBr流率 100 100 100 蝕刻時(:12流率 20 20 20 • VAT閥設定 可變 可變 可變 傳送(負荷)電壓 136.6 127.7 139.4 傳送(負荷)電力(瓦) 60.5 61.8 60.4 測試(i),以比例5:1 變動調整(HBr+Cl2) 多晶矽蝕刻率(AAnin) 2027 0.25% 2032 -12.10% 1786 RF之前總氣體流率(seem) 130 蝕刻時HBr流率 111.4 90.4 105 蚀刻時Cl2流率 22.26 18.16 21 VAT閥設定 230 230 230 傳送(負荷)電壓 135 128.4 136.4 傳送(負荷)電力(瓦) 54.5 58 54,2 測試(ii),變動HBr+Cl2 固定流率2〇 seem 多晶矽蚀刻率(A/min) 2104 -0.38% 2096 -14.80% 1786 -24- ----------I I t--------訂---------線 〈請先閲讀背面之!意事項再填寫本頁) 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) 4 3 692 3 : A7 B7 五、發明說明(22 ) 經濟部智慧財產局員工消費合作社印製 第一個 多晶矽 蚀刻率 晶圓 (#1) 蝕刻率 變化% 第二個 多晶碎 蝕刻率 晶圓 (#6) 蝕刻率 變化% 第三個 多晶砂 姓刻率 晶圓 (#12) RF之前總氣體流率(_) 137 蝕刻時HBr流率 104 89.1 106.4 蝕刻時Cl2流率 20 20 20 VAT閥設定 230 230 230 傳送(負荷)電壓 134.5 127.2 136.1 傳送(負荷)電力(瓦) 56.9 57.7 54.9 測試(iii),變動 Cl2+HBr 固定流率100 seem 多晶矽蚀刻率(A/min) 2066 -11.60% 1826 3.50% 1890 RF之前總氣體流率(scon) 135 蝕刻時HBr流率 100 100 100 蚀别時Cl2流率 20 5.9 32.1 VAT閥設定 230 230 230 傳送(負荷)電壓 133.2 125.9 138 傳送(負荷)電力(瓦) 53.4 54.4 50.8 測試(iv),以更高的泵 浦速度重複步驟iii。 變動Cl2+ HBr流率固 定 100 seem 多晶矽蝕刻率(A/min) 2501 -20.70% 1982 5.10% 2083 RF之前總氣體流率(seem) 153 蚀刻期間HBr流率 100 100 100 蝕刻期間Cl2’流率 55 13 42 VAT閥設定 260 260 260 (請先閱讀背面之注意事項再填寫本頁) -25- 本紙張尺度適用中國國家標準(CNS)A4規格<210 X 297公釐) 436923 - A7 __B7 五、發明說明(23 ) 第一個 多晶碎 蝕刻率 晶圓 (#1) 蚀刻率 變化% 第二個 多晶矽 蚀刻率 晶圓 (#6) 蚀刻率 變化% 第三個 多晶梦 蚀刻率 晶圓 (#12) 傳送(負荷)電壓 128.7 120.7 131.4 傳送(負荷)電力(瓦) 53.2 53.1 52.3 測試(V),只變動Cl2 ; HBr流率=0 多晶矽蝕刻率(A/min) 3057 1.84% 3114 -0.79% 3089 RF之前總氣體流率(scan) 124 蝕刻時HBr流率 0 0 0 蝕刻時Cl2流率 101 104 110 VAT閥設定 200 200 200 傳送(負荷)電壓 130.6 133 136.3 傳送(負荷)電力(瓦) 54.8 53.7 54.6 以上已經説明了本發明應用之原理、較佳具體實施例與 操作模式。但是本發明不因此而受限於討論到的特定具體 實施例。因此,上述具體實施例應視爲解説性質,而非限 定性質,且應瞭解精通此技藝之人可在不背離以下申請專 利範圍所定義之本發明範疇下將這些具體實施例加以變 化。 (請先閱讀背面之注意事項再填寫本頁)^ 3 592 3-V. Description of the invention (19) Electron electrons obtain a large amount of energy. As such, depending on the equipment and the actual process, OES may not provide the required degree of plasma element monitoring. The effect of the treatment room walls (such as side walls, inserts, sprinklers, dielectric windows, etc.) on the change of the cast rate has been investigated by coating the treatment room walls with a passivating substance. For example, the coating of the processing chamber may use various substances such as ceramics or organic substances. Although ceramic substances have been found to be of little help in stabilizing the etch rate of polycrystalline silicon, organic substances such as polytetrafluoroethylene (ie, Teflon TEFLONT) have been found to provide surprisingly good results. According to the present invention, combined control for the purpose of etch rate stabilization With one or more process gas flow rates, the etch rate change of several batches of wafers (such as photoresist, oxidized surface, polycrystalline silicon, and dummy wafers) can be reduced to less than 5%, more It is better to reduce it to less than 2%. The stability of these etching rates is equivalent to an improvement of 5P% in order compared with the traditional processing process. ^ The stability of the etching rate can be improved with or without a stable coating. It is a processing chamber configuration with a low processing chamber capacitance below 300 pF, more preferably below 200 pF. With the improvements available according to the present invention, the etching process can be expected to be performed without the need to start production wafer production. , Execute the silicon adjustment wafer through the plasma chamber. (Please read the precautions on the back before filling this page) Installation -------- Order --------- line! Intellectual property of the Ministry of Economic Affairs Printed by the Bureau's Consumer Cooperatives-22- This paper is in use _ Home Standard (CNS) A4 Specification ⑽ 297 Gongchu 4 4692 3 A7 5 ---------- Description of Invention (2〇) Form II Crystal S Sequential Wafer Number Wafer Type 1 Polycrystalline Rare Rice Carving Rate 2 Bad Silicon / Adjustment 3 Adjustment 4-Adjustment 5 Adjustment 6 Polycrystalline Dream Rice Carving Rate 7 Photoresist Coating 8 Photosensitive Anti Money 9 Photosensitive Resist 10 Photoresist 11 Photoresist 12 Polycrystalline silicon etch rate processing parameters include the following: total pressure 10 mTorr, TCPTM power 350 watts, offset frequency power 100 watts, HBr flow rate 100seem, 012 flow rate 20 seem, ESC 8Torr Helium, 60 ° C, # tick duration 60 seconds. J I-^. —------ Order ----- I-- (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -23- This paper The scale is applicable to China Standard for Household Standards (CNS) A4 (210 X 297 mm) 43 692 3 B7 A7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (21) Form III First etching rate Second Etching rate third polycrystalline silicon change% polycrystalline chip change% polycrystalline sand etch rate etch rate etch rate wafer wafer wafer (# 1) (# 6) (# 12) standard open loop parameter polysilicon etch rate (A / min) Not measured 2127 -12.80% 1854 Total gas flow rate before RF (seem) 120 HBr flow rate during etching 100 100 100 During etching (: 12 flow rate 20 20 20 • VAT valve setting variable variable variable transmission ( Load) Voltage 136.6 127.7 139.4 Transmission (Load) Power (Watt) 60.5 61.8 60.4 Test (i), adjusted by 5: 1 (HBr + Cl2) Polysilicon Etching Rate (AAnin) 2027 0.25% 2032 -12.10% 1786 RF Front total gas flow rate (seem) 130 HBr flow rate during etching 111.4 90.4 105 Cl2 flow rate during etching 22.26 18.16 21 VAT valve setting 230 230 230 Transmission (load) voltage 135 128.4 136.4 Transmission (load) power (W) 54.5 58 54 , 2 Test (ii), Variable HBr + Cl2 Fixed flow rate 20 Seem Polycrystalline silicon etching rate (A / min) 2104 -0.38% 2096 -14.80% 1786 -24- ---------- II t- ------- Order --------- Line (Please read the back first! Please fill in this page before filling in this page) This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) ) 4 3 692 3: A7 B7 V. Description of Invention (22) Printed the first polycrystalline silicon etch rate wafer (# 1) by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, and the second polycrystalline etch rate was changed. Circle (# 6) Etching rate change% Third polycrystalline sand Etched wafer (# 12) Total gas flow rate before RF (_) 137 HBr flow rate during etching 104 89.1 106.4 Cl2 flow rate during etching 20 20 20 VAT valve setting 230 230 230 Transmission (load) voltage 134.5 127.2 136.1 Transmission ( Electricity (watt) 56.9 57.7 54.9 Test (iii), change Cl2 + HBr fixed flow rate 100 seem polycrystalline silicon etching rate (A / min) 2066 -11.60% 1826 3.50% 1890 total gas flow rate before RF (scon) 135 etching HBr flow rate 100 100 100 Cl2 flow rate at the time of erosion 20 5.9 32.1 VAT valve setting 230 230 230 Transmission (load) voltage 133.2 125.9 138 Transmission (load) power (W) 53.4 54.4 50.8 Test (iv), higher Pump speed Repeat step iii. Variable Cl2 + HBr flow rate is fixed at 100 seem Polycrystalline silicon etching rate (A / min) 2501 -20.70% 1982 5.10% 2083 Total gas flow rate before RF (seem) 153 HBr flow rate during etching 100 100 100 Cl2 'flow rate during etching 55 13 42 VAT valve setting 260 260 260 (Please read the precautions on the back before filling this page) -25- This paper size applies to China National Standard (CNS) A4 specifications < 210 X 297 mm) 436923-A7 __B7 V. Invention Explanation (23) The first polycrystalline chip with a low etch rate (# 1) The change in the etch rate% The second polycrystalline silicon with an etch rate wafer (# 6) The change in the etch rate% The third polycrystalline wafer with an etch rate wafer (# 12) Transmission (load) voltage 128.7 120.7 131.4 Transmission (load) power (W) 53.2 53.1 52.3 Test (V), only Cl2 is changed; HBr flow rate = 0 Polycrystalline silicon etching rate (A / min) 3057 1.84% 3114 -0.79% 3089 Total gas flow rate before RF (scan) 124 HBr flow rate during etching 0 0 0 Cl2 flow rate during etching 101 104 110 VAT valve setting 200 200 200 Transmission (load) voltage 130.6 133 136.3 Transmission (load) power (W) 54.8 53.7 54.6 The principle, preferred embodiments and operation modes of the application of the present invention have been described above. However, the invention is not so limited to the specific embodiments discussed. Therefore, the above specific embodiments should be regarded as illustrative rather than limiting, and it should be understood that those skilled in the art can change these specific embodiments without departing from the scope of the present invention as defined by the scope of the patent application below. (Please read the notes on the back before filling this page)

n U -δ -----:——:線 經濟部智慧財產局員工消费合作社印製 -26- 本紙張尺度適用令國國家標準(CNS)A4規格(210 χ 297公釐)n U -δ -----: ——: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs -26- This paper applies the national standard (CNS) A4 specification (210 χ 297 mm)

Claims (1)

8 88 8 ABCD 4 3 692 3 六、申請專利範圍 i .一種以最低蝕刻率變動連續處理個別半導體基體的方 法,其包括下列步驟: ---------裝— {請先閲讀背面之注意事項再填寫本頁) (a) 在電漿蝕刻室中’將半導體基體放在基體支撐 上; (b) 維持蝕刻室的真空; (c) 藉由供應蚀刻氣禮給蚀刻室並使蚀刻氣體通電以 於蝕刻室中形成電漿的方式蝕刻基體的暴露面; (d) 將基體從蝕刻室取出;以及 (e) 重複步騾(a-d)於蝕刻室中連續蝕刻額外的基體, 其中蝕刻步驟的實施係藉由保持一定量的活性氣體, 以足以使重複步驟(c)時所處理的每個基體獲得可重複 的蝕刻率之程度來與基體的暴露面相接觸。 2.如申請專利範圍第1項之方法’其中半導體基體包括一 多晶矽層’於步驟(c)時以HBr及<:12蝕刻該多晶矽。 3 ·如申請專利範圍第1項之方法,其中在步驟(c)中姓刻室 保持在100 mTorr以下的真空壓力,一真空泵浦會使該 蝕刻室形成真空’其中一調整閘閥係於步驟(c)中保持 在固定位置使真空泵浦與蝕刻室内部分開^ 4 .如申請專利範圍第1項之方法’其中在步驟(c)中該基體 經濟部智慧財產局員工消費合作社印製 支撐會將一 RF偏頻提供給基體。 5 .如申請專利範圍第1項之方法,其中蝕刻氣體的至少— 個組成之流率會在重複步驟(c)時増加。 6.如申請專利範圍第1項之方法,其中蝕刻氣體的至少— 個組成之流率會在步驟(c)時被調整以保持蝕刻室内的 -27- --~-—I 本紙張尺度適用中國B家標準(CNS ) A4規格(210 X 297公釐) A8 B8 C8 D8 4 3 S92 3 申請專利範圍 固定壓力。 7. 如申請專利範圍第Μ之方法,其中蚀刻氣體的至少一 個組成之流率係根據步驟⑷中㈣丨室内的—個或多個 活性物質的即時分析來調整。 8. 如申請專利範㈣Μ之方法,其中飽工或非跑工天線 使姑刻氣體通電進入電漿狀態,其中使用電介質部件 將天線與蝕刻室内部分開,其中該電介質部件至少會 與基體支撑共同擴張,而蚀刻室之電容約6〇{) #或以 下。 9. 如申請專利範圍第8項之方法’其中電介質部件包括聚 四乙烯塗層用於面向基體支撑,而處理室具有一處理 室電容約200 pF或以下。 10. —種電漿蝕刻裝置,其包括: 電漿蝕刻室,其内部具有一基體支撑,該蝕刻室包 括電介質部件用於面向基體支撐; 耽體供應,用於提供蚀刻氣體進入蚀刻室内部; 天線,其使用電介質部件與處理室内部分開,該天 線輸送能量給RF通過電介質部件並使蝕刻氣體通電進 入電漿狀態; 眞空泵浦,用於使處理室内部形成眞空,該眞空泵 浦使用調整閘閥與處理室内部分開;以及 控制器’用於保持一定量的活性氣體以足以在整批 基體的連續單一基體蚀刻期間獲得蝕刻室内所處理之 每個基體之可重複蝕刻率的程度’來與基體的暴露面 -28- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------------ --------訂---------線 I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 3 2 S 3 8 00 00 25 ABCD 經濟部智慧財產局員工消費合作社印製 六、申請專利範圍 相接觸。 11.如申請專利範園第1 〇項之電漿蝕刻裝置,其中該控制 器會連續調整蝕刻氣體的至少一個組成的進入蝕刻室 的流率。 I2·如申請專利範園第i 〇項之電漿蝕刻装置,其中該眞空 泵浦會保持蝕刻室内部的眞空壓力於100 mTorr以下, 且在整批基體的連續單一基體蝕刻期間在蝕刻每個蚀 刻室内所處理的基體時,該控制器會使該閘閥保持在 一固定位置。 13.如申請專利範圍第丨〇項之電漿蝕刻裝置,其中該基體 支撑包括電介質部件用於提供RF偏頻,在整批基體的 連續單一基體蚀刻期間在蚀刻每個轴刻室内所處理的 基體時,該控制器用於調整RF偏頻至每個基體。 i4·如申請專利範圍第i 〇項之電漿蝕刻裝置,其中該控制 器會在整批基體的連續單一基體蝕刻期間,調整蝕刻 氣體的一個或以上組件的流率爲比先前基體群所用流 率爲高的流率以用於後續的基體群。 15, 如申請專利範圍第丨〇項之電漿蝕刻裝置,其中該控制 器會在蝕刻基體時調整蝕刻氣體的一個或以上組成的 流率以提供蝕刻室内的固定眞空壓力。 16. 如申請專利範圍第1 〇項之電漿蝕刻裝置,其中該控制 益'會在蚀刻基體時根據蚀刻室内的一個或以上活性物 質的即時分析來調整蝕刻氣體的一個或以上的組成的 流率。 -29- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) ------------^--------訂---------線 I (請先閱讀背面之法意事項再填寫本頁) 4369^〇 ABCD 六、申請專利祀圍 17.如申請專利範圍第1 0項之電漿蝕刻裝置,其中該電介 質部件會至少與該基體支撐共同擴張,且該蝕刻室^ 有蝕刻室電容約600 pF或以下。 18‘如申請專利範圍第1 7項之電漿蝕刻裝置,其中該電介 質部件包括聚四乙烯塗層用於面向該基體支撐,該触 刻室具有蝕刻室電容約200 pF或以下。 19.如申請專利範園第1 〇項之電漿蝕刻裝置,其中在蝕刻 個別基體時’該控制器會在該真空泵浦的固定栗浦速 度下維持該蚀刻室内的固定壓力。 20_如申請專利範圍第1〇項之電漿蝕刻裝置,其中具有多 晶矽層的基體會被支撐在基體支撐上,該氣體供應會 以可調流率提供HBr與Ch至蝕刻室内,其中控制器用於 控制真空泵浦保持固定泵浦速度、控制該閘閥保持固 定位置、控制該氣體供應以固定流率保持HBr的流率、 及控制該氣體供應改變足量的Cl2流率以補償該蝕刻室 内牆壁對蝕刻氣體活性物質的吸收作用。 ---- - II - I , -----1 n n -、订 (請先閲讀背面之注意事項再填寫本頁} 經濟部智慧財產局員工消费合作社印製 -30- 未紙張尺度逋用中國围家揉準(CNS ) A4洗格(210X:297公釐)8 88 8 ABCD 4 3 692 3 VI. Scope of Patent Application i. A method for continuously processing individual semiconductor substrates with the lowest etching rate variation, including the following steps: --------- 装 — {Please read the back first Note: Please fill in this page again.) (A) 'Place the semiconductor substrate on the substrate support in the plasma etching chamber; (b) Maintain the vacuum of the etching chamber; (c) Supply the etching chamber with the etching gas and make The etching gas is energized to etch the exposed surface of the substrate in a manner to form a plasma in the etching chamber; (d) removing the substrate from the etching chamber; and (e) repeating steps (ad) continuously etching additional substrates in the etching chamber, wherein The etching step is performed by maintaining a certain amount of active gas in contact with the exposed surface of the substrate to a degree sufficient to obtain a repeatable etching rate for each substrate processed in the step (c). 2. The method according to item 1 of the patent application scope, wherein the semiconductor substrate includes a polycrystalline silicon layer, and the polycrystalline silicon is etched with HBr and <: 12 in step (c). 3. The method according to item 1 of the scope of patent application, wherein in step (c), the engraving chamber is maintained at a vacuum pressure below 100 mTorr, and a vacuum pump will cause the etching chamber to form a vacuum. One of the adjustment gate valves is in step ( c) Keep the vacuum pump and etching chamber partly open at a fixed position ^ 4. As in the method of applying for the scope of patent No. 1 'wherein in step (c), the Intellectual Property Bureau of the Ministry of Economic Affairs, the employee's consumer cooperative printed support will An RF offset frequency is provided to the substrate. 5. The method of claim 1 in which the flow rate of at least one composition of the etching gas is increased when step (c) is repeated. 6. The method according to item 1 of the patent application scope, wherein the flow rate of at least one component of the etching gas is adjusted in step (c) to maintain -27 in the etching chamber. --- This paper size applies China B standard (CNS) A4 specification (210 X 297 mm) A8 B8 C8 D8 4 3 S92 3 Patent application scope fixed pressure. 7. The method according to the scope of patent application, wherein the flow rate of at least one composition of the etching gas is adjusted according to the real-time analysis of one or more active materials in the chamber in step (i). 8. For the method of patent application, the saturated or non-running antenna energizes the engraved gas into the plasma state. The dielectric part is used to separate the antenna from the etching chamber. The dielectric part is at least shared with the substrate support. Expansion, and the capacitance of the etching chamber is about 60 () # or less. 9. The method according to item 8 of the patent application, wherein the dielectric member includes a polytetraethylene coating for supporting the substrate, and the processing chamber has a processing chamber capacitance of about 200 pF or less. 10. A plasma etching device, comprising: a plasma etching chamber having a substrate support therein, the etching chamber including a dielectric component for supporting the substrate; a body supply for supplying an etching gas into the interior of the etching chamber; An antenna, which is separated from the processing chamber using a dielectric component, which transmits energy to the RF through the dielectric component and energizes the etching gas into the plasma state; a vacuum pump is used to form a vacuum inside the processing chamber. The vacuum pump is adjusted by using The gate valve is partially open from the processing chamber; and the controller 'is used to maintain a certain amount of reactive gas to a degree sufficient to obtain a repeatable etch rate for each substrate processed in the etching chamber during the continuous single substrate etching of the entire batch of substrates' The exposed surface of the substrate-28- This paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ------------ -------- Order --- ------ Line I (Please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 3 2 S 3 8 00 00 25 ABCD Cooperative six printing, contact patent scope. 11. The plasma etching device according to item 10 of the patent application park, wherein the controller continuously adjusts the flow rate of at least one component of the etching gas into the etching chamber. I2. The plasma etching device according to item i 0 of the patent application park, wherein the vacuum pump keeps the vacuum pressure inside the etching chamber below 100 mTorr, and etches each of the substrates during the continuous single substrate etching of the entire batch. The controller keeps the gate valve in a fixed position while etching the substrate being processed in the chamber. 13. The plasma etching device according to the scope of the patent application, wherein the substrate support includes a dielectric component for providing RF offset frequency, and is processed in each shaft etch chamber during continuous single substrate etching of the entire batch of substrates. For bases, this controller is used to adjust the RF offset to each base. i4. If the plasma etching device of item i 0 of the patent application scope, the controller adjusts the flow rate of one or more components of the etching gas during the continuous single substrate etching of the entire batch of substrates than the flow used by the previous substrate group. The rate is high for subsequent matrix groups. 15. For example, the plasma etching device according to the scope of the patent application, wherein the controller adjusts the flow rate of one or more components of the etching gas when the substrate is etched to provide a fixed vacuum pressure in the etching chamber. 16. For example, the plasma etching device of claim 10, wherein the control device will adjust the flow of one or more components of the etching gas according to the instant analysis of one or more active materials in the etching chamber when the substrate is etched. rate. -29- This paper size applies to China National Standard (CNS) A4 specification (210 X 297 public love) ------------ ^ -------- Order ------ --- Line I (please read the legal notices on the back before filling in this page) 4369 ^ 〇 ABCD VI. Patent Application Scenario 17. If you apply for a plasma etching device with the scope of patent application No. 10, the dielectric part will Co-expand at least with the substrate support, and the etching chamber has an etching chamber capacitance of about 600 pF or less. 18 ′ As in the plasma etching device of claim 17 in the scope of patent application, wherein the dielectric member includes a polytetraethylene coating for supporting the substrate, the etching chamber has an etching chamber capacitance of about 200 pF or less. 19. The plasma etching device according to item 10 of the patent application park, wherein when the individual substrate is etched, the controller maintains a fixed pressure in the etching chamber at a fixed pumping speed of the vacuum pump. 20_ If the plasma etching device of the scope of patent application No. 10, the substrate having a polycrystalline silicon layer will be supported on the substrate support, and the gas supply will provide HBr and Ch to the etching chamber at an adjustable flow rate, where the controller is used Control the vacuum pump to maintain a fixed pump speed, control the gate valve to maintain a fixed position, control the gas supply to maintain a HBr flow rate at a fixed flow rate, and control the gas supply to change a sufficient amount of Cl2 flow rate to compensate for the wall in the etched room. Absorption effect of etching gas active material. -----II-I, ----- 1 nn-、 Order (Please read the notes on the back before filling this page} Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy -30- Not used on paper China Weijiazhuang Standard (CNS) A4 Washer (210X: 297mm)
TW88121794A 1998-12-30 1999-12-13 Method and apparatus for etch rate stabilization TW436923B (en)

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