經漓部中央標準局員工消費合作社印策 436717 A7 _________B7 五、發明説明（1 ) 發明領域 本發明大致關於積體電路設計之領域，特別是包含在 使用預定模組的積體電路中的記憶體¥設計。 發明背景 資料處理系統需要漸多的高效能記憶體次系統以提供 由系統設計限制所設下的資料儲存及資料流通。例如圖像 控制器需要與日倶增的大量記憶體。工作於高頻之下，以 支援高解像度顯示及複雜的圖像表現功能。 使用超大型積體電路（VL S I )的積體電路（ I C s )的漸增的容量容許先前由數個分離晶片所達成的 功能被內建於單一晶片中。其可提供顯著的性能增進以及 增加可靠度及較低的系統成本。將記憶體內建於存取該記 憶體的相同晶片可提供類似的優點。 電子設計自動化（EDA)系統一般被用以設計I C 。這種系統容許設計者在IC的製造之前指定並模擬設計 的作業。E D A系統的許多功能中還包括將記憶體倂入具 有許多不同功能元彳牛的一 I C中之功能。 不幸的是，已知的設計系統僅提供有限數量的可被倂 入一設計中的D R A Μ記憶體。其結果爲I C設計可能必 需作妥協或改變與可得的DRAM記憶體的尺寸配合。例 如，一較所需爲大的D R A Μ模組可能必需被採用。其結 果爲DRAM的一部份，也就是I C的一部份，將爲無用 ’使原先可能作其它用途的晶片空間被浪費。或者，設計 - - ^^1 d I 士^m 1^1 (請先閲讀背面之注意事項再填寫本頁). 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公嫠）-4 - Λ3 67 ^ A7 ___B7___ 五、發明説明（2 ) 可能被改變以使用可得的D R A Μ，但如此導致因容許可 得的D R AM模組的尺寸操控I C的其它部設計而使設計 變得複雜。因此，需要一種用以將D RAM併入一積體電 路設計中的一改良系統及方法。 發明槪述 本發明有利地促使D R A Μ倂入一積體電路設計中。 在本發明一-主旨中，多數個預定模組被提供以容許由I C 設計者以選擇適當的模組以設計一具有由設計者所指定的 容量及功能特性的D R A Μ。藉此方式，本發明的實施例 有利地容許一 I C設計者將一 D R A Μ，其達到特定設計 的需求，設計於一 I c中，而非強迫設計者改變I c的設 計或使用額外的晶片空間以便使用特殊的預定D RAM模 組° 在一較佳實施例中，一 EDA系統被提供，其包含多 數個可由I C設計者選擇以指定一I C晶片的DRAM的 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 預定模組。預定模組可包括多.數個可被群組化爲不同構型 以便指定出具有由設計者所指定的列’行數及字長度的 D RAM的核心細胞。該預定模組亦可包括多數個額外模 組以指定包括列及行地址輸入線’一寫入致能輸入線’一 時鐘信號輸入線及資料輸入及輸出線的完備dram。此 額外模組可包括列及行解碼器以分別對由模組所接收的列 及行地址作解碼’位元線感應放大器以將資料儲存至及復 原自核心細胞，地址緩衝器’輸入/輸出緩衝器及其它電 本纸張尺度適用中國囤家橾準（CNS M4規格（21 Ox 297公釐} - 5 - 4367 1 A7 B7 五、發明説明（1 2 3 ) 路測試及重複邏輯。 本發明的這些及其它功能及優點可藉由考慮以下的本 發明的較佳實施例的詳細敘述而更爲了解。在此敘述中， 將經常參照所附的圖式。 圖式的槪要敘述 圖1爲一積體電路的一高階方塊.圖， 圖2铵採用本發明的主旨的一電子設計自動化（ E DA)系統的一方塊圖：以及 圖3爲依照本發明的主旨所建構的一動態隨機存取記 憶體（D R A Μ )的一方塊圖。 經濟部中央標準局員工消費合作社印製 主要元件對照表 10 0 10 2 10 4 10 6 10 8 2〇〇 2 0 2 2 0 4 2 0 6 2 0 8 2 1〇 (請先聞讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家棣準（CNS ) A4規格（210X297公釐）-6 - 1 C晶片 輸入/輸出電路 組合及序列邏輯 2 靜態記憶體 動態隨機存取記憶體 電子設計自動化系統 處理器 3 E D Α處理器 儲存裝置 顯不器 輸入裝置 經濟部中央標準局員工消費合作社印製 436717五、發明説明（4 ) 2 1 2 2 1 4 2 15 2 16 2 1 8 2 2 0 2 2 2 2 2 4 - 2 2 6 2 2 8 3 0 2 303.1 〜303.8 304a,304b,304a',304b' 3 1〇 310a,310b,310a',310b' 3 16 3 18 3 14 3 0 4 A7 B7 模組 D R A M模組 其它模組 模組 字線感應放大器驅動器模組 輸入一輸出 /〇）模組 雜項模組 行解碼器模組 列解碼器模組 .字線感應放大器模組 DRAM 次模組 Core — 256 細胞 行解碼器 B L S A I / 0細胞 Μ I S C細胞 列解碼器 核心細胞 較佳實施例的詳細敘述 圖1顯示一電路的高階方塊圖，該電路可被包含於依 照傳統的超大型積體電路（VL S I )技術所設計及建構 的一積體電路（1C)中。1C記億體100包括用以接 ^^^1· ^^^^1 ^^^^1 ^^^^1 fl^il nfe ^^^^1 脅 、τ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐）-7 - A7 B7 4367 1 7 五、發明説明（5 ) 收傳送至晶片的信號及用以自晶片傳送信號的輸入/輸出 電路。組合及序列邏輯1 〇 4將控制功能及/或路徑設定 於晶片中。將資料儲存於晶片中可由靜態記憶體1 〇 6或 動態隨機存取記憶體（DRAM) 108所執行。靜態記 憶體1 0 6可爲例如正反器1閂’或採用靜態隨機存取記 憶體（S R A Μ )陣列的較高密度記憶體等不同型式之一 。DRAM1 0 8可被用.以在'稍微低之速率在晶片的給定 區域上達成一較S RAM爲高之儲存密度° 本發明的較佳實施例有利地提供多數個可由1 c晶片 的設計者選擇以依照I C晶片1 0 0所要的規格而設計 DRAM1 〇 8的預定模組。圖2顯示採用本發明的主旨 的一電子設計自動化（EDA)系統200的方塊圖。處 理器2 0 2執行一儲存於儲存裝置2 0 6中的EDA程式 2 0 4。EDA程式2 0 4提供顯示用的輸出至一EDA 程式2 0 4的使用者於一顯示器2 0 8上並經由一個或多 個傳統輸入裝置2 1 0自使用者接收使用者的輸入。 處理器亦可採用諸如由Sun Microsystems，Mountain View，加州，所出售的Sparc工作站的商業上可得的以一 般目的程式的電腦之形式。此工作站亦可使甩傳統輸入裝 置¢210)，顯示器（208)及儲存裝置（206) 。E D A 程式亦可採用由 Viewlogic Corportation, Marlboro ，麻州所售出的商業可得的軟體包裝之形式。此系統包括 諸如輪廓補捉，邏輯模擬，測試向量及波形產生’及設置 及定路徑等不同功能，以協助並簡化I C設計工作。 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）-8 - I--------'裝------訂-----Γ線 (請先閎讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 A7 d367 ^ ____B7_ 五、發明説明（6 ) 摸組212包括多數個DRAM模組214及其它可 被I C設計者所選擇以指定I C的功能特性的其它模組2 1 5。模組2 1 5代表用以產生諸如於圖1中之1 〇 2， 1 0 4或1 0 6中所見的電路的預定模組。特別是，模組 2 1 6可被設計者採用以藉由適當選擇預定組合，序列及 儲存電路以設置一 I C晶片的輸入/輸出電路及設計晶片 所執行的功能。在一較佳實施例中，模組2 1 2採用由前 述的E D A-系統藉由編輯以前述商業可得的輪廓捕捉包裝 的方式輸入的電路設計所產生的標準格式SPICE/Netlist的 形式。 D R A Μ模組2 1 4有利地併用多數個模組以容許將 諸如圖1中的1 0 8中所見的一 DRAM裝配於I C晶片 1 0 ◦。D R A Μ模組2 1 4中包括核心細胞模組2 1 6 ，位元線感應放大器驅動器（B S D )模組2 1 8 ’輸入 —輸出（I / 0 )模組2 2 0，雜項（Μ I S C )模組 222，行解碼器224，列解碼器226及位元線感應 放大器（BLSA)模組228。 核心細胞模組216提供多數個可被單獨或與其它核 心細胞陣列組合使用的核心細胞陣列以藉由E D Α系統 2 〇 〇的方式構建一 D R A Μ模組。該核心細胞被利地設 計以容許在一單一 D R A Μ模組中的核心細胞的多種組合 。如此容許I C設計者指定具有設計所需的尺寸及組織的 I C晶片所需的一 DRAM。在一較佳實施例中’設有如 下的三種核心細胞的密度及字長度： I. K ! - : - - . - -- - I · - -- I : , . ^^1 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙浪尺度適用中國國家標準（CNS ) A4规格（2[〇X297公釐） -9- d367 ^ A7 B7 五、發明説明（ 核心細胞 Core Core Core 2 5 6 2 2 4 19 2 列/行 2 5 6 / 2 5 6 2 2 4 / 2 5 6 1 9 2 / 2 5 6 經濟部中央標隼局貝工消費合作杜印製 核心細胞可爲採用一傳統每一細.胞具有單一電容，單 一電晶體的·傳統設計。 BSD模組218將信號控制爲BLSA228。 B S D模組2 1 8具有一與B L SA模組2 2 8之一對一 對應關係。在一較佳實施例中BSD模組218包含如下 所述的對應至B L S A模組2 2 8中之電路的個別電路。 I /〇模組2 2 0運作以藉由於讀取作業中感應一來 自BLSA228的信號並將該信號轉換至一33伏或 5伏信號，並在一寫入作業中，將一3·3或5伏信號轉 換至一具有由B L SA 2 2 8,所使用之特性的信號，而將 進入及輸出自BL SA細胞2 2 8的信號作緩衝。在一較 佳實施例中，I / 0模組2 2 0可爲例如一位元，二位元 或四位元寬。 雜項模組2 2 2設置各種不同的支援電路，諸如列及 行地址輸入緩衝器，用以產生DRAM電路所需的諸如在 DRAM模組中的字線的高電壓（Vu)，一背向偏壓（ VBB)及一細胞板電壓（V«：b)等之特定電壓的電壓產生 器。雜項模組2 2 2亦包括測試電路以容許D R A Μ模組 ^^^1 ^^^1 ^^^1 ^^^1 ^^^1 .^n 1 __ (請先閲讀背面之注意事項再填寫太頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）-10 -The Ministry of Central Standards Bureau ’s Consumer Cooperative Cooperative Mark 436717 A7 _________B7 V. Description of the Invention (1) Field of the Invention The present invention relates generally to the field of integrated circuit design, especially the memory included in the integrated circuit using predetermined modules. ¥ Design. BACKGROUND OF THE INVENTION Data processing systems require increasing numbers of high-performance memory subsystems to provide data storage and data circulation set by system design constraints. For example, the image controller needs a large amount of memory to increase with the sun. Work under high frequency to support high-resolution display and complex image expression functions. The increasing capacity of integrated circuits (ICs) using very large integrated circuits (VLSI) allows functions previously achieved by several discrete chips to be built into a single chip. It can provide significant performance improvements as well as increased reliability and lower system costs. Building the memory in the same chip that accesses the memory provides similar advantages. Electronic design automation (EDA) systems are commonly used to design ICs. This system allows the designer to specify and simulate the design work before the IC is manufactured. Many of the functions of the E DA system also include the function of storing memory into an IC with many different functions. Unfortunately, known design systems provide only a limited amount of DR A M memory that can be incorporated into a design. As a result, IC designs may need to be compromised or changed to match the size of available DRAM memory. For example, a larger D R AM module may be necessary. The result is a part of the DRAM, that is, a part of the IC, which will be useless, so that the chip space that might have been used for other purposes is wasted. Alternatively, design--^^ 1 d I 士 ^ m 1 ^ 1 (Please read the precautions on the back before filling out this page). This paper size applies the Chinese National Standard (CNS) A4 specification (210X297mm)-4- Λ3 67 ^ A7 ___B7___ 5. Description of the Invention (2) It may be changed to use the available DRA M, but this leads to the complexity of the design by allowing the size of the available DR AM module to control other parts of the IC. Therefore, there is a need for an improved system and method for incorporating D RAM into an integrated circuit design. SUMMARY OF THE INVENTION The present invention advantageously facilitates the integration of DRMA into a integrated circuit design. In the first aspect of the present invention, a plurality of predetermined modules are provided to allow an IC designer to select an appropriate module to design a DR A M having the capacity and functional characteristics specified by the designer. In this way, embodiments of the present invention advantageously allow an IC designer to design a DRA M that meets the requirements of a specific design and design it in an I c instead of forcing the designer to change the design of I c or use additional chips Space to use special pre-defined D RAM modules. In a preferred embodiment, an EDA system is provided that contains a number of DRAMs that can be selected by the IC designer to designate an IC chip. The Central Standards Bureau Employee Consumer Cooperative Printed (please read the notes on the back before filling this page) to order the module. The predetermined module may include a plurality of core cells that can be grouped into different configurations so as to specify a D RAM having a column number, a row number, and a word length specified by a designer. The predetermined module may also include a plurality of additional modules to specify a complete dram including column and row address input lines 'a write enable input line', a clock signal input line, and a data input and output line. This additional module may include column and row decoders to decode the column and row addresses received by the module, respectively, and a bit line sense amplifier to store and restore data to and from core cells, address buffers, input / output. Buffers and other electronic paper sizes are applicable to Chinese storehouse standards (CNS M4 specifications (21 Ox 297 mm)-5-4367 1 A7 B7 V. Description of the invention (1 2 3)) Road test and repetitive logic. The present invention These and other functions and advantages can be better understood by considering the following detailed description of the preferred embodiments of the present invention. In this description, reference will always be made to the accompanying drawings. Schematic description of Figure 1 Is a high-level block diagram of an integrated circuit. FIG. 2 is a block diagram of an electronic design automation (EDA) system using the subject matter of the present invention: and FIG. 3 is a dynamic random structure constructed in accordance with the subject matter of the present invention. A block diagram of the memory access (DRA M). The comparison table of the main components printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 10 0 10 2 10 4 10 6 10 8 2 200 2 0 4 2 0 6 2 0 8 2 1〇 (Please read the note on the back first Please fill in this page again for this matter) This paper size is applicable to China National Standard (CNS) A4 specification (210X297mm) -6-1 C chip input / output circuit combination and sequence logic 2 Static memory dynamic random access memory electronic design Automation system processor 3 ED Α processor storage device display device input device printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy 436717 5. Invention Description (4) 2 1 2 2 1 4 2 15 2 16 2 1 8 2 2 0 2 2 2 2 2 4-2 2 6 2 2 8 3 0 2 303.1 ~ 303.8 304a, 304b, 304a ', 304b' 3 1〇310a, 310b, 310a ', 310b' 3 16 3 18 3 14 3 0 4 A7 B7 module DRAM module other module module word line induction amplifier driver module input one output / 0) module miscellaneous module row decoder module column decoder module. Word line induction amplifier module DRAM sub module Core — 256-cell row decoder BLSAI / 0 cell M ISC cell column decoder core cell detailed description of a preferred embodiment of the core cell Figure 1 shows a high-level block diagram of a circuit that can be included in a conventional ultra-large integrated circuit (VL SI) Technology Design and Construction In a integrated circuit (1C). The 1C memory module 100 includes ^^^ 1 · ^^^^ 1 ^^^^ 1 ^^^^ 1 fl ^ il nfe ^^^^ 1 τ (Please read the notes on the back before filling in this page) This paper size applies to Chinese National Standard (CNS) A4 specification (210 × 297 mm) -7-A7 B7 4367 1 7 V. Description of the invention (5) Received and transmitted to the chip Signals and input / output circuits for transmitting signals from the chip. The combination and sequence logic 104 sets control functions and / or paths in the chip. The storage of data in the chip can be performed by static memory 106 or dynamic random access memory (DRAM) 108. The static memory 106 can be one of different types such as flip-flop 1 'or a higher density memory using a static random access memory (SR A M) array. DRAM 108 can be used at a slightly lower rate to achieve a higher storage density than S RAM at a given area of the wafer. The preferred embodiment of the present invention advantageously provides a number of designs that can be processed by 1 c chips. The user chooses to design a predetermined module of the DRAM 10 in accordance with the specifications required for the IC chip 100. FIG. 2 shows a block diagram of an electronic design automation (EDA) system 200 employing the subject matter of the present invention. The processor 2 0 2 executes an EDA program 2 0 4 stored in the storage device 2 06. The EDA program 204 provides display output to a user of the EDA program 204 on a display 208 and receives user input from the user via one or more conventional input devices 2 10. The processor may also take the form of a general purpose computer such as the Sparc workstation sold by Sun Microsystems, Mountain View, California. This workstation can also use traditional input devices (210), displays (208), and storage devices (206). The E D A program may also take the form of a commercially available software package sold by Viewlogic Corportation, Marlboro, Mass. This system includes different functions such as contour capture, logic simulation, test vector and waveform generation, as well as settings and routing to assist and simplify IC design. This paper size applies to Chinese National Standard (CNS) A4 specification (210X297 mm) -8-I -------- 'installation ------ order ----- Γ line (please read first Note on the back, please fill in this page again.) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 d367 ^ ____B7_ V. Description of the invention (6) The touch group 212 includes a plurality of DRAM modules 214 and other components that can be selected by the IC designer. Other modules that specify the functional characteristics of the IC 2 1 5. Module 2 1 5 represents a predetermined module for generating a circuit such as that seen in FIG. 1, 102, 104 or 106. In particular, the module 2 16 can be used by a designer to set the input / output circuits of an IC chip and design the functions performed by the chip by appropriately selecting predetermined combinations, sequences, and storage circuits. In a preferred embodiment, the module 2 1 2 is in the form of a standard format SPICE / Netlist generated by the aforementioned ED A-system by editing a circuit design input in the manner of the aforementioned commercially available outline capture package. The D R A M module 2 1 4 advantageously uses a plurality of modules in combination to allow a DRAM such as that seen in 108 in FIG. 1 to be mounted on the IC chip 10. DRA Μ module 2 1 4 includes core cell module 2 1 6, bit line sense amplifier driver (BSD) module 2 1 8 'input-output (I / 0) module 2 2 0, miscellaneous (Μ ISC ) Module 222, row decoder 224, column decoder 226, and bit line sense amplifier (BLSA) module 228. The core cell module 216 provides a plurality of core cell arrays that can be used alone or in combination with other core cell arrays to construct a DR A M module by the ED A system 2000. The core cells are advantageously designed to allow multiple combinations of core cells in a single DRAM module. This allows IC designers to specify a DRAM required for IC chips with the size and organization required for design. In a preferred embodiment, 'the following three core cell densities and word lengths are provided: I. K!-:--.---I ·--I:,. ^^ 1 (Please read first Note on the back, please fill out this page again.) The paper printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs applies the Chinese National Standard (CNS) A4 specification (2 [〇X297mm) -9- d367 ^ A7 B7 V. Description of the invention (Core Core Core 2 5 6 2 2 4 19 2 Columns / Rows 2 5 6/2 5 6 2 2 4/2 5 6 1 9 2/2 5 6 The core cell can be a traditional design where each cell has a single capacitor and a single transistor. The BSD module 218 controls the signal to BLSA228. The BSD module 2 1 8 has a BL SA module 2 2 One-to-one correspondence relationship of 8. In a preferred embodiment, the BSD module 218 includes individual circuits corresponding to the circuits in the BLSA module 2 2 8 as described below. The I / 〇 module 2 2 0 operates to borrow Since a signal from the BLSA228 is sensed during a read operation and converted to a 33 volt or 5 volt signal, a The 3 · 3 or 5 volt signal is converted to a signal having the characteristics used by BL SA 2 2 8 and the signals entering and output from BL SA cells 2 2 8 are buffered. In a preferred embodiment, The I / 0 module 2 2 0 can be, for example, one-bit, two-bit, or four-bit wide. Miscellaneous modules 2 2 2 are provided with various supporting circuits such as column and row address input buffers to generate DRAM. Voltage generators with specific voltages such as the high voltage (Vu) of the word line in the DRAM module, a back bias (VBB), and a cell plate voltage (V «: b). Miscellaneous mode Group 2 2 2 also includes test circuits to allow DRA Μ modules ^^^ 1 ^^^ 1 ^^^ 1 ^^^ 1 ^^^ 1. ^ N 1 __ (Please read the notes on the back before filling in Page) This paper size is applicable to China National Standard (CNS) A4 (210X297mm) -10-
4367 W A7 B7 五、發明説明（8 ) 的測試，重複電路以容許在DRAM1 〇 8的製造中之缺 陷，及其它諸如諸出致能及寫入致能電路的雜項控制邏輯 〇 列解碼器2 2 6自Μ I S C細胞中的地址輸入緩衝器 接收地址線並將地址線解碼以選擇在一 D R A Μ模組的每 一核心細胞中的多數列中之一。在一讀取作業中，在所選 列中的每一位元被讀出至適當B L S.A細胞2 2 8中。在 一讀取作業·中*在B L S Α細胞2 8中的每一位元被寫入 至所選的列。列解碼器模組2 2 6宜選擇2 5 6列中之一 〇 行解碼器2 2 4自包含於Μ I S C細胞中的地址輸入 緩衝器接收行地址線並將地址線解碼以選擇儲存於B L S Α細胞2 2 8中的位元之一。在一較佳實施例中，行解碼 器模組2 2 4爲2 5 6位元寬。 B L S A模組2 2 8當作一在寫入作業中儲存資料至 核心細胞中且在讀取作業中自核心細胞讀取資料的中間緩 衝器。BLSA模組228相應於一列中的每一行具有一 個別位元線感應放大器電路，如此，在一較佳實施例中 B L SA模組2 2 8具有相應於行解碼器模組2 2 4的 2 5 6位元的每一位元的電路。 敘述於此的每一模組2 1 2可採用傳統形式，除非此 間另有指定。4367 W A7 B7 5. Test of Invention Description (8), repeating the circuit to allow for defects in the manufacture of DRAM1 08, and other miscellaneous control logic such as enabling and writing enabling circuits. Column decoder 2 The 26 receives the address line from the address input buffer in the M ISC cell and decodes the address line to select one of a plurality of columns in each core cell of a DRA M module. In a read operation, each bit in the selected column is read into the appropriate BL S.A cell 2 2 8. In a read operation *, each bit in BL S A cell 28 is written to the selected column. The column decoder module 2 2 6 should select one of the 2 5 6 columns. The row decoder 2 2 4 receives the row address lines from the address input buffer contained in the M ISC cell and decodes the address lines to be selectively stored in the BLS. One of the bits in A cells 2 2 8. In a preferred embodiment, the row decoder module 2 2 4 is 2 56 bits wide. The B L S A module 2 2 8 acts as an intermediate buffer that stores data in the core cells during a write operation and reads data from the core cells during a read operation. The BLSA module 228 has a bit line sense amplifier circuit corresponding to each row in a column. Thus, in a preferred embodiment, the BL SA module 2 2 8 has 2 corresponding to the row decoder module 2 2 4 5 6-bit per-bit circuits. Each module 2 1 2 described herein may be in a conventional form unless otherwise specified herein.
圖3顯示依照本發明的主旨所設計的一D R AM 3 0 2。該DRAM3 0 2包括八個相同的次模組 本纸诔尺度適用中國國家橾準（CNS ) A4規格（210 X 297公釐）-11·FIG. 3 shows a D R AM 3 0 2 designed in accordance with the spirit of the present invention. The DRAM3 0 2 includes eight identical sub-modules. The paper size is applicable to China National Standards (CNS) A4 specifications (210 X 297 mm) -11 ·
In - - ^^1 ^^1 - 1- - -- 士穴 -- II - - ^^1 In -5 (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 4367 1 Α7 Β7 經濟部中央標準局負工消費合作社印製 五、發明説明（9 ) 3〇3. 1 ’ 303 . 2 ’ …，303. 8。該 DRAM 3 0 2亦包括一Μ I S C細胞3 1 8及一對行解碼器 32〇 . 1及320 . 2 ’其分別各對應於四個次模組 303.1 -303. 4 及 303. 5- 303.8。 每一次模組303包括表示爲304a ，3〇4b， 3〇4a —及304b 一的Core — 256細胞的四個 核心細胞。核心細胞3 0 4 a及3 0. 4 a >共用一共同 BSD 3-12a及一列解碼器314a。核心細胞 304b及304b '被相似地與BSD 312b及列 解碼器3 1 4 b —起設置。每一核心細胞具有一相關的對 應 BLSA310 (表示爲 310a ，31〇a 一， 310b，310b >) 。一 I/O細胞相關於核心細胞 304a及304b，而一 I/O細胞316>相關於核 心細胞304a >及304 一。I/O細胞3 16決定自 每一核心細胞取回的字的寬度。1位元寬之一 I/0細胞 導致自每一核心細胞讀出一位元，其意謂著有1 6位元自 D R A Μ 3 0 2被一次讀出。 模組2 1 4可以多種方式組合以創造不同的儲存容S 及字寬度。此種儲存容量及字寬度的一例子可如以T之表 1所示： 本纸浪尺度適用中國國家標率（CNS ) Α4規格（210X297公釐）-12 - ^—^1 — n n ϋ — — ^ 裝—f (請先閱讀背面之注意事項再填寫本頁)In--^^ 1 ^^ 1-1---Shixue-II--^^ 1 In -5 (Please read the precautions on the back before filling out this page) System 4367 1 Α7 Β7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives V. Invention Description (9) 30.3.1 '303. 2'…, 303.8. The DRAM 3 02 also includes one M ISC cell 3 1 8 and a pair of row decoders 30.1 and 320.2 'which respectively correspond to four sub-modules 303.1-303.4 and 303.5-303.8. . Each module 303 includes four core cells represented as 304a, 304b, 304a— and 304b—Core—256 cells. The core cells 3 0 4 a and 30. 4 a > share a common BSD 3-12a and a row of decoders 314a. Core cells 304b and 304b 'are similarly set up with BSD 312b and column decoder 3 1 4b. Each core cell has an associated corresponding BLSA310 (denoted as 310a, 31〇a, 310b, 310b >). An I / O cell is associated with core cells 304a and 304b, and an I / O cell 316 > is associated with core cells 304a > and 304-1. I / O cells 3 16 determine the width of the words retrieved from each core cell. One I / 0 cell that is one bit wide results in one bit being read from each core cell, which means that 16 bits are read at one time from DR A M 3 02. Modules 2 1 4 can be combined in various ways to create different storage capacities S and word widths. An example of such storage capacity and word width can be shown in Table 1 of T: The scale of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -12-^ — ^ 1 — nn ϋ — — ^ 装 —f (Please read the notes on the back before filling out this page)
，1T, 1T
4367 W A7 B7 五、發明説明（10 ) 記憶體類 型 雜項模組 行解碼器 列解碼器 核心細胞 位元線感 應放大器 位元線感 應放大器 驅動器 輸入/輸丨 64kx32: misc col 一 64 row_256 core—256 bis a一2 bsd_2 iol. _256 32kx64: misc col一64 row 一 256 core 一 256 blsa_2 bsd_2 iol. 256 56kx32: misc col一64 row_224 core—224 blsa_2 bsd_2 iol. 224 28kx64; misc col 一 64 row_224 core 一224 blsa_2 bsd_2 iol· 224 48kx32: misc col—64 row_192 core 一 192 blsa_2 bsd_2 iol· _192 24kx64: misc col_64 row 一 192 core一 192 blsa 一 2 bsd_2 iol. J92 32kx64: misc col_64 row_256 core 一256 blsa一 2 bsd_2 iol. 256 I6kxl28: misc col 一 64 row 一 256 core一256 blsa一2 bsd_2 iol· 256 28kx64: misc coi_64 row 一 224 core 一 224 b[sa一 2 bsd_2 iol. •224 14kxl28: misc col 一64 row一224 core_224 blsa—2 bsd_2 iol_ .224 24kx64; misc col一64 row一 192 core 一 192 blsa 一 2 bsd_2 iol_ .192 12b(128: misc col_64 row_192 core一 192 blsa一 2 bsd_2 iol_ .192 ---------^ ! (請先Η讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 表1 在表1中，最左行（類型）以深度及字寬度定義一 DRAM302，如此記憶體類型64kx32 i具有 6 4 k位置之深度且一次可被.寫入至或讀出自3 2位元。 DRAM 3 0 2的十二種類型的每一種使用相同的 Μ I S C模組2 2 2，相同的行解碼器模組2 2 4，相同 的BLSA228及相同的BSD218。行解碼器模組 224 (co 1_64)自64行中選一，而每一模組 本紙張又度適用中國國家標準（CMS > Α4規格（2丨Ο X 297公釐）-13- A7 4367 1 7 B7___ 五、發明説明（11 ) 2 2 4函蓋2位元線對。列解碼器模組2 2 6及1//〇模 組2 2 0因所選的核心細胞而變動。持別是’在核心細胞 中的列數量決定列解碼器核心細胞2 2 6的寬度及I /◦ 模組2 2 0的寬度。例如’具有2 5 6列的Core _ 2 5 6 模組將需要一 2 5 6位元寬的列解碼器模組。 圖3的DRAM 3 0 2的儲存容量可藉由加入或減去 次模組3 0 3而被變大或變小。例如.，D R A Μ 3 0 2的 容量可藉由-加入次模組3 0 3而被放大以在M i s c模組 3 1 8的任一側上提供五個次模組3 0 3 (而非所示的四 個），或者DRAM302的容量可藉由減去次模組 3 ◦ 3而被減小以在M i s c模組3 1 8的任一側上提供 三個，二個或一個次模組3 0 3。但是次模組不需與模組 3 1 8對稱。 DRAM3 0 2的作業爲習知的。DRAM3 0 2藉 由耦合至包含於Μ I S C細胞3 1 8中的地址輸入緩衝器 的地址線所定址。地址輸入緩衝器提供列及行地址線至行 解碼器3 1 0及列解碼器3 1 4。列解碼器3 4自每一核 心細胞3 0 4中的2 5 6列中選擇一列。儲存於所選的列 中的每一行內的資料被自核心細胞3 0 4中讀出，並送至 位元線感應放大器3 1 0。在一讀取作業中，行解碼器 3 1 8選擇一行以使在適當位元線感應放大器中的資料被 經由I/O細胞3 1 6自DRAM輸出。包含於BLSA 3 1 0中的資料接著被寫入至由列解碼器所選擇的列中。 在一寫入作業中，在I/O細胞3 1 6中的資料被 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐)~-14 - ~~~ I» - 1 ml »1« -- ^^^1 n ^^^1 In \ ^ (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 4367 W A7 B7 五、發明説明（12 ) BLSA3_ 10傳送至由行解碼器3 18所選擇的行中。 應了解到在此所討論的諸如細胞的特定寬度及密度等 之特定機構及技術主要係爲說明本發明的主旨之應用在不 脫離本發明的精神及範圍之下，可對所述之方法及裝置作 多種變更設計。 (請先閣讀背面之注意事項再填寫本頁) 裝. 訂 經濟部中央標準局—工消費合作杜印製 本纸張尺度適用中國國家標準（CNS ) A4規格（210X2,97公釐）-15 -4367 W A7 B7 V. Description of the invention (10) Memory type Miscellaneous module row decoder column decoder core cell bit line induction amplifier bit line induction amplifier driver input / output 64kx32: misc col 64 row_256 core—256 bis a one 2 bsd_2 iol. _256 32kx64: misc col one 64 row one 256 core one 256 blsa_2 bsd_2 iol. 256 56kx32: misc col one 64 row_224 core—224 blsa_2 bsd_2 iol. 224 28kx64; misc col one 64 row_224 core one 224 blsa_2 bsd_2 iol · 224 48kx32: misc col—64 row_192 core-192 blsa_2 bsd_2 iol · _192 24kx64: misc col_64 row-192 core-192 blsa-2 bsd_2 iol. J92 32kx64: misc col_64 row_256 core-256 blsol-2 256 I6kxl28: misc col one 64 row one 256 core one 256 blsa one 2 bsd_2 iol · 256 28kx64: misc coi_64 row one 224 core one 224 b [sa one 2 bsd_2 iol. • 224 14kxl28: misc col one 64 row one 224 core_224 blsa—2 bsd_2 iol_ .224 24kx64; misc col one 64 row one 192 core one 192 blsa one 2 bsd_2 iol_ .192 12b (128: misc col_64 row_192 core one 192 blsa 2 bsd_2 iol_ .192 --------- ^! (Please read the notes on the back before filling out this page) Printed by Employee Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy (Type) Defines a DRAM302 by its depth and word width, so the memory type 64kx32 i has a depth of 64 k locations and can be written to or read from 32 bits at one time. Twelve types of DRAM 3 02 Each of them uses the same M ISC module 2 2 2, the same row decoder module 2 2 4, the same BLSA228 and the same BSD218. Line decoder module 224 (co 1_64) Choose one from 64 lines, and each module of this paper is also applicable to Chinese national standards (CMS > Α4 specification (2 丨 〇 X 297 mm) -13- A7 4367 1 7 B7___ V. Description of the invention (11) 2 2 4 Covers 2-bit wire pairs. The column decoder module 2 2 6 and 1 // 〇 module 2 2 0 are changed due to the selected core cells. Yes 'The number of columns in the core cell determines the width of the column decoder core cell 2 2 6 and the width of the I / ◦ module 2 2 0. For example' Core with 2 5 6 columns _ 2 5 6 modules will require one 2 5 6-bit wide column decoder module. The storage capacity of DRAM 3 0 2 in Fig. 3 can be increased or decreased by adding or subtracting the sub module 3 0 3. For example, DRA M 3 The capacity of 0 2 can be enlarged by adding sub-modules 3 0 3 to provide five sub-modules 3 0 3 (instead of the four shown) on either side of Misc module 3 1 8 , Or the capacity of DRAM302 can be reduced by subtracting the submodule 3 ◦ 3 to provide three, two or one submodule 3 03 on either side of the Misc module 3 1 8. But The secondary module does not need to be symmetrical with module 3 1 8. DRAM3 0 2 The assignment is conventional. DRAM3 0 2 is addressed by address lines coupled to the address input buffer contained in the M ISC cell 3 1 8. The address input buffer provides column and row address lines to the row decoder 3 1 0 and column decoders 3 1 4. Column decoder 3 4 selects one of the 2 5 6 columns in each core cell 3 0 4. The data stored in each row in the selected column is extracted from the core cell 3 Read in 0 4 and send it to the bit line sense amplifier 3 1 0. In a read operation, the row decoder 3 1 8 selects a line so that the data in the appropriate bit line sense amplifier is passed through the I / O Cell 3 1 6 is output from DRAM. The data contained in BLSA 3 1 0 is then written to the column selected by the column decoder. The data in I / O cell 3 1 6 is written in a write operation Applicable to Chinese paper standard (CNS) A4 size (210X297 mm) ~ -14-~~~ I »-1 ml» 1 «-^^^ 1 n ^^^ 1 In \ ^ (Please first (Please read the notes on the back and fill in this page.) 4367 W A7 B7 printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (12) BLSA3_ 10 In the selected row of the device 3 18. It should be understood that the specific mechanisms and technologies such as the specific width and density of cells discussed herein are mainly used to illustrate the subject matter of the present invention without departing from the spirit and scope of the present invention. In the following, a variety of design changes can be made to the method and device described. (Please read the precautions on the back before filling out this page.) Binding. Ordered by the Central Bureau of Standards of the Ministry of Economic Affairs—industrial-consumer cooperation Du printed paper sizes are applicable to the Chinese National Standard (CNS) A4 (210X2, 97 mm) 15-