AU8171198A - Method and apparatus for incorporating dynamic random access memory design modules into an integrated circuit chip design - Google Patents
Method and apparatus for incorporating dynamic random access memory design modules into an integrated circuit chip designInfo
- Publication number
- AU8171198A AU8171198A AU81711/98A AU8171198A AU8171198A AU 8171198 A AU8171198 A AU 8171198A AU 81711/98 A AU81711/98 A AU 81711/98A AU 8171198 A AU8171198 A AU 8171198A AU 8171198 A AU8171198 A AU 8171198A
- Authority
- AU
- Australia
- Prior art keywords
- integrated circuit
- random access
- access memory
- dynamic random
- circuit chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US88417397A | 1997-06-27 | 1997-06-27 | |
| US08884173 | 1997-06-27 | ||
| PCT/US1998/013340 WO1999000752A1 (en) | 1997-06-27 | 1998-06-25 | Method and apparatus for incorporating dynamic random access memory design modules into an integrated circuit chip design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| AU8171198A true AU8171198A (en) | 1999-01-19 |
Family
ID=25384108
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| AU81711/98A Abandoned AU8171198A (en) | 1997-06-27 | 1998-06-25 | Method and apparatus for incorporating dynamic random access memory design modules into an integrated circuit chip design |
Country Status (3)
| Country | Link |
|---|---|
| AU (1) | AU8171198A (en) |
| TW (1) | TW436717B (en) |
| WO (1) | WO1999000752A1 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015065307A1 (en) * | 2001-03-27 | 2015-05-07 | Jeng-Jye Shau | Cost saving methods using pre-defined integrated circuit modules |
| TWI406146B (en) * | 2009-02-20 | 2013-08-21 | Accton Technology Corp | Method for design a modulation circuit |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5351197A (en) * | 1989-04-13 | 1994-09-27 | Cascade Design Automation Corporation | Method and apparatus for designing the layout of a subcircuit in an integrated circuit |
| JPH0828476B2 (en) * | 1991-06-07 | 1996-03-21 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| KR950011636B1 (en) * | 1992-03-04 | 1995-10-07 | 금성일렉트론주식회사 | Dynamic random access memory having reelected layout and layout design thereof |
| US5488583A (en) * | 1994-09-22 | 1996-01-30 | Micron Technology, Inc. | Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits |
| US5757655A (en) * | 1996-08-26 | 1998-05-26 | Micron Technology, Inc. | Method and system for producing dynamic property forms and compacting property databases |
-
1998
- 1998-06-25 AU AU81711/98A patent/AU8171198A/en not_active Abandoned
- 1998-06-25 WO PCT/US1998/013340 patent/WO1999000752A1/en active Application Filing
- 1998-07-20 TW TW087110396A patent/TW436717B/en active
Also Published As
| Publication number | Publication date |
|---|---|
| TW436717B (en) | 2001-05-28 |
| WO1999000752A1 (en) | 1999-01-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase |