TW432514B - Damascene process for integrating low-k material - Google Patents

Abstract

The present invention discloses a damascene process for integrating low-k material, which can easily integrate low-k material in the damascene process. The method of the present invention comprises: utilizing the manner of depositing a sacrificial layer (such as polysilicon), etching, and filling trench by dielectric layer to form a sacrificial damascene in the structure of low-k dielectric layer; then removing the sacrificial layer to define a conductive trench or via hole in the dielectric layer; and finally filling the true conductive layer (such as copper) to form the damascene structure. In accordance with the method of the present invention, it is only required to define pattern on the sacrificial layer without directly etching the low-k material, thereby eliminating the issues of etching, ash, and post clean in using low-k material.

Description

432514 V. Description of the Invention (1) [Field of the Invention] The present invention relates to semiconductor process technology, and more particularly to a novel process capable of integrating a low dielectric constant (l0w-k) material in a mosaic structure. [Background of the Invention]

^ In recent years, in order to meet the development of 70-piece size reduction and increase the speed of component operation, copper metal with low resistance constant and high electron migration resistance has gradually been used as the material of metal interconnects, replacing the conventional metal Aluminum metal process technology. Among them, the mosaic interconnect technology with copper metal can not only reduce the interconnect size and reduce the R c time delay, but also solve the problem of difficult copper metal etching, so it has become the main development of multiple interconnects today. trend. The damascene process is different from the traditional metallization process in which a metal pattern is first defined and a trench is filled with a dielectric layer. The method is to first etch a groove of a metal line on a flat dielectric and then fill the metal layer. And finally remove the excess metal to obtain a flat structure with metal embedded in the dielectric layer. In the current dual-damascene process technologies, including 'trench-first', 'via-iirstl', 'self_aUgned ", etc. In order to further understand the background of the present invention, the "via_first," process will be used as an example for description below. Referring to FIG. 1A, a semiconductor substrate 100 is first provided, and a dielectric layer 130, a coin stop layer 140, and a dielectric layer 150 are sequentially deposited as an intermetal dielectric layer (IMD). The material of the etch stop layer 14 is usually silicon nitride (SiaN4) or silicon oxynitride (SiON). Then, using the lithography imaging program in the introduction

43 25 1 4 V. Description of the invention (2) A photoresist layer 155 with a via pattern is formed on the surface of the 1 'electric layer 150, and anisotropic etching is performed as a mask until the dielectric layer is formed. The formation of the via hole in 130 is 160.凊 Referring to FIG. 1B, after removing the photoresist 155 described above, a photolithography layer 165 with a wire pattern is formed on the substrate by another lithography imaging procedure, and this is an anisotropic money engraving for the mask To form a wire trench 170 in the dielectric layer 150. Among them, the stop layer 14 is used to prevent the neodymium layer from penetrating the underlying dielectric layer 130. After the photoresist 1 65 is removed in a conventional manner, a double damascene structure is obtained, including via holes (via ho 1 e) 1 60 and conductive line trenches 170. Please refer to FIG. Ic ′ After completing the above-mentioned dual-iron structure, the production of the interconnecting wires and metal plugs can be performed. First, a conformal barrier layer 175 is formed on the substrate. Then, a copper metal layer 1 80 is deposited by chemical vapor deposition (CVD), physical vapor deposition (p), or electrochemical deposition (ECD) to fill the above-mentioned interlayer holes 60 ′ and the wires. Groove 1 70. Finally, a chemical mechanical polishing method (p) is used to remove the excess barrier layer 175 and copper metal layer 180 on the dielectric layer 150 to obtain a mosaic interconnect and plug structure. On the other hand, in order to reduce the parasitic capacitance between the metal wires and the RC delay of the component as much as possible ', various low-k materials are currently being actively developed, such as FSG, HSQ, FLARE, PAE ~ 2, SILK, etc. to replace the traditional oxide layer. However, because 1 ow-k materials are not mature in various aspects such as etching, ash, post clean, etc., it is still a challenge to integrate them into the inlaid steel process.

432514

For i ::; gas engraving, 'Some iOwk materials have an increase in the dielectric constant of Γ at the time of' (while the porosity is not uniform at the time of removal, the ash removal is different from the internal porosity ' As a result, in terms of lightning and x (ash), the oxygen used in photoresist removal to ash passes through the second k material (especially the * organic iow_k material), and the dielectric constant and pattern size are ⑽. Adding a silicon oxide layer on the k material can be used as protection, but this also makes the whole

= :, hanging value increased. In addition, the acid and alkaline solutions used in post-cleaning also attack low-k materials, which affects the dielectric constant. [Summary of the Invention] * In view of this, the main object of the present invention is to provide a novel mosaic process' which can directly integrate low-k materials into the mosaic structure, while avoiding the above problems. ) In order to achieve the above-mentioned purpose, the present invention mainly uses a method of depositing [sacrificial yan / 如 such as polycrystalline spar)-aftertaste-the dielectric layer to fill the trench, and first forms a sacrificial layer repeatedly embedded in the 10wk dielectric layer. The structure 'then removes the sacrificial layer, leaving a conductive trench / via hole in the 10w_k dielectric layer, and finally fills in a real conductive layer (such as steel) to form a damascene structure. According to the method of the present invention, it is only necessary to define the pattern of the sacrificial layer, and it is not necessary to directly etch the 10w-k material, so the difficulties of the low-k material in etching, deashing, and post-cleaning can be avoided. The selection of the sacrificial layer may be any existing material that has matured in the above aspects, such as polycrystalline silicon, amorphous silicon, aluminum metal, and the like.

4325 1 4 V. Description of the invention (4) The process of the present invention can be applied to the production of a single damascene structure. The main steps include: (a) depositing a sacrificial layer on a semiconductor substrate and defining it as a wire; Structure; (b) depositing a low dielectric constant layer and planarizing it until the wire structure is exposed; (c) removing the wire structure by etching, leaving a wire groove in the low dielectric constant layer; And (d) filling a conductive layer in the wire trench to form a damascene structure. The process of the present invention is more applicable ;: In the production of the double-wound embedded structure, the main steps include: (a) a first sacrificial layer is deposited on a semiconductor substrate " ^, and it is defined as a plug Structure; (b) deposit a first low dielectric constant layer and planarize it until the plug structure is exposed; (c) deposit a second sacrificial layer and define it as a wire structure; (d) deposit a second low The dielectric constant layer is planarized until the wire structure is exposed; (e) the plug structure and the wire structure are removed by etching, leaving a via hole and a wire trench in the low dielectric constant layer; and (F) filling a conductive layer in the via hole and the wire trench to form a double damascene structure. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes the preferred embodiments in detail with the accompanying drawings as follows: [Simplified description of the drawings]-, Figures 1A to 1C are a series of cross-sectional views, which are used to illustrate the conventional double-mounting process. Figures 2A to 2F are a series of cross-sectional views for explaining a mosaic process of a preferred embodiment of the present invention. 【Symbol Description】

432514 V. Description of the invention (5) 100 ~ substrate; 130 ~ dielectric layer; 14 ~ etching stop layer; 150 ~ dielectric layer; 155 ~ photoresist mask; 160 ~ interlayer window; 165 ~ photoresist mask ; 17 ～ lead groove; 175 ～ barrier layer; 180 ～ copper metal layer; 500 ～ substrate; 51 ～ plug structure; 520 ~ low dielectric constant layer; 53 ～ wire structure; 54 ～ low Dielectric constant layer; 550 ~ via hole; 560 ~ conductor trench; 570 ~ conductive layer. [Embodiment] This embodiment is described by taking the dual damascene process as an example according to the above method, but it should be understood that the process of the present invention can also be applied to a single damascene process. Wait, no. The formed element system includes a semi-insulating layer, step 1 of the present invention, the spear = 2 to FIG. 2F, and the FIGS. 2A to 2F are cross-sectional views for explaining the preferred embodiment. The damascene process of the present invention is applicable to the substrate 500: for example, a silicon wafer, and a semiconductor element such as a MOS transistor, a resistor, and a logic element that can be shaped above it. In order to simplify the diagram, only a flat substrate 5 〇13 In the description, " substrate, '-the word system includes various coatings on semiconductor wafers that have been covered on the wafer ;, the surface of the substrate is round 2 metal:: the uppermost layer exposed, such as a silicon wafer The surface and bright mosaic process includes the following steps: As shown in Figure 2A, AL |. HO, and defines it as: 拎 窠 \ half-pull conductor substrate sacrifice layer ~ ash removal and other aspects = belonging layer ' As long as the neodymium surgery is mature in the existing materials, such as polycrystalline stone,

4-3 25 1 4 V. Invention "" —" Yue Ri Shi Xi,-Shao metal layer, etc. In this way, it can be easily defined as a plug structure according to the traditional lithography and afterglow procedures. After coating a photoresist layer on the sacrificial layer, a plug pattern is defined in the photoresist by a lithography process, and then anisotropic etching is performed by reactive ion etching (RIE). The plug pattern is transferred from the photoresist layer to the sacrificial layer underneath. Finally, the photoresist is removed from the king substrate and the result shown in Figure 2A is obtained. Step 2 ^ Figure 2B, in the above semiconductor substrate 5GQ A low-dielectric-constant layer 520 is deposited with the plug structure 51 ^ and planarized until the plug structure 5 i formed by 刖. The first low-dielectric-constant layer 520 can be deposited on the substrate by chemical vapor deposition. The dielectric constant 丄 丄 is as follows: The dielectric constant materials include: doped special ... existing low dielectric high gasification type low dielectric constant materials and dielectric constant materials, etc., can be applied to the present invention. Low property; 1 layer of dielectric constant material ⑽), lightly doped oxygen: layer = ㈡ homogeneous low dielectric constant materials: F4, P; FE. Porous low dielectric constant including ary ene

AerogeU, Xerogels, NanogUss.丨 For example, after the deposition, low dielectric constant, good coarseness (CMP) is used for planarization, and then moxibustion is performed using a chemical mechanical polishing method. Step 3 The structure shown in Figure 2B is served. 4 3 2 5 1 4 V. Description of the invention (7) As shown in Figure 2C, the name p 彳 ren ^ / the dielectric constant layer 52 and the plug structure "」 道; layer, and according to the traditional lithography And the program will: Define a wire structure 5 3 0. The sacrificial layer 530 can also be a mature material such as polycrystalline silicon, amorphous silicon, aluminum, etc. ^ ^ 'Metal layer structure 51G and the right one is the same as U, should the wire structure 53 〇 It has the same material as the plug structure 5 10 to facilitate subsequent etching and removal. Step 4: As shown in FIG. 2D, another low dielectric constant 540, U is deposited on the surface of the substrate, and U is filled into the gap between the wire structures 53, and planarized by a chemical mechanical mapper method (CMP). The surface of the lead structure 53 is exposed. In this way, a plug structure 5 i 0 composed of a sacrificial layer and a wire junction are formed and embedded in the low dielectric constant layers 520 and 54. '' The material of the low dielectric constant layer 540 may be any one of a doped oxide layer, an organic dielectric constant material, a high fluorinated low dielectric constant material, and a porous rhenium dielectric constant material, but it is preferably, Can be used with low-level & layer 520 materials. & Step 5 As shown in FIG. 2E, by selective etching, the plug structure 510 and the wire structure 530 are removed, and the via holes 5 5 0 and the wire trenches are left in the low dielectric constant layers 520 and 540. 5 6 0. 1 This step can be achieved by wet silver engraving. 'Select an appropriate etchant for the sacrificial layer and the low dielectric constant material. Usually, it can achieve a very high etching selection. Immersi etch and spray etching

Page 10 d325 1 4 V. Description of the invention ^ 1 In this process. Step 6 As shown in FIG. 2F, a conductive layer 570 is finally filled in the exposed via hole 55o and the wire trench 560 to complete the fabrication of the dual damascene structure. Although the material of the conductive layer 570 is not particularly limited, only the resistance value of the conductive layer 570 should be lower than that of the sacrificial layer to make sense. Therefore, the material of the conductive layer 570 is preferably a copper metal layer. Before depositing the conductive layer 570, a conformal barrier layer (not shown) can usually be deposited on the substrate to help subsequent metal adhesion and prevent its diffusion. "For steel, the appropriate barrier The layer materials include: tantalum (Ta) 'nitride button (TaN)' tungsten nitride (medical), as well as conventional and j-nitride (TiN). The conductive layer 570 can be deposited by a chemical vapor deposition (CVD) method, a physical vapor deposition method (pVD), or an electroplating deposition method (ECD). For example, ‘the ionized metal plasma MP may be used to form a seed layer of 300-1500A first, and then a conductive layer is formed on the seed layer by electroplating. -After the conductive layer 570 is deposited, it can also be chemically and mechanically polished to remove the excess conductive material on the dielectric layer to obtain the double-embedded structure shown in Figure 2F. It should be noted that 'all of the above steps do not need to carry out the engraving of the low dielectric constant layer), so it is possible to avoid the various difficulties of # w-k materials in #cutting, ash removal, and post-cleaning. In addition, the same sacrificial layer, such as polycrystalline silicon or aluminum, is very mature in all aspects of etching. Therefore, the method of the present invention can easily integrate 10w-k materials into the mosaic structure.

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Claims (1)

432514 1. A method of integrating the low-thin thundercylinder electric anode material and 4 in 0 steps: The explosive process includes the following, (a) deposition on a semiconductor substrate-a sacrificial layer, a wire structure; It is defined as (b) depositing a low-dielectric-constant wire structure; degenerating the liver until exposed (c) etching to remove the wire structure, leaving a wire groove in the above; and Several layers of guidance. (4) Fill a conductive layer in the wire trench to form a damascene junction 2 2 According to the damascene process described in item 1 of the scope of patent application, the electric layer in the basin has a lower resistance than the sacrificial layer value. Eight " 3. The inlay process as described in item 2 of the scope of patent application, wherein the conductive layer is a copper metal layer. 4. The post-mounting process as described in item 3 of the patent application park, wherein the sacrificial layer is a metal layer, a polycrystalline stone layer, or an amorphous silicon layer. 5. The mosaic process as described in item 1 of the scope of patent application, wherein the low dielectric constant material is selected from the following groups: doped oxide layer, organic low dielectric constant material, high fluorinated type Low dielectric constant materials and porous low dielectric constant materials. 6 · The inlaying process as described in item 1 of the scope of patent application, wherein step (b) is a chemical mechanical polishing method. 7. The damascene process according to item 1 of the scope of patent application, wherein step (c) is to remove the above-mentioned wire structure by a wet etching method. 4 8 2 5 1 4 VI. Patent application scope 8. The mosaic process as described in item 1 of the patent application scope, wherein steps (c) and (d) further include depositing a barrier layer on the wire trench in. 9. A mosaic process for integrating a low dielectric constant material, comprising the following steps: (a) depositing a first sacrificial layer on a semiconductor substrate and defining it as a plug structure; (b) depositing a first low dielectric constant Layer, and planarize it until the plug structure is exposed; (c) deposit a second sacrificial layer and define it as a wire structure; o (d) deposit a second low dielectric constant layer and planarize it, Until the wire structure is exposed; (e) removing the plug structure and the wire structure by etching, leaving a via hole and a wire trench in the low dielectric constant layer; and (ί) the via hole and the wire A conductive layer is filled in the trench to form a double damascene structure. 10. The damascene process according to item 9 of the scope of the patent application, wherein the conductive layer has a lower resistance value than the sacrificial layers. 11. The damascene process according to item 10 of the scope of patent application, wherein the conductive layer is a copper metal layer. 1 2. The mosaic process according to item 11 of the scope of patent application, wherein the first sacrificial layer and the second sacrificial layer may be the same or different from each other, such as an aluminum metal layer, a polycrystalline layer, or an amorphous layer. Floor. 1 3. The mosaic process according to item 9 of the scope of patent application, wherein the first low dielectric constant material and the second low dielectric constant material may be the same or different Page 14 432514 Page 15