TW432326B - Microcomputer - Google Patents

Abstract

Embedded registers are divided to the first registers 5, 7 and the second registers 4, 6. Via the third major lines XAB, XDB along with the second major lines YAB, YDB, they can be accessed in parallel. Consequently, core 2 of CPU can simultaneously transfer two data to DSP engine 3. The third major lines XAB, XDB and the second major lines YAB, YDB together with the first major lines IAB, IDB of external port as well as the second major lines YAB, YDB together with the first major lines IAB, IDB of external port are all individualized. Core 2 of CPU is parallel with the second register 4, 6 and the access of the first registers 5, 7 can be done externally.

Description

Printed by the Consumer Cooperative of the Central Bureau of Standards, Ministry of Economic Affairs: C 0 ^ Ό A7 ____B7_ V. Description of Invention (i) [Technical Field of Invention] The present invention relates to a semiconductor integrated circuit with a central processing unit and a digital signal processing unit. The related logic LSI is related to the effective technology applicable to microcomputers that need to be processed quickly. [Previous technology]. For example, a microcomputer in which a multiplier and an arithmetic logic operation device are installed on the same substrate is disclosed in Japanese Patent Application No. 4—296 778 or US Patent Application No. 1 4 5 1 5 7. According to the above patents, for example, the logic LS I chip of the microcomputer has a central processing unit, a bus, a memory, and a multiplier. In particular, when reading data from the memory, the central processing unit will instruct the multiplication command of the read data. Transfer to the signal line of the multiplier. As a result, when the central processing unit reads the data from the memory *, the instruction on the multiplication command of the read data is transferred from the central processing unit to the multiplier, so the data can be directly transferred between the memory and the multiplier. [Problems to be Solved by the Invention] The present inventors have studied the problem of speeding up digital signal processing by installing a digital signal processor and a central processing unit in a pair of L SIs. At that time, although the previous technology mentioned above can directly receive data from the memory and transfer it to the multiplier to achieve high-speed multiplication processing, it did not consider that the central processing unit should implement the instruction fetch when the pipeline processing is intended to be executed by the central processing unit. A situation where the cycle coincides with the storage access cycle used for multiplication processing. Also, it is not considered that the complex operands used for adding or multiplying from the memory are calculated in parallel. The paper size is common Chinese National Standard (CNS) A4 specification (210X297 mm)-4-(Please read the precautions on the back before filling (This page) 4 3 into. Μ Α7 Β7 _ V. Description of the invention (2) The problem of speeding up the calculation processing. It is also clear that at this time, if the relationship between the central processing unit and the external access relationship is not considered, the microcomputer will be used. Unfavorable situation * Also, it is found that when the digital signal processor is assembled on a pair of L s 1 'in order to suppress the increase of logic scale such as the instruction decoding circuit as much as possible', it is also necessary to consider the allocation of CPU instructions and DSP instructions or DSP instructions Format "The purpose of the present invention is to install the digital signal processing unit and the central processing unit in a pair of LSIs to speed up digital signal processing. Another object of the present invention is to install the digital signal digital unit and the central processing unit in one. In the case of LSI, the increase of its physical scale is strongly suppressed. The foregoing and other objects and new features of the present invention should be understood from the description of this specification and the drawings. 〕 Here is a brief description of the representative outline of the invention disclosed in this application. The microcomputer is: the central processing unit (2) * and I »I _--------«. 士 又-· I _ I I ------ Ding U3. -Τ (Please read the precautions on the back before filling out this page) The Central Office of Standards of the Ministry of Economy Staff Consumer Cooperatives Printed Line General Manager

Address 3 and IX address and M) pass B select A select X group, machine B manages Y at A, middle B said A before I from C

Line ’s total 5 sites, ground devices, 2 storages, 1 storage, 1}, Β, Α, I storage, C storage, C, line, ground, address group, ground machine, 1 machine, and 1st place.

Line & main site storage and storage 3 2nd and first} Take B and store A address I and C The line group switchboard physical location is located in the middle of the first place, and then connect to B I- ί AX 4 And this paper size is in accordance with the Chinese National Standard (CNS > A4 size (210 × 297 mm)-5-^ 3: s A7 B7. The Central Bureau of Standards, Ministry of Economic Affairs, Shellfish, Consumers, Cooperation, Printing, Printing, Printing 5.) Description of the invention (3 '1 I is connected to the first memory 1 and the second memory and the central processing unit transmits 1 1 the first data bus (IDB) > and 1 1 »connects to the second memory and transmits the second data Bus (1 I Please [1 YDB) t and read first f * read it l is connected to the third data bus of the second memory to transfer data C back 1 j of YDB) 1 and Zhuyin 1 antecedent 1 is connected to the description 1st address bus and 1st number The external connection of the bus □ item again! Fill in 1 circuit (1 2) * and write the book 1 Connect the data bus t connected to the aforementioned 1st to jiste 3rd digital signal processing unit with the same operation as the central processor page 1 1 set (3 ) And 1 1 The white central processing unit will control the operation of the digital signal processing unit 1 1 The DSP control signal (2 0) will be transmitted to the control unit of the digital signal processing unit 1 The signal will be sent to the semiconductor integrated circuit on 1 substrate 〇1 I The built-in memory according to the above method considers the product and operation of the digital signal processor (3 1 1 I). The two memories are stored in the first memory (5 7) and the second memory 1 1 ′ (4 6). The third bus (XABXDB) and the second bus Ί (YABYDB) can access 0 in parallel, so the CPU core 2! 1 can transfer 2 data at the same time with the built-in memory. ΓΊΓ is sent to the digital signal Processing unit 1 signal 0 and 1 The 3rd bus (XAB 9 XDB) and the 2nd bus (1 IYAB • YDB) are connected to the external 1st bus (IAB 1 Ί IIDB) — the same as the individual »so the central processing unit system Parallel to the access of the 2nd storage unit 1 (4 i 6) and the 1st storage unit (5 > 7), the external storage 1 1 storage unit can also be accessed 9 as mentioned above because it is separately connected to the central processing unit (2 ) Of! 1 1st to 3rd address bus (IAB > XAB »YAB) 1 1 This paper size applies to China National Standard (CNS) A4 specification (2 丨 OX297 mm) -6-A7 43 23 2 6 B7 V. Description of the Invention (4) ^^ 1--I---II----1—. ^^ 1-1-(Please read the precautions on the back before filling this page) and data bus (IDB , XDB, YDB), so using these three internal buses * can implement different memory access actions at the same time period. Therefore, it is easy to cope with the situation that the program or data exists in the external memory and speed up the arithmetic processing. In order to improve the usability of the microcomputer, R AM and R 0M may constitute the first memory and the second memory, respectively. "In order to speed up the address form for the repeated calculation of the product and operation of the central processing unit, the central processing unit is provided with a module. The number address output section (2 0 0) is suitable. At this time, the address formed by the modulo address output section is preferably output on the second or third address bus. The aforementioned digital signal processor includes the first to third data buses (1 DB, YDB, XDB) The first to third data buffering devices (MDB I, MDBY, MDBX) of individual interfaces and the multiple storage devices (3 05 ~ printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economy) 3 0 8), and a multiplier (304) and an arithmetic logic operator (302) connected to the aforementioned internal bus, and decode the aforementioned DSP control signal to control the aforementioned data buffering device, multiplier logic operator, and register The decoder (3 4) of the operation of the device is composed of a microcomputer focusing on the so-called instruction code, that is, the central processing unit (2) 1 and the memory (4 ~ 7) controlled by the aforementioned central processing unit, and in the aforementioned The digital signal processing unit (3) that transfers data between the memory and the central processing unit to synchronize with the operation of the central processing unit will be semiconductor integrated circuit on a substrate. The instruction system that can be implemented by the microcomputer, including the CPU instruction that the central processing unit (2) should implement, and the paper size of the central office that applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) 4 3 2 3 2 6 Economy Department _ Printed by the Central Consumers 'Bureau Employee Consumer Cooperative A7 B7_ V. Description of the invention (5) Processing of address calculation and other part of the processing unit's burden to take data.' Digital signal processing unit (3) OSP instruction to be implemented * The central processing unit is an instruction recorder (2 5) containing a 16-bit fixed-length CPU instruction for the central processing unit and a 16-bit or 32-bit DSP instruction for the digital signal processing unit taken out via the aforementioned data bus. And according to the plural digits of a part of the instruction taken by the foregoing instruction recorder, the CPU instruction and the DSP instruction are identified, and the control signal of the DSP control signal (20) for the operation of the digital signal processing unit and the operation of the central processing unit are formed with the recognition result. The decoder (2 4) of the CPU control signal for control is formed, for example, the CPU instruction allocates the upper 4 bits of the instruction code to ^ 0000, ~ 1 10, and the range of "DSP instruction" refers to Most of the code partitioned upper 4 > range 111. The uppermost 6 digits of the instruction code are assigned to the 1 1 1 0C ^ and '1 1 1 1 0 1 " range of instructions. The DSP instructions are also 16-bit long instruction codes. The command with the highest 6 digits of the command code being a 1 1 1 1 1 is a command code with a length of 32 digits. There is no instruction assigned in the range of 1 1 1 1 in the top 6 digits of the instruction code, and the range is regarded as an unused area. As described above, since the code allocation for the instruction with a maximum of 32 digits is set as the above rule, Decoding a part of each instruction code, for example, the uppermost 6-bit decode ', that is, a decoder of a small logical scale can determine that the instruction width is a cpu instruction, a 16-bit DSP instruction, or a 32-bit D sp instruction. Without having to decode all 3 and 2 bits all at once ...] >!-I — I HI. I .....- · 1-I. 1-----In .I \ ~~ ^ (Please read the precautions on the back before filling out this page) This paper size is applicable to Chinese National Standard (CNS) A4 specification (210X297 mm) -8-43 '3 A7 B7 Staff Consumer Cooperation of the Central Standards Bureau of the Ministry of Economic Affairs 6. Description of the invention (6) The aforementioned decoder includes: a first decoding circuit that decodes the upper 6 bits of the recorder to form the aforementioned CPU decoding signal (2 4 3) and DSP decoding signal (244). (240), and when the first decoding circuit recognizes a 32-bit long DSP instruction, it outputs a signal that encodes the lower 16 bits of the instruction recorder. When identifying other instructions, output the code that means outputting invalid code to the circuit (2 4 2), and use the output of the aforementioned DSP decoding signal and code conversion circuit as the DSP control signal (2 0) * Focus on In the instruction format of the DSP instruction, the microcomputer includes a central processing unit (2) and a digital signal processing unit (3) synchronized with the operations of the aforementioned central processing unit, and an internal bus (connecting to the aforementioned central processing unit and the aforementioned digital signal processing unit) IDB), a microcomputer integrated with semiconductor integrated circuits, in which the aforementioned central processing unit is equipped with the first code field that implements digital transfers between digital signal processing units that specify the central processing unit (Figure 1 6-bit DSP instructions (9 to 0 bits) of the first format instruction, and the second code area with the same format as the aforementioned first code area, (Figure A, Area A of the 32-bit DSP instruction illustrated in Figure 21) and For the digital signal processing unit, use the third code area specified in the second code area for the digital processing operation (Figure 20, Figure 21, exemplified by 32 bits D) SP area (B area)) The second format instruction is implemented by the control device. Therefore, the implementation of the control device, when implementing the instructions of the first and second format, can have a common translation of the first code area and the second code area (please read the precautions on the back before filling this page) Applicable to China® Home Standard (CNS) A4 specification (2 [0 × 297 mm) _ g _ A7 4 3 2 3 2 6 V. Description of the invention (The decoding device of code logic is beneficial to the reduction of the logic scale of microcomputers. The first format instruction and the second format instruction have a fourth field indicating that they are in the first format or the second format (for example, 16-bit 0 SP instructions, 15--10 bit 3, 2-bit DSP instructions 3 2 Bit ~ 2 6 bit)

Q The aforementioned implementation control device includes an instruction register (25) for the first format instruction and the second format instruction, and the first code area and the fourth code area or the first code area for the instruction contained in the aforementioned instruction register. The decoding device (240) for decoding in the 2nd code area and the 4th code area, and the implementation device for implementing the aforementioned data transfer control based on the real address operation of the decoding result. The aforementioned instructions, registers, and the first code are held in common. Field and 4th code field or 2nd code field and 4th code field upper field (UIR) and used to maintain the 3rd code field lower field (LIR), and the decoding device is based on the 4th field. As a result of the decoding, a control signal (248) indicating that the aforementioned instruction register holds the second format instruction, and based on the control signal, means 242, 242A for supplying the code data of the third code domain from the lower-level domain to the digital signal processing unit, 242B. [Embodiment] Fig. 1 shows all block diagrams of a microcomputer 1 according to an embodiment of the present invention. The microcomputer shown in the figure is formed by semiconductor integrated circuit manufacturing technology. This paper is applicable to the national standard (CNS) A4 specification (210X297 mm) -10- (please read the precautions on the back before filling this page) Install. Set the central standard of the Ministry of Economic Affairs and the printout of the Consumer Cooperative Cooperative 432326 A7 B7 Printout of the Consumers' Cooperative Work of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (8) A semiconductor substrate such as monocrystalline silicon. CPU core 2 (CPU Co re) 2 of the processing unit, DSP Engine 3 of the digital signal processing unit > X -R0M4, Y — R0M5 -X — RAM6, Y — RAM7, Interrupt Controller 8. Bus controller (Bus state conttroller) 9. Built-in peripheral circuit (Peripheral circnit) 1 0, 1 1 and external memory interface (External Memory Interface) 1 2 * Clock pulse generator (〇? 0) 13. The aforementioned another ruler 〇4, ¥-ruler 〇 \ 15 is a reading memory dedicated for reading instructions or constant data, or can be exchanged and rewritten, X — RAM6 and Y-RAM7 are stored as one of the data Or C Agile memory used in PU core 2 and DSP engine 3's operating fields, etc. The aforementioned X—R0M4 and X—RAM6 are collectively referred to as the internal instruction / data parent memory_memory (Internal Instrnecution / Data X Mem) and the Y- R0M5 and Y-RAM7 are collectively referred to as internal memory for internal instructions / data (Internal 丨 nstrnction / Data Y Mem) ° The microcomputer 1 of this embodiment has a bus structure including: an internal address bus IAB combined with external storage connected to α12 and unbound On the internal data bus I DB, the internal address bus XΑΒ of the external memory interface 12 and the internal address bus XD Β, external memory interface 12 and the internal data bus YDB of the external memory interface 12, and peripheral circuits 1 are built in. '1 1 Peripheral address bus PAB and peripheral data bus PD Β. The control bus is omitted and its illustration corresponds to a pair of places ^ nm i I----·: i----- -n-One eJ (Please read the notes on the back before filling this page) This paper size applies to Chinese National Standard (CNS) A4 size T 210X 297 mm) _ 11 Printed by the Central Consumers Bureau of the Ministry of Economic Affairs, Consumer Cooperatives 43 23 2 6 a? ___B7 V. Description of the invention (9) Address bus and data bus settings. The CPU core 2 is connected to the data bus I DB of the substrate via the external storage interface 12, and the sub-controller 8 supplies a distribution signal 80. The CPU core 2 supplies the DSP engine 3 with a control signal 20 for controlling the DSP engine 3. The CPU core 2 further outputs the address signals to the address buses I A B which can be connected to the outside of the substrate through the external memory interface 1 and the address buses XAB and YAB which are not connected to the external memory interface 1 2. CPU core 2 is a non-overlapping two-phase clock signal Ci ockl output by the clock pulse generator (CPG) 13 and Cl ock2 is the reference clock signal action. The CPU core 2 will be described in detail later, except that the CPU core 2 in FIG. 1 shows a representative register file 21 1, an arithmetic logic operator (ALU) 22, an address adder (Add-ALU) 23 decoder 24, Instruction Register (JR) 25. The register file 21 is arbitrarily used as an address register or a data register, and includes a program counter and a control register. The decoder 2 4 decodes the instruction fetched by the instruction register 25 to form an internal control signal (not shown in FIG. 1) and a control signal 20. Instruction register (IR) 25 * The 16-bit upper-side area (ϋ I R) and the lower-side area (L I R). Details will be described later, but the value of the lower-side area (L I R) can be optionally shifted to the upper-side area (UIR). It also omits the execution order of instructions when an exception occurs, such as controlling interrupts, or the diagram of a sequence control circuit that uses hardware to control the retraction and return of the internal state of the exception. The DSP engine 3 is connected to the aforementioned data buses I DB, XDB, YDB, and the clock signals Cl ockl and C 1 ock2 are used as the standard. The paper size is applicable to the Chinese storehouse standard (CNS) A4 specification (210X297) ~-(Please (Read the notes on the back before filling out this page)

d3222S Α7 Printed by the Consumer Procurement Cooperative of the Central Procurement Bureau of the Ministry of Economic Affairs Ⅴ7. Description of the invention (10) Acts as a reference clock signal. The DSP engine 3 will be described in detail later, but the DSP engine 3 shown in FIG. 1 shows a representative data register file 3 1, an arithmetic logic operator and a shifter (ALU / Shifter) 3 2, and a multiplier (MAC) 3 3, and the decoder 34. The data register file 3 1 is used for product and operation calculations. "The decoder 3 4 decodes the control signal 20 provided by the CPU core 2 to form the internal control signal of the DSP engine 3 (the illustration is omitted in Fig. 1). X — ROM4 and X — RAM6 are connected to the address buses I AB and XAB and the data buses I DB and XDB. Y-ROM 5 and Y-RAM 7 are connected to the address buses IAB, YAB and data buses IDB, YDB. The built-in memory considers the product and operation of the DSP engine 3. The two sides are integrated into the X memory 4, 6 and Y memory 5, 7 and can be accessed in parallel by the internal buses XAB, XDB and YAB, YDB, respectively. Furthermore, the internal buses XAB, XDB and YAB · YDB and the external lines IAB and IDB are all individualized. * Parallel to the access of X memory 4, 6 and Y memory 5 · 7, external memory can also be stored. take. The X memory 4, 6 and the Y memory 5, 7 are used as data for the product and operation of the D S P engine 3, and are used in the field of memory, constant data, and the like. In addition, X — RAM, Y — RAM can also be used as the memory area or work area when the data of CPU core 2 is used. * The aforementioned interrupt controller 8 is used to input the interrupt request signals (Interrupts) of the built-in peripheral circuits 1 0 1 1 1 etc. 8 1 ^ Accept the interrupt request according to the priority order of various interrupt requests or the masking of the interrupt request. The interrupt request will be accepted according to the interrupt vector of the accepted interrupt request. This paper is in accordance with the national standard (CNS > A4). Specifications (210X 297mm) _ Ί _ (Please read the notes on the back before filling out this page) 4 〇c ν),; ι 〇 Β7 Ministry of Economic Affairs " Central Standards Bureau, Consumer and Industrial Cooperation, Du Printing 5. Inventions Explanation (] 11) 1 I 8 2 is output on the address bus IAB, and the interrupt signal 8 0 is output on 1 1 C Ρ U core 2 〇1 The bus status controller 9 is connected to the address bus IA Β • PB AB / «-Ν 1 1 Please I« rh-t Data bus ID Β 1 Ρ DB, control and connection to the address bus PB A Β Read 1 I Read 1 and data total Built-in peripheral circuit 1 0, 1 1 and C P U core 2 back connection f 1 □ control. . Note 1 External memory connection □ 1 2 is connected to the address bus IA Β and the total data and then 1 fill 1 line IDB t connected to the microcomputer 1 outside the substrate, the address is omitted (not shown) write A [page and bus] f Implementation of external interface control Q 1 Figure 2 shows an example of the address mark of microcomputer 1. The micro 1 1 computer 1 of this embodiment manages the address space specified by 32 bits. The bit width of the aforementioned address bus 1 1 IAB is 3 2 digits. There are exceptions in its address space. The vector field X_R 0 Μ space (address 1 I space allocated at X — R 0 Μ 4), X_RA Μ space (allocation X-RA Μ 7 address space) 1 1 IT — R 0 Μ space (address space allocated to Y-R 0 Μ 5) Υ-1] RA Μ space (address space allocated to Υ-RA Μ 7), the internal circuit allocation space C of 1 side Hidden peripheral circuits 10 1 1 allocated address space 1 I) and so on. 1 cf.l The distribution of the example in Figure 2 is X — R 0 Μ 4 series 2 4 Κ 1 B! X-RA Μ 6 series 4 κ B, Υ 1 R 0 Μ 5 series 2 4 κ Β-1 1 Y — RA Μ 7 is 4 κ Β 〇I according to Figure 2 ♦ 1 β in the progression table is Η ^ 0 0 0 0 0 0 0 1 1 I Η 0 0 0 0 0 3 FF 2 5 6 Β Area allocation exception 1 1 Logic vector area 0 in Η-0 0 0 0 0 4 0 0 i 1 Η j »0 1 FFFFFF Normal space available for allocation 0 Normal space 1 1 This paper scale is applicable to China National Standard Vehicle (CNS ) Α4 size (210X 297 mm) _ 14 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, printed by the Industrial Cooperative Cooperative V. Invention Description (l2) is used as a storage area that can be connected to the outside of the microcomputer 1. From H'02000000 to H / 〇2005FFF, X-ROM space is allocated. At Η — 02006000 to H < 02006FFF, X — RAM space is allocated. Η < 02007000 to H > 02007FFF becomes X — RA Μ — Mirror space. When accessing this, you actually access Η ** 200200 0 0 to H — 02006FFF X-RAM space. 02008000 ~ H, 0200FFFF becomes X — RAM, RAM — Mirror space, access here, actually access H-02000000 ~ H > 02007FFFF X-RAM-ROM space and X-RAM space, ^ 1-1002010000 ~ 9 > 2015 corpse? ? Allocate y — ROM space ”in ΗΌ2016000 ~ Η a 020 1 6FFF, allocate Y — RAM space. ΗOne 0201700 ~ H'02017FFF is the Y-RAM-Mirror space. When you access it, you actually access it. ΗOne 02016000 ~ H> 02016FFF Y-RAM space. 02018000 ~ H-0201FFFF becomes Y-ROM, RAM-Mirror space 'access here is actually access to H / 〇2010〇〇〇 ~ H'〇2017FFF Y-ROM space and Y-RAM space "H- 02020000 ～ Η — 〇7FFFFFFF Allotment of general space ”Applies Chinese National Standard (CNS) A4 (210X297 mm) to this paper size_ 15-(Please read the notes on the back before filling this page) 432328 A7 B7 Central Printed by the Standards Bureau Consumer Cooperatives V. Description of the Invention (13, > 1 1 Η 0 8 0 0 0 0 0 0 Η 1 FFFFFFFF > Allocation 1 I Appropriate Area 0 The Promise Area 9 In the user base (real base 1) [Take 7 evaluation substrates (used for emulation, etc.) when assigning 1 I Please \ ASE space (control space for emulation) Field 0 in the news 1 I read 1 Η 2 0 0 0 0 0 0 0 Η 2 7 FFFFFFF Allocate 1 on the back 1 1 Normal space 9 in Η 8 2 8 0 0 0 0 0 0 • «V Yilou i Η FFFFF 0 FF 9 portions of the contract area 0 field and 1 guides | Η FFFFFF 0 0 Η FFFFFFFF allocation of the register address value of the built-in peripheral circuit with the built-in peripheral circuit allocation field Ά 1 1! 1 Figure 3 shows the details of the CPU core 2 of the modulo address output section. 1 1 1 Order 1 block 1 «dl circle a At Figure 3 The part enclosed by the dotted line in the figure is the modulo address output section 2 0 0 0 modulo address The output unit 2 0 0 outputs the value output from the modulo address register (1 1 such as A 0 X) to the 1 I address bus (such as XAB) and the final buffer (such as Μ ABX). ) Add the value output from the modulo address register (A 0 X) and store it again. 1 I update the address in the modulo address register (A 0 X) and output the electric power. The data access 1 I address used for the repeated operation of the product sum operation is recorded as a random logic circuit (Random Logic C ir cu it) f 1 2 0 1 The circuit block is a decoder 2 4 containing the circle 1 or the foregoing Sequence control | Circuits »Circuit blocks such as control registers or status registers 9 1 I raj 1 C 1 > C 2» DR »A 1 > B 1 A 2 1 1 1 Β 2) in 0 The representative bus inside CPU core 2 〇CPI 1 The connection between U core 2 and data bus IDB is in the aforementioned instruction register (I 1 1 This paper size applies to China National Standard (CNS) Λ4 specification (2 丨 OX 297 mm) _ ^ Indian Consumer Standards Cooperative Standards Bureau of the China Standards Bureau of the Ministry of Economic Affairs r- 4 d-'4 3 23 2,6 Β7 _ V. Description of the invention (14) R) 2 5 and Data Buffer 2 0 3 Implementation "The instruction fetched by the instruction register (IR) 2 5 is supplied to the random logic circuit (

Random Logic Cibcuit) The purpose of 2 0 1 is to describe the decoder 2 4 and so on. The interface between C P U core 2 and the address bus I AB is implemented in a program counter (P C) 2 0 4 and an address buffer (Address Buffer) 2 0 5. The interface between the CPU core 2 and the address bus XAB is implemented in the memory address buffer (from the 8th parent) 2 0, 1; the interface between the core 2 and the address bus 38 is in the memory address buffer (MABY) 2 0 7 implementation. The address information is input to the path of the address buffer 2 0 5 and can be selected from the total number C 1, A 1, A 2, and the address information is input to the path of the address buffer 206 and 207, which can be selected from the bus Cl 'C2' A1 , A2 is selected. The arithmetic operator (AU) 208 is used to increase the value of the program counter 204. 209 is a general-purpose register (Reg). 2 1 0 is an index register (IX) modified by adding an address and a subscript. 2 11 is also used to add Index modified index register (Iy), 2 1 2 is a special adder (PAU) for address operation, 21 3 is an arithmetic logic operator (ALU) 〇 control bit MXY is designated to address bus XA B or address bus YAB Perform modulo operation on any address, specify address bus AB with logical value '1' * specify address bus YAB with logical value. The control bit DM indicates whether the modulo operation is performed or not, with a logical value ^ 1 _ indicates that the modulo operation is performed, and the logical value "0 " indicates that no modulo operation is performed. The modulo start address register (MS) 2 1 4 stores the modulo operation Start address, modulo end address register (ME) 2 1 5 Stores modulo operation end address. · This paper size applies Chinese National Standard (CNS) A4 specification (210X 297 mm) ~ ~~ ---.----- -^ ------ ΐτ ------ 一 I (Please read the notes on the back before filling this page) A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (15) 1 | Modular Address Register (A 0 X »A 1 X) 2 1 6 is the current storage 1 [The electrical address register in the modulo address 2 1 7 is the modulo end address 1 address register (Μ Ε) 2 1 The value of 5 is compared with the modulo address register (A 0 X 1 I 谙 1 > A 1 X) 2 1 6 The value of the comparator (C MP) 2 1 8 is a comparison first read 1 I read 1 comparator 2 1 7) Output control Μ XY * D Μ 3 inputs are logically backed 1 | AND gate of 1 value > 2 1 9 Selects the value of the bus C 1 and the modulo start address Remarks | I Register (Μ S) 2 1 Selector of the value of 4 The above items are used for related matters and then 1 1 Fill in the modulo operation of the address bus XAB 0 Selector 2 1 9 is the value 1 output by the AND gate script Φ- I 2 1 8 Selection register (MS) 2 1 4 Page 1 1 Value Gives the selected value to the modulo address register (A 0 XA 1 X) 1 1 2 1 6) modulo address register 2 1 6 is selected to use A 0 X Or ί 1 A 1 X. Square 1 modulo address register (A 0 y A 1 y) 2 2 6 is the current address register that stores the modulo address of the current 1 I in 1 2 2 7 is the end of the comparison modulo 1 I address register (Μ E) 2 1 5 and modulo address register (1 1 f, AA 0 y A 1 y) 2 1 6 Comparator (C MP) 1 2 2 8 is the output of comparator 2 2 7 «a control bit MX X y reversal bit and 1 i 之 0 Μ 3 AND logic gate of the product 2 2 9 Selection of the value of the bus C 2 1 and the value of the modulo start address register (MS) 2 1 4 w 1 I The above components are used for the modulo operation of the address bus Υ AB 9 selector I 2 2 9 The value of the JQB series 1 output selection register (1 1 I M S) by the AND gate 2 2 8 gives the selected value to the modulo address register (1 1 IA 0 y A 1 y) 2 2 6 Modular address register 2 2 6 System selection 1 1 Use either A 0 y or A 1 y 9 1 1 This paper size applies to China National Standard (CNS) A4 (2Ϊ0 × 297 mm) _ 18 _ 432326 A7 B7 V. Description of the invention (16) modulo address register (A〇y, Aly) 226 is a current address register that stores the current modulo address 2 2 7 series compares the value of the modulo final address register (ME) 2 15 with the modulo Address register (AOy, Aly) 216 value of the comparator (CMP), 228 is the output of the comparator 2 2 7 and the control bit MXY inversion bit and the control bit Ό 3 of the logical input product AND gate, 2 2 9 is a selector for selecting the value of the bus C 2 and the value of the modulo start address register (MS) 2 1 4. The above items are used for the modulo operation of the address bus YA B. The selector 2 2 9 is a logical value of the AND gate 2 2 8 " ^ 1 'outputs the value of the selection register (MS) 2 1 4 and gives the selected value to the modulo address register (A〇y, Aly) 226 . The modulo address register 226 chooses to use either AOy or Aly *. Also, it is recorded in the random logic circuit 2 0 1 0 P Code means the code provided by the instruction register 25 and CONST means a constant value. The modulo operation of the CPU core 2 will be described below. For example, the modulo address register (A0x) 2 16 is used to perform the modulo operation to form the address information for the address bus XAB. Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards and Quarantine of the Ministry of Economic Affairs! ≫ 1----I— I un * ni H ------- Ding (Please read the notes on the back ^ | ^ before filling this page ) First write the modulo operation start address into the modulo start address register (MS) 2 1 4 and write the modulo operation end address into the modulo end address register (ME) 2 1 5 respectively. Write the starting modulo operation address value into the modulo address register (AOx). Second, because the modulo operation is performed on the address bus XAB, the control bit MXY that decides to perform modulo operation on any of the addresses of XAB and YAB is written with a logical value * 1〃 (When performing modulo operation on the address bus YAB, Write the logical value '0〃 into the paper. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) _ IQ _ Cooperating with the staff of the Bureau of Standards of the Ministry of Economic Affairs Du printed 4 3 ^ ^ ^ " A7 B7 5 、 Description of the invention (17) 1 I system M X Υ) 9 Finally, the logical value% 1 is written into the control bit for determining whether to perform modulo operation 1 I D Μ 0 1 i J modulo operation ΛύΓ The calculation instruction is, for example, Μ 0 VS ♦ W @ AX t DX 0 This 1 1 Please refer to the f instruction description. AX is the modulo address register (A 0 X) 2 1 6 or the modulo first read 1 digit address register (A 1 X) 2 1 6 DX is corresponding The registers in the DSP engine back τδ 1 1 3 〇 Figure 3 DX 9 is not shown At 1 hour, j is read from the modulo address register (A 0 X) 2 1 6 > input storage item and then 1 1 store the address buffer (Μ ABX) 2 0 6 and arithmetic M series arithmetic unit ($ 本 ALU ) 2 1 3 〇 Input memory address buffer (Μ ABX) page! The value of I 2 0 6 is still output address bus XAB »Specify the address 0 of XR 0 Μ 4 or IIXRA Μ 6 On the one hand, input the arithmetic logic unit (I | ALU) 2 1 3 modulo address register (A 0 X) 2 1 6 The value of I is the addition level register (IX) 2 1 0 value or constant (Const) III Implementation and index register (IX) 2 The addition of 1 0 is the implementation of the instruction II. M 0 VSW @ AXIX) DX Isochronous addition is always the II real instruction MU 0 VSW @ AXDX etc. The addition result is obtained by the t 'I arithmetic logic operator (ALU) 2 1 3 Output 〇. Arithmetic logic operation I | device (ALU) 2 1 3 The output value enters the selector 2 1 9 The output of this selector I t selector 2 1 9 is stored in the modulo start address register I (MS) 2 1 4 and the output of the modulo operation start j selector 2 1 9 is arithmetic. The output of the logic operator (ALU 1 1) 2 1 3 »or the modulo start address register (MS) 2 1 4 1 1 The value 9 is determined as follows. 0 The modulo address register (A 0 X) 2 1 6 value 1 The value of I and the modulo final address register (ΜΕ) 2 1 5 »is often more than 1 i This paper size applies to the Chinese national standard {CNS) A4 specification (2IOX297 public celebration) Love 20 _ A7 B7 Central Bureau of Standards, Ministry of Economic Affairs Du Yinzhuang, Employee Consumption Cooperation V. Invention Description (18 1 I Comparator (C MP) Comparison 9 If not, it will output logical value 0 0 White 1 I Comparator (C MP) 2 1 7 Output value system and control Bit D Μ »ί I Μ XY __ Same in irtn Xingmen 2 1 8 Collection of product (in this example 9 because D Μ, 1 i please 1 Γ Μ XY average logic value 1 1 Therefore, the value of comparator 2 1 7 is the same as the white AND gate first read 1 I read I 2 1 8 output 0) input selector 2 19 0 selector 2 1 9 in the white ftrt back 1 1. The input value of gate 2 1 8 is logical value 1. When the modulo start address is selected, the note 1 register (MS) 2 1 4 is the value 1 and the logical value% 0 Μ value is selected as the white calculation item and 1 is filled. i The output value of the arithmetic operation unit (ALU) 2 1 3 is 0%. This equipment 1 is at the white AND gate 2 1 8 Λτλ. The input value is a logical value 0. During the following period, ν ^ < · 1 1 Continue to select arithmetic Output value of logic (ALU) 2 13 • So output address 1 t The value of bus XA Β updates the modulo final address register (Μ Ε) 1 1 2 1 5 and the modulo address buffer CA 0 X) 2 The value of 1 6 is the white AND gate when ordering I 2 1 8 The value of the input selector 2 1 9 becomes a logical value 1 1 I j Select The value of the digital start address register (MS) 2 1 4 Therefore, the 1 1 I modulo address register (A 0 X) 2 16 is initialized by the value of the modulo start address 1 1 (MS) 2 1 4 1 The above modulo operation explained the operation when using the modulo address register (A 0 X) 1 1 2 1 6 However, the modulo instruction M 0 VS * W @ AX »AX of DX can be specified in the modulo address register (A 1 X) 2 1 6 0 1 I Specify the logic value 0 to control MX Y to address the address bus I Υ A Β Modular operation »At this time, 1 must execute the modulo operation instruction M 0 VS t 1 1 Ι W @ AX 1 AX AX is changed to the specified index address register (I 1 A 0 y) 2 2 6 or (A 1 y) 2 2 6 The value A y is used, and 0! 1 is assigned to the control bit D Μ & gt It can also be referred to as the implementation of the modulo calculation of ΓΓΓ 〇 1 1 Use a ruler on paper to mark the standard of the home country 7 centimeters 7 9 2 4 3 2 3 2 6 A7 B7 Printed by the cooperative V. Description of the invention (19) 1 [圚 4 represents the DSP engine 3 — example block diagram] recorded as a random logic 1 1 series circuit (Ran c 01D Logic Cir CU lit) 3 0 1 circuit block 131 1 ί I refers to the decoder 3 4 and control circuit in Figure 1! And the control register and state 1! Please refer to the circuit block of the state register, etc. 9 Other DSP engines 3 have > Read first for arithmetic logic 1 1 Read | ALU) 3 0 2 * Shifter (SFT) 3 0 3 > Back 1 1 Multiplier (Μ AC) 3 0 4 »Register (R e S) 3 0 5, please note this [Register (A 0 A 1) 3 0 6 9 register (Y 0 Y 1) item and then 1 1 3 0 7 register (X 0 > X 1) 3 0 8 store data buffer write one hundred pack I (Μ DBI) 3 0 9 store data Buffer (Μ DBX) Male 1 1 I 3 1 0 Store data buffer (Μ DBY) 3 1 1 0 Store data [! Buffer (Μ DBY) 3 1 1 connects the data bus YDB and the bus 1 1 D 2 0 stores the data buffer (Μ DBX) 3 1 0 connects the data / pB 1 line XDB and the bus D 1 〇 stores the data buffer (Μ DBI) 1 1 3 0 9 is connected to data bus IDB and bus C 1 D 1, A 1 i 1 Β 1 0 multiplier (Μ AC) 3 0 4 is white bus A 1 and B 1 input 1 1 1 input data Output the corresponding multiplication result to the bus C 1 and D 1 〇1 J Shifter (SFT) 3 0 3 White bus A 2 The input data will be shifted 1 I The output result will be output to the bus C 2 9 Arithmetic logic Arithmetic unit (ALU) 1 3 0 2 White bus A 2 and B 2 input data and output the result of the vehicle to the total 1 1 line C 2 1 Figure 5 shows the format and instructions of the instructions contained in the instruction system of the microcomputer 1 1 code — — Example 0 Microcomputer 1 supports CPU instructions and DSP instructions 2 1 1 Type I instructions 0 All CPU instructions and DSP instructions A part »is a 1 6 1 long command code. The DS DS command becomes a 3 2 long command code 1 1 This paper size is applicable to China National Standard (CNS) A4 (2 〖〇X297mm） -22 -Consumption cooperation between employees of the Central Bureau of the Ministry of Economic Affairs, Du Duanzhuang 4 3 2 3 2 6 A7 _____ B7___ V. Description of the invention (2). CPU instructions, that is, instructions that are implemented by CPU core 2 without having to make the DSP engine act. The DSP instruction is a part of processing such as address operation or operand access to CPU core 2. The DSP engine implements the instruction. The CPU instruction allocates the highest 4 digits of the instruction code in the range of 0 000 " ~ '1 1 10〃 "The DSP instruction allocates the highest 4 digits of the instruction code in the range of' I 1 1 1 # * more The uppermost 6 digits of the instruction code are allocated in the range of 1 1 1 00 'and t 1 1 1 1 0 1 ". The DS P instruction is also a 16-bit long instruction code. The uppermost 6 digits of the instruction code are t 1 1 1 1 10 ", which are 32-bit long instruction codes. In the uppermost 6 digits of the instruction code, the range 1 1 1 1 1 is not assigned instructions, and its range is used as an unused area. An undefined instruction area 'will use this area to further expand the instruction code. From the instruction format, it can be known that 'the uppermost 6 bits of each instruction code are decoded, that is, a decoder of a small logic scale can determine that the instruction width is a CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP. Instruction or undefined instruction. In the C P U instruction format of FIG. 5, η η η η is the designated area of the destination operand. Dddd is the shifted instruction area. I i i i i i i i is the designated area of the immediate value. In addition, the nnnn of the ADD instruction is also the designated field of the source operand, and the operation result is stored in nnnn * Furthermore, the aforementioned modulo operation instruction described in FIG. 3 corresponds to the instruction MOVS, W @ R2, AO of FIG. 5 However, the instruction description in Figure 5 is different from that described in Figure 3. ° This paper is different in this form. The paper size applies to China National Standard (CNS) A4 (mm). _ ---:- -^ ---- 参 ------ < 玎 ------- (Please read the notes on the back before filling in this page)

A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention (21) 1 | J is actually the same. 1 I decoder 3 4 connection configuration example 9 is taken out according to the instructions of the microcomputer as 3 2 bits 1 I please f unit> in the instruction register (IR) 2 5 implementation 0 decoder 2 4 has a read 1 I read I The first decoding circuit 2 4 0 > the second decoding circuit 2 4 1 »and the code conversion back Jf 1 1 circuit 2 4 2 The first decoding circuit 2 4 0 is the instruction register (IR note drawing |) 2 5 Upper 16-bit field (CIR) value translation brick 1 according to the instruction and then 1 fill in the instructions for CPU instructions 1 or 16 for DSP instructions 1 or 32 for 2 bits% IDSP instructions installed * to form CPU decoding Signal 2 4 3, DSP decoded letter page • w 1 ί r No. 2 4 4 1 Code conversion control signal 2 4 5 and shift control signal 1 1 2 4 6 0 2nd decoding circuit 2 4 1 Decodes the CPU decoding signal 2 4 3 1 1 to form the processor or register inside the CPU core 2 Select various internal control signals of order 1 * lie (CPU control signal) 2 4 7 〇 Code change 1 | Switch circuit 2 4 2 Press the code to change the control signal 2 4 5 when activated 1 I shrink or still output instructions Register (IR) 2 5 Lower side 16 1 1 y-field (LIR) The number of bits of information held in the code conversion control signal 2 4 5 1 When inactive, information indicating that its output is invalid (Won-1 I Op er at ion Code) 〇 The code conversion circuit 2 4 2 replaces the signal with the output of the invalid 1 information 2 4 5 When the inactive state is on the lower side of the 16-bit field 1 1 (LIR) the meaning of the value 9 You can also choose Implements DSP decoding signal I 2 4 4 and code conversion circuit 2 The output of 4 2 is described as 1 1 IDSP control signal 2 0 is supplied to the decoder 3 of the DSP engine 3 4 0 刖 1 1 is described as the first decoding circuit 2 4 0 1 Because it is stored in the instruction register W ( IR 1 1) 2 5 16-bit upper field (UIR) 6-bit top 1 1 This paper wave scale is applicable to China National Standard (CNS) A4 specification (210X297 mm) _ 24

4 3 2 G A7 B7 Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives. 5. Description of the invention (22)! 1 Decode r to determine whether the instruction code is a CPU instruction »or 16-bit 1 JDSP instruction or 3 2 Bit DSP instruction 〇1! I When the decoded instruction is 16-bit instruction * Code conversion control signal 1 I Please 1 2 4 5 becomes inactive 1 So the code conversion circuit 2 4 2 Read the output table first 1 1 Read \ Won Op er at ion Code showing invalid output 〇 Also, decoded instruction 1 6 back 1 1 Shift instruction signal when 1-bit instruction 2 4 6 Activation 9 Accept this instruction and send a note 1 Register (IR) 2 5 is to move the lower 16-bit field (LIR) item by 1 and fill the value to the upper 16-bit field (LIR) »Use the shifted instruction I as a true second instruction All or part of it is used, for example, on the page 1 1 instruction register IR above the 16th jaw area UIR store 16 bits [1 CPU instruction in the lower side area LIR store 3 2 bits DS P instruction 1 1 of Description of the upper 16-bit instruction code 〇 First stored in the upper order 1 side 16 16-bit field UIR 16 6-bit CPU instruction in the first decoding circuit 1 I 2 4 0 decoding according to the result CPU -F +-heart 2 implements its instruction storage lower 1 1 | side 1 6-bit field LIR 3 2 bit DSP instruction above 16-bit 1 1 疒 instruction code data is transferred to upper-side 16-bit field UIR 〇 at this time 1 random logic circuit 2 0 1 The arithmetic operation unit AU 2 0 8 should be implemented. 1 1 The address stored in the program counter PC is calculated. 9 The program counter 1 PC stores the address calculated by the arithmetic operation unit AU 2 0 8. The address i 1 is calculated. According to the address stored in the program counter PC, the above 3 2 digits of the IDSP instruction are lower than the 16 digits of the instruction code data 1 and the stored 1 is 1 1 I The instruction memory is transferred to the lower side of the instruction register 1 6 bit area 1 1 LIR 0 Therefore ♦ 32-bit DSP instructions are stored in the instruction register 1 1 IR 〇 and 32-bit DSP instructions stored in the instruction IR 2 2-bit DSP instructions »Translated 1 1 Central Standard of the Ministry of Economic Affairs 扃 Printed by Employee Consumer Cooperatives 4 3 ?)),-,-*. ·, 'Ί V. Invention Description (23) The encoder 24 is provided to the decoder 34 of the DSP instruction engine 3. Also, although other methods are not shown, the plural instruction pre-fetch buffer is set in the CPU core 2. The plural pre-fetch buffer is a designation that should be implemented before the current instruction pre-fetch cycle. The prefetch buffer transfers the 32-bit DSP instructions above the 16-bit instruction code data from the lower-level LIR to the upper-side 16-bit VIR as described above. The random logic circuit 2 0 1 selects the 32-bit DSP above. The lower 16 bits of the instruction is the instruction prefetch buffer for data prefetch. Read the specified code data of the lower 16 bits of the 32-bit DSP instruction from the selected instruction prefetch buffer and store them in the LLR in the lower bit area of the instruction register IR. When the complex decoded instruction is a 16-bit CPU instruction, the D S P decoded signal 2 4 4 becomes a code representing TTon-Operatiori. When the decoded instruction is a 16-bit DSP instruction, the CPU control signal 247 forms a second decoding circuit 241 according to the CPU decoding signal 243. The control signals inside the DSP engine 3 are essentially decoded by the decoder 34 to form a DSP translation. Code signal 244 »When the decoded instruction is a 32-bit DSP instruction, the CPU control signal 247 forms a second decoding circuit 24 1 according to the decoded signal 243. The control signal inside the DSP engine 3 is decoded by the decoder 3 4 The outputs of the DSP decoding signal 2 4 4 and the code conversion circuit 2 4 2 are formed. The instruction system of the microcomputer 1 has 16-bit and 32-bit instruction code tables. As described above, since 16-bit long instructions are processed differently from 32-bit long instructions, their actions are described in detail. First explain 16-bit long instruction 3 The first decoding stove 240 is the instruction A7 B7. U3. (Please read the precautions on the back before filling this page) This paper is a universal Chinese standard (CNS) A4 specification (2 丨 0X297mm) _ 26-4 3 2 ^ -26 A7 B7 Printed by the consumer cooperation of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (24) 1 I register (2 R) 2 5 Take out 3 2 digits The upper order of the instruction code is 1 6 1 1 I-bit decoding> In the first decoding circuit 2 4 0 ♦ The highest order of the instruction code is known 1] The 6-bit code is% 1 1 1 1 1 0 1 1 1 1 1 For other than 1-dimension, 1 I please J 1 is a 16-bit long instruction »Therefore, at this time, the CPU decodes the signal 2 4 3 and reads first 1 I Read 1 The DSP instruction decodes the signal 2 4 4 — same as the 9 register (Back 1 IIR) 2 5 Lower 1 16-bit area LIR instruction code data shifting attention [I in upper 1 16-bit area U 2 R shift control signal 2 4 6 Sexuality 9 items JL 1 1 Fill in 1 Intrinsic shift control letter wE 2 4 6 Instruction register (IR) 1 2 5 This is to move the instruction code stored in the lower 16-bit LIR to the page 1 1 High-order 16-bit field U 2 R 9 Shift instruction code is followed by first 1 1 code circuit 2 4 0 decoded 0 CPU instruction output by decoder 2 4 decoded signal 2 4 3 is output to the second decoding circuit 2 4 1 The DSP order I decoding signal 2 4 4 is supplied to the DSP engine 3 〇 t t 1st decoding circuit 1 I 2 4 0 Makes a code conversion when it is known as a 16-bit long instruction The control letter 2 4 5 1 1 I is inactive, so the code conversion circuit 2 4 2 forms a code nt- indicating that the instruction code of the lower 16 16 bits 1 1 is invalid as a part of the DS P control signal. 〇 On the DSP engine 3 Side 9 will output 1 of the first decoding circuit 2 4 0 [DSP decoding signal 2 4 4 and Code conversion circuit 2 4 2 The generation 1 code signal is used as the DSP control signal. 2 When it is input> Decoder 3 4 Implementation 1 1 The decoding of the DSP control signal 2 0. The reason for the 6-bit DSP instruction • 丨 I code conversion circuit 2 4 2 The output of the DS ρ control signal is a signal indicating that there is no 1 1 effect. Therefore, the decoder 3 4 focuses on the DSP decoding signal 2 4 4 t and outputs 1 1 to the DSP engine 3. Multiplier (Μ AC) 3 0 4 »Arithmetic logic 1 1 Series arithmetic unit (ALU) 3 0 2) and shifter CSF Ding) 3 0 3 1 1 This paper size applies to China National Standard (CW) A4 (210X 297 mm) _ 27-Control letter printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 3 23 2 6 A7 B7 V. Description of the invention (25). The DSP engine 3 performs arithmetic processing according to each control signal. Next, a 32-bit long instruction will be described. The first decoding circuit 2 40 in the CPU core 2 stores a 32-bit instruction code in an instruction register (LR) 25. The upper 16 bits are decoded by the first decoding circuit 240, and the decoded signal 243 · 244 ^ is output at the first decoding circuit 240. It is known that the highest 6 bits of the instruction code are > 1 1 1 1 1 It is a 32-bit long instruction, so the code conversion control signal 2 4 5 is activated. Therefore, the code conversion circuit 242 'transcodes the instruction code of the lower 16 bits of the instruction register (IR) 25 *. It is the same as the DSP decoding signal 2 4 4-It is supplied as the DSP control signal 2 0. The decoder 3 4 decodes the DSP instruction control signal 2 0 to form the control signal of the DSP engine 3. The decoders 24 and 34 can be implemented in, for example, random logic circuits. FIG. 17 shows another embodiment corresponding to the circle 6. The embodiment of FIG. 6 illustrates that the instruction data of the lower field L I R of the instruction register 25 is shifted to the upper field U I R. The embodiment of FIG. 17 'is between the aforementioned instruction register 25 and the internal data bus IDB' and has a series of two-stage instruction prefetch buffers 2 5 0, 2 5 1 'forming the instruction prefetch queue. The selector 2 5 2 Select instruction prefetch buffer 2 5 0 '2 5 1 holds data to instruction register 25. Each instruction prefetch buffer 2 5 0, 2 5 1 and instruction register 2 5 hold data in 3 2-bit units, and its holding action is controlled by control signals 01 to ¢ 3 (synchronized with CLK1) * Although not shown in the figure Instruction, each instruction prefetch buffer 2 5 0 '2 5 1 and instruction register ^ The paper size applies to the Chinese national standard (CNS > A4 specification (210X 297 ft)) _ π---- -----I- nn · 11. ^^ 1 In 1 ^ 1 fn n (Please read the notes on the back before filling out this page) Printed by the Staff Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economics 132326 A7 _____B7 V. Description of Invention (26) Device 2 5 ' It has a main vertical structure. The main segment is synchronized with the rising of the corresponding control signal to implement the latching action of the input. Therefore, the pre-fetch instruction data is stored in the two-stage serial instruction pre-fetch buffer 2 5 0, 2 5 1. The aforementioned selector 2 5 selects the 3 or 2 bits of command data supplied to port P a or the 3 2 bits of command data supplied to port P b according to the selection control signal < 6 4. a Supply the instruction pre-fetch buffer 2 5 0 upper 1 16-bit area CPB 1 is the lower side, the instruction pre-fetch Buffer 2 5 1 Lower-order 1 6-bit area LPB 2 is upper-order 3 2-bit instruction data. Port P b is supplied with 32-bit original instruction data stored in the instruction prefetch buffer 251 * Thus, instruction prefetch Buffer 2 5 1 Selector 2 5 2 when holding 3 2-bit D SP instruction. Select the output of port Pb to set the 32-bit DSP instruction in the instruction register 2 5. Instruction prefetch buffer 2 5 1 When holding 16-bit DSP instructions or 16-bit CPU instructions in the upper field UPB2, the selector 252 selects the output of the port Pb to set the 16-bit instructions in the command register 2 5 upper field UIR »Instruction When the prefetch buffer 2 5 1 holds 16-bit D SP instructions or 16-bit CPU instructions in the lower field LPB2, since the selector 252 * selects the output of the port Pa, the 16-bit instruction can be set. In the instruction register 25, the upper field UIR. The instruction prefetch buffer 2 5 1 holds the 16-bit DSP instruction upper 16 bit instruction code in the lower field LPB 2, and the instruction prefetch buffer 2 5 0 sets the 3 When the 16-bit instruction code of the lower-order side of the 2-bit DSP instruction is held at UPB 1 of its upper-level area, Due to the selector 2 5 2, the paper size of the paper used to select the port P a applies to the Chinese National Standard (cns) m specification (2! 〇χ297 mm) _ 29 _ — '------: ----: Clothing ------ ίτ ------ 1 I {Please read the precautions on the back before filling out this page} Printed by the Ministry of Economic Affairs Central Procurement Bureau Off-line Consumer Cooperatives A7 _ B7 V. Description of the invention ( 27) The 32-bit DSP instruction can be set in the instruction register 2 5 * * 2 5 3 in Fig. 17 forms the latch control signal of the aforementioned instruction prefetch buffer 1, 2, and 2 of the instruction register 2 5 The control logic of the latch control signal 0 3 and the aforementioned selection control signal 44. The control logic 2 5 is based on the control signal 2 4 8 indicating the 16-bit instruction or the 32-bit instruction and the instruction prefetch buffer 2 50 0; the remaining instruction code states of each field are not implemented to form the aforementioned control. Signal 0 1 ~. The control logic 2 5 3 forms part of the control logic for instruction fetch. In addition, the aforementioned control signal 2 4 8 is the first decoding circuit 2 4 0 to decode the command code data supplied from the upper register U 5 of the upper register field 5 to the upper 6 bits, and the details will be described later. The instruction code data is set in the instruction register 2 5 according to the aforementioned control logic 2 5 3 as follows. The instruction fetch from the outside is the instruction fetch time of the CPU core 2 (for example, the instruction fetch stage IF in the plural stage pipeline stage described later), and the instruction prefetch buffer 250 is implemented when there is room to re-store 32-bit instruction code data. When the instruction fetch is executed at its time * instruction The prefetch buffer 2 5 1 leaves unimplemented instructions. Stored in the instruction prefetch buffer 2 51. In the first state of the UPB 2 and LPB 2 instruction codes that are not implemented by both parties, the instruction prefetch buffer 2 5 1 to 3 2-bit output is sent by the selector 2 through port Pb. 5 2 Select and set to command register 2 5. —Only stored in the instruction prefetch buffer 2 5 1 in the lower area LPB 2 instruction code is not implemented in the second state, the prefetch instruction prefetch buffer 2 50 0 in the upper area UPB 1 and the instruction prefetch buffer The command code data of the lower field L PB 2 of the controller 2 5 1 is set via the port P a to the paper size of the instruction book. The applicable Chinese National Standard (CNS) A4 specification (210X297 mm) _ ~ U.---I-II —- ---. I--I —i ^^ 1 (Please read the notes on the back before filling in this page) 4 A7 B7 V. Description of the invention (28) Register 2 5 In the first state described above, the decoding circuit 2 40 decodes the result of the instruction code data set in the upper field UIR of the instruction register 25. In order to form a 32-bit instruction, the instruction prefetch buffer 2 5 0 The pre-fetched 3 2-bit instruction code data is previously transferred to the instruction pre-fetch buffer 2 5 1. -On the other hand, when a 16-bit instruction is detected from the decoding result, the self-instruction pre-fetch buffer 2 50 to the secondary buffer 2 51 are not shifted. In the aforementioned second state, after the data of the instruction register 25 is set by the port Pa, the 32-bit instruction code data pre-fetched by the instruction pre-fetch buffer 2 50 is still shifted and set in the instruction pre-fetch buffer.器 2 5 1. After the shift * If the instruction prefetch buffer 2 50 has unimplemented instruction code data, the instruction prefetch buffer 2 50 prefetches the instruction code data in the next instruction prefetch time. With this kind of control, after the instruction fetch time, the unprocessed instruction code data is set in the instruction register 2 5 * At this time, the instructions to be implemented are 16-bit CPU instructions, 16-bit DSP instructions, or 32-bit DSP instructions. The upper 16 bits must be supplied to the first decoding circuit 24 0. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs ------ ^ ---------- (Please read the note on the back before filling this page) Figure 6 Code Conversion Circuit 2 4 2 | In Fig. 1 7 is composed of a selector 2 4 2_ A and a code conversion logic 2 4 2 B = Also, the first decoding circuit 2 4 0, it is illustrated in Fig. 6 whether the decoded instruction code is 1 or not. The 6-bit instruction forms a control signal 2 4 5, 2 4 6 to control its level, and in the example in FIG. 17, an instruction code identifying the decoding thereof is output. 1 6-bit instruction or 32-bit instruction (3 2 in this embodiment) The bit instruction is a control signal 248 used by the DSP instruction. Selector 242A, the control signal 248 paper size. Applicable to China National Standard (CNS) A4 specification (2 丨 0X297 hex) _ μ A7 4 3 2 3 2 6 ____B7_ V. Description of the invention (29) ί ^^^ 1 · Kn ^^^ 1 In m 1 JT (please read the note on the back first and then fill in this page) It means that when selecting 16-bit instructions, 'select Ν ο η 0 perati 〇n C 〇dew ο p provides code conversion logic 242B, control Signal 248 indicates that when 32-bit DSP instructions are used, the instruction code of the lower-level area LIR of the instruction register 25 is provided to the code conversion logic 242B »Code conversion logic 242B. Although not specifically limited, the instruction code of the lower-level area LIR instruction code of the instruction register 25 A part of the data, such as code information for register selection, is modified to a form output suitable for the decoder 34 of the DSP engine 3. In the embodiment of Figure 17 printed by the Central Bureau of Standards, Ministry of Economic Affairs and Consumer Cooperatives, the first decoding circuit 240 interprets the 16-bit instruction code data held by the instruction register 25 in the upper field UIR. • Decodes the obtained CPU signal. 2 4 3 is supplied to the second decoding circuit 243, and DSP decoding signal 244 is supplied to the decoder 34. The CPU decoding signal 2 4 3 is intentional in either the CPU instruction or the DSP instruction, and is supplied to the second decoding circuit 241 and the second decoding circuit 241 to decode the CPU decoding signal 2 4 3 and output the CPU core. 2Control information for address calculation and data calculation to be implemented, and internal storage X — ROM 4, Y-ROM5, X — RAM, Y-RAM, and external storage access, stop bus and data line selection and control Information, etc. 'As mentioned above, for the DSP instruction, the necessary address calculation and data bus selection are also implemented by the CPU core 2. The aforementioned DSP decoding signals 2 4 4 are supplied to the first decoding circuit 2 4 as described above. When the instruction code is code data for DSP instruction, it becomes an intentional decoding signal. The intentional D S P decoding signal 2 4 4 contains, for example, designated information such as a register in the D S P engine 3 that transfers data between the memories accessed by the address operation performed by the CPU core 2. The paper scale for the first decoded electric paper is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 0X297 male thin) _ 32 _ 4r, Guang Λ -Λ-+, Guang N ci c ο ^ 〇 Α7 Β7 Central Ministry of Economic Affairs Printed by the sample consumer cooperative of the staff. V. Description of the invention (30) When the instruction code of 1 2 4 0 is a CPU instruction, the DSP decoded signal 1 1 2 4 4 becomes an invalid code 9 1 1 More details are included. Code of the aforementioned DSP instruction 1 1 I in the instruction system of the microcomputer 1. Figure 18 and Figure 19 respectively show the 16-digit D S P instruction. Please read the 1 1 instruction code diagram 20 and Figure 21 for the 32-digit D S P instruction. Read the back 1 code. As mentioned above, the DSP instruction allocates the first 1 bit of the 4 most significant side of the instruction code to '1111, and the 6 most significant side of the instruction code is%. Then 1 1 1 1 110 0, and' 111 10 1 ^ 16 DSP instructions of 6 bits k. Let 6 bits of the highest order side of T instruction code be '1111 1 0'. Page 1 f Let DSP instructions of 32 bits be 1 g. I Figure 1 of 8 The instruction format of the 1 1 16-bit DSP instruction shown in Section 1 (X Side of Data Transfer) is the data between the X memory (X — ROM 4 and I »X -RA Μ 6) and the built-in registers of the DSP engine 3. 1 I transfer instruction. In the above instruction format > AX, A y are designated to be included in the register array 2 0 9 (refer to Figure 3) of the ICPU core 2 register 1 1 f »AX, 0 ^ is the designated register R 4, AX = '1 ^ Is designated 1 | register R 5 »A y = " 0 ^ is designated register R 6 1 Ay '1 1 1 I is designated register R 7. DX, D y, D a are designated registers included in 1 DSP engine, DX = '0 〃 designated registers X 〇, D 1 1 X =, designated registers X 1, D y =' 0 " designated registers 1 Device Y 0, D y = '1 is designated register Y 1' D a =, 0 / f 1 1 is designated register A 0, D a = • ft 1 f is designated register A 1 g 1 1 IX, I y Represents an immediate value. 1 I Figure 1 9 The instruction format of the 16-bit DSP instruction is connected to the micro 1 1 The paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) _ 33 _ Employee Consumer Cooperatives, Central Bureau of Standards, Ministry of Economic Affairs Print A7 _B7_ V. Description of the invention (31) The data transfer instruction between the unillustrated memory outside the computer 1 and the built-in register of the dsp engine 3. A s specifies the registers included in the register array 2 0 9 (refer to FIG. 3) of the built-in CPU core, and D s specifies the registers XI, X0, Y1, Y0, A1 that are built in the DSP instruction engine. AO and register array 305 (See Figure 4) Registers included. The format of the 32-bit DSP instruction is a field representing the code of the 1-bit DSP instruction (bit 31 to bit 26), a block A (bit 25 to bit 16) and a block B (bit 1 5 to bit 0). Figure 20 shows the code of the information group A and its corresponding mnemonic, and Figure 21 shows the code of the information and the corresponding mnemonic when it looks at the B group. The code of the A field shown in FIG. 20 is the same as the code of bit 9 to bit 0 of the 16-bit DSP instruction shown in FIG. 18, and it is shown in column A of the 20th column (X Side of Data Transter). The code of the block is to specify the data transfer between the X memory (X-R0M4 ,, X-RAM6) and the built-in registers of the DSP engine 3. The code of the block A in the second block (Y Side of Data Transter) Provides data transfer between Y memory (yrOM5, Y-RAM7) and the built-in registers of DSP engine 3. The contents of the bits Ax 'Ay' Dx, Dy, Da contained in the A block are exactly the same as those in Figure 18 * Figure 2 The code of the B block shown in Figure 1 specifies the arithmetic operations and logical operations implemented in the DSP engine 3 Load / store processing between 'shift operations' registers. For example, stipulate that the multiplication (PMULS), subtraction (PSXJB), and addition (PADD) implemented in the D sp engine 3 are applicable to the national standard (cns) A4 specification (mm) -34 -------- ----- Installation ------ Order (please read the notes on the back before filling out this page) Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 432326 A7B7 V. Description of Invention (32) Enter (PRND) , Shift (PSHL), logical product (PAND), exclusive logical sum (XOR), logical sum (OR), add (PINC), subtract (PDEC), clear (CLR) and other operations or within the DSP engine 3 Implemented load (PLDS) and storage (PSTS). The third block (3 0 Operand Optr-ation with Condition) in Figure 21 is a conditional code. Its condition (if cc) is a logical value that can select the DC (data completion) bit (indicating that the data has been processed) or See. The actual 32-bit D S P instruction is described as an arbitrary combination of the B field code and the A field code. That is, the 32-bit D S P instruction fetches the operation object of the internal or external computing object of the microcomputer 1, and specifies the processing to be performed inside the D S P engine. As can be understood from the above description, the address calculation for operand fetching and the selection of the data bus are implemented by the CPU 2. The 32-bit D S P instruction specifies the code of the A field to be fetched from the 16-bit D S P instruction. The 16-bit D S P instruction is used to initialize the internal registers of the DSP engine 3. Referring to FIG. 17 and the like, it is shown that the code data of the A field of the 32-bit DSP instruction is set in the instruction register 2 5 upper field UIR »Also, the 16-bit DSP instruction having the same format as the A field is also Set in the upper field UIR »Therefore, no matter what, CPU core 2 will also perform the required address calculation and data fetch (or operand fetch). The necessary data bus can be selected. In other words, 3 2 bit DSP instructions will be implemented. Decoding circuit for data fetching (or operand fetching) and data fetching (or operand) for implementing 16-bit DSP instructions. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm). _ (Please read the precautions on the back before filling this page)-* --- Γ-

* 1T 4 3 23 2 6 The consumer cooperation of the Central Bureau of Standards of the Ministry of Economic Affairs of the People's Republic of China Du Yinzhuang A7 B7_ V. Description of invention (33) 240, 241 is shared, which is also beneficial to the reduction of the logical scale of microcomputer 1. The designated information of the internal register of the D S P engine 3 designated by the A field of the 3-bit D S P instruction and the designated information of the internal register of the D S P engine 3 designated by the 16-bit D S P instruction are supplied to the DSP engine 3 as the aforementioned DSP decoding signal 244. Whether the DSP decoded signal 2 4 4 is intentional or not is determined by decoding the 4 bits of the uppermost side of the upper field UIR by the first decoding circuit 2 4 0 described above. Next, the content of the arithmetic control of the microcomputer of this embodiment will be described with reference to the instruction implementation schedule of Figs. The microcomputer 1 of this embodiment implements five stages of pipeline operations in the stages of I F, ID, EX, MA, WB / DSP. IF is the instruction fetching phase, ID is the instruction decoding phase, EX is the operation implementation phase, MA is the memory access phase, and WB / DSP is the phase of fetching data obtained from the memory into the registers of the CPU core 2 or the DSP engine 3 implementation DSP instruction phase. In each figure, Instrnction / Data Access indicates the memory access via the internal bus I AB and IDB. The access object is the built-in memory 4 ~ 7 and may also be the external memory of the microcomputer 1 "XY Mem. Access indicates the internal total XAB, XDB, YAB, YDB memory access and access objects are limited to built-in memory 4 ~ 7. Isnt, Fetch refers to the instruction fetch time of the instruction register (IR) 2 5; Fetch, Reg means the instruction register (IR) 2 5; Sonrce Data Ont refers to the source data output; Destination In refers to the input time of the destination data> Destination Register means Destination register. Pointer Reg means text register, Address Calc, address calculation * Deta Fetch means data fetch, Dsp C.ontrol (Please read the precautions on the back before filling this page) This paper's music standards are applicable to the Chinese National Standards ( CNS) A4 specification (210 × 297 mm) _ 36-Central Ministry of Economic Affairs, Central Bureau of Justice, Consumer Cooperation, Du printed 432326 A7 B7 V. Description of the invention (34) Signal Decorated Timing means DSP control with decoder 3 4 Decoding time of signal 2 0. Figure 7 shows the implementation time chart of the ALU operation instruction inside CPU core 2. Here we will add ADD Rm, Rn as an example of ALU operation instruction. Synchronize the storage with the rising of the clock signal ciock2 immediately before the IF phase. Time, the address of the instruction (ADD, Rm, Rn) to be implemented is output to the IAB of the address bus. The memory access operation is implemented in the Instruct i on Data Mem, Access IF stage Specifically, the decoding of the address specified by the address bus I AB is performed during the rising of the clock signal Clock 1 to the rising of the clock signal Clock 2, and is implemented during the rising of the clock signal Clocfc2 in the IF phase to the rising of the next clock signal Cloctl. Instruction access. Therefore, the clock signal Clock2 from the IF phase rises and the instruction is output to the data bus. The instruction output from the data bus IDB is synchronized with the rise time of the clock signal Clock1 in the ID phase and is taken into the instruction register (IR) 2 5. In the D phase, implement the decoding of the data taken into the instruction register (IR) 2 5. Synchronize with the rise time of the clock signal Clockl in the EX phase, access the register that stores the source data * and round the value of the register to The internal bus Al, B1 of CPU core 2 «In the instruction ADD Rm, Rn will make the registers specified in Rm and Rn become source registers. Rm and Rn can instruct any register in CPU core 2 (in Figure 3, you can specify the register 209 Any of the registers AOx, Alx 'Ix * A〇y'Aly · Iy,-Rm and Rn? Output to the internal bus A1 of CPU core 2, and the data of B 1 are in the paper size application National Standard (CNS) A4 Specification (2 丨 0X297mm) _ π _ (Please read the precautions on the back before filling this page) • Equipment-3 2 6 A7 B7 ____ 5. Description of the invention (35) Operation logic operation (ALU) 2 1 3 performs the addition operation. The result is output to the internal bus C1 of the CPU core 2. The calculation result output on the internal bus C1 of the CPU core 2 is synchronized with the rise time of the clock signal Clock2 in the E and X phases, and is stored in the destination register (the destination register becomes the register specified in Rn by the ADD Rm and Rn instructions). As described above, the ALU operation instructions inside the CPU core 2 complete the instruction implementation operations in the pipeline stages of IF, ID, and EX *. Figure 8 shows the timing of the data read operation from the memory to the CPU core 2. Here MOV, L @ Rm, Rn is an example of the data read operation from the memory to the CPU core 2 to describe its operation. Since the operations of instruction fetch (IF) and instruction decode (ID) are the same as those in Fig. 7, detailed descriptions of the parts are omitted. The rise time of the clock signal Clockl, which is synchronized with the E X phase, is used as the data of the register of the address pointer to be output on the internal bus A 1 of the CPU core 2. In this example, the register that becomes the address pointer is the register designated by Rm. The register that can be specified in Rm is an arbitrary register included in OP U core 2 (in FIG. 3, any register that is included in Reg can be designated ‘AOx’ Alx, Ix, A〇y, Aly ’ly as Rm). The data output on the internal bus A1 of the CPU core 2 is stored in the address buffer 205, and the rise time of the clock signal Clock2 synchronized with the E X phase is output on the address bus. On the one hand, the data output on the internal bus A 1 of the CPU core 2 is performed by the arithmetic logic operation unit (ALU) 2 13 "At this time, the arithmetic logic operation unit (ALU) 2 13 performs 0 addition operation" The result is output in This paper size applies to Chinese standards (CNS > A4 size (2I0X297)) _ 38 _ 11 III-~ II n (Please read the precautions on the back before filling this page) Central Office of Standards, Ministry of Economic Affairs, Consumer Cooperatives Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 432326 A7 ____ B7 V. Description of the Invention (36) The internal bus Cl of CPU core 2. The results of the computation on internal bus C 1 of CPU core 2 are synchronized at the EX stage The rise time of the clock signal Clock 2 is stored in the pointer register (in this case, the register designated by Rm). In the Instrnction / Data Mem, Aecess, the clock signal Clock 1 in the M A phase rises to the clock signal Cl ock2 During the rising period, it is synchronized with the EX stage: the rising time of the clock signal Clock 2 'implementation of the address from the address bus I AB'. The clock signal Clock 2 in the MA phase rises to the next clock Data access is implemented during the rising of Clockl. Therefore, the clock signal Clock2 from the MA phase rises to output data on the data bus 1 DB 4 and the data on the data bus 1 DB is synchronized to the clock signal Clock 1 of the WB / DSP phase. The rise time is taken into the CPU core 2 'and the data is output to the internal bus DW of the CPU core 2. The rise time of the clock signal Clock2 synchronized to the WB / DSP phase stores the data on the internal bus DW of the CP core 2 Destination register 'Complete action β' In this example, the destination register becomes the register specified in R η β The register that can be specified in R η is any register included in CPU core 2 (In Figure 3, any register in Reg can be specified ' A〇x, Alx 'IX, A〇y, Aly, Iy is Rn) »As above, read the data from the memory to the CPU core 2 into the action instructions, using the IF, ID, EX, MA / DSP pipeline stage 5 Complete the instruction implementation action e Figure 9 shows the time chart of writing action instructions from the CPU core 2 to the memory. Here are MOV, Lrm, @Rn for the action of reading data from the CPU core 2 to the memory—exemplary description Action. Due to instruction Paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) —39-ί —: -------- ^ ------. Η ------ I (Please read the Please fill in this page again.) Printed on the A7 B7 of the Central Bureau of Standards and Quarantine of the Ministry of Economic Affairs. Fifth, the description of the invention (37) The operation of fetching (IF) and instruction decoding (ID) is the same as that in Figure 8, so its parts are omitted. Detailed description. The rise time of the clock signal Clock 1 which is synchronized with the E X phase, and the data of the register as the address pointer is output on the internal bus A 1 of the CPU core 2. In this example, the register that becomes the address pointer is the register designated by Rm. The register that can be specified in R η is any register that is included in CPU core 2 (in Figure 3, any register that is included in R eg can be specified, and A〇x, Alx, Ix, A〇y, and Aly 'Iy as Rn) . The data output on the internal bus A1 of the CPU core 2 is stored in the address buffer 205, and the rise time of the clock signal Clock2 synchronized with the E X phase is output on the address bus I A B. On the one hand, the data outputted to the internal bus A 1 of the CPU core 2 is performed by the arithmetic logic unit (ALU) 213 ^ At this time, the arithmetic logic unit (ALU) 213 performs 0 addition operation. The calculation result is output to the internal bus C1 of the CPU core 2 «The calculation result output to the internal bus c 1 of the CPU core 2 is the rise time of the clock signal Clock 2 synchronized with the EX phase and stored in the finger decoding (this When registering Rn and @Rn in MOV, L, the address calculation is performed in the Ex stage, and at the same time, the preparation of outputting the data to be written into the memory to the data bus IDB is implemented. The rise time of the clock signal Clockl which is synchronized with the stage of E X is transferred from the internal bus DR of the CPU core 2 by the register storing the data to be written into the memory. In this example, the decoding of the data that should be written into the memory becomes a register designated by Rm. The register that can be specified in Rm is any decoding included in CPU core 2 (I · * _. 1 I-! I -1. I I —r ^ i 1 ^ 1 1. ^^ 1 (Please read the back first Note: Please fill in Mu Yu again.) The paper size of the edition is applicable to China National Standards (CNS). Λ4 is current (210X 297 mm) _ 432 ^ 26. Printed by A7 B7. Explanation (38) In FIG. 3, Reg can be specified in any register, and AOx, Alx, Ix, A0y, Aly, and Iy are Rm). The value of the internal bus d r output to the CP core 2 is the data bus I D Β which is synchronized with the rising time of the clock signal Clock2 in the MA stage. In Instrnction / Data Mem. Access, the clock signal Cl ockl rises to the clock signal in the phase A. The rise time of Clock 2 is synchronized with the rise time of the clock signal Clock 2 in the EX phase. The translation of the address of the output address bus I AB The code is synchronized with the rise time of the clock signal Clock 2 in the MA phase and written into the wheel for the completion of the data from the data bus IDB. The action instructions are written from the memory to the data of the CPU core 2. Since the CPU core 2 completes the operation at the time when the data is output to the data bus IDB, the operation is completed in the four-stage pipeline stage of IF, ID, EX, MA β Figure 10 shows Time chart when the DS P instruction is implemented. Take PADDC Sx, Sy, Dz NOPX, NoPY as an example of D S P instruction to explain its operation. This instruction implements the addition of the data stored in the registers in DS Engine 3, and does not implement the data transfer instructions between DS Engine 3 and X-R0M4 and X-RAM6, and Y-R0M5 and Y-RAM7. The instruction fetching operation is the same as circle 7, so detailed description of the part is omitted. In the ID stage, the instruction code decoded by the CPU core 2 during the clock signal Clock1 to the clock signal Clock2 is implemented, and the result of the instruction code decoding will be output as the DSP control signal 20 at the time of the clock signal Clock2 in the ID stage. In DSP Engine 3. Applicable to China Paper Standard (CNS) A4 (210X 297 mm) _ 'I-" (Please read the precautions on the back before filling this page) • Binding and _B7____, V. Description of the invention ( 39) DSP engine 3. When the DSP control signal 2 is input from the CPU core 2, the DSP control signal input during the MA phase is decoded. 4 Synchronize with the rise time of the clock signal Clockl of the WB / DSP phase. The value is output to the internal buses A2 and B2 of the DSP engine 3. In this example, the register storing the source data becomes the register designated by SX and S y, and the register that can be designated in SX and S y is any register in DSP Engine 3 (any register in 'Reg * in Figure 4 can be designated as Sx and Sy). The data of the internal bus A2 and B2 of the DSP engine 3 are output to the arithmetic logic operation unit (ALU) 302. The result is output to the internal bus C2 of the DSP engine 3. The output result of the internal bus C2 of the DSP engine 3 is synchronized with the rise time of the clock signal Clock 2 in the WB / D SP phase and stored in the destination register. In this example, the destination register becomes the register designated by D z. The register that can be specified in D 2 is any register in D S P engine 3 (Figure 4 is any register in Reg). The above DSP instructions are completed in five pipeline stages of IF, ID, EX, MA * WB / DSP. Printed by Shelley Consumer Cooperative of China Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this page) 圊 1 1 indicates the time from the X, Y memory 4-7 to read the data into the DSP engine 3 action instructions Figure. Here is an example of MOVX. W, @AX, DX, M0VY. W @ Ay, Dy as instructions for reading data from X, Y memory 4 ~ 7 to DSP engine 3. This instruction will The data stored in the addresses specified by AX and A y are transferred to the instructions specified by DX and D y. The instruction fetching and the operation of the instruction decoder are the same as those in Figure 10, so the detailed description of this part is omitted-this paper size applies China National Standard (CNS) A4 Specification (2 丨 0X 297 public address) _ 42-Duplicate printing of employee cooperation of the Central Standards Bureau of the Ministry of Economic Affairs

V. Description of the invention (40 implementation of white X t Υ memory 4 to 7 when reading data from the DSP engine 3 into the operation instructions f access to the memory address to form the CPU core 2. Therefore, the clock signal Clockl rise time synchronized with the EX phase To access the register that stores the address that should be accessed, output the value of the register to the internal bus A 1 ~ A 2 of C P ϋ core 2. In this example, the register that stores the address that should be accessed becomes AX, which is designated by Ay Registers. The registers that can be specified in Αχ are the registers A0χ and A1χ that contain CPU core 2, and the registers that can be specified in Ay are the registers A0y and A 1 y 0 that are contained in CPU core 2. They are completely from C PU core 2. The data of the internal bus A 1 ~ A 2 are stored in the memory address buffer (MABX, MAB Y). The rise time of the clock signal Clock 2 synchronized with the EX phase is output on the address bus XABYAB β. The internal bus of the CPU core 2 is output. The data of A 1 A 2 uses ALU [213, PAU212 for address calculation. At this time, ALU 21 3 and PAU 2 1 2 perform 0 addition operation 9 The calculation result is output to the internal buses C 1 and C 2 T of the CPU core 2. The calculation result is output to the internal bus C 1 and C 2 of the CPU core 2 and is stored in the pointer during the rise of the clock signal Clock2 in the EX phase. Register (that is, the register P designated by AX and Ay in the X, Y memory 4 7 t from the clock signal Clockl to the clock signal Clock2 rises, implements the EX phase clock signal Cloc- k2 output rise time Decoding of addresses on the address bus XAB, YAB »The clock signal Clock2 in the M A phase rises to the next clock signal Cl 0C k]. Data access is performed during the rising period. Therefore, the clock signal C1 0 in the MA phase The rise of C k2 will output the data to the data bus XDB. This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) _ 43 ~ 43 23 26 Α7 Α7 Β7 V. Description of the invention (41), YDB. The data of the output data bus XDB and YDB are taken from the rise time of the clock signal Clockl synchronized to the WB / DSP phase. The DSP engine 3 supplies data to the internal buses D1, D 2 of the DSP engine 3 »The rise time of the clock signal Clock2 synchronized to the WB / DSP phase stores the data on the internal bus D1'D2 of the DSP engine 3 in the destination register to complete the action . In this example, the destination register becomes the register designated by DX and DY. The register that can be designated in D X is the register X0, XI contained in DSP engine 3, and the register that can be designated in Dy is the register YO 'Y1 contained in DSP engine 3. As mentioned above, the data read operation instruction from the memory to the DSP engine 3 is completed by the five-stage pipeline stages of IF, ID, EX, MA, WB / DSP. The data read operation of the parallel operation is independent of each other. The buses XAB, XDB, YAB, and YDB allow the CPU core 2 to access X and Y memories 4 to 7. Fig. 12 shows the time circle of writing data from the DSP engine 3 to the X, Y memories 6, 7; Here is an example of MOVX.W Da, @ A X Μ Ο V Y * W Da, ®Ay is an operation instruction written from the DSP engine 3 to the X * Y memory 6, 7 into the operation instruction. This instruction is an instruction to transfer the data stored in the register designated by D a to the address stored in the register designated by A X and A y. Instruction fetching, the operation of the instruction code is the same as that in Figure 1 *, so detailed descriptions of it are omitted | When the data from the DSP engine 3 to the X * Y memory 6, 7 is written into the operation instruction • Storage address to be accessed Form a CPU core 2. Therefore, the clock signal Clockl c synchronized with the EX phase, please read the precautions on the back before filling in this page.> Binding This paper size is applicable to the Chinese national standard (CNS > A4 size (210 × 297 mm)) Printed by the Standards Bureau Consumer Cooperatives / 13 23 26 at B7 V. Description of the invention (42) Rise time, access the address register that should be stored, and output the value of the register to the internal bus A 1 ~ A2 of CPU core 2 Synchronize with the rise time of Clock signal Clockl in the MA phase, access the internal register of DSP Engine 3 which stores the data to be transferred, output the value of this register to the internal bus D1 | D2 of DSP Engine 3, and store it in the stored data Buffer (MDBX, MDBY. In this example, the internal register of the DSP engine 3 that stores the data to be transferred becomes the register designated by D a. The register that can be designated by D a includes the registers A 0 and A 1 of the DSP engine 3. The rise time of the clock signal Clock2 synchronized with the MA phase, and the data stored in the storage data buffer (MD BX, MDBY) are output on the data bus XDB, YDB. The time synchronized with the MA phase The rise time of Clock 1 is used to access the internal registers of DSP Engine 3 that store the data to be transferred, and output the value of this register to the internal buses D1 and D2 of DSP Engine 3. * Store them in the storage data buffer (MDBX, MDBY ) ^ In this example, the internal register of the DSP engine 3 that stores the data to be transferred becomes the register designated by D a. The register that can be designated by D a is included in the registers A0 and A 1 of the DSP engine. The clock signal Clock synchronized to the MA phase 2 rise time, the data stored in the storage data buffer (MDBX, MBDY) is output on the data bus XDB, YDB. In X, Y memory 6, 7 in the MA phase, the clock signal Clockl rises to the clock signal Clock 2 During the rising period, the rising time of the clock signal Clock2 in the EX phase is used to decode the addresses output on the address bus XAB and YAB. The clock signal in the MA phase is based on the Chinese National Standard (CNS) A4 specification (210X 297 mm). _ 45 _ '(Please read the notes on the back before filling in this page >> Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Consumer Cooperatives, A7, B7, V. Description of the invention (43) Clock2 Data is accessed during the rising period of the next clock signal Clockl. Therefore, the data of the output data bus XDB, YDB are written from the rising of the clock signal Clock 2 of the MA stage. The data of 7 is written into the action instruction to complete the action in the four pipeline stages of IF, ID, EX, MA. The write operation of the parallel items is because the independent buses XAB, XDB and TAB, YDB enable the CPU core 2 to access the X, Y memories 4, 6. FIG. 13 shows the time circle of the data read operation from the memory to the DSP engine 3. MOVS, L®AS, and DS are examples of the data read operation instruction from the memory to the DSP engine 3 to explain the operation. This instruction is an instruction to transfer the data stored in the address designated by AS to the register designated by DS. The basic operation is the same as the data reading operation from X, Y memory 4 ~ 7 to DSP engine 3 shown in Fig. 11. • The difference between Fig. 11 and Fig. 13 is that Fig. 11 shows that the target memory is X. , Y memory 4 ~ 7 uses X bus and Y bus, and Fig. 13 uses the bus IAB and I DB because the target memory is the microcomputer 1 connected to the memory supporting the space. Synchronize with the rise time of the clock signal Clockl in the EX phase, obtain the register with the address that should be accessed, and output the value of the register to the internal bus A 1 of the CPU core 2. In this example, the register storing the address to be accessed becomes the register designated by AS. The register that can be designated by AS is any register contained in Reg * of CPU core 2. The data output on the internal bus A 1 of the CPU core 2 is stored in the address buffer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm > _ --.----- ^ ---- ------ Order ------ 缂-* (Please read the notes on the back before filling out this page) 4 3 23 2 6 A7 B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Description of the invention (44) The device 2 0 5 is synchronized with the rise time of the clock signal Clock 2 in the EX phase and is output on the address bus I AB. On the one hand, the data outputting the internal bus A 1 of the CPU core 2 is an arithmetic logic operation unit ALU 2 1 3, Implementing Address Operations> At this time, the arithmetic logic unit ALU213 performs 0 addition operation. The operation result is output to the internal bus C 1 of the CPU core 2. The output is output to the internal bus C 1 of the CPU core 2. The operation result is The rise of the clock signal Clock 2 synchronized to the EX phase is stored in the pointer register (ie, the register designated by As). In the memory to be accessed, the rise of the clock signal Clock 1 in the MA phase to the rise of the clock signal Clock 2 During the period when the EX phase clock signal Clock 2 rises The data output from the address bus I AB is decoded at the same time, and data access is performed during the rise of the clock signal Clock2 in the MA phase to the rise of the next clock signal Clock1. Therefore, the data is raised from the rise of the clock signal ciock2 in the MA phase. The output data bus I DB. The data of the output data bus I DB are synchronized to the WB / DSP phase clock signal Clockl. The rising time is taken into the DSP engine 3 and the data is supplied to the internal bus D 1 of the DSP engine 3. Synchronized to the WB / DSP The rise time of the clock signal Clock 2 of the stage stores the data on the internal bus D 1 of the DSP engine 3 in the destination register to complete the action. In this example, the destination register becomes the register designated by D s. It can be designated by the register of D s It is an arbitrary register in DSP engine 3. As the above reads the action instruction from the memory to the DSP engine 3, it completes the action in the pipeline stage of IF, ID, EX, MA, WB / DSP in 5 stages. Figure 1 4 indicates that the self-directed DSP engine 3 reads the data from the memory. The scale of this paper applies the Chinese national standard (cns) a4 specification Ui〇x; i97 mm > -47-{Please read the note on the back first Then fill in this matter watts) as · set. B7 Central Bureau of Standards, Ministry of Economic Affairs negative consumer cooperative work printed V. invention is described in (45) as the time chart. MOVS ‘LDS @ AS’ is an example of an action instruction written into the memory from the DSP engine 3 to illustrate its action. This instruction is an instruction to transfer the data stored in the address designated by DS to the register designated by AS. The basic operation is the same as the data writing operation from DSP engine 3 to X, Y memory shown in Figure 12: The difference between circle 12 and Figure 14 is that Figure 12 shows that the target memory is X, Y memory. Use the bus XAB, XDB bus YAB, YDB, and circle 14 because the target memory is the microcomputer 1 connected to the memory of the support space, so use the bus I AB, I DB «synchronize with the rise time of the clock signal Clockl in the EX stage, and save the The register with the address of the transfer destination, and the value of the register is output to the internal bus A1 of the CPU core 2. In this example, the register storing the address to be accessed becomes the register designated by AS. The register that can be designated by A S is any register included in the register Reg of CPU core 2. The data output on the internal bus A 1 of the CPU core 2 is stored in the address buffer 2 0 5 and synchronized with the rise time of the clock signal clocks in the EX stage. It is output on the address bus I AB The data of the bus A 1 is calculated by an arithmetic logic operation unit ALU213. At this time, the arithmetic logic unit ALU2 1 3 performs 0 addition operation. The calculation result is output to the internal bus C1 of the CPU core 2. The calculation result output on the internal bus C 1 of the CPU core 2 is synchronized with the clock signal of the EX phase ^ 0 £; the rise time of 112 is stored in the pointer register (that is, the register designated by As s). Rise time of clock signal Clock 1, 48-This paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) ------ ^ ---- buttoning -------- II --- --- Wei _ (Please read the notes on the back before filling out this page) 432326 Printed by the Central Samples Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives, printed A7 B7 V. Description of the invention (46) DSP engine that will store the data to be transferred The value of the internal register 3 is output to the internal bus D1 of the DSP engine 3 and stored in the storage data buffer (MDB2). Synchronous to the rise time of the clock signal ciock2 in the MA phase. The data stored in the storage data buffer (MD B I) is output to the data bus I DB * In this example, the internal register of the DSP engine 3 storing the data to be transferred is a register designated by P s. The register that can be specified in D s is any register in DS engine 3. The memory to be accessed is from the rise of the clock signal Clockl to the rise of the clock signal Clock2 in the MA phase, and is output to the address register of the address bus IAB with the rise time of the EX phase clock signal Clock2, and the clock signal ciock2 in the MA phase Data access is performed during the period from the rising to the next clockl Clockl. Therefore, the rise time of the clock signal Clock 2 at the MA stage is the time when the data output from the DSP engine 3 is written into the memory. As mentioned above, the data write precession instruction from the DS engine 3 to the external memory is completed in the pipeline stage of the four stages of I F, 1 D, EX, MA. Next, PADD SX > S y-D η PMUL. Se, Sf-Dg, MOVX, W®AX, Dx, MOVY, W®Ay, Dy is an example of a DSP operation instruction, and its operation will be described using FIG. 15 "This instruction It is a command for transferring data from X-R0M4 and X-RAM6 and Y-R0M5 and Y-RAM7 to DSP Engine 3. Combine the actions of Figure 10 and Figure 1. Because the instruction is fetched, the operation of the instruction decoder is the same as that in Fig. 10, so detailed description of the part is omitted. The scale of this paper applies the Chinese National Standard (CNS) A4 specification (210X297 mm) -49-I. --II-m,-J —-—-!-{_ I Γ U3., Νβ (Please read the back first Please pay attention to this page, please fill in this page) Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperative, 4 3? 1 2 6 A7 B7 V. Description of the invention (47) Implementation of reading instructions from X, Y memory to DSP engine 3 data At this time, the address of the accessed memory forms c PU core 2. Therefore, in synchronization with the rise time of the clock signal Clockl in the stage E and X, the register holding the address to be accessed is accessed. The value of the register is output to the internal buses A 1 to A 2 of the CPU core 2. In this example, the register storing the address to be accessed becomes the register designated by Ax and Ay. The registers that can be designated in Ax are the registers A0x, Alx containing CPU core 2, and the registers that can be designated in Ay are the registers AOy, A1y in CPU core 2. The data output on the internal buses A1 ~ A2 of the CPU core 2 are stored in the memory address buffers (MABX, MABY). The rise time of the clock signal Clock2 synchronized with the Ex stage is output on the address buses XAB and YAB. On the one hand, the data of the internal buses A1 to A2 of the output of the CPU core 2 are implemented by ALU213 and PAU212. (At this time, ALU213 and FAU212 implement 0 addition operation. "The operation result is output to the internal buses C1 and C2 of CPU core 2. The operation result output to the internal buses C1 and C2 of CPU core 2 is synchronized to the clock of the EX phase. The rising period of the signal Clock 2 is stored in the pointer register (that is, the registers P designated by Αχ and Ay are stored in the X and Y memory. During the rise of the clock signal Clock 1 in the MA phase to the rise of the clock signal Clock2, the EX phase clock is implemented. The rise time of the signal Clock 2 is output on the address bus XAB, YAB address decoding, and data access is implemented during the rise of the clock signal Clock2 in the stage M A to the rise of the clock signal Clock 1 in the next stage. Therefore * from the MA stage The rise of the clock signal Clock2 will output the data to the data bus XDB 'This paper size applies to the Chinese national standard (CNS> A4 specification (210X297 mm go _ n I ~' installed ~ 1 I... Order (please read the note on the back first) Refill this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs __B7__ V. Description of the Invention (48) YDB. The data of the output data bus XDB and YDB are clock signals synchronized to the WB / DSP stage. The rise time of Clockl is taken into the DSP engine 3 and the data is supplied to the internal buses D1 and D2 of the DSP engine 3. The rise time of the clock signal Clock2 synchronized to the WB / DSP phase stores the data on the internal buses D1 and D2 of the DSP engine 3. Complete the action in the destination register (Distinction Reg). In this example, the destination register is the register specified in DX and DY. The register that can be specified in DX is the register XO, X1 contained in the DSP engine 3, and can be specified in the register of Dy YO, Y1 in DSP Engine 3 are parallel to the above data transfer, and also perform DSP operations at the same time. Synchronize the rise time of Clockl Clockl in the WB / DSP phase, access the register storing the source data, and output the value of the register to the DSP. Engine 3's internal buses A1, A2, B1, B2 »In this example, the register that stores the source data is an ADD (addition) operation structure as the register designated by SX and Sy, and MUL (multiplication) operation becomes Se and S f Specified registers. Registers that can be specified in Sx, Sy, Se, and Sf are arbitrary registers inside the DSP engine 3. The data of the internal bus A1 and B1 of the DSP engine 3 are output. The multiplication operation is implemented in MAC304. The result is output to the internal bus C 2 of the DSP engine 3. The operation results of the internal buses C 1 and C 2 of the DSP engine 3 are synchronized to the rise time of the clock signal Clock 2 of the WB / DSP phase. , Stored in the destination register. In this example, the destination register 'is D η when ADD is operated, and MU L is the paper standard designated by D g as the general Chinese National Standard (CNS) M specification (2ί〇 × 297 公 η _ JH.-- "-—ί--! n. --- -11--I n --- n I-X 1 ^ 1 ^ 1 * _ i— (Please read the notes on the back before filling this page) Ministry of Economic Affairs A7 ________B7_ printed by the Central Bureau of quasi-government cooperation V. Invention Description (49) Register. The registers that can be specified in D η and D g are arbitrary registers inside DSP Engine 3. As above, the implementation is stored in DSP Addition and multiplication of the data in the registers in the engine 3 are implemented from X — R0M4 or X — RAM6 and γ — ROM5 or Y-RAM7 to the data transfer instruction of the DSP engine 3 with IF, ID, EX, MA, WB / The pipeline phase of the 5th stage of the DSP is completed.

Instl · PADD AO, MO, AO P M U L A 1 * X 〇 · A 1 MOVX. W @ R4-X1 -MOVY.W @ R6, Y0 I ns t 2: ADD R 8 1 R 9

Inst 3: ADD R 1 0 > R 1 1 I n s 14: ADD, R 1 2 'R 1 3 The 4 consecutive instructions are the second example of the D S P operation instruction * The operation will be described using FIG. 16. The 4 instructions are examples of using the address buses I AB, XAB, and YAB at the same time to achieve different actions in the same clock cycle. "The instructions of inst; l to Inst4 are the same as those in Fig. 7 and Fig. 15, so their parts are omitted." Detailed description. First • Instl's I F stage, implement Instl's instruction fetch. Since Inst2 is the I F phase during the 2 D phase of Instl, the instruction fetch is executed. When address calculation for access to X, Y memory is implemented in the EX stage of Instl * 圚 Inst 2 is the IR stage, so instruction decoding is implemented, and because this paper size applies the Chinese National Standard (CNS) A4 specification (2Ϊ0 × 297 mm) ) _ _ ~ --------- ^ ------- ^ ------ ir ------ I (Please read the notes on the back before filling this page) Economy Printed by the Consumer Standards Cooperative of the Ministry of Standards of the People's Republic of China 4. . 2 6 A7 _____B7_ V. Description of the invention (50) Inst3 is an I F stage, so the instruction is fetched. In the MA phase of Instl | The addresses calculated in the EX phase are output on the address bus XAB, and YAB (the actual output address time is from the rise time of the clock signal Clock2 in the EX phase) is taken in from the data bus XD B and YD B data. At this time, inst2 is the E and X stages, and the ADD operation tables of R8 and R9 are implemented. Inst3 is the I and D stage to implement instruction decoding. Inst4 outputs the address of Inst4 to the address bus for the I F phase. The actual output time to the address bus I AB is from the rise time of the clock signal Clock 2 before the half cycle of the I F phase of Ins t4. This time is the same as the time when the address is output to the address bus XAB and YAB in Instl (after the half of the EX phase and the first half of the MA phase). * That is, the address bus XAB and YAB are used for data transfer. In the address bus I AB Used for instruction fetch. The microcomputer 1 has internal address buses I A B, XAB, YAB and internal data buses IDB, XDB, YDB connected to the CPU core 2. Therefore, these three internal buses can be used to implement different storage, storage and fetch operations at the same clock cycle. After that, Instl implemented DSP operations in the WB / DSP phase to complete the operation. Inst2 has completed the operation. Inst3 is the EX phase to perform the ADD operation of R 1 0 and R 1 1 to complete the operation. Inst4 implements the instruction decoding for the ID phase. Only the EX phase of Inst4 is implemented in the cycle, and the ADD operation completion of R 1 2 and R 13 is performed. According to this embodiment, the following effects are obtained. The built-in memory is considered (please read the notes on the back before filling in this I). The paper size of the binding and binding is applicable to China National Standard (CNS) A4 (210X 297 mm) -53-Μ Β7 Central standard rate of the Ministry of Economic Affairs Printing by the Office of the Consumer Cooperative Cooperative V. Description of the invention (51) 1 | Product and operation of DSP engine 3 9 2 Face Y memory 5 > 7 and 2 1 I Face X memory 4 t 6% C Ρ U heart 2 with internal bus XAB) 1 1 XDB and internal bus YA Β 9 YDB can be accessed in parallel with Y memory 1 1 Please 1 i memory 5 7 and X memory 4 6 9 So 1 can be white built-in memory 4 first} 1 At the same time, 2 data were transferred to the DSP engine 3 a. 1 because of the internal bus back 1 XAB > XD Β and internal bus YAB > YDB will be connected to the internal bus IAB of external service 1 »ID Β Pre-individualization> Therefore, CPU core 2 flat item and then 1 I line X memory 4 9 6 and Υ memory 5 > 7 can also be accessed externally. Book 1 is installed for memory access α. As mentioned above, there are 3 kinds of address pages connected to the CPU core 2 1 1 Bus IA Β • XAB » Υ AB and data assembly IDBXDB 1 1 »YDB Therefore, this kind of internal bus can be used to implement 1 I different memory access operations with the same clock cycle. Therefore, it is also easy to deal with the situation where the program or data exists in the external I memory. High-speed operation can be realized. 0 1 1 I The above-mentioned X memory 4 6 and Y memory 1 1 I are composed of RA Μ and R 0 Μ. The usability of microcomputer 1 1 is as above. Memory 2 is X memory 4 6 β 1 and Y memory 5, 7 each memory has R 0 Μ and RA Μ 1 1 »Make RA Μ as data memory 9 R 0 Μ as program memory, so Points 1 | off data storage and process Type memory transfers 2 data in parallel to DS 4 (1 Ρ engine 3 1 and can be executed in parallel pipeline to effectively execute the instruction fetch 9 digits) I data transfer > and operation 1 1 1 because the CPU core 2 has modulo to stop output Department 2 0 0 »Speed up the product of 1 1 C 〇PU heart 2 and the address for repeated calculations such as lotus calculation 1 1 1 1 This paper size applies Chinese national standard (€ ~ 5) 8 4 specifications ( 210 乂 297 mm) —54- Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs d ^ 23 2 6 Α7 Β7_ V. Description of the Invention (52) For example, the CPU instruction assigns the upper 4 digits of the instruction code to 0 0 0 0 '~ 1 1 〇'e DSP instruction is to assign the highest 4 digits of the instruction code to the range of * 1 1 1. The top 6 digits of the instruction code are allocated in the 1 1 1 〇〇 # and 1 1 1 1 0 1 'range. The DSP instructions are also 16-bit long instruction codes. The upper 6 bits are * 1 1 1 1 10 # instructions, which are 32-bit long instruction codes. In the uppermost 6 digits of the instruction code, the range of 1 1 1 1 I " " is not assigned. The range is used as the unused jaw field. As mentioned above, because the According to the above rule, if a part of each instruction code is decoded, for example, the uppermost 6 bits, the decoder with a small logic scale can determine that the instruction width is a CPU instruction 16-bit long DSP instruction, or 32-bit long. DSP instructions without having to decode all 32 bits all at once. As shown in Figure 17, after the instruction fetch time, the unprocessed instruction code data is set in the instruction register 25. At this time, the instruction to be implemented is not a 16-bit CPU instruction, a 16-bit DSP instruction, or a 32-bit DSP. Any one of the instructions must supply the upper 16 bits to the first decoding circuit 2 4 0. Referring to FIG. 17 and the like, it is shown that the code data of the A field of the 32-bit DSP instruction is set in the instruction register 2 5 upper field UIR »Also, the 16-bit DSP instruction having the same format as the A field is also Set to the upper field ϋ IR. Therefore, in any case, the c PU core 2 'can also perform the required address calculation and data fetching. The necessary data bus is applicable to the paper standard of China National Standard (CNS) A4 (2 丨 0.〆297 mm) 55- — _.------------ ^ ------ 1T ------ Wonderful, I (Please read the notes on the back before filling this page) B7 Central Standards of the Ministry of Economic Affairs Office staff consumer cooperatives printed five 'invention descriptions (53). In other words, the decoding circuits 240 and 241 required for fetching data for implementing 32-bit DSP instructions and fetching data for implementing 16-bit DSP instructions are shared. This is also beneficial to the logic scale of microcomputer 1. Reduce the logical scale of the microcomputer 1. The invention of the present inventors has been specifically described above according to the embodiments, but the present invention is not limited thereto, and various changes can be made as long as the scope of the invention is not exceeded. For example, the identification of CPU instructions, 16-bit DSP instructions, and 32-bit DSP instructions is not limited to the use of the upper 6 bits of the instruction, which can be increased or decreased with the number of instruction codes. In addition, the function of shifting 16 bits below the instruction register to the upper position can be replaced with another function. In addition, the number of registers or types of arithmetic units included in the CPU core or DSP engine are not limited to the above-mentioned embodiments, but may be appropriately changed. The number of memories is not limited to two and can be increased. • The number of memories can be combined to increase the number of address buses and data buses connected to the memory. For example, a Z memory is newly set in addition to the X and Y memories. The address bus ZAB is connected between the CPU and the Z memory, and the data bus ZDB is connected between the DSP engine and the Z memory. According to this structure, not only the data from the X and Y memories are taken into the DSP engine during the product sum operation, but the data completed by the pre-instruction operation currently being implemented can be simultaneously written into the Z storage circuit via the Z bus. Each instruction is fetched into the operation data writing memory, so it can improve the problem solving ability of the microcomputer as a whole. The present invention is most suitable for the use of a microcomputer for controlling the compression and elongation processing or filtering processing of information of a mobile communication device, the servo control, the image processing of a printer, and the like. [Effects of Invention] This paper uses the Chinese National Standard (CNS) A4 specification (210X297 mm) _ 56 — (Please read the note on the back before filling this page). A7 _______ B7 printed by the agency V. Invention description (54) The representative effects of the inventions disclosed in this application are briefly described as follows * That is, the built-in memory takes into consideration the product and operation of the digital signal processor, The first memory and the second memory can be accessed in parallel by the third bus and the second line, so the central processing unit can transfer the two data from the built-in memory to the digital signal processing unit at the same time. And the second bus, and the central processing unit that is externally connected to the external 丨 bus, can independently access the second memory and the first memory for external storage access. As mentioned above, because there are separate connections to the central processing unit The first to third types of address buses and data buses, and the three internal buses can be used to implement different memory access operations at the same clock cycle, so even programs or data exist in external memory It is easy to cope with and achieve high-speed operation processing. Furthermore, since the built-in memory is two-sided, the first and second memories each have ROM and RAM. Since RAM is used as data storage, ROM is used as program memory. Separate data memory and program memory, can transfer 2 data in parallel to the digital signal processing unit, and can effectively implement instruction fetch, data transfer and operation by parallel pipeline processing. Therefore, when the digital signal processing unit is installed in one LSI together with the central processing unit, the digital signal processing can be speeded up a. It is identifiable because it decodes a part of the instruction code by mixing CPU instructions with DSP instructions This instruction is a DSP instruction or a 16-bit long paper size standard that is applicable to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) ------------------ t .--- --- IT ------ I (Please read the note on the back before filling in this f) -Ο ί-4 3 23 2 3 A7 _B7 V. DSP instruction of the description of the invention (55), or 3 2 Bit length DSP instructions are used to assign instruction codes, that is, a decoder of a small logical scale can determine the type of instructions without having to decode all 3 or 2 bits all the time. Therefore, the digital signal processing unit is installed together with the central processing unit. When an LSI is used, the physical scale of the LSI can be suppressed as much as possible. Due to the instruction format of the DSP instruction, the first code area (bit 9 to bit 0 of the 16-bit DSP instruction shown in Figure 18) shown in Figure 18 is used to transfer data between digital signal processing units to the central processing unit. The first format instruction and the second code area having the same format as the aforementioned first code area (Fig. 20, Fig. 21, A 2-pack of the 32-bit DSP instruction A group) will be used in this second code The calculation processing of the transfer data specified in the field. The third code field specified for the digital signal processing unit. Figure 20 'Figure 21 illustrates the 32-bit DSP instruction in the R block of the second format instruction, and implements the second and second format instructions. As the device, a decoding device having common decoding logic for the first code area and the second code area can be used. This can also reduce the logic scale of the microcomputer. Brief description of the figure: Figure 1: All block diagrams of a microcomputer related to an embodiment of the present invention. Figure 2: Example address diagram of a microcomputer. Figure 3: Block diagram showing the CPU core of the modular address output section in detail. i: An example block diagram of a DSP engine. This paper is applicable to the standard ^ " ^ Standard (CNS) A4 (210X 297 mm) _ '—---------- • installed ------ 1T ------ ^ ( Please read the precautions on the back before writing this page) Ministry of Economic Affairs_Central Standards Bureau®: Industrial and Consumer Cooperative Cooperatives Printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperation Du printed 43232ο Α7 __Β7 _, _ V. Description of the invention ( 56) Figure 5: An example of the instruction format and instruction code of a microcomputer. Figure 6: A block diagram showing the connection structure between the decoder of the CPU core and the decoder of the DSP engine. Figure 7: ALU inside the CPU core Figure 8: Implementation time chart of the instruction to read data from the memory into the CPU core Figure 9: Implementation time chart of the instruction to write data into the memory from the CPU core Figure 10: When the DSP instruction is implemented An example time chart. Figure 1 1: Implementation time chart for reading data from the X, Y memory into the DSP engine. Figure 1 2: Implementation time chart for writing data from the DSP engine into the X, Y memory. &Quot; Figure 13: Implementation time chart of instructions for reading data from DSP engine into memory Figure 14: Writing data from DSP engine into memory Instruction implementation time chart. Fig. 15: An example implementation time chart of a DSP operation instruction. Fig. 16: An example time chart when a DSP operation instruction is continuously implemented. Fig. 17: A block diagram showing another embodiment corresponding to 圚 6. 》 Figure 18: The 16-digit DS P instruction code indicating the transfer of data between the built-in memory of the microcomputer and the built-in registers of the DSP engine 3 is the standard of the Chinese paper standard (CNS) A4 (210X297 mm). _ ------------ ^ ------ tr ------. ^ (Please read the notes on the back before filling in this page) A7 B7 Bureau of Standards, Ministry of Economic Affairs Du-work and consumer cooperation Du printed 5. Inventory (57) Instruction format diagram. Figure 19: Instruction format of 16-bit DSP instruction code that specifies the data transfer between the external memory of the microcomputer and the built-in registers of the DSP engine 3. Figure * nan bBf 2 0: The instruction format of the A-group of the 32-bit DSP instruction when it is focused on the code of the information group and its corresponding mnemonic, etc. Figure 2 1: The 3-digit D is focused on the D The format of the instruction of the B group of the SP instruction and the corresponding instruction format of the mnemonic, etc. »C Symbol Description] 1« a ..... * Microcomputer 2 • 1 «...... CPU Core (Central Processing Unit) 2 0 ...... «4 · CPU control signal 2 4 ...... · * Decoder 2 4 0 ... * * ·… the first decoding circuit 2 4 1… ι · ι… 2nd decoding circuit 2 4 2…… code conversion circuit 2 4 3…… CPU decoding circuit 2 4… DSP decoding circuit 2 4 5… ψ ψ ψ… code conversion control signal 2 4 7…… … CPU control signal 2 5 ......… Instruction register 2 5 0, 2 5 1 ......... Instruction fetch buffer 2 0 0…… modulo address output section ---- ----------- ^ ------ 1T ------! (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS > A4 Specifications (2ΪΟ × 297mm) —60 ％ _ Staff Consumption of Central Bureau of Standards, Ministry of Economic Affairs Du printed 432326 A7 B7 V. Description of the invention (58) 2 0 6-2 0 7 ......... memory address buffer 2 12 ......... address arithmetic unit 2 1 3 ......... Arithmetic and Logic Operator 2 14 ......... Modulus Start Address Register 2 15 ......... Modulus End Address Register 2 16- 2 2 6 .......: * Modulo Address Register 3 ......... DSP Engine (Digital Signal Processing Unit) 3 4 ......... Decoder 3 0 2 ......... arithmetic logic operator 3 0 4 ......... multiplier 3 0 9, 3 1 0, 3 1 1 ......... Storage data buffer 4 ......... X — R Ο Μ (second memory) 5 ......... Υ — R Ο Μ (first memory) 6 ..... .... X — R AM (second memory) 7 ......... Y — RA Μ (first memory) 12 ......... External memory interface. —.—; ------ install ------ order ------ uniform '-(Please read the precautions on the back before filling this page) This paper size applies to Chinese National Standards (CNS) Α4 Specifications (210X297 mm) _ 61-

Claims (1)

: ΐ ❸-Dagger-π, Patent Application No. 85114414, Chinese Patent Application Amendment, Republic of China, August 1989 Amendment 1 · A microcomputer, that is, the central processing unit, and access control by the aforementioned middle processing unit The memory, the data bus that transfers data between the aforementioned memory and the central processing unit, and the digital signal processing unit that synchronizes the actions of the central processing unit with the preamble, are included in a 1-chip microcomputer. The data bus fetches 16-bit fixed-length CPU instructions for the central processing unit, and 16-bit or 32-bit DS P instructions for the digital signal processing unit, and one of the instructions fetched according to the aforementioned instruction register Part of the complex digits • Identify the CPU instruction and DS P instruction, and with the recognition result, form the decoder of the aforementioned digital signal processing unit using the DS P control signal and the central processing unit ’s CPU control signal decoder = 2. The microcomputer as described in item 1 of the scope of patent application *, wherein the aforementioned decoder includes an instruction register The upper 16-bit decoding forms the first decoding circuit of the aforementioned CPU decoding signal and DS P decoding signal, and when the D SO instruction of the first decoding circuit 3 is 2 bits long, the lower bit of the instruction register is output 1 6 Bit-coded signals, and when other instructions are identified, a code conversion circuit that outputs an invalid code is output, and the aforementioned DSP decoded signal and the output of the code conversion circuit are used as d SP control signals. 3. A kind of microcomputer, which includes a central processing unit and a digital signal processing unit synchronized with the actions of the aforementioned central processing unit, and is connected to the aforementioned central location. The paper size applies to the national standard (CNSU. 丨 specifications (21ϋ X 297) · 坌) ------------ Order at ----------------, line-(Please read the precautions on the back before filling this page) Employees of the Ministry of Economic Affairs-Ministry of Intellectual Property, Consumer Cooperative Print [] h π, patent application scope ---- The internal bus of the Ministry of Economic Affairs-Ministry of Intellectual Property Bureau employee yellow cooperative printed circuit unit and the aforementioned digital signal processing unit to semiconductors An integrated circuit-based microcomputer, in which the aforementioned central processing unit is provided with a first format instruction in a first code area for implementing digital transfer between digital signal processing units for the central processing unit, and having the same code as the first code The field is the same as the second code field of the same format, and the digital signal processing unit is provided with an implementation control device for the second format command of the third code field that specifies the calculation processing of the transferred number specified in the second code field. 4. The microcomputer according to item 3 of the scope of patent application, wherein the first format order and the second format instruction have a fourth field indicating that they are in the first format or the second format. 5. The microcomputer according to item 4 of the scope of patent application, wherein the aforementioned implementation control device includes an instruction register > which is commonly used for the foregoing first format instruction and second format instruction, and an instruction which contains the instruction register fetched from the foregoing instruction register. The decoding device for decoding the first code area and the fourth code area, or the second code area and the fourth code area, and an implementation device for performing an address calculation based on the decoding result and implementing the aforementioned data transfer control are β 6 The microcomputer according to item 5 of the scope of patent application, wherein the instruction register has a common area for holding the first code area and the fourth code area or the second code area and the upper area of the fourth code area, and is used in The lower field of the third code field is maintained, and the decoding device is based on the decoding result of the fourth field, and the output indicates the aforementioned instruction ------------ machine -------- --Order --------- line (please read the notes on the back before filling in this page) ^ 3 23 2 6 S i) h π, the patent application range register holds the control signal of the second format instruction, According to its control signal, The lower-level field is made up of a device that supplies code data in the third code field to the aforementioned digital signal processing unit. "7-A data processing device on a semiconductor substrate includes a central processing unit, and a memory accessed by the central processing unit, and is connected to The data bus of the foregoing memory and the central processing unit, and the digital signal processing unit whose operations are controlled by the central processing unit; wherein the central processing unit includes a connection with the aforementioned data switchboard, and the instructions provided by the data switchboard are used to take out the memory supply instructions. An instruction register and a decoder connected to the foregoing instruction register; wherein the foregoing instruction includes the first instruction of the first bit length used by the central processing unit, and the digital signal processing unit used by the foregoing data exchange unit to be combined The second instruction which is longer than the first bit or the second instruction which is longer than the first instruction; wherein the aforementioned decoder decodes a plurality of bits of a part of the instruction fetched by the aforementioned instruction register, and identifies the The instruction fetched by the instruction register is the first instruction, or the second instruction or neither. Printed by the Consumer Affairs Cooperative of the Ministry of Economic Affairs and Industry Bureau (please read the precautions on the back before filling out this page) 8 _If the data processing device of the scope of patent application item 7, the aforementioned decoder fetches the aforementioned instruction register When the command is identified as the first command, a first control signal r for controlling the central processing unit is generated. The decoder recognizes the command fetched from the command register as the second command and the second control signal of the digital signal processing unit. 9 If the data processing device according to item 8 of the scope of patent application, wherein the aforementioned instruction register includes the first long upper area and the first long lower area, the paper is also applicable to the Chinese National Standard (CNTS) A1 specification (J10 X 297 public hope) a 3-4 3 2 3 2 6 i) h 7T, please apply for the patent range to become the second bit length; where the aforementioned decoder includes the instruction code to fetch the upper bit area of the aforementioned instruction register to decode And generating a decoding circuit for the first control signal and a decoding signal, and a code conversion circuit, wherein the code conversion circuit recognizes the instruction fetched by the instruction register as the second long bit in the decoder. When it is 2 instructions, it outputs a signal that instructs the instruction code fetched from the lower area of the aforementioned instruction register, and when the decoder recognizes it as an instruction other than the second instruction with the second bit length, it outputs a code that means 1 to output an invalid code. ; Wherein the decoding signal and the output of the conversion circuit become a second control signal. (Please read the note on the back before filling in this page) I -------- Order ---------- Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs + 1 country standard (CNSW specifications (210 x 297)