TW424192B - Microcomputer - Google Patents

Abstract

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Therefore, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

Description

A7 B7 424192 V. Description of the Invention (1) [Technical Field of the Invention] The present invention is related to the logic LS 1 of semiconductor integrated circuit with a central processing unit and a digital signal processing unit, that is, it is applicable to the current speed. Microcomputer processing technology is effective. [Previous technology] For example, it is described in a microcomputer in which a multiplier and an arithmetic: logic operation device are installed on the same substrate. There are Japanese Patent Application No. 4-2 9 6 7 7 8 or US Patent Application No. 1 4 5 1 5 7 number. According to the above patents, for example, the logic LS I chip of the microcomputer has a central processing unit's bus, memory, and multiplier, and especially when reading data from the memory, the readout from the central processing unit will multiply the data. The command instruction is transferred to the signal line of the multiplier. As a result, since the central processing unit reads the data from the memory, the central processing unit transfers the instruction about the multiplication command of the read data to the multiplier, so the data can be directly transferred between the memory and the multiplier. [Problems to be Solved by the Invention] The present inventors have discussed the problem of speeding up digital signal processing by installing a digital signal processor and a central processing unit on a dual LSI. At that time, although the previous technology mentioned above can be self-reserved. The data can be directly transferred to the multiplier to achieve high-speed multiplication. However, the central processing unit was not considered when the pipeline processing was planned by the central processing unit. A situation where the instruction fetch cycle and the storage access cycle used for multiplying processing should coincide should be implemented. Also, the paper size of the complex operand table for adding or multiplying by reading from memory in parallel is not considered. The paper size of China National Standard (CNS) A4 (210X297 mm ----------- L II) is applicable. P! (Please read the notes on the back before filling out this page) Order printed by the Central Laboratories of the Ministry of Economic Affairs and printed by the Shellfish Consumer Cooperatives 4242121 * A7 _____B7 V. Description of the invention (2) The problem of speeding up the processing of the operation. See more At this time, if the access relationship between the central processing unit and the external access is not considered, the microcomputer may be used poorly. Also, when the digital signal processor is assembled in a pair of LS I, it is found that when trying to suppress the instruction decoding circuit, etc. For increasing the logic scale, it is also necessary to consider the allocation of CPU instructions and DSP instructions or the format of the DSP instructions. The object of the present invention is to install the digital signal processing unit and the central processing unit in a dual LSI to speed up digital signal processing. Another object of the present invention is to suppress the increase of the physical scale when the digital signal digital unit and the central processing unit are installed in an LSI together. The foregoing and other objects and new features of the present invention are described by The description of the manual and the accompanying drawings should be understandable. [Methods to Solve the Problem] The following is a brief summary of the representative inventions disclosed in the following: 0 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (Please read the note on the back first) Please fill in this page again for details.) That is, the microcomputer will be: the central processing unit (2), and the first to third address buses (IAB, YAB, XAB) selected from the aforementioned central processing unit and connected to the aforementioned first address Line (IAB) and second address bus YAB, the first memory (5, 7) accessed by the address of the central processing unit, and connected to the aforementioned first address bus (I AB) and third address bus (XAB), The second memory (4, 6) accessed by the address of the central processing unit and the paper size are applicable to the Chinese National Standard (CNS) A4 specification (2I0X 297 mm) 424192, B7 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs V. Description of the invention (3) 1 1 The first data bus (ID Β) connected to the first and second memories and the aforementioned γ | π central processing unit to transmit and transfer data and 1 Connected to the second data bus (1 1 YDB) of the first memory transfer data, and please read i 1 Connected to the third data bus (remember 1 1 IYDB) of the second memory transfer data, and note 1 1 External connection to the aforementioned first address bus and first data bus □ Item 1 I and 1 circuit (12), and fill in 1 Connect to the aforementioned first to third data buses Same as the CPU page | Group Action Digital Signal Processing Unit (3) and 1 [From the central processing unit, the DSP control signal (2 0) that controls the operation of the aforementioned digital signal processing unit 1 1 1 is transmitted to the control of the digital signal processing unit 1 Customized signal It will be converted into a semiconductor integrated circuit on 1 substrate. 0 1 1 According to the above method, the built-in φ device is considered a digital signal processor (3 1 1 The sum of product 2 operations on the first memory (5 i 7) and the second memory 1 | • (4, 6) 9 by the third bus (XAB 5 XD Β) and the second bus line: (YAB, Ύ DB ) Can be accessed in parallel respectively. Therefore, the CPU core 2 1 1 [can store 2 data at the same time to the digital signal processing unit 1 1 signal 0 and 3rd bus (XABXDB) and 2nd bus (1 1 YAB, YDB) and the first bus (IAB 3 1 1 IDB) connected externally to α — so the central processing unit is parallel to the second storage 1 1 (4, 6) and the first storage (5 ΐ 7 ) Access can also be accessed by external memory 1 I memory. As mentioned above, there are 1 1 | three kinds of address buses (IAB > XABYAB) 1 1 connected to the central processing unit (2). 1 1 1 This paper is applicable to the national standard (CNS) A4 specification (21 OX 297 mm) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4241 92, yo A7 _B7__ V. Description of the invention (4) and data bus (I DB, XDB, YDB), so the three internal buses can be the same The time period implements different memory access operations. Therefore, it is easy to cope with the situation that the program or data exists in the external memory and speed up the arithmetic processing. In order to improve the usability of the microcomputer, the first memory and the second memory may be constituted by R AM and R 0.M, respectively. In order to speed up the address form for the repeated calculations of the product and operation of the central processing unit, it is preferable that the central processing unit be provided with an modulo address output unit (20Q). At this time, it is preferable that the address generated by the analogue land output unit is output on the second or third address bus optionally. The aforementioned digital signal processor includes first to third data buffer devices (MDB I, MDBY, MDBX) with individual interfaces to the first to third data buses (IDB, YDB, XDB) and can be connected to each data via an internal bus A complex register device (3 05 ~ 308) of the buffer device, a multiplier (304) and an arithmetic logic operator (302) connected to the internal bus, and decoding the DSP control signal to control the data buffer The device, the multiplier logic operator, and the decoder (34) registering the operation of the device. Focusing on the so-called instruction code microcomputer, that is, the central processing unit (2), and the memory (4-7) controlled by the aforementioned central processing unit, and transferring data between the aforementioned memory and the central processing unit to synchronize with the central processing unit The operating digital signal processing unit (3) will be integrated into a semiconductor integrated circuit on one substrate. The instruction system that can be used by the microcomputer includes the CPU instructions to be implemented by the central processing unit (2) and the paper size of the central office using the Chinese National Standard (CNS) A4 specification (210X297 public celebration) — .1— HIIIP (Please read the precautions on the back before filling this page) Order printed by the Consumers Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 2 4 19 2 ~-at ____B7_ V. Description of the invention (5) Address calculation used by the management unit to take data Wait for a part of the processing, the OSP instruction that the digital signal processing unit (3) should implement. The aforementioned central processing unit is an instruction recorder (2 5) containing a 16-bit fixed-length CPU instruction for the central processing unit taken out via the aforementioned data bus and a 16-bit or 32-bit DSP instruction for the digital signal processing unit. According to the plural digits of a part of the instruction fetched by the foregoing instruction recorder, the CPU instruction and the DSP instruction are identified, and the DS P control signal (2 0) and central processing for the operation control of the digital signal processing unit are formed with the identification result. The unit's operation is controlled by the decoder (2 4) of the CPU control signal. For example, the C P U instruction allocates the upper 4 digits of the instruction code in the range of 0 0 0 0 " ~ 1 1 0 ". The DSP instruction allocates the top 4 digits of the instruction code in the range of "1 1 1 1 '. In addition, the uppermost 6 digits of the instruction code are allocated in the range of 1111 100 〃 and "1 1 1 1 0 1", and the DSP instruction is also a 16-bit long instruction code. The first 6 digits of the instruction code are '1 1 1 1 1', which is a 32-bit long instruction code. The uppermost 6 digits of the instruction code are in the range of 1 1 1 1 and the instruction is not allocated. The range is regarded as the unused area. As mentioned above, since the code allocation for the maximum 32 digits of instruction is set as the above rule, Decoding a part of each instruction code, such as the uppermost 6 bits, can determine that the instruction width is a CPU instruction ^ 1 6-bit DSP instruction, or a 32-bit DSP instruction. Without having to decode all 32 bits all at once. This paper size applies to Chinese National Standard (CNS) A4 specification (2 丨 0X297mm) I — 1 — — lf (Please read the notes on the back before filling this page)-, Tr 42 4 1 9 2: ^ A7 B7 5. Description of the invention (6) The aforementioned decoder includes: a first decoding circuit that decodes the upper 6 bits of the recorder to form the aforementioned CPU decoding signal (2 4 3) and DSP decoding signal (244). (240), and when the first decoding circuit recognizes a 32-bit long DSP instruction, it outputs a signal that encodes the lower 16 bits of the instruction recorder. When identifying other commands, the output means a code replacement circuit (2 4 2) that outputs an invalid code, and the output of the aforementioned DSP decoding signal and code conversion circuit is used as the DSP control signal (2 0). Focusing on the instruction format of the DSP instruction, the microcomputer includes a central processing unit (2), a digital signal processing unit (3) synchronized with the operation of the aforementioned central processing unit, and an internal bus that commonly connects the aforementioned central processing unit and the aforementioned digital signal processing unit (IDB), a microcomputer that is integrated into a semiconductor integrated circuit, printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). The aforementioned central processing unit is equipped with The central processing unit specifies the first format instruction of the first code field of the digital transfer between the digital signal processing units (9 to 0 bits of the 16-bit DSP instructions shown in FIG. 18), and has the same first code as the aforementioned first code. Field The second code field of the same format (the field A of the 32-bit DSP instruction illustrated in Figure 20 and Figure 21) and the digital signal processing unit specifies the third code field that uses the arithmetic processing of sending numbers specified in the second code field. (Fig. 20, Fig. 21 exemplifies the B area of a 32-bit DSP instruction) The second format instruction is implemented by a control device. Therefore, the implementation of the control device, when implementing the instructions of the first and second format, can adopt the common translation paper size applicable to the Chinese national standard (CNS > A4 specification (210X297 mm) for the first code area and the second code area. ) ^ 24192 A7 B7 Printed by the Consumers 'Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs V. Invention Description (7) -1 | The decoding device of code logic is beneficial to the reduction of the logic scale of microcomputers 0 1' | The second format instruction has the 4th field for the 1 1 I 1 format or the second format (for example, 16-bit DSP instructions 1. 15-bit 10-bit 3 2-bit DSP instructions 3 2-bit 2 (6 digits) Please read 1 1 Read 1 0 Read I back 1 The aforementioned implementation control device contains a command register (2 5) and a note 1 I that are commonly used to describe the first format instruction and the second format instruction Contained in the aforementioned instructions The first code collar of the instruction fetched from the register is f I field and 4th code field or 2nd code field and 4th code field. Page 1 | Decoding Device (2 4 0) J and I] I Decoding the mouth of the fruit address, the implementation of the implementation of the described data transfer control 1 1 implementation of the device 0 1 Order the aforementioned instruction register has the first code area [1 and 4 code area or the second code area and the second code area 4 Upper field of the code field 1 1 Field (UIR) and used to hold-· > f- Describe the lower field of the 3rd code field 1 | (LIR) and the aforementioned decoding device is based on the decoding of the fourth field Result output display> The description instruction register holds the control of the second format instruction 1 1 I signal (2 4 8) according to its control signal 5 white forward lower field forward 1 1 1 mentioned digital 1W processing unit Device 1 1 2 4 2 ， 2 4 2 A 2 4 2 B 0 1 1 1 C Example 1 1 [Figure 1 shows the microcomputer 1 related to the embodiment of the present invention— * Box 1 1 Figure 0 The microcomputer in the same figure is formed by semiconductor integrated circuit manufacturing technology 1 1 This paper size is applicable to China National Standards (CNS) A4 specifications (2 丨 OX 297 mm) _-Staff Consumption of the Central Bureau of Standards, Ministry of Economic Affairs Cooperative printed 4 2 4 19 2: ^ J A7 B7 V. Description of the invention (8) A semiconductor substrate such as single crystal silicon. Microcomputer 1 is composed of CPU Core 2 of central processing unit, DSP Engine 3 of digital signal processing unit > X-R0M4 — R0M5 — RAM6 »Y — RAM7 'Interrupt Controller 8. Bus controller (Bus state conttrol ler) 9. Built-in peripheral circuits (

Peripheral circuit) 1 0, 1 1_, external storage interface (Externa! Memory Interface) 1 2, clock pulse generator (CPG) 1 3. The aforementioned X-ROM4, γ-rOM5 are read memory dedicated for reading instructions or constant data, etc., or can be electrically rewritten. Also, 1 ^ and 6, ¥ -1 ^ eight] \ / The 17 is used as one of the data to store or use the memory of the CPU core 2 and the DSP engine 3 in the operating field. The aforementioned X-R0M4 and X-RAM6 are collectively referred to as X memory for internal instructions / data (丨 nterna 1 I nstrmgc ΰ t 丨 ο η / 0 &amp; (^ 116116111), and ^ — 1 ^ 〇] ^ 5 and ¥ — Shakuhachi 1 ^ 7 is collectively called Internal Instl ^ ction / Data Y Mem °. The micro-brain 1 of this embodiment has a bus structure including: an internal address combined with the external memory interface 12 Bus I AB and internal data bus X AB which is not combined with internal data 'Data bus I DB, external storage interface 12 and internal data bus X AB which is not integrated with internal data bus XDB, external storage interface 12 and internal data bus YD B, and the peripheral address bus PAB and peripheral data bus PDB for the built-in peripheral circuits 1 0, 11 and the control bus are omitted. The illustrations correspond to the Chinese paper standard (CNS &gt); A4 specification (210 × 297 mm) 11 (Please read the Note # on the back before filling out this page) b. Order. Printed by the Consumer Standards Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 424192 'A7 _____ B7 V. Description of Invention (9) Bus and data bus design The C PU core 2 is connected to the data bus I DB of the chip via the external storage interface 12 and can be distributed to the sub-controller 8 to provide a distribution signal 80. The CPU core 2 supplies the control signal 20 for controlling the DSP engine 3 to the DSP engine. 3. The CPU core 2 also outputs the address signals to the address bus IAB which can be connected to the outside of the substrate via the external memory interface 12 and the address bus XAB and YAB which are not connected to the external memory interface 12. The CPU core 2 generates clock pulses (CPG) 13 output of the non-heavy # dual-phase clock signal C1 CK1, Clock 2 is the action reference clock signal action. Details on CPU core 2 will be described later, but CPU core 2 in Figure 1 Register register 2 1, arithmetic and logic operation unit (eight 1; 2), address adder (multiples &lt; 3 £ 3-person 1 ^ 11) 2 3 decoder 2 4, instruction register (JR) 2 5. Register file 2 1 is arbitrarily used as an address register or data register, and also contains a program counter and a control register. Decoder 2 4 decodes the instruction fetched by instruction register 25 to form an internal control signal (omitted in Figure 1) Its illustration) and control signal 2 0. Instruction register (IR) 2 5, respectively It is made up of 16 upper-side areas (UI R) and lower-side areas (LIR). Details will be described later, but the lower-side area (LIR) can be moved to the upper-side area (UIR). The control is omitted. The execution order of the instruction when an exception occurs, such as an interrupt, or the diagram of a sequence control circuit that uses hardware to control the avoidance and return of the internal status of the exception. The DSP engine 3 is connected to the aforementioned data buses I DB, XDB, and Y06. The clock signal (: 1001 <1, (: 1001 ^ 2) is the standard for the paper. The Chinese National Standard (CNS) is applied. A4 specification (2 丨 0 X 297 mm) (Please read the precautions on the back before filling in this page)

424 彳 92 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention (10) Act as a reference clock signal. The DSP engine 3 will be described in detail later, but the DSP engine 3 in FIG. 1 shows the representative data register file 3 1, the arithmetic logic operator and shifter (ALU / shifter) 3 2, and the multiplier (MAC) 3 3, and the decoder 3 4. The data register file 31 is used for product and operation. The decoder 34 decodes the control signal 20 provided by the CP + U core 2 to form an internal control signal of the DSP engine 3 (the illustration is omitted in FIG. 1). X — ROM 4 and X — RAM 6 are connected to the address bus IAB, XAB and data bus IDB, and XDB-ROM 5 and Y_RAM7 are connected to the address bus i AB, YAB and data bus IDB, YDB. The built-in memory considers the product and operation of the DSP engine 3. The two sides are integrated into the X memory 4, 6 and Y memory 5, 7, which can be accessed in parallel by the internal buses XAB, XDB, YAB, and YDB, respectively. In addition, the internal buses XAB, XDB and YAB, YDB and the external lines IAB and IDB are individualized, so parallel access to X memory 4, 6 and Y memory 5, 7 can also be stored in external storage. take. X memory 4, 6 and Y memory 5, 7 are used as the memory area for the product and operation data of the DS P engine 3, and the memory area for constant data. In addition, when X — R Α Μ, Y-r a Μ can also be used as the data of CP core 2 to record the jaw area or work area. The aforementioned interrupt controller 8 inputs the interrupt request signals (Interrupts) 8 1 of the built-in peripheral circuits 10, 11 and so on, and accepts the interrupt requests according to the priority order of various interrupt requests or the masking of interrupt requests with intelligence. Accepted interruption request interruption vector (丨 n'terrupt Vector) This paper wave standard is applicable to China National Standard (CNS) A4 specification (2 [0X297 mm) _ --------- ο installation-(please first Read the notes on the back and fill in this page) Order 424 1 92 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (11) 1 8 2 Output to the address bus IAB Output interrupt signal 8 0 to 1 C Ρ U core 2 〇1 The bus status controller 9 is connected to the address bus IA Β 5 Ρ AB 1 1 | and the data bus ID Β y PB DB 9 control and connected to the address bus PB AB Please read the 1 and the data bus first Built-in peripheral circuit 1 0 »1 1 and read back of CPU core 2 | β I ＣControl 0 Note 1 I Meaning | | External storage connection □ 1 2 is connected to the address bus IA Β and data items 1 I and 1 line ID Β is connected to the microcomputer 1 on the outside of the substrate. Bus and data bus J Implementation and external connection □ Control 0 End of page 1 I Figure 2 shows an example of the address mark of microcomputer 1 0 Microcomputer 1 of this example, I 1 Computer 1 manages the address space specified by 32 bits 0 The address bus 1 1 | IAB has a bit width of 3 2 〇 There are exceptions in its address space 1 Order the same with the maxillo-mandibular region »X — R 0 Μ space (allocated at X — R 0 Μ 4 address 1 1 space) 9 X-RA Μ space (allocation X-RA Μ 7 address space) I 1 Τ-R OM space (allocation space of Y-R 0 Μ 5) Y-1 1 RA Μ space (allocated to Υ RA Μ Address of 7 Space) »Built-in cycle r I V. Side circuit allocation space (built-in peripheral circuits 1 0 9 1 1 allocated address space 1 1 I space) etc. α The distribution of the example in Figure 2 is X — R 0 Μ 4 Series 2 4 K 1 1 Β &gt; X — RA Μ 6 Series 4 KB 9 Υ-R OM 5 Series 2 4 Κ B 1 I Υ — RA Μ 7 Series 4 κ Β 0 1 1 Figure 2 9 1 6 In the progression table, Η 0 0 0 0 0 0 0 0 0 0 1 i Η 0 0 0 0 0 3 FF of the space 2 5 6 Β field allocation exception 1 physical vector jaw field 0 at Η 〆 0 0 0 0 0 0 4 0 0 1 1 Η 0 1 FFFFFF Allocable normal space 0 Normal space \ 1 1 This paper size is applicable to China National Standard (CNS) A4 (210X297 mm) _ κ 424 192 ^ A7 B7 Central Bureau of Standards, Ministry of Economic Affairs Printed by the employee consumer cooperative V. Invention Description (12)-1 I Guaranteed as connectable microcomputer 1 External storage area 0 in 1 Η ~ 0 2 0 0 0 0 0 0 Η ^ 0 2 0 0 5 FFF 1 Assign X 1 — R 0 Μ space 0 at 〆 〆 0 2 0 0 6 0 0 0 1 I Η ~ 0 2 0 0 6 FFF, allocate X _ RA Μ space 0 Please read 1 first Η ^ 0 2 0 0 7 0 0 0 Η ^ 0 2 0 0 7 FFF becomes X — read back 1 | R Α Μ-Μ irr or space 1 When you access here, you are actually accessing attention 1 | Η ^ 0 2 0 0 6 0 0 0 Η ^ 0 2 0 0 6 X of FFF — item 1 1 R Α Μ space 0 H 0 2 0 0 8 0 0 0 Refill this ί 1 Η &quot; 0 2 0 0 FFFF becomes X-RA Μ RAM page 1 1 Mi rr ο r space 9 access here 3 actually access 1 1 Η ~ 0 2 0 0 0 0 0 0 Η ^ 0 2 0 0 7 FFFF X-1 IRA Μ ~ R OM space and X-RA Μ space 1 Order I Η &quot; 020 1 0 .0 0 0 Η &gt; 2 0 1 5 FFF allocation Y — 1 1 R 0 M space 0 in Η 2 0 2 0 1 6 0 0 0 1 1 ^ 020 1 6 FFF allocation Υ one R Α M space 0 1 1 Η &quot; 020 1 7 0 0 Η ^ 0 2 0 1 7 FFF system becomes Y — line, RAM — Mirror space &gt; Access here is actually access 1 1 Η ^ 020 1 6 0 0 0 Η ^ 0 2 0 1 6 of FFF Υ — 1 1 IRAM space o Η-0 2 0 1 8 0 0 0 1 [Η ^ 020 1 FFFF becomes Y — R 〇Μ ί RA Μ 1 1 Μ irror space 9 access here 9 actually exists Take 1 1 Η ^ 020 1 0 0 0 0 Η ^ 0 2 0 1 7 FFF-f IR 0 M space and γ-RAM space. Η 0 2 0 2 0 0 0 0 ~ 1 I Η ^ 0 7 FFFFFFF normal space allocation 0 0 1 1 15 This paper size applies the national standard (CjsjS) A4 size (210X297 mm) 424 1 92 A7 B7 5 Explanation of the invention (13) 08000000 ~ 1FFFFFF.FF, which allocates the contract area. The pre-restricted jaw field cannot be accessed when the user substrate (real substrate) is used, and the evaluation substrate (used for emulation, etc.) At that time, it is allocated as the ASE space (control space emulated by the utility) area. At 2 2 0 0 0 0 00 ～ ～ 2 7 FFFFFFF, the general space is allocated. At Η 28 000 000 ～ H / FFFFFOFF, the portion is allocated to the contract area. At H ^ FFFFFFO 0 to H> FFFF'FFFF, the register address of the built-in peripheral circuit is allocated. The built-in peripheral circuit allocation collar is printed. 0 Printed by the Central Consumer Bureau of the Ministry of Economy Staff Consumer Cooperatives. The block diagram of the CPU core 2 of the output section. In Figure 3, the part enclosed by the dotted line is the modulo address output section 2 0. The modulo address output section 2 0 0 will be determined by the modulo address register (such as A0X :) Output buffer (eg M ABX) is output to the address bus (such as XAB), and at the same time, an addition device (such as ALU) is used to add the output from the analog address register (AOX) to implement the address update output action stored in the analog address register (AOX) The blocks are sequentially updated to form data access addresses for repeated operations such as product-sum operations. The circuit block recorded as a random logic circuit (R and 0m Logical C ircui) 2 0 1 includes the decoder 2 of FIG. 1 4 or the above-mentioned sequence control circuit, and the circuit block of the control register or status register, etc. In Figure 3, Cl, C2, DR, A1, B1, A2,

B 2 and 0 W respectively represent the representative buses in the CP core 2. The interface between the CPU core 2 and the data bus i D0 is in the aforementioned instruction register (I 16 (Please read the precautions on the back before filling out this page) This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) 4 2 4 1 9 2 Λ A7 B7 Printed by the Consumers 'Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (14) I 1 R) 2 5 and data buffer (De ta E' U ff € r 2 0.3) implemented. Ί Purpose 1 Let the instruction fetched by the register (IR) 2 5 be supplied to the random logic circuit (1 Ra nd τ τη I '〇gic C it CU it) 2 0 1 of the aforementioned decoder 2 4 etc. QC 1 1 PU core 2 The connection P to the address bus IAB is the program counter (please read 1 i I first) 2 0 4 and the address buffer (Addr es Bu ffer) 2 0 5 implementation 0 back 1 1 CPU core 2 and the address bus XAB The connection P is in the memory address buffer. Note 1 1 (Μ ABX) 2 0 6 Implementation. 5 CPU core 2 and address bus. AB 1 item 1 I then 1 1 / interface is Storage Address Buffer (Μ ABY) 2 0 7 Fill in the address information input address buffer 2 0 5 to implement the total number of white C 1, page ν _ ^-IA 1, A 2 select 3 and address information Input memory address buffer 1 1 2 0 6, 2 0 7 Path white bus C 1 C 2 9 A 1, I 1 1 A 2 Select 0 Arithmetic Operator (AU) 2 0 8 Used for program count 1 Subscriber 2 0 4 値 Increase 0 2 0 9 is a general-purpose register (R eg) 1 1 2 1 0 is an index register (IX) modified by using the address plus a subscript &gt; 1 1 2 1 1 is also used in Index register with index modification (I y) 9 1 I 2 1 2 Adder (PAU) for address arithmetic 2 1 3 Line: I arithmetic logic operator (A B U) 0 1 1 | Control Bit M XY specifies either the address bus XAB or the address bus 1 1 1 YAB — performs modulo operation on the address »logically 値% 1 designates 1 1 Bus A Β S specifies the address by logic 値 0 ft. Bus YA Β 0 Control 1 1 bit D M indicates whether to perform modulo operation. Logical 値 1 indicates that modulo 1 is performed. Number 0 Μ indicates that modulo operation is not performed. 〇 Modular start 1 | Address register (Μ S) 2 1 4 Store modulo operation start address modulo 1 I Address register (Μ E) 2. 1 5 Store modulo operation end address 0 [1! Applicable to this paper size China National Standard (CNS) M specifications (210X297 mm) 17-Printed by the Ministry of Economic Affairs-6-Central Bureau of Standards Shellfish Consumer Cooperative Co., Ltd. This paper is printed in accordance with Chinese National Standards (CNS) Α4 specifications (2! 〇Χ2ί &gt; 7 mm )-? A 1 9 2-^. A7 __B7_. V. Description of the invention (15) Modulo address register (ΑΟχ, Α1χ) 2 1 6 is the electrical address register that stores the current modulo address, 2 1 7 is the comparison mode Number end of address register (ME) 2 1 5 and modulo address register (AO X, Alx) 2 1 6 of the comparator (CMP) 2 1 8 is the output control of comparator 2 1 _7 &quot;) Out of MX, the AND gate of '3 input of DM, 2 1 9 is a selector for selecting bus C 1 and modulo start address register (MS) 2 1 4. The above items are used in Regarding the modulo operation of the address bus XAB. The selector 219 is a logical output of the AND gate 2 1 8 &quot; 1 'output selection register (MS) 2 1 4 and gives the selected selection to the modulo address register (ΑΟχ, Α1χ) 2 1 6). The modulo address register 2 1 6 chooses to use either AO x or A.lx. Modulo address register (AO y, A1 y) 2 2 6 is the current address register that stores the current modulo address: 2 2 7 is the modulo end address register (ME) 2 1 5 and the modulo address register (80 0, 6 1 ¥) The comparator of 216 (〇 "?), The output of 2 2 8 series comparator 2 2 7 and the inverted bit of control bit MXY and the input of 摈 〇M23 AND gate, 2 2 9 is the selector of the bus C 2 and the modulo start address register (MS) 2 1 4. The above pieces are used for the modulo operation of the address bus YA Β. Selector 2 2 9 is the logical 値 'of the AND gate 2 2 8 output selection register (MS) 2 1 4 and gives the selected 値 to the modulo address register (AO y, A1 y) 2 2 6. Modulus The address register 2 2 6 chooses to use either AO y or A1 y. (Please read the notes on the back before filling this page) Order 424 ΐ 9 2-Karma A7 _I_B7 V. Description of the invention (ie) Modular address Register (AO y, A1 y) 2 2 6 is the current address register 2 2 which stores the current modulo address 2 7 is the modulo final address register (ME) 2 1 of the 5 and modulo address register (A 0 y (please read the precautions on the back before filling this page), A ly) 21 6 of the comparator (CMP), 228 is the comparator 2 2 7 Output and control bit MXY's inversion bit and control bit _ 0 The 3 input of M is an AND gate of logical product. 2 2 9 is the selector of the bus C 2 and the modulo start address register (MS) 214. The above pieces are used for the modulo operation of the address bus YAB. The selector 2 2 9 is the logic of the AND gate 2 2 8. The output selection register (MS) 2 1 4 is used to give the selected one to the modulo. Number address register (A0y, Aly) 226. The modulo address register 226 chooses to use either A 0 y or A 1 y. Also, it is described in the random logic circuit 2 0 1 0 0 P Cede means the instruction register 2 5 Supply means the code of 飮, CONST means the constant 意.

I will describe the operation of the modulo operation of the CPU core 2. For example, the modulo address register (AO X) 2 1 6 is used to form the address information for the address bus XAB in the round operation. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, first write the modulo operation start address into the modulo start address register (MS) 2 1 4 and write the modulo operation end address into the modulo end address register (ME) 2 1 5. Write the starting modulo operation address into the modulo address register (AOx). Secondly, because the modulo operation is performed on the address bus XAB, the control bit MXY which decides to perform modulo operation on any of the addresses of XAB and YAB is written into the logic 値 '1 (when performing modulo operation on the address bus YAB Logic is written into the paper. The paper size is applicable to Chinese National Standard (CNS) A4 (210X297 mm) _ IQ-Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 2419 'A7 __B7___ V. Description of the invention (17) Control M XY). Finally, the logic 値 1 'is written into the control bit DM which determines whether the modulo operation is performed. The modulo operation instructions are, for example, MOVS, W @ Ax, Dx. In the instruction description, Δχ is an analog address register (AO X) 2 1 6 or an analog address register (A1 X) 2 1 6. Dx corresponds to a register in the DSP engine 3. Figure 3 does not show that when Dx ° executes the above-mentioned modulo operation instruction, 値 is read from the modulo address register (AO X) 2 1 6 and input to the memory address buffer (MABX) 2 0 6 and the arithmetic logic unit (ALU). 2 1 3. The input memory address buffer (MABX) 2 0 6 is still the same as the output address bus X A B, which specifies the address of X R 0 Μ 4 or XRAM 6. On the one hand, the modulo address f register (A L U) 2 1 3 (A 0 X) 2 1 6 is an addition change register (I X) or a constant (c0nst). Implementation and addition of the index register (IX) ^ 2 1 〇 'is implementation instruction MOVS, W @ Ax, I xj)' Dx isochronous addition is always the real instruction MOVS, W @ Ax, Dx, etc., the result of this addition Department of

I Arithmetic Logic Operator (ALU) \ 2 1 3 Output. It is output by the arithmetic logic operation unit (ALU) 2 1 3, and the system enters the selector 2 1 9. The output of the other side of this selector 219 is stored in the modulo start address register (M S) 2 1 4 which violates the start address. The output of the selector 2 1 9 is the output of the arithmetic logic operator (ALU) 2 1 3, or one of the modulo start address register (MS) 2 1 4. The decision is as follows. The address of the modulo address register (A0x) 216 and the address of the modulo end address (M.E) 2 1 5 are often applied by the Chinese national standard (CNS &gt; A4 specification (; 10 × 297 mm)) _ 20-I ---------- (Please read the notes on the back before filling out this page) Order 424192, s Printed by the Shellfish Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economy ) 1 Comparator (C MP) Compare 9 If it is not consistent, output logic 値 0 Μ 0 White J Comparator (C Μ Ρ) 2 1 7 The output system and control bit D Μ 9 ί Μ XY are in AND gate 2 1 8 Use logic (in this example, r-rt because D Μ 1 1 I Μ XY is logic 値 1 Μ ί) so the comparator 2 1 7 is still the same as the white AND gate, please Hu J 1 2 1 8 lose. Output 0 ) Input selector 2 19 〇 Selector 2 1 9 In white and Ια) Read back 1 1 Gate 2 1 8 The input 値 is logical 値 '1 &quot; When the modulo start address is selected, send W} Note 1 [Idea 1 I memory (MS) 2 1 4 0 値 Select the calculation item 1 1 1 The output of the arithmetic logic unit (ALU) 2 1 3 値 〇 Fill in K. Put Maben in the white AND gate 2 1 8 The input 値 is logic 値 0 during the following page 1 I performance selection The output of the arithmetic logic (ALU) 2 1 3 値 .1. /-So the output address 1 1 I of the bus XA Β is updated sequentially. End of modulo address register (Μ E) 1 1 I 2 1 5 is the same as the modulo address buffer (A 0 X) 2 1 6 is the same as the order 1 5 5 AND gate 2 1 8 Input selector 2 1 9 The complete logic 1 Μ 1 i 9 Select the modulo start address register (MS) 2 1 4 of 値 〇 Therefore, 1 1 modulo address register (A 0 X) 2 1 6 is registered by the modulo start address 1 1 . (M S) 2 1 4 値 Initialization 0 Line Γ The above-mentioned modulo operation explained the operation when using the modulo address register (A 0 X) 1 I 2 1 6 However, the modulo instruction M 〇 can also be specified. VS 3 W @ AX 1 1 I 9 The AX of DX is specified in the modulo address register (Α. 1 X ') 2 1 6 0 1 1 And the logic 値 0 is specified in the control MX Y to access the address bus! 1 Υ A Β Modulo operation 〇 At this time, the modulo operation instruction M 〇VS, 1 1 W @ AX, AX j of DX must be changed to the designated index address register (1 i A 0 y) 2 2 6 or (A 1 y) 2 2 6値 A y 〇 is used and 0 1 1 is assigned to the control position D Μ. The implementation of the modulus M can also be prohibited. 0 1 1 This paper size applies the Chinese National Standard (CNS) A4 specification (21QX297 mm &gt; 21 4.2 4丨 9 2-$ &quot; Α7 _______ Β7 V. Description of the Invention (l9) Figure 4 shows an example block diagram of the DSP engine 3, which is recorded as a random logic circuit (Random Logic Circuit) 3 0 1 circuit block diagram, including Figure 1 Decoder 3 4 and control circuit, and circuit blocks of control register and status register, etc. Other DSP engines 3 have: Arithmetic Logic Operator (ALU) 3 Q 2, Shifter (SFT) 3 0 3, Multiplier (MAC) 304, register (Reg) 305, register (AO, A1) 30 6, register (Υ〇., Y1) 30 7, register (× 〇, XI) 308, storage data buffer (MDB I) 3 0 9, storage data buffer (MDBX) 3 1 0, storage data buffer (MDBY) 3 1 1. Store data buffer (MDBY) 3 1 1 is connected to data bus YDB and bus D2. The memory data buffer (MDBX) 3 1 0 is connected to the data bus XDB and the bus D 1. Stored Data Buffer (MDB I) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economy 3 0 9 is connected to the data buses I D B and C 1, D 1, A 1, B 1. Multiplier (MAC) 304 inputs data from buses 1 and 61 and outputs the corresponding multiplication results to buses C 1 and D 1. The shifter (S FT) 3 0 3 inputs data from the bus A 2 and outputs the shift calculation result to the bus C 2. The arithmetic logic operator (AL if) 3 0 2 inputs data from the buses A 2 and B 2 and outputs the operation result to the bus C 2. Fig. 5 shows an example of the instruction format and instruction codes included in the instruction system of the microcomputer 1. The microcomputer 1 supports two types of instructions: C P U instruction and D S P instruction. All CPU instructions and part of the DSP instructions are 16-bit long instruction codes. The remaining DS P instructions become 32-bit long instruction codes. The paper size is applicable to China National Standard (CNS) A4 (210X297 mm) _ 22 -A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (20) | 0 C PU instruction does not need to make the DSP engine act.> Instructions implemented by C PF UJ core 2 ° DSP instruction system will Address operations or operand access 1 1 and some processing are burdened by the CPU core 2. The DS RP engine implements the instructions 1 Order 0 Please first [1 C PF U instruction is to allocate the upper 4 bits of the instruction code to KJ Read back 1 I Sr 1 1 0 0 0 0 Μ 1 1 1 0 range. DS P instruction is to assign Note 1 of the instruction [the highest 4 digits of the code are allocated in the range of 1 1 1 1 Jf. The more significant 6 digits of the command meaning 1 I 1 are allocated to 1 1 1 1 0 0 and f The 1 1 1 1 0 1 range instruction also turns the DS P instruction into a 16 I 1 I bit long instruction code. The first 6 digits of the instruction code are 1 1 I 1 1 1 1 1 1 0 The instruction 5 is a 3 2 digit long instruction code 0. Among the 1 1 1 the highest 6 digits of the instruction code are 1 1 1 1 1 1 1 ff The range is not divided into 1. The order is assigned with its range 丨 as 1 Unused area Undefined instruction area 9 will benefit 1 [Use this area to expand 丨 Instruction code 0 can be known from the instruction format> will each 1 1 The uppermost bit of the instruction code 丨 6-bit decode% on the side can decode on a small logic scale 1 1 The device determines that the instruction width is 丨 C PU U instruction J 1 6-bit DS PD instruction 9 wire: •-or 3 2 Bit length DS P instruction or undefined decree 0 1 1 In the CPU instruction format of Figure 5, J η η η η is 1 of the operand of g 1 1 I specifies the instruction field of the dddd displacement of the jaw area 1 1 1 ii 1 1 i is the designated field of 1! (Immediately. The η η η Π of the ADD instruction is also the designated field of the Shanghai 1 1 operand. The calculation results are stored in η η η η 〇 and 9 The aforementioned modulo operation instructions described in accordance with 1 1 and FIG. 3 correspond to the instructions in FIG. 1 1 Μ 〇 VSW @ R 2, A 〇 &gt; However, the instruction description system in FIG. 5 Operand 1 I refers to the description form k. Figure 3 illustrates different contents. 0 This form is different. 1 1 This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 mm> _ 4 2 4 1 9 2 A7 j. B7 V. Invention description (21) is actually the same. (Please read the notes on the back before filling this page) Figure 6 shows the connection between decoder 2 4 of CPU core 2 and decoder 3 4 of DSP engine 3 Configuration example. It is fetched into 32-bit units according to the instruction of the microcomputer and implemented in the instruction register (IR) 25. The decoder 2 4 includes a first decoding circuit 2 4 0, a second decoding circuit 2 4 1, and a code. Change the printed circuit of the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 2 4 2. The first decoding circuit 2 4 0 decodes the 16-bit field (CIR) 値 of the upper instruction side of the instruction register (IR) 2 5. According to the instruction, it is a CPU instruction, or a 16-bit DSP instruction, or 3 2 Bit DSP instructions form CPU decode signal 2 4 3, DSP decode signal 2 4 4, code conversion control signal 2 4 5 and shift control signal 2 4 6. The second decoding circuit 2 4 1 decodes the CPU decoding signal 2 4 3 to form various internal control signals (C P U control signals) 2 4 7 which implement the internal processor or register selection of the C PU core 2. The code conversion circuit 2 · 4 2 is used to compress or still output the instruction register (IR) 2 5 while the code conversion control signal 2 4 5 is activated. When the signal 2 4 5 is deactivated, information indicating that the output is invalid (Won — Operation Code) is output. The code conversion circuit 2 4 2 is to replace the signal 2 4 5 with an output of invalid information. The lower jaw region (L I R) 値 on the lower side is 1.6. It can also be realized by a selector. The outputs of the DS P decoding signal 2 4 4 and the code conversion circuit 2 4 2 are used as the DSP control signal 2 0 to supply the decoder 3 of the DSP engine 3 4 ° The aforementioned first decoding circuit 2 4 0, Stored in the instruction register (IR) 2 5 above the i-side 16-bit area (UIR) the uppermost 6 sides

I This paper uses the Chinese National Standard (CNS) A4 specification (2 [0X297 mm) —24-U 1 9 2: ^ J A7 ____B7__ 5. Description of the invention (smart decoding, you can determine that the instruction code is CPU instructions, or 16-bit DSP instructions, or 32-bit DSP instructions. (Please read the notes on the back before filling out this page.) The instructions printed and decoded by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs are 16-bit At the time of the instruction, the code conversion control signal 2 4 5 becomes inactive, so the code conversion circuit 2 4 2 outputs a Won Operation Code indicating that the output is invalid. Also, when the 16-bit instruction of the decoded instruction is shifted, the control signal 2 4 6 Activate and accept the instruction register (IR) 25. The 16-bit area (LIR) on the lower side is shifted to the 16-bit area (LIR) on the upper side. Implement all or part of the instructions. For example, in the instruction register IR, 16-bit field UIR stores 16-bit CPU instructions, and in the lower-side field LIR stores 32 2-bit DSP instructions. Above 16-bit instructions Explanation of the situation of the code. First, it is stored on the upper side 1 6-bit field UIR 1 6-bit CPU instruction is decoded in the first decoding circuit 2 4 0, and according to the result, CPU core 2 executes its instruction, storing the lower side 1 6-bit field LIR 3 2-bit DSP instruction upper bit 1 The 6-bit instruction code data is transferred to the upper-side 16-bit field u 1 R. At this time, the random logic circuit 2 0 1 performs an arithmetic operation on the arithmetic operator AU 2 0 8 which should be stored in the address of the program counter PC. The program counter PC stores the address of the result of the operation calculated by the arithmetic operator AU 2 Q 8. According to the address stored in the program counter PC, the 16-bit instruction code data below the 32-bit DSP instruction is stored in it. The instruction memory is transferred to the 16-bit area LIR on the lower side of the instruction register I. Therefore, the 32-bit DS P instruction is stored in the instruction register IR. The 32-bit DSP instruction stored in the instruction IR is a paper scale of the translation Applicable to China National Standard (CNS) A4 specification (210X297 mm) -25 A7 B7 V. Description of the invention (23) The encoder 2 4 is provided to the decoder 3.4 of the DSP instruction engine 3. The other methods, although not shown, But set the complex instruction prefetch buffer to CP Within Ut 2. The complex prefetch buffer is a designation that should be implemented before the current instruction prefetch cycle. No such prefetch buffer is based on the 16-bit instruction code data above 32-bit DSP instructions When transferring from the lower-level LIR to the upper-side 16-bit UIR, along with the machine logic circuit 2 0 1, the above-mentioned 32-bit DSP instruction lower-order 16-bit instruction code data pre-fetch buffer is selected. Read out the designated code data of the lower 16 bits of the 32-bit DSP instruction from the selected instruction prefetch buffer, and store them in the LLR in the side field below the instruction register IR. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). When the complex decoded instruction is a 16-bit CPU instruction, the DSP decoded signal 2 4 4 becomes the Won-Operation Code. When the decoded instruction is a 16-bit DSP instruction, the CPU control signal 2 4 7 forms a second decoding circuit 2 4 1 according to the CPU decode signal 2 4 3. The control signal inside the DSP engine 3 is essentially translated. The encoder 3 4 decodes to form a DSP decoded signal 2 4 4. When the decoded instruction is a 32-bit DSP instruction, the CPU control signal 2 4.7 becomes the second decoding circuit 2 4 1 according to the decoded signal 2 4 3. The control signal inside the DSP engine 3 is the decoder 3 4 Interpretation forms the output of the DSP decoded signal 2 4 4 and the code conversion circuit 2 4 2. The instruction system of the microcomputer 1 has 16-bit and 32-bit instruction code tables. As described above, since 16-bit long instructions are processed differently from 32-bit long instructions, their actions are described in detail. The 16-bit long instruction will be explained first. The first decoding circuit 2 4 Q will instruct the paper size to apply to the Chinese national ladder. (CNS> A4 specification (2) 0'〆297 mm) _ 26 A7 B7 4 ^ 4192: '^ V. Description of the invention ( 24) Register (2 R) 2 5 out of the 3 2 digits of the instruction code, 'upper 16 bits are decoded, and in the first decoding circuit 2 4 0, the highest 6 digits of the instruction code are known as * 111110 〃, * 11111〃 are 16-bit long instructions, so at this time together with the output of the CPU instruction decode signal 2 4 3 and DSP instruction decode signal 2 4 4. Set the instruction register (1 R) 2 5 to the lower bit 1 The 6-bit LIR instruction code data is shifted to the upper position 16. The 6-bit U2 R shift control signal 2 4 6 is activated. The flexible shift control signal 2 4 6 is the instruction register (IR) of the Ministry of Economic Affairs. The central government bureau employee consumer cooperative printed 2 5 is to move the instruction code stored in the lower 16-bit field LIR to the upper 16-bit field U2R. The shifted instruction code is then processed by the first decoding circuit 2 4 0 Decoding. The CPU instruction decoding signal 2 4 3 output by the decoder 2 4 is output to the second decoding circuit 2 4 1 and the DSP decoding signal 2 4 4 is provided. When the DSP engine is 3 ° and the first decoding circuit 2 4 0 is a 16-bit long instruction, the code conversion control signal 2 4 5 is inactive. Therefore, the code conversion circuit 2 4 2 indicates the lower 16 bits. The invalid instruction code is formed as part of the DSP control signal. On the DSP engine 3 side, the DSP decoding signal 2 4 4 output by the first decoding circuit 2 4 0 and the code conversion circuit 2 4 2 are output When the code signal is input as the DSP control signal 20, the decoder 34 executes the decoding of the DSP control signal 20. The 16-bit DSP instruction is generated by the DSP control signal generated by the code conversion circuit 2 4 2 Becomes a signal indicating invalidity, so the decoder 3 4 focuses on the DSP. The decoded signals 2 4 4 output the multiplier (MAC) 3 0 4 in the DSP engine 3, the arithmetic logic operator (ALU) 302, and Shifter (SFT) 303 This paper size is applicable to the national standard of China (CNS> A4 size (210 X 297 mm) _ 2 7 The paper size printed by the staff consumer cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is applicable to the Chinese national standard (CNS) A4 specification (210 X 297 mm) 4 1 9 2,: s-A7 __ ^ _ B7_ 5. Control of invention description (25), etc. Monk. The DSP engine 3 executes the arithmetic processing according to the control letter. Next, the 32-bit long instruction is explained. The first decoding circuit 2 4 0 inside the CPU core 2 stores the 32-bit instruction code in the instruction register ( LR) 2 5. The upper 16 bits are decoded by the first decoding circuit 2 40 and the decoded signals 2 4 3 and 2 4 4 are output. In the first decoding circuit 2 4 0, the code conversion control signal 2 4 5 is activated because it knows that the highest 6-bit code of the instruction code is' ^ 1 1 1 1 1 0 7 when it is a 32-bit long instruction. Therefore, the code conversion circuit 2 4 2 performs a code conversion on the instruction codes of the lower 16 bits of the instruction register (IR) 2 5. The code-transformed information is supplied with the DSP decoded signal 2 4 4—the same as the DSP control signal 2 0. The decoder 3 4 decodes the DSP instruction control signal 20 to form a control signal of the DS engine 3. The decoders 24, 34 can be implemented in, for example, a random logic circuit. 0 (1, 7 represents another embodiment corresponding to FIG. 6. The embodiment of FIG. 6 illustrates that the instruction data of the lower-order area LIR of the instruction register 25 is moved to the upper-order area UIR. The embodiment of FIG. 17 is described above. Between the instruction register 25 and the internal data bus IDB, there are two series of instruction prefetch buffers 2 5 0, 2 5 1 constituting the instruction prefetch queue, and the selector 2 5 2 selects the instruction prefetch buffer 2 5 0 The holding data of 2 51 are supplied to the instruction register 25. Each instruction prefetch buffer 2 5 0., 2 51 and the instruction register 25 are used to hold data in units of 32 bits. The holding action is controlled by the control signal ~ 03. (Synchronized with CLK1) control. Although not specifically shown, each instruction prefetch buffer 2 5 0, 2 5 1 and instruction register 28-— I — I — f (Please read the precautions on the back before filling this page ) Order 424 192:? A7 __ ^ _ B7_ V. Description of the invention (26) The device 2 5 has a main vertical structure, and the main segment is synchronized with the rising of the corresponding control signal to implement the latching action of the input. Therefore, the prefetch The previous and next instruction data are stored in the instruction prefetch buffer 2 2 0, 2 5 1 in series. The selector 2 5 selects the 32-bit command data supplied to the port Pa or the 32-bit command data supplied to the command register 25 according to the selection control signal 0 4. The pre-fetch of the command is supplied to the aforementioned port Pa. Buffer 2 5 0 high-order 1 6-bit area CPB1 is the low-order side, and the instruction prefetch buffer 2 5 1 low-order 16-bit area LPB 2 is the high-order 3 2-bit instruction data. The port Pb supply is stored in the instruction The 32-bit original instruction data of the prefetch buffer 251. Thus, the instruction prefetch buffer 2 5 1 holds 3 2 bits of DSP instructions and the selector 2 5 2 selects the output of port Pb to set the 3 2 bits. The DSP instruction is set in the instruction register 2 5. The instruction prefetch buffer 2 5 1 holds the 16-bit DSP instruction or the 16-bit CPU instruction in the upper field UPB 2 when the selector 2 5 2 selects the output of the port Pb Central of the Ministry of Economic Affairs. The Bureau of Standards and Industry Cooperatives can set the 16-bit instruction in the upper register UIR of the instruction register 25. The instruction prefetch buffer 2 5 1 sets the 16-bit DSP instruction or the 16-bit DSP instruction. When the CPU instruction is held in the lower area LPB2, the selector 2 5 2 By selecting the output of port Pa, this 16-bit instruction can be set in the upper register field UIR of the instruction register 2. The instruction prefetch buffer 2 5 1 keeps the 16-bit DSP instruction above the 16-bit instruction code in the lower order Area LPB 2, and the instruction prefetch buffer 2 5 G holds the 32-bit DSP instruction lower side 16-bit instruction code in its upper area UPB 1, because the selector 2 5 2 selects the input of port P a 29-This paper size applies to Chinese National Standard (CNS) A4 (210X297 mm)-Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 4 24192,:, A7 ___ £ 7 ____ 5. Description of the invention (2 is enough This 32-bit DSP instruction is set in the instruction register 25. 2 5 3 in FIG. 17 are the control logics of the latch control signal θ 1, 0 2 of the aforementioned instruction prefetch buffer, the latch control signal 0 3 of the instruction register 25, and the aforementioned selection control signal 04. The control logic 2 5 is based on the control signal 2 4 8 indicating a 16-bit instruction or a 32-bit instruction and the instruction prefetch buffer 2 5 0, 2 5 1 in which the remaining instruction code states are not implemented, forming the aforementioned control. Signal 0 1 ~ 0 4. The control logic 2 5 3 forms part of the control logic for instruction fetch. In addition, the aforementioned control signal 2 4 8 is the first decoding circuit 2 4 0 which supplies the instruction code data from the upper register U 5 of the instruction register 25 to the upper 6 bits. The details of the decoder are described later. The instruction code data is set in the instruction register 2 5 according to the aforementioned control logic 2 5 3 as follows. The instruction fetch from the outside is at the instruction fetch time of the CPU core 2 (for example, the instruction fetch stage IF in the plural stage pipeline stage described later), and the instruction prefetch buffer 2 50 has room for re-storing 32-bit instruction code data Implementation. When the instruction is fetched within its time, the instruction prefetch is slowed down. The punch 2 5 1 remains unrealized &amp; Stored in the field of the instruction prefetch buffer 2 5 1 UPB2 "When the first state of the instruction code of both sides of the LPB2 is not implemented, the instruction prefetch buffer 2 5 1 3 2 bit output

I is selected by the selector 2 5 2 via the port Pb and set in the instruction register 2 5. On the one hand, the instruction and code stored in the lower-order area LPB 2 of the instruction prefetch buffer 2 51 are not implemented, and the prefetch instruction is prefetched in the upper area UPg 1 and the instruction prefetch 2 50 0 Buffer 2 5 1 The instruction code data of the lower area LPB 2 is set to the instruction via port P a

__ I This paper size is applicable to China National Standards (CNS) A4 specification Ulf x297 male &gt; __3〇- (Please read the precautions on the back before filling in this page)% Order-.Q, Central Ministry of Economic Affairs Printed by the employee's consumer cooperative of the Bureau 424192 ”1 A7 __ ___ B7 _.___ V. Description of the invention (28) Register 2 5. In the aforementioned first state; the decoding circuit 2 4 0 will be set in the upper field of the instruction register 2 5 UIR As a result of the decoding of the instruction code data, in order to construct a 32-bit instruction, the 32-bit instruction code data pre-fetched in the 250 pre-fetch buffer is transferred to the instruction pre-fetch buffer 2 5 1 ° ― When a 16-bit instruction is detected from the decoding result, the data shift from the instruction prefetch buffer 250 to the secondary buffer 2 51 is not performed. In the aforementioned second state, the instruction is executed via the port Pa. After the data in register 25 is set, the 32-bit instruction code data prefetched by the instruction prefetch buffer 2 50 is still shifted and set in the instruction prefetch buffer 2 5 1 ° After the shift, if the instruction prefetch Fetch buffer 2 5 Q When there is unimplemented instruction code data, the instruction prefetch buffer 2 5 0 An instruction prefetch time prefetches the instruction code data.. With this control, after the instruction fetch time, the unprocessed instruction code data is set in the instruction register 25. At this time, the instructions to be implemented are 16-bit CPU instructions 1 6-bit DSP instructions or 32-bit DSP instructions, one of the upper-side 16 bits must be supplied to the first decoding circuit 2 4 0. The code conversion circuit 2 4 2 illustrated in FIG. 6 is shown in FIG. 1 by the selector 2 4 2A and code conversion logic 2 4 2B. In addition, the first decoding circuit 2 4 0 is explained in FIG. 6 according to whether the decoded instruction code is a 16-bit instruction to form a control signal to control its level 2 4 5 , 2 4 6 In the example in FIG. 17, a control signal for outputting a 16-bit instruction or a 32-bit instruction (in this embodiment, the 32-bit instruction is a DSP instruction) is output. 2 4 8 .Selector 2 4 2A, control signal 2 4 8 This paper size applies Chinese National Standard (CNS) A4 specification (210X: 297 mm) ------— IIP! (Please read the precautions on the back before (Fill in this page) Order 424 1 92.: ^ J A7 ___B7 V. Description of the invention (29) When indicating a 16-bit instruction, select Non Operation Cq.dew c _p Provides code conversion logic 2 4 2 B, control signal 2 4 8 indicates 3 2 bit DSP instructions, and supplies the instruction code of the lower register LIR in the instruction register 25 to the code conversion logic 2 4 2 B. Code conversion logic 2 4 2 B, although it is not particularly limited, but a part of the instruction code data of the lower-order area LIR of the instruction register 2 5 such as the code information for register selection is modified to be suitable for the decoder 3 4 of the DSP engine 3 Morphological output. Ministry of Economic Affairs_Central Bureau of Labor Standards, Consumer Consumption Co., Ltd. Printed Figure 17. In the embodiment, the first decoding circuit 2 4 0 interprets the 16-bit instruction code data held by the UIR in the upper field of the instruction register 25 and decodes the obtained CPU. The signal 2 4 3 is supplied to the second decoding circuit 2 4 3, and the DSP decoded signal 2 4 4 is supplied to the decoder 3 4. The CPU decoding signal 2 4 3 is intentionally supplied to either the CPU instruction or the DSP instruction, and is supplied to the second decoding circuit 2 4 1. The second decoding circuit 2 4 1 decodes the CPU decoding signal 2 4 3 and outputs the control information for the address calculation and data operation to be performed by the GPIO core 2 and the internal storage X-R 0M 4, Y — R0M5 , X — RAM, Y — RAM, and external storage access control bus and data line selection control information. As mentioned above, for the DSP instruction, the necessary address calculation and data bus selection are also implemented by the CPU core 2. The aforementioned DSP decoding signal 2 4 4 is the same as described above. When the instruction code supplied to the first decoding circuit 24 0 is code data for DSP instruction, it becomes an intentional decoding signal. The intentional DSP decoding signal 2 4 4 contains, for example, designated information such as a register in the DS engine 3 that transfers data between the memories accessed by the address operation performed by the CPU core 2. The paper size for the first decoded electric book is applicable to the Chinese National Standard (CNS) A4 specification (21.0X297 mm) _ 424 ί 92 Factory A7 ______ Β7 ___ V. Description of the invention (When the instruction code for Road 2 4 0 is a CPU instruction, DS.P decoding signal 2 4 4 becomes invalid code. (Please read the precautions on the back before filling this page.) The code of the aforementioned DSP instruction contained in the instruction system of microcomputer 1 is described in more detail. Figure 18 and Figure 19 shows the instruction code of the 16-bit DSP instruction. Figure 20 and Figure 21 show the instruction code of the 32-bit DSP instruction. As mentioned above, the DSP instruction allocates the 4 most significant bits of the instruction code to 1 1 1 #, 6 bits of the uppermost side of the instruction code are '^ 111100, and' 111101, are 16-bit DSP instructions, and 6 bits of the uppermost side of the instruction code are, 1 1 1 1 1 0, of The instruction system becomes a 32-bit DSP instruction. Figure 1 shows the first column (XS 丨 de of Data Transfer). The instruction format of a 16-bit DSP instruction is X memory (X — ROM4, X — RAM6) and DSP. Data transfer instructions between the built-in registers of Engine 3. In the above instruction format, AX, A y are specified to be included in Registers of the register array 2 0 9 (refer to Figure 3.) included in CPU core 2, Ax. = '0, designated register R4, Ax =' 1, designated register R.5, Ay = designated register R 6, A y &quot; 1 Printed by the Consumer Cooperatives of the Central Bureau of Standards, Ministry of Economic Affairs

, Is designated register R7 〇Dx * Dy, Da is designated register included in DSP engine, = * 0, designated register X〇, D x = designated register XI, Dy = designated register Y0, Dy = '1, Designated register Y1, Da = designated register AO, Da = designated register A1. I X, I y means immediately. The instruction format of the 16-bit DSP instruction shown in Figure 19 is connected to the micro-paper. The size of the paper is applicable to China National Standard (CNS) A4 (210X297 mm) Data transfer instructions between the memory shown and the built-in registers of the D s P engine.3. A s specifies the registers included in the register array 2 0 9 (refer to FIG. 3) of the built-in C PU core 2 and D s specifies the registers XI 'X〇, Y1, Y0, A1, AO, and registers that are built into the DSP instruction engine. Registers included in array 3 0 5 (see Figure 4). The format of the 32-bit DS P instruction is the field representing the code 1 1 1 1 of the 32-bit DSP instruction (bit 3 1 to bit 2 6), the A field (bit 25-bit 16), and B field (bit 15 to bit 0). Figure 20 shows the code of the information group A and its corresponding mnemonic, and Figure 21 shows the code of the information and the corresponding mnemonic when it looks at the B group. The code of the A group shown in Figure 20 printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs is the same as the code of bits 9 to 0 of the 16-bit DSP instruction shown in Figure 18 The code of the tfA field set in the column (X Side of Data Transter) specifies the data transfer between the X memory (X — ROM4, X-RAM6) and the built-in registers of the DSP engine 3. The second block (Y Side of Data The code of the A block shown in Transter) specifies the data transfer between the Y memory (y ROM5, Y-RAM7) and the built-in registers of the DSP engine 3. The contents of the bits A X, A y, Dx, Dy, and Da contained in the A field are exactly the same as those in the garden 18. The code of the B field shown in FIG. 2 specifies the arithmetic operations, logical operations, shift operations, and load / store processing between registers, which are implemented inside the DSP engine 3. For example, stipulate that the multiplication (PMULS), subtraction (PSUB), and addition (PADD) implemented within the DS: P engine 3 are in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) _ {Please read first Note on the back, please fill out this page again) 34-4. Z 4 l 9 2 A7 ___B7 ___ V. Description of the invention (32) PRND, shift (PSHL), logic. Product (P AND), exclusive logic And (XOR), logical sum (OR), addition (PINC), subtraction (PDEC), clear (CLR), etc., or the load (PLDS) and storage (PSTS) implemented within the DS.P engine 3. Figure 2 The third block (3 0 Operand Optr- + atiQn _with Condit 丨 on) is a code with a condition, and its condition (if cc) # can select the DC (data completion) bit (indicating that the data has been processed) The logic of 値 or see. The actual 32-bit D S P instruction is described as an arbitrary combination of the B field code and the A field code. That is, the 32-bit D S P instruction fetches the operation object of the internal or external microcomputer 1 and specifies the processing to be performed inside the D S P engine. As can be seen from the above description, the address operation for fetching operands and the selection of the data bus are implemented by CP2. The code of the A field in the 32-bit DSP instruction is the same as the 16-bit D S P instruction. 1 6. The bit DS command is used for initial setting of the registers in DS engine 3 and so on. Printed by the Employees' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs Refer to Figure 17 and other figures. The code data that constitutes the A block of 32-bit DSP instructions is set in the upper-order field UIR of the instruction register 25. In addition, 16-bit DSP instructions having the same format as the A block are also set in the upper field U I R. Therefore, in any case, the CPU core 2 can also perform the required address calculation and data fetch (or operand fetch). The necessary data bus can be selected. In other words, the decoding circuit required to implement the data fetch (or operand) for 32-bit DSP instructions and the data fetch (or operand) for 16-bit DSP instructions -35 * (Please read the back Note: Please fill in this page again) This paper size is applicable to China National Standard (CNS) A4 specification (210X297 mm) Α7 Β7 V. Description of the invention (33) 2 4 0, 2 4 1 It is also beneficial to share this point Micro-computer 1 shrinks in logic. 3 The designated information of the internal register of the DSP engine 3 designated by the A field of the 2-bit DSP instruction and the designated information of the internal register of the DSP engine 3 designated by the 16-bit DSP instruction are used as the aforementioned DSP decoding signal 2 4 4 are provided to the DSP engine 3 . Whether the DSP. Decoded signal 2 4 4 is intentional or not is determined by decoding the 4 bits of the uppermost side of the upper field UIR by the first decoding circuit 2 4 0 described above. Next, the content of the arithmetic control of the microcomputer of this embodiment will be described with reference to the instruction implementation schedule of Figs. The microcomputer 1 of this embodiment implements the five-stage pipeline action of the IF, 10, £ 乂, "August, 1 ^ 6/03? Stage. IF is the instruction fetch phase, ID is the instruction decoding phase, EX is the operation implementation phase, MA is the memory access stage, WB / DSP is the data fetched from the memory into the CPU core 2r printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this purchase) Register Phase or DSP engine 3 implementation of DSP instructions. In each figure, Instrnct: ion / Dat; a Access means via internal bus IAB: [DB memory access, access object is built-in memory 4 ~ 7 outside also May be external memory of microcomputer 1. XY Mera, Access means internal total 1TAB, YDB memory access, access objects are limited to built-in memory 4 ~ 7. Isnt, Fetch means instruction register (_I R) 2 5 instructions Fetch, Reg means instruction register (IR) 2 5, Sonrce Data Ont means source + data output, Destination In means input time of destination data, Destinati id n R eg 丨 ster means destination register. Pointer Reg Means text register, Address Calc, address calculation, Deta Fetch means data fetching, Dsp Control This paper size is applicable to China National Standard (CNS) A4 specification (2! 0X297 mm) _ _ Staff Consumption of Central Bureau of Standards Printed by the cooperative Α7 ------- Β7 ____ V. Description of the invention (34)

Signal Decorated Timing means the decoding time of the DSP control signal 20 of the decoder 34. FIG. 7 shows a timing chart of the ALU operation instruction inside the CPU core 2. ADD Rm, Rn is an example of the ALU operation instruction. 0 The memory is synchronized with the rising time of the clock signal ClQCk2 immediately before the IF phase, and the address of the instruction (ADD, Rm, Rn) that should be implemented. Output on I AB of the address bus . Memory access operations are performed during the Instruction Data Mem, Access IF phase. Specifically, the decoding of the address specified by the address bus I AB is performed during the rise of the clock signal Clockl to the rise of the clock signal CUck2, and the instruction is executed during the rise of the clock signal CUck2 in the IF phase to the rise of the next clock signal Clockl access. Therefore, the clock signal CUcIi2 rises from the stage I F to output the instruction to the data bus. The instruction output on the data bus I D B is synchronized with the rising time of the clock signal CUckl in the I D phase, and is taken into the instruction register (I R) 2 5. In the ID phase, the data of the instruction register (IR 0 2 5) is decoded. Synchronized with the rise time of the clock signal CUckl in the Ex phase, the register storing the source data is accessed, and the register is output to the CPU core 2. Bus A1, B1. In the instructions ADD Rm, Rn will make the registers specified in Rm and Rn become source registers. Rm and Rn can instruct any register inside CPU core 2 (in Figure 3, any register in register 2 0 9 can be specified A 0 X, Alx, lx, A. Oy, Aly, Iy, Rm, and Rn? Output to the CPU core 2. The data of the bus A 1 and B 1 are applied to the Chinese paper standard. A4 size (210X 297mm) _ 37 (Please read the notes on the back before filling this page)

4 24 19 2 &quot; * ^ 1 A7 __B7____ 5. Description of the invention (35) {Please read the precautions on the back before filling in this page) The arithmetic logic unit (ALU) 2 1 3 The addition operation is performed, and the result is output to the CPU The internal bus C1 of the core 2. The calculation result output on the internal bus C1 of the CPU core 2 is synchronized with the rise time of the clock signal Clock2 in the E and X phases, and is stored in the destination register (the destination register becomes the register specified in Rn by the ADD Rm and Rn instructions). As described above, the ALU operation instruction inside the CPU core 2 completes the instruction implementation action in the pipeline stages of I F, I D and EX. Fig. 8 is a timing chart showing the data read operation from the memory to the CPU core 2. Here MOV, L @ Rm, Rn is an example of the data read operation from the memory to the CPU core 2 to describe its operation. Since the operations of instruction fetch (IF) and instruction decode (ID) are the same as those in Fig. 7, detailed descriptions of them are omitted. The rise time of the clock signal Clockl, which is synchronized with the EX phase, is used as the number of registers of the address pointer _ is output inside the CPU core 2. i. Bus A 1. In this example, the register that becomes the ground. ± i pointer becomes the register designated by R m. The register that can be specified in Rm is any register included in the CP core 2. In Figure 3, any register that can be specified in R e g is printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs

m R ο save as system, y 摅 I number, y-t ΙΑ A line, total &gt; Department ο within A, 2 X core IU, PXC 1 out of A, lose X ο The stage of time X Ε in the same step 5 ο 2 The device rushes to the site of the total line of the storage line and rises in the output and output P C on the output side

Core U

u ULLAA Headquarters 1 1 2 2}} 3 3 Α Shi Shi Line Shi 8 8 &amp; operation ο 之 加 镎-the device calculates WE 遢 此 # The series is the logic logic fruit calculation At the moment, 〇 is calculated based on this.

I centimeter 7 9 2 X Printed by A7 B7 of the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (The internal bus Cl of CPU core 2. The results of the output of internal bus C 1 of CPU core 2 are synchronized to EX The time above the clock signal Clock 2 of the phase is stored in the pointer register (at this time, the register designated by Rm). In 丨 nst: rnction / Data Mem, Aecess, the clock signal Clockl in the Μ phase rises to the clock During the rising period of the signal Clock2, the decoding is performed synchronously with the rising time of the clock signal CUck2 in the EX phase, and the address output on the address bus I AB is decoded, and the rising period of the clock signal Clock2 in the MA phase is raised to the next clock signal Clockl. Data access. Therefore, the clock signal Clock2 from the MA phase rises to output data to the data bus IDB. The data output from the data bus IDB is synchronized to the clock signal Clockl rise time from the WB / DSP phase and is taken into the CPU core 2. Output data to the internal bus DW of the CPU core 2. Synchronize the rise time of the clock signal Clock 2 in the WB / DSP phase, and output the data on the internal bus DW of the CPU core 2. Stored in the destination register., Complete the action. In this example, the destination register becomes the register specified in R n. The register that can be specified in R η is included in any register of CPU core 2 (in Figure 3, the register in Reg can be specified Arbitrary register, AOx, Alx, Ix, A0y, Aly, Iy is Rn). As above, the data is read from the memory to the CPU core 2. The action instructions are read in IF, ID, EX, MA, WB / DSP 5 sections The pipeline stage completes the execution of the instruction. Figure 9 shows the time chart of writing the operation instruction from the CPU core 2 to the memory. Here are MOV, LRm, @Rn for the operation of reading data from the CPU core 2 to the memory. An example illustrates the action. Because the paper size of this instruction is applicable to China National Standard (CNS) A4 (210X297 mm) 39 --------- 丨 — (Please read the precautions on the back before filling this page ) Order tr 4 2 4 192: ^ A7 B7 Employee Cooperative Cooperative of Central Standards Bureau of Ministry of Economic Affairs

V. Description of the invention (37)-1 | Fetch (IF), the operation of instruction decoding (ID) is the same as that of Fig. 8. Therefore, 1 detailed description of the part is omitted. 1 Synchronize with the rise time of the clock signal C 1 0 c k 1 at the stage of E X, and do 1 I _ The data of the register of the address pointer is output to the inside of CPU core 2. Please refer to the 1 1 I bus A 1. In this example, the register that becomes the address pointer is the register designated by the R m read back 1 1 f. The register that can be specified in R η is an arbitrary register included in Note 1 j of CPU core 2 (I, any register that can be specified in R eg can be specified. Note 1 I, A 0 X, A 1 X » IX, A 0 y, A 1 y, I y are taken as %% and 1 R η). Data output on the internal bus A 1 of the CPU core 2> Store page 1 1 Stored in the address buffer 2 0 5 and synchronized to the clock signal of the Ex stage 1 1 The rise time of Cl ock2 is output on the address bus [AB °- -The data of the output 1 1 1 on the internal bus A 1 of the CPU core 2 is calculated in the arithmetic logic unit 1 (r) (ALU) 2 1 3. At this time, the arithmetic logic operation unit (1 1 A.L U) 2 1 3 performs 0 addition operation. The calculation result is output on the internal bus C 1 of CPU core 2 1 and the output result on the internal total 1 I line C 1 of CPU core 2 is synchronized with the clock signals C1 0 C kri and _ 2 in the EX phase. Rise time is stored in the finger decode '(in this case, the 1 1 1 register designated by R η), the instruction M 0 V, R η in L, @ R η is 9 and the address operation is performed at Ε X stage 1 1 At the same time, the data output 1 1 which should be written into the memory is implemented. The preparation of the data bus ID Β is synchronized to the clock signal of the phase Ε X. The rise time of the clock signal 1 1 C 1 ock 1 is used to store the data that should be written into the memory. 1 1 The device outputs 値 to the internal bus DR of CPU core 2. In this example, the decoding of the data that 1 storage i 1 should write into the memory becomes a register designated by R m. 0 I The register that can be designated in R m is an arbitrary decoding included in the CPU core 2 (1 1 I Paper size applies to Chinese national standard (CNS M4 specification (210X297 mm) 40 Printed by Shellfish Consumer Cooperative of the Ministry of Economic Affairs of the People's Republic of China and the Ministry of Economic Affairs 4 24 1 92: ^ 4 A7 __B7_ V. Description of the invention (38) Designated Reg, in any register, A Ox, Alx, lx, A0y, Aly, Iy is Rm). Output to the internal bus dr of the CPU core 2 is synchronized to the clock signal C 1 ock 2 of the MA phase Rise time output data bus ID Β. At 1:13 (; 1 *! 1 (: 1; 丨 〇11 / 0 & 纟 &) ^ _ 111. Person &lt; ^ 633at] ^ 1 six-phase clock signal CUckl During the period from the rise to the clock signal Clock2, the rise time of the clock signal CUck2 synchronized to the EX stage is used to decode the address of the output address bus I AB, and the rise time of the clock signal Clock2 synchronized to the MIMO stage is written to the output. The data of the bus IDB is completed as an action. From the memory to the CPU The data of 2 is written into the operation instruction. Because the CPU core 2 completes the operation at the time when the data is output to the data bus IDB, the operation is completed in the four-stage pipeline stages of IF, ID, EX, MA. Figure 10 shows the time when the DSP instruction is implemented. Time chart. Take PADDC Sx, Sy, Dz NOPX, NOPY as an example of the D SP instruction to explain its operation. This instruction implements the addition of the data stored in the DS P engine 3 and does not implement the DSP engine 3 and X -ROM4 and X-RAM6, and instructions for data transfer between Y—ROM5 and .Y—RAM7. The instruction fetching operation is the same as that in FIG. 7 and its detailed description is omitted. It is implemented on the clock signal in the stage of .1 D The decoding of the instruction code fetched by CPU core 2 during the period from CUckl to Clock2 will output the result of decoding the instruction code as the DSP control signal 20 at the time of the clock signal Clock2 in the ID phase. Paper size applies to China National Standard (CNS) A4 specification (2i0 × 297 mm) _ (Please read the back: Cautions before filling out this page) Order A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (39) DSP engine 3 0 White CPU core 2 When DSP control signal 2 0 is input &gt; Decode the DSP control signal input during the M A phase 0 Synchronize W signal C1 0 C k L rise when W Β / DSP phase At time t, access the storage source data register 9 and output the register to the DS PB engine 3 internal bus A 2 Β 2 0 In this example, 9 the storage source data storage register SB W becomes the register designated by SX and S y * can be specified The registers in SX and S y are arbitrary registers inside DSP engine 3 (any register in R & 9 in Figure 4 can be designated as SX and S y) 〇 Output DSP engine 3 internal bus A 2 9 B 2 Data in calculation-AfT * m logical operation unit (ALU) 3 0 2 The result of the operation is output to the internal bus C 2 of the DSP engine 3 0 The operation result of the internal bus C 2 of the DSP engine 3 is output to the WB / Clock Letter for DSP Phase The rising time of the number C ί 0 C k 2 is stored in the register 0 of S. In this example, the 9 destination register becomes the register designated by D 2 and the register that can be designated in DZ is any register inside DSP engine 3. (Figure 4 is R eg Any register within) a. As above, DS instruction 9 is completed with IF 1 ID, EX 9 Μ A &gt; WB / DSP 5-stage pipeline stage 0. Figure 1 1 shows white X, Y memory 4-7 direction The data of the DSP engine 3 should be in accordance with the time of the movement instruction. 0 Here is 〇 〇VXWAX &gt; DX 9 Μ VYW @ A y? D y is used as the white X 1 Y storage instrument 4 &lt; ^ w 7 to the DSP engine An example of the 3 data read instruction is its operation. 0 This instruction is an instruction that transfers the data stored in the address specified by AX and A y to the register specified by DX and D y. 0 The instruction fetches 9 The operation cause of the instruction decoder Same as Fig. 10, so detailed description of this part is omitted Ming 0 This paper wave scale is applicable to Chinese national standards (CNS &gt; A4 specification (210X297 mm) _ 仏 A7 B7 V. Description of invention (40) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in) (This page) When the X, Y memories 4 to 7 are used to read the data into the DSP, the memory 3 accesses the address of the memory to form the CPU core 2. Therefore, the rise time of the clock signal Clcickl synchronized with the stage E and X is accessed to register which stores the address to be accessed, and the register is output to the internal bus A1 ~ A2 of cPU core 2. The register that stores the address to be accessed in this example becomes the register designated by Ax and Ay. The registers that can be specified in Aχ include the registers AO X and A1 X of CPU core 2, and the registers that can be specified in Ay are the registers AO y and A 1 y in CPU core 2. The data output on the internal buses A 1 to A 2 of the CPU core 2 are stored in the memory address buffers (MABX, MABY) and synchronized to the rise time of the clock signal CUck2 in the phase E and X are output to the address buses XAB and YAB. On the one hand, the data output from the internal buses A1 to A2 of the CPU core 2 are implemented by ALU2 1 3 and PAU2 1 2 for address calculation. At this time, ALU213 and PAU212 implement 0 addition operation. The calculation result is output to the internal buses C 1 and C 2 of the CPU core 2, and the calculation result output to the internal bus C 1 and C 2 of the CPU core 2 is synchronized with the rise of the clock signal Clock 2 in the EX phase and stored in Pointer register (that is, registers P designated by Ax and Ay in X, Y memory 4 ~ 7, during the rise of the clock signal C! Ockl in the MA phase to the rise of the clock signal CUcli2, implement the EX phase clock signal Cioc-k2 The rise time is output on the address bus XAB and YAB to decode the address. Data is accessed during the rise of the clock signal CUck2 in the MA phase to the rise of the next clock signal Clockl. Therefore, the rise of the clock signal Clock2 in the MA phase The data output data bus XDB cardiophysical scale is applicable to the Chinese national standard (CNS> A4 specification (210X297mm) _-A7 B7 4 241.92 :, V. Description of the invention (41) (Please read the precautions on the back before filling this page ), YDB. The data of the output data bus XDB, YDB is the same as the rise time of the clock signal CUckl in the WB / DSP phase. It is taken into the DSP engine 3 and the data is supplied to the internal buses D1 and D2 of the DSP engine 3. Synchronized with WB / The rise time of the clock signal Clock2 in the DSP phase stores the data on the internal buses D 1 and D 2 of the DSP engine 3 in the destination register to complete the action. In this example, the destination register becomes the register designated by D. X and DY. The registers that can be specified in DX are the registers XO, X1 included in DSP engine 3, and the registers that can be specified in Dy are the registers YO, Y1 contained in DSP engine 3. As above, the data is read from the memory to DSP engine 3. The advance instruction is completed by the five pipeline stages of IF, ID, EX, MA, WB / DSP. The parallel data read operation is performed by the CPU core via the independent buses XAB, XDB, YAB, and YDB. 2 Can access X, Y memory 4 ~ 7. Printed by the Consumer Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs. Figure 12 shows the time chart from the DSP engine 3 to the X, Y memory 6, 7 written into the action. Take MOVX.W Da, @ Αχ Μ Ο VY * W Da, @Ay is an example of an action instruction written from the DSP engine 3 to the X, Y memory 6, 7 to illustrate the action. This instruction is stored in D a The data of the specified register is transferred to the storage in AX and A y The instruction of the address of the register. The operation of the instruction fetching 'instruction code is the same as that in Figure ii, so the detailed description of it is omitted, and the data from the DS P engine 3 to the X, Y memory 6, 7 is written into the operation instruction. The storage address that should be accessed forms the CPU core 2 °, so it is synchronized to (the clock signal of Clockl's private paper scale is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm)) Printed by the Central Standard of the Ministry of Economy 4 24 192 ^ A7 __B7__ V. Description of the invention (4. Rise time, access the address register that should be accessed by storage, and output the register to the internal bus A 1 ~ A 2 of CPU core 2. Synchronize with the MA stage The rise time of the clock signal CUckl accesses the internal register of the DSP engine 3 which stores the data to be transferred, and outputs the register to the internal buses D 1 and D 2 of the DSP engine 3 and stores it in the storage data buffer ( MDBX, MDBY. In this example, the internal register of the DSP engine 3 storing the data to be transferred becomes a register designated by Da. The registers that can be designated by Da are the registers A 0 and A 1 containing the DSP engine 3. The rise time of the clock signal Clock2 synchronized to the MA phase, and the data stored in the storage data buffer (MD BX, MDBY) are output on the data bus XDB, YDB. Synchronized with the rise time of the clock signal Clock 1 in the MA stage, accesses the internal register of DS: P engine 3 that stores the data to be transferred, and outputs this register to the internal buses D1, D2 of DSP engine 3, and stores it in Store data buffers (MDBX, MDBY). In this example, the internal register of the DSP engine 3 storing the data to be transferred becomes a register designated by D a. The registers that can be designated by D a are the registers A 0 and A 1 contained in the DS P engine. The rise time of the clock signal CUck 2 synchronized with the MA phase, and the data stored in the storage data buffer (M D B X, M B D Y) are output on the data bus X D B, YDB. During the rising period of the clock signal ClockI to the clock signal Clock in the X and Y memories 6, 7 at the stage of MA, the address output on the address bus XAB and YAB is decoded with the rising time of the clock signal Clock2 in the EZ stage. Clock signal at MA stage I.— 1 — — — — — (Please read the notes on the back before filling this page) The paper size of the paper is applicable to the Chinese National Standard (CNS) M specification (2 | 〇χ297mm) 45- 424192 A7 ________B7 V. Description of the invention (

Data access is implemented during the period from the rise of Clock2 to the next clock signal Clockl. Therefore, the data of the output data buses XDB and YDB are written from the rising of the clock signal ClQck2 in the MA phase. As described above, the data from the DSP engine 3 to the X, Y memories 6, 7 is written into the action instructions. The actions are completed in the four stages of the pipeline stages of I F, ID, Ε X, and Μ A. The write operation of the parallel items is because the independent buses X A B, XDB and TAB, YDB enable the CPU core 2 to access the X and Y memories 4, 6. FIG. 13 is a timing chart showing a data read operation from the memory to the DSP engine 3. Here MOVS, L @ AS, DS is an example of an operation instruction for reading data from the memory to the DS P engine 3 to explain its operation. This instruction is an instruction to transfer the data stored in the address designated by AS to the register designated by DS. Printed by the Central Bureau of Standards of the Ministry of Economic Affairs and Consumer Cooperatives The basic operation is the same as the data reading operation from X, Y memory 4 to 7 to DSP engine 3 shown in Figure 11. The difference between Fig. 11 and Fig. 13 is that Fig. 11 shows that the target memory is X, Υ memory 4 ~ 7, so X bus and Υ bus are used, and Fig. 13 shows that the target memory is microcomputer 1 connected to the support Space memory, so use bus I ΑΒ, ID Β. Synchronize with the rise time of Clock signal Clockl in the IX stage, obtain the register with the address that should be accessed, and output the register to the internal bus A 1 of CPU core 2. In this example, the register that stores the address to be accessed becomes the register designated by AS. The register designated by AS can be any register contained in the Reg of CPU core 2. The data output on the internal bus A 1 of the CPU core 2 is stored in the address buffer. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) (Please read the precautions on the back before filling this page) 46 -A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs 424192: ^ V. Description of the invention (44) The device 2 0 5 is synchronized with the rise time of the clock signal Clock 2 in the EX phase. On the one hand, the data output from the internal bus A 1 of the CPU core 2 is implemented by an arithmetic logic operation unit ALU 2 1 3 to perform an address operation. At this time, the arithmetic logic unit ALU 2 1 3 performs 0 addition operation. The calculation result is output to the internal bus C 1 of the CPU core 2. Output 'is on the internal bus C 1 of the CPU core 2. The operation result is stored in the pointer register (that is, the register designated by As) in synchronization with the rising of the clock signal Clock2 in the E and X phases. In the memory to be accessed, during the rise of the clock signal Clockl in the MA phase to the rise of the clock signal Clock2 *, the decoding of the address output on the address bus I AB with the rise time of the EX phase clock signal Clock2 is performed. Data access is performed during the rise of the clock signal CUck2 to the rise of the next clock signal Clockl. Therefore, the rising of the clock signal C [ock2 from the MA stage outputs the data to the data bus IDB. The data of the output data bus I D B is synchronized with the rise time of the clock signal Clockl in the WB / D SP phase and is taken into the DS engine 3 to supply the data to the internal bus D 1 of the DS engine 3. The rise time of the clock signal Clock 2 synchronized with the WB / D S P phase stores the data on the internal bus D 1 of the D S P engine 3 in the destination register to complete the operation. In this example, the destination register becomes the register designated by D s. The register that can be specified in Ds is any register in DSP Engine 3. As mentioned above, the data read operation instruction from the memory to the d S P engine 3 is completed by the pipeline stage of the five stages of I F, ID, EX, MA, W B / D SP. Figure 14 shows the reading of the data from the self-directed DSP engine 3 to the memory. The paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) (Please read the precautions on the back before filling this page)

47 Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 24 1 9 2? Can A7 _ B7_____ V. Description of the invention (time chart of the work. MOVS, LDS @ AS., Is from the DSP engine 3 to the memory An example of the data writing operation instruction is to explain the operation. This instruction is an instruction to transfer the data stored in the address specified by DS to the register specified by AS. The basic operation is shown in Figure 12 from DSP engine 3 to X, Y The data write operation of the memory is the same. The difference between Figure 12 and Figure 14 is that Figure 12 is because the object memory is X, and the memory uses the bus XΑΒ: KDB bus ΥΑΒ, YDB, and Figure 14 because of The target memory is the microcomputer 1 connected to the memory that supports the space, so the bus I ΑΒ, I DB is used. Synchronized with the rise time of the clock signal CUckl in the EX phase, a register that has the address of the transfer destination is stored, and the register is output to C The internal bus A 1 of PU core 2. In this example, the register storing the address to be accessed becomes the register designated by AS. The register designated by AS can be included in the register R eg of CPU core 2. register. The data of the internal bus A 1 of the CPU core 2 is stored in the address buffer 2 0 5 and synchronized with the rise time of the clock signal Clock 2 in the EX stage, and is output on the address bus j AB. On the one hand, the internal contents of the CPU core 2 are output. The data of bus A 1 is implemented by the arithmetic logic operator ALU2 1 3. At this time, the arithmetic logic operator ALU 2 1 3 performs 0 addition operation. The result of this operation is output to the internal bus C1 of CPU core 2. Input The calculation result on the internal bus C 1 of the CPU core 2 is stored in the pointer register (that is, the register designated by As) synchronized with the rise of the clock signal CUck2 in the EX phase. The rise time of the clock signal Clockl synchronized in the MA phase , (Please read the note on the back before filling in this page) .-α · Order_ This paper size is applicable to China National Standard (CNS) Α4 specification (210X297 mm) 48-Printed by the Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The paper size of the paper is applicable to the Chinese National Standard (CNS) M specification (210X297 mm) 424192, $ &quot; Λ7 ___; _ B7_ V. Description of the invention (46) The DSP engine 3 that will store the data to be transferred will be sent in The output of the memory is output to the internal bus D1 of the DSP engine 3 and stored in the memory data buffer (MDB2). The rise time of the clock signal Clock2 synchronized with the MA phase. The data stored in the memory data buffer (MDB I) is input From the data bus Γ DB. In this example, the registers inside the DSP engine 3 storing the data to be transferred become the registers designated as D s. The register that can be specified in D s is any register in DSP engine 3. The memory to be accessed is from the rise of the clock signal Clockl to the rise of the clock signal CUck2 in the MA phase, and is output to the address register of the address bus IA B with the rise time of the EX phase clock signal Clock2. Data is accessed during the period from the rise of Clock2 to the rise of Clock1, the next clock signal. Therefore, the rise time of the clock signal Clock2 in the MA stage is written into the memory by the data output from the DSP engine 3. As mentioned above, the data write precession instruction from the DS engine 3 to the external memory is completed with the pipeline stages of the four stages of I F, ID, EX, and MA. Second is PADD Sx, Sy, Dn P M U L.

Se, Sf, Dg, MOVX, W @ AX, Dx, MOVY, W @ Ay, and Dy are examples of DSP operation instructions, and their operation will be described with reference to FIG. 15. This instruction is implemented by transferring data from X — R0M4 and X — RAM6 and Y — R0M5 and Y — RAM7 to the DSP engine 3. The instructions in Figure 10 and Figure 1 are combined. Because the instruction is fetched, the operation of the instruction decoder is the same as that in Fig. 10, so detailed description of the part is omitted. 49----------- C% ------ 1T ------ (Please read the precautions on the back before filling out this page) Shellfish Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs The printed paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm) 4 2.4 ί 92 I, at * Β7 V. Description of the invention (Sentences are implemented from X, and the memory reads data from DSP Engine 3 When operating instructions, the address of the memory to be accessed forms the CPU core 2. Therefore, the rise time of the clock signal CUckl in phase Ε X is synchronized, the register holding the address to be accessed is accessed, and the address of the register is output to the CPU. The internal bus A 1 ~ A 2 of the core 2. In this example, the register storing the address to be accessed becomes the register designated by Ax and Ay. The register that can be designated at Aχ contains the register A 0 X, A 1 of the CPU core 2 X, and the registers that can be specified in Ay are included in the registers AOy and A1 y of CPU core 2. The data output to the internal bus A 1 ~ A .2 of CPU core 2 are stored in the memory address buffers (MABX, MABY) The rise time of the clock signal CU ck 2 synchronized to the Ex phase is output on the address bus XAB and YAB. On the one hand, it outputs the CPU core 2 The data of the internal buses A1 to A2 are implemented with ALU2 1 3 and PAU2 12. (At this time, ALU213 and PAU212 implement 0 addition operation. The result of this operation is output to the internal buses C 1 and C 2 of CPU core 2 and output. The calculation results of the internal buses CI and C 2 of the CPU core 2 are synchronized with the rising of the clock signal Clock2 in the EX phase and stored in the pointer register (ie, the registers P designated by Αχ and Ay are stored in the X and Y memory in the MA phase During the rise of the clock signal CUckl to the rise of the clock signal Clock2, the decoding of the address of the EX stage clock signal Clock 2 to the address bus XAB and YAB is implemented, and the clock signal Clock2 in the MA stage rises to the next Data access is performed during the rise of the clock signal Clockl. Therefore, the data is output to the data bus XDB from the rise of the clock signal ClQck2 in the MA phase, 50-——— II 丨 丨 (Please read the precautions on the back before filling this page ) Order '424192 ^ i B7 Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (48) 1 IYDB 0 Output data bus XD Β, Υ DB The data is synchronized with the clock signal C 1 0 C kl at the WB / DSP stage. The rise time is taken into 1 DSP engine 3. The data is supplied to the internal bus of DSP engine 3. D 1 »1 1 D 2 〇 Synchronized with WB / DS Please read 1 I \ rise time above the clock signal C 1 ck 2 in the P phase. The internal bus D 1 &gt; D 2 of the DSP engine 3 is stored and read back 1 i stored in the huge register (Di sti η at i 〇η R eg) to complete the action. Note 1 I means 1% in the example. The destination register is JCS ^ Registers specified in DX and DY 0 Assignable items 1 1 and 1 I Registers in DX are included in the DSP Engine X's register X 0 9 X 1 Writer 1 The register that can be specified in D y is DS in engine 3 0 f Y 1 .. Page 1 1 I 0 Parallel to the above data transfer, the DS P operation is also performed at the same time. 1 1 1 1 Clock signal synchronized to WB / DSP phase C 1 0 C k 1 Rise time I order 9 Access to register of storage source data &gt; Lead the output of register to DSP 1 1 Internal bus A of engine 3 A 1 A 2 Β 1 B 2 〇 In this example, the register that stores _ i 1 source data is ADD (addition) operation. It is said to be the register specified by SX and | S y, and M UL (multiplication) operation will become S e and scrap. The register 0 specified by S f can be specified in SXS y S e and S ί I 1 I Register 9 is any of the registers in DSP 3 Engine 0 Output DS 1 1 P Engine 3's internal bus A 1 B 1 The data is multiplied by M AC 3 0 4 1 1 and the result is output to the internal bus C 1 of the DSP engine 3. The output is output to the internal bus C 1 and C 2 of the DSP engine 3. The result is synchronized with WB / DS P clock signal C 1 〇ck I 3 rise 1 I time is stored in the register of g Device σ The register of g in this example is ADD 1 1 | It becomes D η S when it moves and M becomes it when it moves D 1 1 1 This paper size applies the Chinese National Standard (CNS) A4 specification (2丨 〇 × 297mm) — A7 B7 V. Description of the invention (49) Register. The registers that can be specified in Dn and Dg are arbitrary registers inside the DSP engine 3. As described above, the data stored in the DSP engine 3 register is added, multiplied, and the instructions for transferring data from X-R0M4 or X-RAM6 and γ-R0M5 or Y-RAM7 to DSP engine 3 are IF, 10 , And again, 3 ^ 8, double 6/03? Stage 5 pipeline stage to complete the action. Give:

Instl: PADDAO, MO, AO PMUL A 1, X0, A1 M0VX..W @ R4, X1, MOVY.W @ R6, Y0 I ns t 2: ADD R8, R9 I ns t 3: ADD R10, R11

Inst4 ADD »R1 2» R1 3 The 4 consecutive instructions printed by the Consumers' Consortium of the Central Bureau of Standards of the Ministry of Economic Affairs are the second example of the D S P operation instructions. Use Figure 16 to describe the operation in month B. The 4 instructions use the address buses I A B, X A B, and YAB simultaneously to achieve the same clock cycle. Examples of different actions. Since the command operations of lnstl to Inst4 are the same as those in Fig. 7 and Fig. 15, detailed descriptions of the parts are omitted. First, in the I F stage of instl, the instruction fetch of lnstl is implemented. In the 2D stage of lnstl, [nst2 becomes the I F stage. Stage, so the instruction fetch is implemented. When the address calculation for access to X, Y memory is implemented in the EX stage of lnstl, the instruction Inst2 is the IR stage, so the instruction decoding is implemented, and because of this paper size, China National Standard (CNS) A4 specification (210X297 mm) ) (Please read the precautions on the back before filling this page) 52-4 2 4 19 2 ': ^ Λ · Α7 __Β7 _ V. Description of the invention (5〇) lnst3 is the IF stage, so the instruction is taken out. In the MA phase of InsCl, the addresses calculated in the EX phase are output on the address bus XAB, and YAB (the actual output address time is from the rise time of the clock signal Clpck2 in the EX phase) is taken in from the data bus XD B and YD B data. At this time, Inst: 2 is the EX stage to perform the AD D operation to complete the operation of R 8 and R 9; lnst; 3 is the I D stage to implement the instruction decoding. Inst4 outputs the address of Inst4 to the address bus for the I F phase. The actual output time to the address bus IAB is from the rise time of the clock signal C.l Qck 2 before the half cycle of the I F phase of Inst 4. This time is the same as the time when the address is output to the address bus XAB, YAB in Instl (the second half of the EX phase and the first half of the MA phase). That is, the address bus X A B and Y A B are used for data transfer, and the address bus I AB is used for instruction fetch. The microcomputer 1 has internal address buses I A B, XAB, YAB and internal data buses IDB, XDB, YDB connected to the CPU core 2. Therefore, these three internal buses can be used to implement different storage, storage and fetch operations at the same clock cycle. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the notes on the back before filling this page). Instl then implemented DSP operations in the WB / DSP stage to complete the action, Inst2 has completed the action, and nst3 is the EX. Stage. The ADD operation of R 1 0 and R 1 1 is completed. Inst4 performs instruction decoding for the ID phase. The next cycle is only the EX phase of Inst4, and the ADD operations of R 1 2 and R 13 are performed to complete the operation. According to this embodiment, the following effects are obtained. The built-in memory is based on the Chinese paper standard (CNS> A4 size (210X297 gong)) -53-Printed on the paper size applied by the China National Standard (CNS) M size (210X) (Mmm)-/ 0 d 1 P 2. J sentence A7 ______B7__ 5. Description of the invention (51) The sum and operation of the DSP engine 3, 2 facets in the Y memory 5, 7 and 2 facets in the X memory 4, 6, The CPU core 2 can access the γ memory 5, 7 and the X memory 4, 6 in parallel with the internal buses Xαβ, χϋΒ and the internal buses YAB, YDB. Therefore, two data can be transferred from the built-in memories 4 to 7 at the same time. + DSP engine 3. Furthermore, because the internal buses XAB, XDB and internal buses YAB and YDB are connected to the external internal buses IAB and IDB, they are individualized, so CPU core 2 is parallel to X memory 4, 6 and Y memory 5, 7 can also be accessed by external storage. As mentioned above, because there are three kinds of address buses I AB, XAB, YAB and data assembly IDB, XDB, YDB connected to CPU core 2, they can be used. The bus implements different memory access operations at the same clock cycle. Corresponding programs or data can be stored in the external memory to realize high-speed operation. The RAM and ROM constitute the aforementioned X memories 4, 6 and Y memories 5, 7 and can be used in microcomputers. As mentioned above, because The built-in memory is two-faced to X-memory 4, 6 and Y-memory 5. 7-side each of the memories has ROM and RAM, so that RAM is data memory and ROM is program memory, so the data memory and program memory can be separated. The two data are transferred in parallel to the DSP engine 3. In addition, the parallel pipeline processing can effectively execute instruction fetching, data transfer, and calculation. Since the CPU core 2 has an modulo ground output section 2 0, the CPU core 2 can be Addresses for repeated operations, such as product and operation, are accelerated. 0 54----------.- 1¾ -------- ΪΤ ------ (Please read the precautions on the back first (Fill in this page again) 424192: ^ A7 B7 Printed by the Consumer Cooperatives of the Central Sample Bureau of the Ministry of Economic Affairs 5. Description of the invention (㈣ For example, the CPU instruction is the highest order of the instruction code. 1 0 &quot; range. The DSP instruction divides the highest 4 digits of the instruction code Matches the range of "1 1 1 1". The highest 6 digits of the instruction code are allocated to the '&quot; 111100 &lt; &gt; and' * 1] _ 1 1 0 1〃 range instructions, which are also DSP instructions It is a 16-bit long instruction code. The first 6 digits of the instruction code are · * 1 1 1 1 1 0 ', which is a 32-bit long instruction code. In the uppermost 6 digits of the instruction code, the range of '1 1 1 1 1 1 &quot; is not assigned, and its range is regarded as an unused area. As mentioned above, since the code allocation for the maximum 32 digits of the instruction is set as According to the above rules, a part of each instruction code such as the uppermost 6 bits is decoded *, that is, a decoder of a small logic scale can determine that the instruction width is a CPU instruction, a 16-bit DSP instruction, or 32-bit length. DSP instructions without having to decode all 32 bits all at once. As shown in Figure 17, after the instruction fetch time, the unprocessed instruction code data is set in the instruction register 25. At this time, the instruction to be implemented is either a 16-bit CPU instruction, a 16-bit DSP instruction or 3 Any command of the 2-bit DSP instruction must supply the upper 16 bits to the first decoding circuit 2 4 0. With reference to the configuration shown in 囵 17, etc., it is shown that the code data of the A block of the 32-bit DSP instruction is set in the upper field U I R of the instruction register 25. In addition, 16-bit DSP instructions having the same format as the A block are also set in the upper field U I R. Therefore, in any case, the CPU core 2 can also perform the required address calculation and data fetching. The necessary data bus --- ιρΐ (Please read the precautions on the back before filling this page) This paper size applies Chinese National Standard (CNS) A4 specification (210X297 mm) _ η 42A192.j. A7 __B7___ 5. Choice of invention description (53). In other words, the decoding circuits 2 4 0 and 2 4 1 required for fetching data for implementing 32-bit DSP instructions and fetching data for 16-bit DSP instructions are shared. This is also beneficial to the microcomputer 1 The logical scale of the microcomputer 1 is reduced. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page). The above has specifically described the inventor's invention according to the examples, but the invention is not limited as long as it does not exceed the scope of the gist , When various changes can be made. For example, CPU instructions, 16-bit DSP instructions, and 32-bit DSP instructions are not limited to using the uppermost bit of the instruction. The 6 bits can be increased or decreased with the number of instruction codes. The function of shifting the lower 16 bits of the instruction register to the upper position can be replaced by another function. In addition, the number of registers or types of arithmetic units included in the CPU core or the DSP engine is not limited to the above-mentioned embodiment, but may be appropriately changed. In addition, the number of memories is not limited to two and can be increased. The number of memories can be combined to increase the number of address buses and data buses connected to the memory. For example, a Z memory is newly set in addition to the X and Y memories. The address bus ZAB is connected between the CPU and the Z memory, and the data bus ZDB is connected between the DSP engine and the Z memory. According to this structure, not only the data from the X and Y memories are taken into the DSP engine during the product-sum operation, but also the data completed by the pre-instruction operation in the current implementation can be simultaneously written into the Z storage circuit via the Z bus. Because the instruction data is written into the memory with one instruction, the overall problem solving ability of the microcomputer can be improved. The present invention is most suitable for the use of microcomputers for controlling the compression and elongation processing or filtering processing of information for mobile communication equipment, servo control, image processing of printers, and the like. [Effects of the invention] The paper size is applicable to the national standard (CNS) A4 specification (210X297 mm) 56-A7 B7 V. Description of the invention (54) The representative effects of the inventions disclosed in this application are briefly explained as follows . That is, the built-in memory is integrated into the first memory and the second memory in consideration of the product and operation of the digital signal processor. The third bus and the second line can be accessed in parallel, so the central processing unit can The built-in memory transfers two data to the digital signal processing unit at the same time. In addition, the third bus and the second bus, and the first bus that interfaces with the outside, are independent of the central processing unit, and can be used for external storage access in parallel with-access of the second memory and the first memory. · As mentioned above, because there are three types of address buses and data buses connected to the central processing unit, the three types of internal buses can be used to implement different memory access operations at the same clock cycle, so even programs or data Existing in the external memory is also easy to cope with, and can realize high-speed arithmetic processing. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. »\} .I t ^ i II! _ I i I--. I (Please read the back (Please fill in this page for more details) &quot; Furthermore, since the built-in memory is two-sided, the first and second memories have ROM and RAM, and since RAM is used as data storage and ROM is used as program storage, Separate data memory and program memory, can transfer 2 data in parallel to the digital signal processing unit, and can effectively implement instruction fetching, data transfer and calculation by parallel pipeline processing. Therefore, when the digital signal processing unit is installed in one L S I together with the central processing unit, the high-speed digital signal processing can be realized. Due to the mixed instruction of C PU instruction and DSP instruction, a part of instruction code is decoded to identify the instruction. The DSP instruction or 16-bit long paper size is applicable to Chinese National Standard (CNS) A4 specification (2 丨 0X297 mm). ) 57 424 1 9 2: A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Instructions of the invention (55) DSP instructions, or 32-bit DSP instructions to allocate instruction codes. The decoder determines the type of instruction without having to decode all 32 bits all at once. Therefore, when the digital signal processing unit is installed in an L S I together with the central processing unit, the increase of its physical size can be suppressed as much as possible. Due to the instruction format of the DSP instruction, the first code area (the 9th to the 0th bit of the 16-bit DSP instruction shown in FIG. 18) with the first code area specified for the central processing unit is used for data transfer between the digital signal processing units. Format command, and a second code field with the same format as the first code field (a block of 32-bit DSP instructions shown in Figure 20 and Figure 21), and will be used in this second code The calculation processing of the transfer data specified in the field The 3rd code field specified for the digital signal processing unit. Figure 2 0, Figure 2 illustrates the 32-bit DSP instruction, the second format instruction of the R message group, and implements the second and second. As the device of each format, a decoding device having a common decoding logic for the first code area and the second code area can be used. At this point, the logic scale of the microcomputer can also be reduced. Brief description of the figures: Figure 1 · All block diagrams of a microcomputer related to an embodiment of the present invention 0. Figure 2: An example address map of a microcomputer. Figure 3: Block diagram of the cPU core showing the modulo address output section in detail. Figure 4: Block diagram of an example of a DSP engine. This paper size applies to Chinese national standards (CNS &gt; A4 size (210 × 297 mm) u 0〇 installed — (please read the precautions on the back before filling out this page) order-dish. 424192: ^ A7 _B7____ V. Description of the invention (56) Figure 5: An example of the instruction format and instruction code of a microcomputer. Figure 6: A block diagram showing the connection structure between the decoder of the CPU core and the decoder of the DSP engine. 囵 7: Inside the CPU core The implementation time chart of the ALU operation instruction 0 Figure 8: The implementation time chart of the instruction to read data from the memory into the CPU core. 'Figure 9: The implementation time chart of the instruction to write data to the memory from the CPU core. Figure 1 0 : An example timing diagram when implementing DSP instructions. Figure 11: Implementation time diagram of instructions that read data from the X and Y memories into the DSP engine. Figure 12: Implementation of instructions that write data from the DSP engine into the X and Y memories Timing chart .. Figure 13: Implementation time of instructions for reading data into the DSP engine from memory.-Printed by the Central Standards Bureau of the Ministry of Economic Affairs, Shellfish Consumer Cooperatives. Figure 14: Implementation of instructions for writing data into the memory from the DSP engine. Time chart Figure 15: DSP operation instructions Example implementation time chart. Figure 16: Example time chart when DSP operation instructions are continuously implemented. Figure 17: Block diagram showing another embodiment corresponding to Figure 6. Figure 18: Shows the built-in memory of the specified microcomputer and the DSP engine The 16-digit DS P instruction code of the data transfer between the 3 built-in registers is applicable to the National Standard A (CNS) A4 specification (210 X 297 mm). {Please read the precautions on the back before filling in this (Pages) 59-424192 A7 B7 Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. Figure 19: Instruction format of a 16-bit DSP instruction that specifies the data transfer between the external memory of the microcomputer and the built-in registers of the DSP engine 3. Figure 2 0: A diagram showing the instruction format of the code of the information group and its corresponding mnemonic when looking at the A information group of the 32-bit DSP instruction. Fig. 21: A diagram showing the instruction format of the 32-bit D S P instruction when it is looking at the B message group code and its corresponding mnemonic. [Symbols] 1 ......... Microcomputer 2 ......... CPU core (central processing unit) 20 ......... CPU control signal 2 4 ... ... decoder 2 4 0 ......... first decoding circuit. 2 4 1 ......... second decoding circuit 2 4 2 ... ... code conversion circuit 2 4 3 ......... CPU decoding circuit 2 4 4 ......... DSP decoding circuit 2 4 5 ... ... code conversion control signal 2 4 7 ......... CPU control signal 2 5 ......... instruction register 2 5 0, 2 5 1 ........ .Instruction receiving buffer 2 0 0 ......... Modular address output section (Please read the precautions on the back before filling this page)

Order-Weft · This paper size applies Chinese National Standard (CNS) A4 (210X 297 mm) -60-424 1 92 4 'A7 B7 V. Description of the invention (58) 2 0 6 &gt; 2 0 7 ... ... memory address buffer. 2 12 ......... address operator-2 13 ......... arithmetic logic operator 2 14 ... ... modulus start address register 2 15 ......... modulus end address register 2 1 6, 2 2 6 ......... modulus address register 3 ... DSP engine (Digital Signal Processing Unit) 3 4 ......... Decoder 3 0 2 ......... Arithmetic and Logic Operator 3 0 4 ......... Multiplication Memory 3 0 9, 3.10, 3 1 1 ......... storage data buffer 4 ... ... X — ROM (second memory) 5 ..... .... Y— ROM (first memory) 6 ......... X-RA Μ (second memory) 7 ......... Υ — RA Μ (first memory) 12 ......... external storage interface. (Read the precautions on the back before you fill out this page) η ί—Strike. Order printed by the Consumers 'Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. The paper size applies to the Chinese National Standard (€?) 8 4 specifications (210' / 297 mm ) _61

Claims (1)

4 24 A8 B8 C8 D8 6. Scope of patent application Whether the amendment is allowed to be printed by the Central Standards Bureau of the Ministry of Economy 〇Yuexiu. The original patent application No. 84113247 was amended in Chinese. The scope of patent application in the Republic of China was amended in October 1986. 1. A microcomputer characterized by: a central processing unit and the first choice of delivery address from the aforementioned central processing unit To the third address bus, and the first memory connected to the aforementioned first address bus and the second address bus, accessed by the address of the central processing unit, and connected to the aforementioned first address bus and the third address bus, from the central office A second memory for address access of the unit, and a first data bus connected to the aforementioned first and second memories and the central processing unit for transmitting data, and a second data bus connected to the aforementioned first memory for transmitting data, and a connection The third data bus that transfers data in the second memory, the external interface circuit connected to the first address bus and the second data bus, and the data bus connected to the first to third data buses to synchronize the operations of the central processing unit. The digital signal processing unit, and the DS P control signal transmission from the central processing unit to control the operation of the aforementioned digital signal processing unit The control signal line in the digital signal processing unit is included in the semiconductor integrated circuit of 1 Gini "2. The microcomputer as described in item 1 of the scope of patent application, wherein the first memory and the second memory are respectively composed of RAM and R 0M Cheng》 3 The microcomputer as described in item 2 of the scope of patent application, of which (please read the precautions on the back before filling this page) The paper bearing standards are applicable to Chinese national standards (CNS> A4 specification (210X297 mm)) Central Standards Bureau employee consumer cooperatives Yin Chang A8 B8 C8, D8 6. The scope of the patent application The central processing unit also has the function of outputting the address register to the aforementioned second or third address bus and repeating the update of the address register The end of the address is formed by the modular address output section of the address. 4. The microcomputer as described in any one of the claims 1 to 3, wherein the aforementioned digital signal processor includes a separate unit from the aforementioned first to third data buses. The first to third data buffer devices of the interface, and a plurality of register devices that can be connected to each data buffer device via an internal bus, and connected to the front The multiplier and arithmetic logic operator of the internal bus, and the decoding of the aforementioned DSP control signals to control one of the operations of the data buffer device described above, the arithmetic logic operator of the multiplier, and the register device. 5 · — A data processing device on a semiconductor wafer includes a central processing unit, and first to third address buses connected to the central processing unit, and first memories connected to the aforementioned first and second address buses, and connections. A second memory connected to the first and third address buses, a first data bus connected to the first and second memories, and the central processing unit, and a second data bus connected to the first memory, and connected A third data bus in the second memory, and an interface circuit connected to the first address bus and the first data bus, and a digital signal processing unit connected to the first to third data buses, and will control the digital The control signal for the operation of the signal processing unit is from the central processing unit Fuda to the control signal line of the digital signal processing unit. 6. A kind of single-chip microprocessor, which includes the CPU core, and synchronizes with the above CPU core, including d SP of the multiplier, and (CNS) (210x297 ^ -1 :) • p,, \ W c. J i equipment I i II! I order — IIII (Please read the precautions on the back before filling this page) -2-4 2 4 19 2 :, A8 B8 C8 D8 Printed by the Central Bureau of Standards, Ministry of Economic Affairs 1. The patent application Fan Yuan combines the first to third address buses of the above-mentioned CPU core, and the first to third data buses of the above-mentioned CPU core and the above-mentioned DSP, and the first and second places of the above-mentioned combination. The first memory of the address bus and the above-mentioned first and second data buses, and the second memory of the above-mentioned first and third address buses and the above-mentioned first and third data buses. 7. The single-chip microprocessor according to item 6 of the scope of patent application, wherein the above-mentioned CPU core includes: a plurality of general purpose registers, arithmetic and logic operation circuits, and a combination of the first address bus Row, a program counter for accommodating instruction addresses, and a command register combined with the above-mentioned 谄 1 data bus, which contains instructions provided by the first data bus, and which will be stored in the above-mentioned instruction register Instruction decoding, instruction decoder, etc. that generates control signals according to the decoding result. 8 · If the single-chip microprocessor according to item 7 of the patent application scope, wherein the above-mentioned CP_U core further includes: an address output circuit for generating an address to the above-mentioned second and third address buses . 9. The single-chip microprocessor according to item 8 of the scope of patent application, wherein the address output circuit includes: a first address buffer combined with the second address bus, and a third address buffer combined with the third address bus. The second address buffer of the address bus and the calculation of the address capital of the address capital to be supplied to the above-mentioned first to second digit buses are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) 03 , Vs (Please read the notes on the back before filling this page) * 3-ABCD 4 24 19 2 ': ^ VI. Application scope of patent application. (Please read the precautions on the back before filling out this page) 1 0 · If the single-chip microprocessor in the 6th scope of the patent application, the above-mentioned DSP has the above-mentioned instruction decoder to selectively accept the output control The signal is a decoder circuit for generating a control signal for controlling the operation of the multiplier. 1 1 · If the single-chip microprocessor of the 10th scope of the patent application, the above-mentioned DSP further includes: the first to third data buffer circuits that are respectively combined with the first to third data buses, And. The internal buses combined with the above multiplier and the first to third data buffer circuits, the arithmetic logic operation circuit combined with the above internal buses, and the temporary registers combined with the above-mentioned internal buses. 1 2 · If the single-chip microprocessor in the 6th scope of the patent application, * further includes: an external interface combined with the above-mentioned first address bus and the above-mentioned first data bus "1 3 ·-a kind of semiconductor The microprocessor on the substrate includes: Printed CP by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs, and a DSP that synchronizes with the CPU, combined with the first to second address buses of the cPU, and combined The first and second data buses of the above-mentioned CPU and DSP, and the first memory combining the above-mentioned first address bus and the above-mentioned first data bus, and the paper size of the bundle are applicable to the Chinese national standard (CNS says Grid (2 〖〇 &gt; &lt; 297mm) * ^ -4-ABCD 424192 ^ * VI. Patent application approval is combined with the 2nd record of the above-mentioned 2nd address bus and the 2nd data bus 1 4. The microprocessor according to item 13 of the scope of patent application, wherein the above-mentioned CPU includes: the first and the second for the parallel access to the first and the second memory, respectively. The address signals are generated for the addresses of the above 1 and 2 address buses, respectively. Generating means; The above-mentioned DSP includes: means for buffering the first to second data used by the data output from the first and second memories through the first and second data buses. 15. The microprocessor according to item 13 of the scope of patent application, wherein the above-mentioned CPU includes: an instruction decoder that stores instructions, and decodes the instructions that are stored in the instruction decoder, and generates a control signal according to the decoding result. A command decoder, and responding to the above control signals, respectively, the first and second address signals for parallel access of the first and second memories to the bits generated by the first and second address buses, respectively Means for generating addresses, etc .; The above-mentioned DSP includes: the first and second data output by the first and second memories, and the first and second data respectively obtained through the above-mentioned first and second data buses. To the second data buffering means, and the multiplier and arithmetic logic operation circuit for calculating the first to second data provided by the above first to second data buffering means "16 Microprocessor, where the paper Applicable to China National Standard (CNS) A4 specification (210X297 mm) &quot; II i III —— · Order n II line (Please read the precautions on the back before filling this page) Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 4 2 4] 9 p, as ^ BS J C8 D8 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs VI. Patent Application Fanyuan 1 The above DSP responds to the control signal 1 | output by the above instruction decoder for control The above-mentioned multiplier and the above-mentioned 1 I internal control signal decoder circuit for the arithmetic logic lifting circuit please call 1 1 first 1 1 7 * ~ -Single-chip processors include: Read 1 2 Data bus and back 1 1 Note 1 The first and second address buses and messages conveying address signals 1 Combine the above-mentioned first address bus with the above-mentioned first data bus The item 1 is again 1. The 1st memory and the copybook 1 are combined with the above. The 2nd address bus and the 2nd data bus 1 1 2nd memory &gt; and 1 1 | Response — the instruction The implementation of the CPU and 1 response to the 1st and 2nd address signals of the above 1st and 2 1 1 addressing buses respectively will be accessed by the above [1 The 1st and 2nd treasures output by the 1st and 2nd billionth body are taken in the 1st and 2nd data bus mentioned above and taken in 1 bus cycle (bus eye 1, 41 1 I le) The digital signal processing unit J 1 8 of the above-mentioned single-chip processor in item 17 of the patent scope, among which 1 i [1 The above-mentioned CPU contains the above-mentioned first and second address signals 1 No. 1 general-purpose register 9 1 1 1 9 If you ask for a single-chip processor in item 17 of the patent scope, it is 1 I in 1 1 1 The above digital signal processing unit »includes: • Internal bus and junction II combination The multiplier and arithmetic logic operation circuits and materials used in the above internal busbars 1 i This paper size applies to China National Standard (CNS) A4 specification (210X297 mm) -6-4 2 4 19 2 ^ A8 B8 C8 D8 Ministry of Economic Affairs Printed by the Consumer Standards Cooperative of the Central Bureau of Standards 6. Patent application scope register, and the first data buffer circuit combined between the above-mentioned first data bus and the above internal bus, and the above-mentioned second data bus A second data buffer circuit and the like from the internal bus. 20. The single-chip processor according to item 17 of the scope of patent application, wherein the CPU includes an instruction decoder that decodes instructions to generate a control signal: the digital signal processing unit accepts decoding of the instructions in the CPU The decoder control circuit provides an internal control signal decoder circuit that controls the operation of the internal circuit of the digital signal processing unit. 0 2 1. For a single-chip processor with the scope of patent application No. 20, 1 of the above digital The signal processing unit further includes: an internal bus, a multiplier and an arithmetic logic operation circuit combined with the internal bus, a data register combined with the internal bus, and a first data bus combined with the internal bus. The first data buffer circuit between the bus and the internal bus, and the second data buffer circuit combined between the second data bus and the internal bus; etc .; the multiplier and arithmetic logic operation circuit, the above Data register. The first data buffer circuit and the second data buffer circuit are as described above. Internal control signal to control the operation thereof. The paper size is in accordance with the Chinese National Standard (CNS) A4 specification (210X297 mm) (please read the precautions on the back before filling this page) -9 〇-7-424 19 2 A8 B8 C8 · D8 VI. Patent Application Scope 2 2. If the single-chip processor of item 17 in the scope of patent application, @, the above-mentioned CPU includes: a plurality of temporary registers that accommodate the above-mentioned first and second addresses, and an arithmetic and logic operation circuit, and an instruction that accommodates the above-mentioned instructions An instruction register, and an instruction decoder that decodes the instructions stored in the instruction register and generates a control signal according to the decoding @ 果, and is used for generating the first and second bits of the above-mentioned first and second bit buses The address output circuit for the second address, etc .; the operations of the above-mentioned plural registers, the above-mentioned arithmetic logic operation circuit, and the above-mentioned address output circuit are controlled by the above-mentioned control signal "2 3. Such as the scope of patent application The single-chip processor of item 22, wherein the above-mentioned digital signal processing unit further includes: an internal bus, and a multiplier and arithmetic logic operation combined with the internal bus. Circuit, and a data register combined with the above internal bus, and a first data buffer circuit combined between the above first data bus and the above internal bus, and combined with the above second data bus and the above internal The second data buffer circuit between the buses, etc .; the multiplier and arithmetic logic operation circuit, the data register, the first data buffer circuit, and the second data buffer circuit are generated by the internal control signal. Controlling its actions. This paper is fully applicable to China National Standards (CNS) A4 specifications (210X297 mm) 8 8 (Please read the precautions on the back before filling out this page)-Order &Print; Printed by the Central Consumers Bureau of the Ministry of Economic Affairs Consumer Cooperatives 424 Ί 92: A8 B8 C8 D8 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 6. Patent application scope 2 4. For the microcomputer in the first patent application scope, the above-mentioned central processing unit (CPU) includes: General purpose register, arithmetic logic operation circuit, and program counter combined with the above-mentioned first address bus for accommodating instruction addresses, and combined with the above-mentioned first data bus, containing the above-mentioned first data A command register for the instructions provided by the bus, and a command decoder that decodes the instructions contained in the above. Command register, generates a control signal according to the decoding result, and is used to generate the second and third addresses. The address output circuit for the bus to generate an address; the operations of the above-mentioned plural general purpose registers, the above-mentioned arithmetic logic operation circuit, and the above-mentioned address output circuit are borrowed 2 5 controlled by the above control signal * If the microcomputer of item 24 of the scope of patent application, the above-mentioned digital signal processing unit includes: receiving the above-mentioned supplied by the above-mentioned instruction decoder in the central processing unit (CPU) DSP control signals, decoder circuits that generate internal control signals, internal buses, multipliers and arithmetic logic operation circuits combined with the internal buses, and data registers that are combined with the internal buses, and ( Please read the note on the back ^^-item before filling out this page). Binding and ordering ^-This paper size is free to use Chinese National Standard {CNS) A4 specification (210X297 mm) -9-Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printed, 2 4 9 2, Bismuth 1 C8, D8 6. The patent application park combines the first data buffer circuit between the above-mentioned first data bus and the above internal bus, and the above-mentioned second data bus The second data buffer circuit between the bank and the internal bus: the multiplier and arithmetic logic circuit, the data register, and the first data buffer. Circuit and the second data buffer circuit, said internal control signal line by controlling the operation thereof. 26. If applying. The data processing device of the fifth item of the patent scope, wherein the above-mentioned central processing unit (CPU) includes: a plurality of general purpose registers, arithmetic and logic operation circuits, and a combination of the above table Address bus, a program counter for accommodating the address of the instruction, and a command register combined with the above-mentioned first data bus to accommodate the instructions provided by the above-mentioned first data bus, and to be temporarily stored in the above-mentioned instruction Instruction decoding of the decoder, an instruction decoder for generating a control signal according to the decoding result, and an address output circuit for generating addresses for the above-mentioned second and third address buses: the above-mentioned plural general-purpose temporary registers 2. The operations of the above-mentioned arithmetic logic operation circuit and the above-mentioned address output circuit are controlled by the above-mentioned control signal. For example, if the data processing device of the 26th item of the patent application is applied, the paper size is applicable to the Chinese national standard ( CNS) A4 specification (210X297mm) ~ -10-(Please read the precautions on the back before filling this page) Order 424192-- A8 * B8 C8 'D8 VI. Apply for a patent The above-mentioned digital signal processing unit includes: a decoder circuit that receives the control signal supplied by the instruction decoder in the central processing unit (CPU) through the control signal line, generates an internal control signal, and internal The bus, and the multiplier and arithmetic logic operation circuit combined with the above-mentioned internal bus, and the data register combined with the above-mentioned one internal bus, and the combination of the above-mentioned first data-bus and the above-mentioned internal bus The first data buffer circuit between the two, and the second data buffer circuit combined between the second data bus and the internal bus, etc .: the multiplier and arithmetic logic operation circuit, the data register, the first The 1 data buffer circuit and the above 2 data buffer circuit are controlled by the above-mentioned internal control signals ^ (Please read the precautions on the back before filling this page) The paper size printed by the cooperative applies the Chinese National Standard (CNS) A4 (210X297)