541496 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（1 ) 〔技術領域〕 本發明係關於微電腦及電子機器。 〔背景技術〕 在可以處理3 2位元之資料之R I S C方式之微電腦 中，使用規定位元寬之固定長命令。其理由在於使用固定 長度命令時，與使用可變長度命令之情形相比，可以縮短 命令之譯碼所需要之時間，又，可以使微電腦之電路規模 小0 然而，關於3 2位元之微電腦，被記憶在記憶裝置之 處理資料並不經常限定爲3 2位元。全部之資料皆以3 2 位元記述時，資料產生冗長部份之命令變多，記憶體之使 用效率會變差。 因此，由記憶裝置讀出例如1字節（byte )形式之處 理資料，以3 2位元之C P U進行處理之情形，有必要將 1字節資料擴充爲3 2位元資料。 此種之資料擴充處理在以通常之資料爲對象之情形， 不會有太大問題。但是，例如將顯示計算用之數字之1字 節資料視爲減法用之含符號之資料讀出，在將此擴充爲含 符號之3 2位元資料之情形，需要使用高單價之圓筒倒相 器（barrel shifter )等，第1 :有必要實行將1字節資料 向左移位2 4位元之命令，接著，實行將上述1字節資料 向右方向2 4位元算術移位之命令， 在此種之以往技術中，於含符號之資料之擴充處理時 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） -4- 541496 A7 _____ B7 五、發明説明P ) ，有必要實行2個之命令之故，於處理上需要時間，同時 ，使用高單價之圓筒倒相器之故，有硬體變高單價之問題 〇 本發明係鑑於此種課題而成者，其目的在於提供：可 以簡單而且高速進行含符號之處理資料之擴充之微電腦及 使用其之電子機器。 〔發明之公開揭露〕 爲了達成上述目的，本發明之微電腦之特徵爲包含： 具備對於處理資料，配合該資料大小進行零擴充以及 符號擴充之至少其中一方之擴充處理，解讀傳送於所與之 寄存器用之載入命令，輸出對應上述處理資料之大小以及 上述擴充處理之形式之控制信號之命令解讀手段之資訊處 理手段，以及 被連接於上述資訊處理手段，對於上述處理資料，遵 循上述控制信號，進行至規定之處理位元數止之零擴充以 及符號擴充之至少其中一方之擴充處理，向上述資訊處理 手段輸出之擴充手段。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 又，本發明之微電腦係一種：將被記憶於處理資料記 憶手段之處理資料傳送於所與之寄存器用之載入命令，即 包含界定傳送處理資料以及其大小用之資料，以及將界定 處理資料零擴充、符號擴充用之擴充形式之資料之上述載 入命令之目的碼解釋實行之微電腦’其特徵爲包含· 具備解讀上述載入命令之目的碼，輸出資料讀出位址 本紙張尺度適用中國國家標準（CNS ) /\4規^ ( 210X 297公釐1 -5- 541496 經濟部中央標準局員工消費合作社印製 A7 _____ B7五、發明説明P ) 信號，同時，輸出對應上述處理資料之大小以及擴充形式 之擴充控制信號之命令解讀手段之資訊處理手段，以及 被連接於上述資訊處理手段，依據上述資料讀出位址 信號，對於由上述處理資料記憶手段被讀出之處理資料， 遵循上述控制信號，進行至規定之處理位元數止之零擴充 以及符號擴充之至少其中一方之擴充處理，向上述資訊處 理手段輸出之擴充手段。 於此處，上述之微電腦最好爲如下之構成： 包含：記憶包含上述目的碼之各種之目的碼之第1記 憶手段，以及 上述處理資料對應於資料讀出位址而被記憶之作爲上 述處理資料記憶手段之第2記憶手段，以及被設於上述資 訊處理手段，控制由上述第1記憶手段之目的碼之讀出之 命令讀出手段， 上述第1以及第2記憶手段與上述資訊處理手段係經 由匯流排線而被連接， 上述命令解讀手段係： 解讀由上述第1記憶手段被讀出之目的碼，輸出上述 第2記憶手段之資料讀出位址信號之同時，向上述擴充手 段輸出上述擴充控制信號， 上述擴充手段係z 依據上述資料讀出位址信號，將由上述第2記憶手段 被讀出之處理資料遵循上述擴充控制信號，進行至規定之 處理位元數止之零擴充以及符號擴充之至少其中一方之擴 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -6 - 541496 A7 經濟部中央標準局員工消費合作社印製 五、發明説明f ) 充處理以輸出之。 又，本發明之微電腦係一種將被記憶於資訊處理手段 內部之第1寄存器之處理資料傳送於資訊處理手段內部之 第2寄存器用之載入命令，即包含界定傳送處理資料以及 其大小用之資料，以及將界定處理資料零擴充、符號擴充 用之擴充形式之資料之上述載入命令之目的碼解釋實行之 微電腦，其特徵爲： 包含：具備解讀上述載入命令之目的碼，由上述第i 寄存器讀出處理資料以輸出，同時，輸出對應上述資料之 大小以及擴充形式之擴充控制信號之命令解讀手段之資訊 處理手段，以及 被連接於上述資訊處理手段，對於由上述第1寄存器 被讀出之處理資料，遵循上述控制信號，進行至規定之處 理位元數止之零擴充以及符號擴充之至少其中一方之擴充 處理，向上述資訊處理手段輸出之擴充手段， 上述資訊處理手段係將被擴充處理後之上述資料寫入 第2寄存器者。 於此處，上述微電腦最好爲如下之構成： 包含：記憶包含上述目的碼之各種目的碼之第1記憶 手段，以及 被設於上述資訊處理手段，控制由上述第1記憶手段 之目的碼之讀出之命令讀出手段， 上述第1記憶手段與上述資訊處理手段經由匯流排線 而被連接。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家榡準（CNS ) A4規格（210X297公釐） -7- 541496 A7 B7 五、發明説明p ) 依據本發明之微電腦，讀出處理資料，使用將此處理 資料符號或零擴充，載入所與之寄存器用之專用之載入命 令，以及實行上述擴充處理之專用之擴充手段’可以高速 進行處理資料之零擴充、符號擴充。 而且在此擴充處理中，不需要如以往般地使用高單價 而且大型之圓筒倒相器之故，可以使電路整體之構成簡單 而且便宜。 特別是依據本發明，將處理資料符號或零擴充用之專 用之命令之解讀以設於資訊處理手段內部之命令解讀手段 進行，依據此解讀結果之處理資料之擴充係採用：使用不 同於上述資訊處理手段另外形成之擴充手段，在1命令循 環內進行之構成。因此，資訊處理手段之內部例如在微電 腦之C P U內部沒有必要設置上述擴充手段之故，可以使 c P U本身小型而且便宜。而且，經由使上述處理在1命 令循環實行，恰如使擴充手段設於資訊處理手段內之情形 爲同樣之處理速度，可以高速進行上述處理資料之讀出與 擴充。 又，本發明之微電腦係一種： 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 將被記憶於處理資料記憶手段之處理資料傳送於所與 之寄存器用之第1載入命令，即包含界定傳送處理資料以 及其大小用之資料，以及將界定處理資料零擴充、符號擴 充用之擴充形式之資料之上述第1載入命令之第1目的碼 解釋實行之微電腦，同時， 將被記憶於資訊處理手段內部之第1寄存器之處理資 本紙張尺度適用中國國家標準（CNS ) A4規格（210x297公釐） -8 - 541496 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明p ) 料傳送於資訊處理手段內部之第2寄存器用之第2載入命 令，即包含界定傳送處理資料以及其大小用之資料’以及 將界定處理資料零擴充、符號擴充用之擴充形式之資料之 上述第2載入命令之第2目的碼解釋實行之微電腦， 其特徵爲= 包含：記憶包含上述各目的碼之各種目的碼之第1記 憶手段，以及 上述處理資料被對應於資料讀出位址而記憶，作爲上 述處理資料記憶手段之第2記憶手段，以及 與上述第1以及第2記憶手段經由匯流排線被連接之 資訊處理手段， 與上述資訊處理手段經由匯流排線被連接，進行對於 上述處理資料之擴充處理，向上述資訊處理手段輸出之擴 充手段， 上述資訊處理手段包含： 控制由上述第1記憶手段之目的碼之讀出之命令讀出 手段，以及 解讀被讀出之上述第1、第2之目的碼之命令解讀手 段，以及 作爲上述第1以及第2寄存器之機能之複數之寄存器 上述命令解讀手段係： 解讀上述第1之載入命令之第1目的碼，輸出上述第 2記憶手段之資料讀出位置信號，同時，輸出對應上述處 (請先閱讀背面之注意事項再填寫本頁) ··衣· 訂 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） -9- 541496 A7 B7 五、發明説明(7 ) 理資料之大小以及擴充形式之擴充控制信號， 解讀上述第2之載入命令之第2目的碼，讀出由上述 第1之寄存器來之處理資料，同時’輸出對應上述處理資 料之大小以及擴充形式之擴充控制信號’ 上述擴充手段係： 依據上述資料讀出位址信號，對於由第2記憶手段被 讀出之處理資料，遵循上述擴充控制信號’進行至規定之 處理位元數止之零擴充及符號擴充之至少其中一方之擴充 處理，向上述資訊處理手段輸出之同時， 對於由上述第1寄存器被讀出之處理資料，遵循上述 擴充控制信號，進行至規定之處理位元數止之零擴充及符 號擴充之至少其中一方之擴充處理’向上述資訊處理手段 輸出， 上述資訊處理手段係： 將遵循上述第2載入命令被擴充處理之上述資料寫入 第2寄存器者。 經濟部中央標準局員工消費合作社印製 (讀先閱讀背面之注意事項再填寫本頁) 經由如此，在實行將被記憶於處理資料記憶手段之處 理資料做零擴充、符號擴充’傳送於所與之寄存器用之第 1載入命令，以及將被記憶於資訊處理手段內部之弟1寄 存器之處理資料做零擴充、符號擴充’傳送於資訊處理手 段內部之第2寄存器用之第2載入命令之際’可以使用被 設於資訊處理手段之外部之共通之擴充手段以進行上述處 理資料之擴充處理。 因此，資訊處理手段例如微電腦之c p u本身可以小 本紙張又度適用中國國家標準（CNS)A4規格（210X297公釐） -10- 541496 A7 B7 五、發明説明p ) 型而且便宜，而且，可以使C P U內部之處理資料以及外 部之處理資料之擴充配合載入命令高速地進行。 本發明之上述擴充手段最好爲如下之構成： 包含：於每一上述資料之大小，將被讀出之處理資料 零擴充之零擴充手段以及符號擴充之符號擴充手段，以及 遵循上述擴充控制信號，選擇輸出上述各擴充手段之 輸出之選擇手段。 依據本發明，於每一資料之大小設有將處理資料零擴 充之零擴充手段以及符號擴充之符號擴充手段。例如，於 處理3 2位元之資料之資訊處理裝置中，處理資料之大小 有8位元、1 6位元之2種之情形，準備有8位元用之零 擴充手段以及符號擴充手段，以及1 6位元用之零擴充手 段以及符號擴充手段。 而且，處理資料係使用遵循上述擴充控制信號而被選 擇之位元大小之擴充手段，做零擴充或符號擴充而被輸出 〇 經由如此，可以更簡單之電路構成，進行處理資料之 擴充處理。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 於本發明中，上述符號擴充手段最好包含：將處理資 料原原本本地輸出之手段，以及將處理資料之上位之擴充 位元資料全部作爲含符號之信號以輸出之手段以構成之。 又’在微電腦中，設有進行通常匯流排之控制之匯流 排控制單元。因此，上述擴充手段可以作爲上述匯流排控 制單元之一部份之電路以構成之，於提高電路整體之集成 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公變） -11 - 541496 kl B7__________ 五、發明説明P ) 度上較爲理想。 又，本發明之微電腦最好以R 1 S C方式形成者。 R I s c方式之微電腦係以使硬體小型化’謀求高速 化爲目的而被設計者。因此，有很多泛用寄存器’在將命 令組集中於泛用性高者下，可以謀求命令數之削減。 本發明之微電腦最好係：解讀固定長度之命令’依據 該命令進行實行處理以構成之。 使用固定長度之命令與使用可變長度命令相比’可以 縮短命令之譯碼所需要時間，可以使微電腦之電路規模小 。採用固定長度命令之情形，可以防止命令出現冗長部份 ，爲了可以有效率使用記憶體，各命令所必要之位元數最 好偏差少，盡可能短。 本發明之電子機器最好包含上述本發明之微電腦以形 成之。 依據本發明，內藏處理速度快便宜之微電腦之故，可 以提供便宜高機能之電子機器。 〔圖面之簡單說明〕 經濟部中央標準局員工消費合作社印製 衣-- (請先閱讀背面之注意事項再填寫本頁) 圖1係說明本發明被適用之微電腦之合適之實施形態 之機能方塊圖。 圖2 A〜圖2 F爲被內藏於上述微電腦之擴充電路之 具體構成之說明圖。 圖3 A爲選擇複數之擴充電路之輸出用之多路轉換器 之說明圖，圖3 B爲其他實施形態之機能方塊圖。 ϋ張尺度適用中國國家標準（CNS ) A4規枱（210X297公釐） ~~ -12- 541496 A7 B7 五、發明説明（10 ) 圖4 A〜圖4 E爲將載入命令以助記（mnemonic )开多 式表示之說明圖。 圖5爲將8位元處理資料做符號擴充、零擴充之情形 之說明圖。 圖6爲將8位元處理資料做符號擴充、零擴充之情形 之說明圖。 圖7爲本實施形態之微電腦之具體的機能方塊圖。 圖8爲被使用於本實施之其他之實施形態之載入命令 之說明圖。 主要元件對照表 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 1 〇 微 電 腦 1 2 外 部 R 〇 Μ 1 4 外 部 R A Μ 2 0 C P U 2 2 內 部 R 〇 Μ 2 4 內 部 R A Μ 2 6 匯 流 排 控 制單元 3 0、 8 4 命令位址 匯 流 排 3 2、 8 6 命 令資料 匯 流 排 3 4、 8 0 資 料位址 匯 流 排 3 6 ; a > 3 6 b 、8 2 a 82b 資料匯流排 4 0 命令 解 讀 部 4 2 命令 5買 出 部 本紙張尺_度適用中國國家標準（〇呢）六4規格（210'乂297公釐） -13- 541496 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（11 ) 4 4 寄 存 器 群 5 〇 擴 充 部 5 〇 — 1 、 5 〇 — 3 零 擴充 電 路 5 〇 — 2 5 0 — 4 符 號擴 充 電路 5 〇 — 5 非 擴 充 電 路 6 〇 > 6 2 多 路 轉 換 器 8 〇 〇 中 斷 控制 器 8 1 0 串 列 界 面 8 3 0 A / D 轉 換 器 8 4 〇 D / A 轉 換 器 8 5 0 輸 入 璋 8 6 0 輸 出 璋 8 7 〇 I / 〇 ί阜 9 1 〇 筒 頻 發 送 電 路 9 2 〇 低 its 頻 發 送 電 路 9 3 〇 重 置 電 路 9 4 0 分 its 頻 電 路 9 5 〇 Λ 9 6 0 可 程 序 計時 器 9 8 〇 智 慧 型 D Μ A 9 9 〇 筒 速 D Μ A [ 實 施 發 明 之 最 好 之 形 態 ] 接著，佐以圖面詳細說明本發明之合適之實施形態。 (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -14 - 541496 ΑΊ Β7 五、發明説明（12 ) 第1實施形態 圖1顯示本實施形態之電子電路。此電子電路係包含 微電腦10，以及外部ROM 12及RAM 14而被 構成之，這些係經由外部位址匯流排1 6及外部資料匯流 排1 8而被連接。 上述微電腦1 0係包含：各種之命令作爲目的碼而被 記憶之內部R〇Μ 2 2，及各種處理資料被記憶之內部 RAM 2 4，及匯流排控制器單元2 6以構成之。 上述微電腦1 0係包含：3 2位元之命令位址匯流排 3 0，及1 6位元之命令資料匯流排3 2，及3 2位元之 資料位址匯流排3 4，及3 2位元之2組之寫入、讀出用 之資料匯流排3 6 a、3 6 b，這些各匯流排3 0〜3 6 連接C P U 2 0與匯流排控制單元2 6之間。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 再者，上述微電腦1 0包含：3 2位元之命令位址匯 流排8 4，及1 6位元之命令資料匯流排8 6，及3 2位 元之資料位址匯流排8 0，及3 2位元之2組之寫入、讀 出用之資料匯流排8 2 a、8 2 b，這些各匯流排8 0〜 86連接ROM 22，RAM 24與匯流排控制單元 2 6之間。541496 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (1) [Technical Field] The present invention relates to microcomputers and electronic devices. [Background Technology] In the R I S C microcomputer that can process 32-bit data, a fixed-length command with a specified bit width is used. The reason is that when using a fixed-length command, compared with the case of using a variable-length command, the time required to decode the command can be shortened, and the circuit size of the microcomputer can be made smaller. However, the 32-bit microcomputer The processing data stored in the memory device is not always limited to 32 bits. When all the data are described in 32 bits, the command to generate a lengthy part of the data will increase, and the efficiency of memory usage will deteriorate. Therefore, when a memory device reads out processing data in the form of 1 byte and processes it with 32-bit CPU, it is necessary to expand 1-byte data to 32-bit data. This kind of data expansion processing will not cause much problems in the case of ordinary data. However, for example, if the 1-byte data showing the numbers used for calculation is read as the data with symbols used for subtraction, when this is expanded to the 32-bit data with symbols, a high unit price cylinder is required. Phase shifter (barrel shifter), etc., No. 1: It is necessary to execute a command of shifting 1 byte of data to the left by 24 bits, and then to perform an arithmetic shift of the above 1 byte of data to the right by 24 bits. Order, in this kind of conventional technology, when expanding the information with symbols (please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm) -4- 496496 A7 _____ B7 V. Description of the invention P), it is necessary to implement two orders, it takes time to process, and at the same time, because of the use of a high unit price cylindrical inverter, the hardware becomes high unit price Problem The present invention has been made in view of such problems, and an object thereof is to provide a microcomputer and an electronic device using the microcomputer that can easily and rapidly expand data with symbols. [Public disclosure of the invention] In order to achieve the above-mentioned object, the microcomputer of the present invention is characterized by including: an expansion process for processing data, at least one of zero expansion and sign expansion in accordance with the size of the data, and interpreting and transmitting to the register with which The load command used is an information processing means that outputs a command interpretation means corresponding to the size of the processing data and a control signal in the form of the extended processing, and is connected to the information processing means. For the processing data, follow the control signal. Expansion means which performs at least one of zero expansion to a predetermined number of processing bits and sign expansion, and outputs the information processing means. Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). The microcomputer of the present invention is a method for transferring the processing data stored in the processing data storage means to the register. The loading command includes a microcomputer that defines and transmits the processing data and its size data, and the purpose code of the loading command that defines the zero-extension and symbol-expansion expansion data of the processing data. The characteristics are: Contains the purpose code for reading the above loading order, and the address for reading out the output data. The paper size is applicable to the Chinese National Standard (CNS) / \ 4 regulations ^ (210X 297 mm 1 -5- 541496 Staff Consumption of the Central Standards Bureau of the Ministry of Economic Affairs The cooperative prints A7 _____ B7 V. Description of the invention P) signal, at the same time, it outputs the information processing means of the command interpretation means corresponding to the size of the processing data and the expanded control signal in the expanded form, and is connected to the information processing means according to the above Data readout address signal, for processing data read out by the above-mentioned processing data storage means , Follow the above control signals, the processing proceeds to a predetermined number of bits of the zero extension stop and wherein at least one of the expansion process of the expansion symbol, the above-described expansion processing means to the output means of the information. Here, the above microcomputer preferably has the following structure: Containing: a first memory means for storing various purpose codes including the above-mentioned purpose code, and the above-mentioned processing data is stored as the above-mentioned processing corresponding to the data read-out address The second memory means of the data memory means, and the command read means provided in the information processing means to control the reading of the object code of the first memory means, the first and second memory means, and the information processing means It is connected via a bus line. The command interpretation means is: to decode the destination code read by the first memory means, output the data read address signal of the second memory means, and output to the expansion means. The above-mentioned expansion control signal, the above-mentioned expansion means is based on the above-mentioned data read address signal, and the processed data read by the above-mentioned second memory means follows the above-mentioned expansion control signal to perform zero expansion up to a predetermined number of processing bits and Expansion of at least one of the symbols (please read the precautions on the back before filling this page) Applicable Chinese National Standard (CNS) A4 size (210X 297 mm) -6 - 541496 A7 Ministry of Economic Affairs Bureau of Standards employees consumer cooperatives printed V. invention is described in f) charge to the output of the processing. In addition, the microcomputer of the present invention is a load command for transmitting the processing data stored in the first register in the information processing means to the second register in the information processing means, which includes a method for defining the transmission processing data and its size. Data, and a microcomputer that interprets and implements the purpose code of the above-mentioned loading order that defines data in zero-extension and symbol-extension forms of expansion is characterized by: Containing: The purpose code for interpreting the above-mentioned loading order is provided by the above-mentioned The i register reads out the processed data for output, and at the same time, outputs the information processing means corresponding to the size of the data and the command interpretation means of the extended control signal in the extended form, and is connected to the information processing means, and is read by the first register. The output processing data follows the above-mentioned control signal, and performs expansion processing to at least one of the predetermined number of processing bits and zero expansion and sign expansion, and the expansion means output to the above information processing means. The above information processing means will be The above information after the expansion process is written in the second mail Is who. Here, the above microcomputer preferably has the following structure: Containing: a first memory means for storing various purpose codes including the above-mentioned purpose code, and a first memory means provided in the information processing means for controlling the purpose codes of the first memory means The command reading means for reading, the first memory means and the information processing means are connected via a bus line. (Please read the precautions on the back before filling this page) The paper size is applicable to China National Standard (CNS) A4 (210X297 mm) -7- 541496 A7 B7 V. Description of the invention p) Microcomputer according to the present invention, read To process data, use the symbol or zero expansion of the processed data, a dedicated load command for loading the associated register, and a special expansion method to perform the above-mentioned expansion processing. 'Zero expansion and symbol expansion of processed data can be performed at high speed. . Furthermore, in this expansion process, it is not necessary to use a high-priced and large-sized cylindrical inverter as in the past, so that the overall configuration of the circuit can be simplified and inexpensive. In particular, according to the present invention, the interpretation of a dedicated command for processing data symbols or zero expansion is performed by a command interpretation means provided inside the information processing means, and the expansion of the processing data based on the interpretation result is adopted by using: The expansion means formed by the processing means is configured in one command cycle. Therefore, it is not necessary to provide the above-mentioned expansion means inside the information processing means, for example, inside the CPU of the microcomputer, so that the CPU itself can be made small and cheap. Furthermore, by executing the above-mentioned processing in a command cycle, it is possible to read and expand the processing data at a high speed just as if the expansion means is set in the information processing means at the same processing speed. In addition, the microcomputer of the present invention is a type printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling out this page) and transfer the processing data stored in the processing data storage means to the register with which The first loading command of the first loading command, which includes the data for defining the transmission processing data and its size, and the extended form of data defining the zero expansion and symbol expansion of the processing data, is explained and implemented. At the same time, the processing capital paper size of the first register that will be stored in the information processing means applies the Chinese National Standard (CNS) A4 specification (210x297 mm) -8-541496 A7 B7 Staff Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs Printing 5. Description of the invention p) The second loading command for the second register in the information processing means is transmitted, which includes the definition of the transmission processing data and its size data, and the extension of the definition processing data to zero and sign. The microcomputer used in the extended form of the data to explain the second object code of the second loading order above is implemented, Features are: Including: the first memory means for memorizing various purpose codes including the above-mentioned each object code, and the above-mentioned processed data is memorized corresponding to the data read address, as the second memorization means for the above-mentioned memorized data processing means, and The information processing means connected to the first and second memory means via a bus line, and the information processing means connected to the information processing means via a bus line to perform an expansion process on the processing data and an expansion means output to the information processing means, The above information processing means includes: a command reading means for controlling the reading of the object code by the first memory means, and a command reading means for reading the read first and second object codes, and as the first And the function of plural registers of the second register. The above-mentioned command interpretation means is: to decode the first destination code of the first load command, output the data read position signal of the second memory means, and output the corresponding corresponding position ( (Please read the precautions on the back before filling out this page) Home standard (CNS) A4 specification (210X297 mm) -9- 541496 A7 B7 V. Description of the invention (7) The size of the physical data and the extended control signal of the expanded form, interpret the second object code of the second loading command above , Read out the processing data from the first register, and 'output an expansion control signal corresponding to the size of the processing data and the expansion form'. The above-mentioned expansion means is to read out the address signal according to the data, and for the second memory The processing data read out by means is extended to at least one of zero expansion and sign expansion up to a predetermined number of processing bits in accordance with the above-mentioned expansion control signal, and is output to the above-mentioned information processing means. The processing data read from the 1 register follows the above-mentioned expansion control signal, and performs expansion processing to at least one of zero expansion and sign expansion up to a predetermined number of processing bits, which is output to the above-mentioned information processing means, and the above-mentioned information processing means is : Writes the above-mentioned data that has been expanded in accordance with the above-mentioned 2nd load command into the 2nd register. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (read the precautions on the back and then fill out this page). In this way, zero expansion and symbol expansion of the processing data stored in the processing data storage means are implemented. The first load command for the register and the second load command for the second register of the information processing means are transferred to the zero register and the sign expansion of the processing data of the first register stored in the information processing means. On the occasion, it is possible to use the common expansion means provided outside the information processing means to perform the expansion processing of the processing data described above. Therefore, information processing methods such as microcomputer CPUs themselves can be used in small papers and can also be used in China National Standard (CNS) A4 specifications (210X297 mm) -10- 541496 A7 B7 V. Description of the invention p) and cheap, and can make The processing data inside the CPU and the expansion of the external processing data are carried out at high speed in accordance with the load command. The above-mentioned expansion means of the present invention preferably has the following structure: including: a zero-expansion means for zero-expansion of the processed data to be read and a sign-extension sign-extension means for each of the above-mentioned data sizes, and following the above-mentioned expansion control signal , Select the output means to output the above-mentioned expansion means. According to the present invention, a zero expansion means for zero-expanding the processed data and a sign expansion means for sign expansion are provided for each data size. For example, in an information processing device that processes 32-bit data, there are two types of processing data: 8-bit and 16-bit. There are zero expansion methods and sign expansion methods for 8-bit data. And 16-bit zero extension and sign extension. In addition, the processing data is output using zero-bit expansion or sign expansion using the selected bit size expansion method in accordance with the above-mentioned expansion control signal. By doing this, a simpler circuit configuration can be used to perform expansion processing on the processing data. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) In the present invention, the above means of expanding the symbols preferably include: means for processing data to be originally exported locally, and means for processing data The higher-level extended bit data is all constructed as a signal with a sign and output. Also, in the microcomputer, a bus control unit for controlling the normal bus is provided. Therefore, the above-mentioned expansion means can be constituted as a part of the circuit of the above-mentioned bus control unit, in order to improve the overall integration of the circuit. This paper standard is applicable to the Chinese National Standard (CNS) A4 specification (210X 297 public variable) -11-541496 kl B7__________ 5. The description of the invention P) is ideal. The microcomputer of the present invention is preferably formed by the R 1 S C method. The microcomputer of the R I s c method was designed for the purpose of miniaturizing hardware 'and achieving high speed. Therefore, there are many general-purpose registers, which can reduce the number of commands by focusing the command set on those with high general-purpose performance. The microcomputer of the present invention is preferably: a command for interpreting a fixed length is constructed according to the command. Compared with the use of a variable-length command, the use of a fixed-length command can shorten the time required to decode the command, and can make the circuit size of the microcomputer smaller. In the case of fixed-length commands, the command can be prevented from being verbose. In order to use the memory efficiently, the number of bits necessary for each command should be as small as possible and as short as possible. The electronic device of the present invention is preferably formed by including the microcomputer of the present invention described above. According to the present invention, since a microcomputer having a fast processing speed and a low processing speed is built in, a low-cost and high-performance electronic device can be provided. [Simplified description of the drawing] Printing of clothing by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs-(Please read the precautions on the back before filling out this page) Figure 1 illustrates the function of a suitable implementation form of the microcomputer to which the present invention is applied Block diagram. Fig. 2A to Fig. 2F are explanatory diagrams of the specific structure of the expansion circuit built into the above microcomputer. Fig. 3A is an explanatory diagram of a multiplexer for selecting an output of a complex expansion circuit, and Fig. 3B is a functional block diagram of another embodiment. The Zhang scale is applicable to the Chinese National Standard (CNS) A4 gauge (210X297 mm) ~~ -12- 541496 A7 B7 V. Description of the invention (10) Figure 4 A ~ Figure 4 E is the loading command to mnemonic (mnemonic ) Explanatory diagram of open polynomial expression. Fig. 5 is a diagram illustrating a case where 8-bit processed data is subjected to sign extension and zero extension. Fig. 6 is a diagram illustrating a case where 8-bit processed data is subjected to sign extension and zero extension. FIG. 7 is a specific functional block diagram of the microcomputer of this embodiment. FIG. 8 is an explanatory diagram of a load command used in another embodiment of the present embodiment. Main component comparison table (please read the notes on the back before filling this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 1 〇 Microcomputer 1 2 External R 〇 1 4 External RA Μ 2 0 CPU 2 2 Internal R 〇Μ 2 4 Internal RA M 2 6 Bus control unit 3 0, 8 4 Command address bus 3 2, 8 6 Command data bus 3 4, 8 0 Data address bus 3 6; a > 3 6 b, 8 2 a 82b Data Bus 4 0 Order Interpretation Department 4 2 Order 5 Purchase Department Paper Rule _ Degree Applicable to Chinese National Standard (〇 呢) 6 4 Specifications (210 '乂 297 mm) -13- 541496 Central Ministry of Economic Affairs Printed by the Consumer Bureau of Standards Bureau A7 B7 V. Description of the invention (11) 4 4 Register group 5 〇 Extension section 5 〇 1, 5 〇 3 Zero extension circuit 5 〇 2 5 0 — 4 Symbol extension circuit 5 〇— 5 Non-extension circuit 6 〇> 6 2 Multiplexer 8 〇〇 Interrupt controller 8 1 0 Serial interface 8 3 0 A / D converter 8 4 〇 D / A converter 8 5 0 input 璋 8 6 0 output 璋 8 7 〇 I / 〇 fu 9 1 〇 tube frequency transmission circuit 9 2 〇 low its frequency transmission circuit 9 3 〇 reset circuit 9 4 0 minutes its frequency circuit 9 5 〇Λ 9 6 0 Programmable timer 9 8 〇Smart D Μ A 9 9 〇Cylinder speed D Μ A [The best form of implementing the invention] Next, please refer to the figure for details A suitable embodiment of the present invention will be described. (Please read the precautions on the back before filling in this page) The paper size is applicable to Chinese National Standard (CNS) A4 (210X 297 mm) -14-541496 ΑΊ Β7 5. Description of the invention (12) Figure 1 of the first embodiment The electronic circuit of this embodiment is shown. This electronic circuit is composed of a microcomputer 10, an external ROM 12 and a RAM 14, and these are connected via an external address bus 16 and an external data bus 18. The above microcomputer 10 is composed of internal ROM 2 2 in which various commands are memorized as object codes, internal RAM 2 4 in which various processing data are memorized, and bus controller unit 26. The above microcomputer 10 includes: a 32-bit command address bus 30, and a 16-bit command data bus 32, and a 32-bit data address bus 3 4 and 3 2 The data buses for writing and reading of the two groups of bits 3 6 a, 3 6 b. These buses 30 to 36 are connected between the CPU 20 and the bus control unit 26. Printed by the Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Furthermore, the above microcomputer 10 includes: 32-bit command address bus 8 4 and 16 Command data bus 86, and 32-bit data address bus 80, and 32-bit two sets of data read and write data buses 8 2 a, 8 2 b, these Each of the buses 80 to 86 is connected between the ROM 22, the RAM 24, and the bus control unit 26.
匯流排控制單元2 6依據由C P U 2 0被輸出之各 種要求信號（被輸出於上述匯流排之信號等），控制與 ROM 22、RAM 24之間之資料之輸入輸出，或 控制經由外部位址匯流排1 6、外部資料匯流排1 8，此 外部電路例如R〇Μ 1 2、R Α Μ 1 4與C P U 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） -15- 541496 kl B7 ___ 五、發明説明（13 ) 2 0之間之資料之輸入輸出。 上述CPU 20係包含：由ROM 22將各種命 令作爲目的碼讀出用之位址信號輸出之命令讀出部4 2 ’ 以及將由R ◦ Μ 2 2被讀出之目的碼解讀以輸出各種控 制信號之命令解讀部4 0，以及記憶各種位址或處理資料 之泛用之寄存器群4 4以被構成之。本實施形態之微電腦 1 0特別是該C P U 2 0係以可以處理3 2位元之資料 之RISC方式者形成之。 再者，本實施形態之C P U 2 0經由流水線（ pipeline )與載入、儲存型之結構’幾乎所有之叩节在1循 環實行之。全部之命令以1 6位元固定長度被記述’上述 CPU 2 0之處理命令成爲極小之目的碼大小以被構成 之。 經濟部中央標隼局員工消費合作社印製 即，在上述內部R〇M 2 2全部之命令以1 6位兀 固定長度之目的碼被記述之。而且，各目的碼係經由從命 令讀出部4 2經由命令位址匯流排3 0被輸出之3 2位兀 之位址信號而被指定。經由此被讀出之1 6位元之目的碼 ，經由命令資料匯流排3 2，在C P U 2 0之命令解讀 部4 0被解讀，因應該解讀結果之各種運算處理在^ P 11 2 0內部被進行。 如此在命令解讀部4 0被解讀之目的碼之中，大多數 包含將被記憶於內部R A Μ 2 4內之處理資料傳送於所 與之寄存器4 4用之載入命令。 被記憶於上述內部R AM 2 4內之處理資料，依據 -16- (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公楚） 541496 A7 ______ B7 五、發明説明l14 ) 該資料之內容，有1字節（8位元）之資料、1 6字節之 資料、3 2字節之資料之3種類。 相對於此，C P U 2 0係處理3 2位元資料而被構 成，該內部之寄存器群4 4也具有3 2位元之記憶容量。 因此，在上述匯流排控制單元2 6內設有將由R a Μ 2 4被讀出之1字節、1 6位元之資料擴充爲3 2位元 予與輸出用之擴充部5 0。 在圖2顯示本實施形態之擴充部5 〇之具體之構成。 由R A Μ 2 4經由資料匯流排8 2 b被讀出之處理資料 如圖2 A所示般地，經由D I N 0、D I N 1、.. • DIN 3 1之各線而被輸入於上述擴充部5 〇。 經濟部中央標準局員Η消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 本實施形態之擴充部5 0係包含：以圖2 B所示之1 字節處理資料爲對象之第1零擴充電路5 〇 - 1，以及以 圖2 C所示之1字節處理資料爲對象之第1符號擴充電路 5 0 - 2 ’以及以圖2 D所示之1 6位元處理資料爲對象 之第2零擴充電路5 0 - 3，以及以圖2 E所示之1 6位 元處理資料爲對象之第2符號擴充電路5 0 - 4，以及以 3 2位元之處理資料爲對象之非擴充電路5 〇 - 5而被構 成之，如圖2A所示般地，由ram 2 4被讀出之處理 資料分別被輸入這些之各電路5 0 - 1〜5 0 - 5。 上述非擴充電路5 0 - 5在由RAM 2 4被讀出之 處理資料爲3 2位元之情形，將其原原本本地作爲D 〇、 D 1 * · ·〇3 1之輸出資料以輸出之。即將32位元之 輸入資料原原本本地作爲3 2位元資料輸出。 本紙張尺度適财關家縣（CNS )八4娜（2lQx 297公髮） -17- 541496 Μ Β7 五、發明説明（15 )The bus control unit 26 controls the input and output of data between ROM 22 and RAM 24 according to various request signals (signals output from the above bus, etc.) output by the CPU 20, or via external addresses Bus 1 6 、 External data bus 1 18, this external circuit is for example ROM 1 2, R Α Μ 1 4 and CPU This paper size applies the Chinese National Standard (CNS) Α4 specification (210 × 297 mm) -15- 541496 kl B7 ___ V. Description of the invention (13) Input and output of data between 2 and 0. The above-mentioned CPU 20 includes a command reading section 4 2 ′ that outputs various commands as address signals for reading the destination code by the ROM 22 and interprets the destination code read by R ◦ M 2 2 to output various control signals. The command reading section 40 and the general register group 44 for storing various addresses or processing data are configured. The microcomputer 10 in this embodiment, especially the C P U 2 0, is formed by a RISC method capable of processing 32-bit data. Furthermore, almost all the sections of the C P U 2 0 according to the present embodiment are implemented in a loop through a pipeline and a load-and-storage structure. All the commands are described with a fixed length of 16 bits. The above-mentioned processing command of the CPU 20 is made to have a very small target code size. Printed by the Employees' Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. That is, all the internal ROM 2 2 orders described above are described with a 16-digit fixed-length destination code. Each destination code is designated via a 32-bit address signal output from the command reading unit 42 via the command address bus 30. The 16-bit object code thus read is decoded through the command data bus 32, and is decoded in the command interpretation section 40 of the CPU 2 0. The various calculation processing according to the interpretation result is within ^ P 11 2 0 Was carried out. In this way, most of the object codes decoded by the command interpreting section 40 include a load command for transferring the processing data stored in the internal RAM 24 to the register 44. The processing data memorized in the above internal R AM 2 4 is based on -16- (Please read the precautions on the back before filling this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X297 Gongchu) 541496 A7 ______ B7 V. Invention Description l14) The content of the data includes 3 types of 1-byte (8-bit) information, 16-byte information, and 32-byte information. In contrast, C P U 2 0 is constructed by processing 32-bit data, and the internal register group 44 also has a 32-bit memory capacity. Therefore, the above-mentioned bus control unit 26 is provided with an expansion section 50 for extending 1-byte and 16-bit data read out from Ra M 2 4 to 32-bit for output and output. FIG. 2 shows a specific configuration of the extension section 50 of this embodiment. As shown in FIG. 2A, the processing data read out from the RA Μ 2 4 via the data bus 8 2 b is input to the above-mentioned expansion section 5 through the lines of DIN 0, DIN 1, .. 〇. Printed by a member of the Central Standards Bureau of the Ministry of Economic Affairs and a Consumer Cooperative (please read the precautions on the back before filling out this page) The extension section 50 of this embodiment includes: The first byte of processing data shown in Figure 2B is the first 1 zero extension circuit 5 0-1 and the first symbol extension circuit 50 0-2 ′ which targets 1-byte processing data shown in FIG. 2 C and 16-bit processing data shown in FIG. 2 D The object's second zero expansion circuit 5 0-3, and the second symbol expansion circuit 50 0-4 which targets 16-bit processing data shown in FIG. 2E, and the target data which is 32-bit processing. As shown in FIG. 2A, the processing data read by ram 24 is input to each of these circuits 5 0-1 to 50-5 as shown in FIG. 2A. In the case where the processing data read out from the RAM 24 is 32 bits, the above-mentioned non-expansion circuits 50-5 use the original data locally as output data of D 0, D 1 * · · 03 1 to output it. That is, the 32-bit input data is originally output locally as 32-bit data. Size of this paper: Shicai Guanjia County (CNS) 8 4 Na (2lQx 297) -17- 541496 Μ Β7 V. Description of the invention (15)
圖2 B所示之第1零擴充電路5 0 - 1係將經由輸入 線DIN O...DIN 7而被輸入之8位元處理資 料，原原本本地經由8位元之輸出線D 〇、D 1 · · · D 7以輸出而形成。再者’此第1零擴充電路5 0 - 1將經 由剩餘之輸入線D I N 8 · · · D I N 3 1被輸入之 資料遮斷，對這些之輸入線DIN 8···DIN 3 1強制地輸入「〇」之零擴充用信號。而且，將此零擴 充用信號原原本本地對輸出線D8···D31之輸出資 料擴充輸出。 圖2 C所示之第1之符號擴充電路5 0 — 2係將經由 輸入線DIN 〇··.DIN 7而被輸入之8位元處 理資料，原原本本地經由8位元之輸出線D 〇、D 1 .. • D 7以輸出而形成。再者，此第1符號擴充電路5 0 — 2將經由剩餘之輸入線D I N 8 · · · D I N 3 1被 經濟部中央標率局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 輸入之資料遮斷，對這些之輸入線D I N 8 ·.. DIN 3 1強制地輸入8位元資料之符號位元之D I N 7。而且，將此D I N 7之符號信號之資料原原本本 地對輸出線D 8 ··· D 3 1之輸出資料擴充輸出。 即DIN 0〜DIN 7之8位元之處理資料原原 本本地被作爲8位元之輸出資料DO...D7輸出，剩 餘之2 4位元之上位位數D 8 ··. D 3 1被擴充爲 DIN 7之値而被輸出。 如此，本實施形態之第1零擴充電路5 〇 — 1、第1 之符號擴充電路5 0 - 2可以將被輸入之8位元之處理資 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X 297公釐） -18- 541496 經濟部中央標準局員工消費合作社印製 A7 B7 五、發明説明（16 ) 料零擴充或符號擴充爲3 2位元資料以輸出之。 圖2D、E所示之第2零擴充電路50 - 3、第2符 號擴充電路5 0 - 4爲將1 6位元之輸入資料零擴充或符 號擴充爲3 2位元者，其原理基本上與上述第1零擴充電 路5 0 — 1、第1符號擴充電路5 0 — 2相同。即，將經 由輸入線DIN 0...DIN 15被輸入之16位 元之處理資料，原原本本地經由輸出線D 0、D 1 ·· · D1 5以輸出。再者，此第2零擴充電路50 - 3、第2 符號擴充電路5 0 — 4將經由剩餘之輸入線D I N 16 • · -DIN 3 1被輸入之資料遮斷，對這些之輸入線 DIN 16. . .DIN 3 1強制地輸入「〇」之零 擴充用信號或D I N 1 5之符號擴充用信號。而且，將 此擴充用之信號之資料原原本本地對輸出線D 1 6 ... D 3 1之輸出資料擴充輸出。 即DIN 〇〜DIN 15之16位元之處理資料 原原本本地被作爲16位元之輸出資料D〇...D15 輸出，剩餘之16位元之上位位數D16.·.D31被 擴充爲「0」或D I N 1 5之値而被輸出。 而且，這些各電路5 0 - 1〜5 0 — 5之輸出如圖3 所示般地，經由多路轉換器6 0作爲3 2位元處理資料被 選擇性地輸出。而且，經由多路轉換器6 〇被輸出之3 2 位元之處理資料經由資料匯流排3 6 b，向著C P U 2 0被輸出。 經由此多路轉換器6 0之選擇動作係依據由命令解讀 本紙張尺度適用中國國家標準（CNS ) A4&枱（~2j〇X 297公釐） 一 ~ -19 - (請先閱讀背面之注意事項再填寫本頁 衣·The first zero-extension circuit 5 0-1 shown in FIG. 2B is the 8-bit processing data that will be input through the input lines DIN O ... DIN 7 and originally through the 8-bit output lines D 0, D. 1 · · · D 7 is formed by output. Furthermore, 'the first zero extension circuit 5 0-1 will be interrupted by the input data via the remaining input lines DIN 8 · · · DIN 3 1 and forcibly input to these input lines DIN 8 · · · DIN 3 1 The signal for zero expansion of "〇". In addition, the zero expansion signal is originally used to expand the output data of the output line D8 ··· D31. The first sign extension circuit 50-2 shown in FIG. 2C is an 8-bit processing data that will be input through the input line DIN 〇 · .DIN 7 and originally through the 8-bit output line D 〇, D 1 .. • D 7 is formed by output. In addition, the first symbol extension circuit 5 0 — 2 will be printed by the remaining input line DIN 8 · · · DIN 3 1 by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling in this (Page) The input data is interrupted. For these input lines, DIN 8 ················· The DIN 3 1 forcibly enters the sign bit DIN 8 of 8-bit data. Furthermore, the data of the symbol signal of this D I N 7 is originally extended to the output data of the output line D 8 ··· D 3 1. That is, the 8-bit processing data of DIN 0 to DIN 7 is originally output as the 8-bit output data DO ... D7, and the remaining 2 4 bits are higher than D 8 ··· D 3 1 is expanded It is output as of DIN 7. In this way, the first zero extension circuit 5 0-1 and the first sign extension circuit 50-2 of this embodiment can apply the inputted 8-bit processing capital paper size to the Chinese National Standard (CNS) A4 specification (210X 297 mm) -18- 541496 A7 B7 printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs. 5. Description of the invention (16) Expansion of zeros or symbols into 32-bit data for output. The second zero expansion circuit 50-3 and the second symbol expansion circuit 50-4 shown in FIGS. 2D and E are those that expand 16 bits of input data by zero or sign to 32 bits. The principle is basically This is the same as the first zero extension circuit 50-1 and the first sign extension circuit 50-2. That is, the 16-bit processing data inputted via the input lines DIN 0 ... DIN 15 is originally outputted locally via the output lines D 0, D 1 ··· D 1 5. In addition, the second zero extension circuit 50-3, and the second symbol extension circuit 5 0-4 will be interrupted by the input data via the remaining input lines DIN 16 • -DIN 3 1 to these input lines DIN 16 ... DIN 3 1 Forcibly input the signal of zero extension of "0" or the signal of sign extension of DIN 1 5. Moreover, the data of this expansion signal is originally expanded to the output data of the output lines D 1 6 ... D 3 1 locally. That is, the 16-bit processing data of DIN 〇 ~ DIN 15 is originally output as 16-bit output data D0 ... D15, and the remaining 16-bit upper digits D16 ... D31 are expanded to "0 ”Or DIN 1 5 is output. Moreover, the outputs of these circuits 50-1 to 50-5 are selectively output as 32-bit processed data via the multiplexer 60 as shown in FIG. 3. Furthermore, the 32-bit processing data output through the multiplexer 60 is output to the C P U 2 0 through the data bus 36 b. According to the selection action of the multiplexer 60 according to the order, the paper size is interpreted according to the Chinese national standard (CNS) A4 & table (~ 2j〇X 297 mm) one ~ -19-(Please read the note on the back Matters refill this page
、1T 541496 A7 B7 經濟部中央標準局員工消費合作社印製 五、發明説明（17 ) 部4 0被輸出之選擇指令以進行之。 圖4 A〜E顯示被記憶於R〇Μ 2 2內之各種載入 命令之具體例。在此處，爲了容易理解之故，雖將各種載 入命令以助記碼顯示之，但是這些之各載入命令實際上， 爲3 2位元之目的碼被記憶在R〇Μ 2 2內。 於這些之各載入命令中，最初被記述之^ 1 d」係顯 示命令爲載入命令者，接著被記述之「b」、「ub」、 「h」、「uh」、「w」爲由RAM24被讀出之處理 資料之大小及界定將資料進行符號擴充或零擴充之擴充开多 式用之資料。即，「b」、「h」、「w」顯示被讀出之 處理資料之大小分別爲1字節（8位元）、1 6字節、 3 2字節。又，「u」顯示將處理資料零擴充，沒有「u 」之載入命令顯示將處理資料符號擴充。 又，「％r eg 1」顯示將在擴充部5 0被擴充爲 3 2位元而被輸出之處理資料載入之寄存器，在此處’顯 示由寄存器群4 4之中，於r e g 1之寄存器記憶3 2位 元處理資料。 又，最後被記述之「％r e g 2」顯示將處理資料由 RAM 2 4讀出用之位址被記憶之寄存器’在此處’意 指依據被記憶在寄存器群4 4中之r e g 2之3 2位元位 址資料，由RAM 24讀出處理資料。 例如假定依據命令讀出部4 2之指令’由R〇Μ 2 2被讀出如圖4 Α所示之載入命令之目的碼之情形’此 目的碼在C P U 2 0之命令解讀部4 0被解讀。 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規桔（210X 297公釐） -20- 541496 A7 B7 五、發明説明（ΐβ ) 而且，此命令解讀部4 0讀出被記憶在寄存器r e g 2之3 2位元之位址資料，向著匯流排控制單元2 6，經 由資料匯流排3 4輸出此位址資料以及資料大小b。經由 如此，匯流排控制單元2 6由R A Μ 2 4從以該位址資 料被指定之領域，讀出以上述資料大小b被指定之大小之 處理資料，在此處爲1字節之處理資料，對擴充部5 〇輸 入。 此時，命令解讀部4 0依據被包含於圖4 A所示之載 入命令之資料大小「b」，向著被包含於擴充部50之多 路轉換器6 0，選擇第1符號擴充電路5 0 - 2之輸出地 輸出控制信號。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 因此，例如此時由R A Μ 2 4被讀出之1字節之資 料如圖5、圖6所示般之資料時，此1字節資料經由第1 符號擴充電路5 0 - 2，如同圖所示般地，在被符號擴充 爲3 2位元資料之狀態被輸入c P U 2 0，此3 2位元 擴充資料被載入以載入命令指定之寄存器r e g 1。又， 由R〇Μ 2 2如圖4 Β所示般地，將1字節之處理資料 零擴充，載入命令被讀出之情形，與上述載入命令相同地 ， 依據被記憶在r e g 2之位址命令，由R A Μ 24 讀出1字節之處理資料，在擴充部5 〇零擴充爲3 2位元 資料。此時，被讀出之處理資料爲如圖5所示之1字節資 料時，使用第1零擴充電路5 0 - 1，此處理資料如同圖 所示地’被零擴充爲3 2位元後，被載入寄存器Γ e g 1 本纸張尺度適用中國國家標準（CNS ) A4規輅（210X2^^7 -21 - 541496 A7 B7 經濟部中央標準局員工消費合作社印裂 五、發明説明（19 ) 在圖5之8位元資料中，D I N 7之符號位元爲‘ 〇 ’之故，符號擴充與零擴充爲相同之値。但是如圖6之8 位元資料，D I N 7之符號位元爲’ 1 ’之情形，符號擴 充與零擴充成爲不同之値。 使用圖4D、C所示之載入命令，將1 6位元之處理 資料0或符號擴充爲3 2位元，載入寄存器1之情形，命 令解讀部4 0向著擴充部5 0之多路轉換器6 0，除了輸 出旨在選擇第2零擴充電路5 0 - 3或第2符號擴充電路 5 0 - 4之輸出之控制信號之點外，進行與上述第1實施 例相同之動作。 又，實行圖4 E所示之載入命令之情形，命令解讀部 4 0向著擴充部5 0之多路轉換器6 0，除了輸出旨在選 擇非擴充電路5 0 - 5之輸出之控制信號外，進行與上述 載入命令同樣之動作。 如此爲之，依據本實施形態之微電腦1 〇，以簡單支 電路構成，由RAM 24被讀出之1字節、16位元之 處理資料可以簡單而且迅速地符號擴充或零擴充爲3 2位 元之資料。 特別是依據本實施形態，將此種處理資料之擴充經由 1命令循環實行，恰如將擴充部5 0設於C P U 2 0內 之情形般地，以同樣之處理速度可以實行上述資料之讀出 與擴充處理。 第2實施形態 (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -22- 541496 A7 B7 五、發明説明p〇 ) 接著說明本發明之合適之第2實施形態。 本實施形態之微電腦1 0其特徵爲：將被儲存 在CPU 2 0內之寄存器44內之3 2位元資料之內， 例如i字節、或1 6位元之資料，使用匯流排控制單元 2 6之擴充部5 0，零擴充或符號擴充爲3 2位元，儲存 於所希望之寄存器。 在圖3 B顯示爲了此之擴充部5 0之具體之構成。本 實施形態之擴充部5 0係由R A Μ 2 4之資料匯流排 8 2 b來之資料，與經由資料匯流排3 6由C P U 20 被送來之資料，經由多路轉換器6 2被選擇性地輸入而構 成之。對此多路轉換器6 2之選擇指令由命令解讀部4〇 被輸出。 命令解讀部40在由ROM 2 2如圖4所示之形式 之載入命令被讀出之情形，選擇由R A Μ 2 4來之資料 匯流排8 2 b地，控制多路轉換器6 2以外，與上述第1 實施形態同樣地動作。 經濟部中央標準局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁) 又，命令解讀部40在由ROM 2 2如圖8所示形 式之載入命令被讀出之情形，解釋此載入命令，實行將被 記憶在寄存器群4 4內之規定寄存器之3 2位元資料之內 ，8位元或1 6位元之資料做零擴充或符號擴充，載入其 他之寄存器之命令。 以下，說明其詳細。 命令解讀部4 0由被包含於圖8所示之載入命令之讀 出對象之寄存器r s讀出處理資料，將其經由資料匯流排 本紙張尺度適用中國國家標準（CNS ) A4規格（21〇χ297公釐） -23- 541496 經濟部中央標準局員工消費合作社印t A7 B7 五、發明説明f1 ) 3 6 a向擴充部5 0輸出。 與此同時，命令解讀部4 0，多路轉換器6 2選擇輸 出由資料匯流排3 6 a來之處理資料，多路轉換器6 0選 擇由處理資料之大小以及擴充之形式適合之電路5 0 - 1 〜5 〇 - 5來之擴充資料，經由資料匯流排3 6 b向 CPU 20輸出地，向各多路轉換器62、60輸出選 擇指令。 圖8顯示上述載入命令之具體例。此處，爲了容易理 解之故，將各種載入命令以助記碼顯示之。這些之各載入 命令，實際上爲3 2位元之目的碼被記憶在R〇Μ 22 內。 於這些之各載入命令中，最初被記述之「1 d」係顯 示命令爲載入命令者，接著被記述之「b」、「ub」、 「h」、「uh」爲由寄存器rs被讀出之處理資料之大 小及界定將資料進行符號擴充或零擴充之擴充形式用之資 料。即，「b」、「h」顯示被讀出之處理資料之大小分 別爲1字節（8位元）、1 6字節、3 2字節。又，「u 」顯示將處理資料零擴充，沒有「u」之載入命令顯示將 處理資料符號擴充。 又’ 「％ r d」顯示將在擴充部5 0被擴充爲3 2位 元而被輸出之處理資料載入之寄存器。在此處，顯示由寄 存器群4 4之中，於r d之寄存器記憶3 2位元處理資料 〇 又，最後被記述之「％ r s」顯示處理資料被記憶之 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公襲） --------— (請先閲讀背面之注意事項再填寫本頁)1T 541496 A7 B7 Printed by the Consumers' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the invention (17) The selection instructions output by the Ministry 40 are carried out. Figures 4A to 4E show specific examples of various load commands stored in ROM 22. Here, for easy understanding, although various load commands are displayed as mnemonic codes, each of these load commands is actually a 32-bit destination code stored in ROM 22. . In each of these loading commands, the ^ 1 d ”originally described is the person who shows the command as a loading command, and the“ b ”,“ ub ”,“ h ”,“ uh ”, and“ w ”described next are The size and definition of the processed data read out from the RAM 24 are used to expand the data by sign expansion or zero expansion. That is, "b", "h", and "w" indicate that the size of the read processing data is 1 byte (8 bits), 16 bytes, and 32 bytes, respectively. In addition, "u" indicates that the processing data will be expanded by zero, and a load command without "u" indicates that the processing data symbol will be expanded. In addition, "% r eg 1" shows the register loaded with the processing data which is expanded to 32 bits in the expansion section 50 and is displayed in the register group 4 4 in "reg 1". Register memory 3 2 bits for processing data. In addition, the "% reg 2" described last shows the register where the address used for reading the processing data from the RAM 2 4 is stored "here" means that it is based on the 3 of the reg 2 stored in the register group 4 4 The 2-bit address data is read and processed by the RAM 24. For example, suppose that according to the instruction of the command reading unit 42, 'the situation where the target code of the load command is read from ROM 2 2 is shown in FIG. 4A.' This object code is in the command reading unit 40 of the CPU 2 0 Be interpreted. (Please read the precautions on the back before filling this page) This paper size is applicable to Chinese National Standard (CNS) A4 Orange (210X 297 mm) -20- 541496 A7 B7 V. Description of Invention (ΐβ) Moreover, this order is interpreted The unit 40 reads the 32-bit address data stored in the register reg 2 and outputs the address data and the data size b to the bus control unit 26 through the data bus 34. In this way, the bus control unit 26 reads the processing data designated by the above-mentioned data size b from the area designated by the address data by the RAM 24, and here is 1 byte of processing data. And enter it in the extension section 50. At this time, the command interpretation unit 40 selects the first symbol expansion circuit 5 toward the multiplexer 60 included in the expansion unit 50 according to the data size “b” of the load command included in FIG. 4A. 0-2 output control signal. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the notes on the back before filling this page). Therefore, for example, the 1-byte data read out by RA Μ 2 4 at this time is shown in Figures 5 and 6. In the case of general data, this 1-byte data is passed through the first sign extension circuit 5 0-2 as shown in the figure. In the state of being sign-extended to 32-bit data, c PU 2 0 is entered, and this 3 2 The bit extension data is loaded to load the register reg 1 specified by the command. In addition, as shown in FIG. 4B, the ROM 2 2 zero-extends the processing data of 1 byte, and the load command is read out. In the same manner as the load command described above, it is memorized in reg 2 The address command reads 1 byte of processing data from the RA 24, and it is expanded to 3 32-bit data in the extension 500. At this time, when the read processing data is 1-byte data as shown in FIG. 5, the first zero expansion circuit 50 0-1 is used, and the processing data is' expanded to 3 2 bits by zero as shown in the figure. Later, it was loaded into the register Γ eg 1 This paper size is applicable to the Chinese National Standard (CNS) A4 regulations (210X2 ^^ 7 -21-541496 A7 B7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs. ) In the 8-bit data in Figure 5, the sign bit of DIN 7 is '0', so the sign extension is the same as the zero extension. However, as shown in the 8-bit data of Figure 6, the sign bit of DIN 7 In the case of '1', sign expansion and zero expansion become different. Using the load command shown in Figure 4D and C, 16-bit processing data 0 or sign is expanded to 32 bits, and loaded into the register In the case of 1, the command interpretation unit 40 is directed to the multiplexer 60 of the expansion unit 50, except that the output is intended to select the output of the second zero expansion circuit 50-3 or the second sign expansion circuit 50-4. Except for the point of the signal, the same operation as in the above-mentioned first embodiment is performed. Further, the loading command shown in FIG. 4E is executed. In this case, the command interpretation unit 40 is directed to the multiplexer 60 of the expansion unit 50, and performs the same operation as the load command except that it outputs a control signal intended to select the output of the non-expansion circuit 50-5. In this way, the microcomputer 10 according to this embodiment is constituted by a simple branch circuit, and the 1-byte, 16-bit processing data read from the RAM 24 can be simply and quickly sign-extended or zero-extended to 32 bits. In particular, according to this embodiment, the expansion of such processing data is executed through a 1-command cycle, just as when the expansion unit 50 is set in the CPU 20, and the above data can be implemented at the same processing speed. Readout and expansion processing. The second embodiment (please read the precautions on the back before filling out this page) This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) -22- 541496 A7 B7 V. Description of the invention p0) Next, a suitable second embodiment of the present invention will be described. The microcomputer 10 of this embodiment is characterized in that it will be stored in the 32-bit data in the register 44 in the CPU 20, such as i-byte or 16-bit data, using a bus control unit The expansion section 50 of 26, zero extension or sign extension is 32 bits, and is stored in a desired register. FIG. 3B shows a specific configuration of the expansion unit 50 for this purpose. The expansion unit 50 of this embodiment is selected from the data from the data bus 8 2 b of the RAM 24, and the data sent from the CPU 20 via the data bus 36 is selected through the multiplexer 62. It is constituted by sexual input. A selection command for this multiplexer 62 is output by the command interpreter 40. The command interpretation unit 40 selects the data bus 8 2 b from the RA M 2 4 to control the multiplexer 6 2 when the loading command in the form shown in FIG. 4 by the ROM 2 2 is read. The operation is the same as in the first embodiment. Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs (please read the precautions on the back before filling this page). Also, when the order reading section 40 reads out the loading order in the form shown in FIG. 8 by ROM 22, Interpret this load command, implement the 32-bit data stored in the specified registers in the register group 44, the 8-bit or 16-bit data for zero expansion or sign expansion, and load other registers Command. The details are described below. The command interpretation unit 40 reads out the processing data from the register rs included in the read-out target of the load command shown in FIG. 8 and passes it through the data bus. The paper size applies the Chinese National Standard (CNS) A4 specification (21〇 χ297 mm) -23- 541496 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs t A7 B7 5. Invention Description f1) 3 6 a is output to the extension department 50. At the same time, the command interpreting section 40, the multiplexer 62 selects and outputs the processing data from the data bus 3 6a, and the multiplexer 60 selects a circuit suitable for the size and expansion of the processing data. 5 The extended data from 0-1 to 5 0-5 is output to the CPU 20 via the data bus 3 6 b and a selection command is output to each of the multiplexers 62 and 60. FIG. 8 shows a specific example of the above-mentioned load command. Here, for easy understanding, various load commands are displayed as mnemonics. Each of these loading commands is actually stored in ROM 22 with a destination code of 32 bits. In each of these loading commands, the "1 d" described first is the one who shows that the command is a loading command, and the "b", "ub", "h", and "uh" described next are used by the register rs. Read the size of the processed data and define the data used to expand the data by sign expansion or zero expansion. That is, "b" and "h" indicate that the size of the read processing data is 1 byte (8 bits), 16 bytes, or 32 bytes, respectively. In addition, "u" indicates that the processing data will be expanded by zero, and the load command without "u" indicates that the processing data symbol will be expanded. Also, "% r d" shows a register which is loaded with the processed data which is expanded to 32 bits in the expansion section 50. Here, it is shown that 32-bit processed data is stored in the register group 444 in the register group 44. Finally, the “% rs” described last indicates that the processed paper is memorized. The Chinese paper standard (CNS) ) Λ4 specification (210X 297 public attack) --------— (Please read the precautions on the back before filling this page)
、1T -24- 541496 A7 B7 五、發明説明？2 ) 寄存器，在此處，意指讀出被記憶在寄存器群4 4中之寄 存器r s之處理資料。 接著，說明實行上述載入命令之情形之具體例。 在此情形，命令解讀部4 0由被包含於載入命令之資 料之讀出對象之寄存器r s，讀出處理資料，將其經由資 料匯流排3 6 a向擴充部5 0輸出。 此時，命令解讀部4 0選擇由資料匯流排3 6 a來之 輸入地控制多路轉換器6 2。經由如此，由寄存器r s被 讀出之處理資料被輸入各電路5 0 — 1〜5 0 - 5。 又，命令解讀部4 0依據被包含於解讀完之載入命令 之處理資料之大小，以及符號擴充或零擴充之擴充之種類 資料等，向多路轉換器6 0輸出選擇指令。此選擇指令與 上述第1實施形態相同之故，在此省略其說明。 如此，由多路轉換器6 0被符號擴充或零擴充而輸出 之處理資料，經由資料匯流排3 6 b被控制寫入所希望之 寄存器r d。 經濟部中央標準局員工消費合作社印製 (請先閲讀背面之注意事項再填寫本頁) 如以上說明般地，依據本實施形態，C P U 2 0之 外布店路，具體而言，使用被設於匯流排控制單元2 6內 之擴充部5 0，不單可以將由R A Μ 2 4被讀出之處理 資料零擴充或符號擴充爲3 2位元，也可以將被記憶在 CPU 2 0被之寄存器之8位元或1 6位元之處理資料 ’因應需要零擴充或符號擴充爲3 2位元以儲存於所希望 之寄存器。 特別是依據本實施形態，經由將此種處理資料之擴充 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） -25- 541496 A7 B7 五、發明説明p ) 在1命令循環實行之，恰如將擴充部5 0設於C p U · 2 0被之情形，以相同之處理速度可以實行上述資料之讀 出與擴充處理。 再者，依據上述第1以及第2實施形態，經由使此種 之處理資料之擴充在1循環實行，相較於以往可以使碼大 小縮小之故，例如可以有效使用載於晶片（〇 n chi P)上之ROM 22。 圖7顯示本實施形態之微電腦1 〇之具體之機能之方 塊圖。 該微電腦1 0微3 2位元微控制器，包含：C P U 20與ROM 22與RAM 24、高頻發送電路 9 1 〇、低頻發送電路9 2 0、重置電路9 3 0、分頻電 路9 4 0、1 6位元可編程序計時器9 5 0、8位元可編 程序計時器9 6 0、時鐘脈衝計時器9 7 0、智慧型 DMA 980、高速DMA 990、中斷控制器 8 0 0、串列界面8 1 〇、匯流排控制單元（B C U ) 60、A/D轉換器830、D/A轉換器840、輸入 埠850、輸出埠860、 I/O埠870、以及連接彼 等之各種匯流排92、94、96、98、各種銷890 等。 上述C P U 2 0具有存儲棧指向器（stack pointer )專用寄存器S P，進行上述各種之存儲棧指向器專用命 令之解讀、實行。該CPU 20具有上述之構成，作爲 命令解讀手段、命令讀出手段、以及各種命令之實行手段 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X 297公釐） (讀先閱讀背面之注意事項再填寫本頁) -5 經濟部中央標準局員工消費合作社印製 -26- 541496 kl R7五、發明説明f4 ) 之機能。 本發明之微電腦例如可以適用於列表機等之個人電腦 之周邊機器，或攜帶機器等之各種之電子機器。如此一來 ，可以內藏以簡單之構成可以進行高速處理之資訊處理電 路之故，可以提供便宜高機能之電子機器。 又，本發明並不限於上述實施例說明過者，可以有種 種之變形實施。 例如，在上述實施形態中，以本發明適用於R I S C 型之c P U之情形爲例說明之，除此之外之形式之c P U 例如C I SC型之CPU等也可以廣泛地適用。 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS ) Λ4規格（210X297公釐） -27-、 1T -24- 541496 A7 B7 5. Explanation of the invention? 2) Register, in this case, means to read out the processing data of the register r s stored in the register group 44. Next, a specific example of a case where the load command is executed will be described. In this case, the command interpretation unit 40 reads out the processing data from the register r s which is the reading target of the data loaded into the command, and outputs it to the expansion unit 50 via the data bus 36a. At this time, the command interpretation unit 40 selects the input from the data bus 36a to control the multiplexer 62. In this way, the processing data read out from the register r s is input to each of the circuits 50-1 to 50-5. In addition, the command interpretation unit 40 outputs a selection instruction to the multiplexer 60 according to the size of the processing data included in the decoded load command, the type data of sign expansion or zero expansion, and the like. Since this selection command is the same as the first embodiment described above, its description is omitted here. In this way, the processed data output by the multiplexer 60 by sign extension or zero extension is controlled to be written into the desired register r d through the data bus 36 b. Printed by the Consumers' Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs (please read the precautions on the back before filling this page) As explained above, according to this embodiment, the CPU 20 is located outside the shop road. In the expansion section 50 in the bus control unit 26, not only the processing data read out by the RA M 2 4 can be expanded or signed to 32 bits, but also the registers stored in the CPU 2 0 can be expanded. The 8-bit or 16-bit processing data 'needs to be zero-extended or sign-extended to 32-bits in order to store in the desired register. In particular, according to this embodiment, by expanding this processing data, the paper size applies the Chinese National Standard (CNS) A4 specification (210X 297 mm) -25- 541496 A7 B7 V. Description of the invention In other words, as in the case where the extension section 50 is set to C p U · 20, the above-mentioned data reading and extension processing can be performed at the same processing speed. In addition, according to the first and second embodiments described above, by extending such processing data in one cycle, the code size can be reduced compared to the past. For example, it can be effectively used on a chip (〇n chi P) ROM 22 above. FIG. 7 shows a specific functional block diagram of the microcomputer 10 according to this embodiment. The microcomputer 10 micro 3 2 bit microcontroller includes: CPU 20 and ROM 22 and RAM 24, high frequency transmission circuit 9 1 〇, low frequency transmission circuit 9 2 0, reset circuit 9 3 0, frequency division circuit 9 4 0, 16-bit programmable timer 9 5 0, 8-bit programmable timer 9 6 0, clock pulse timer 9 7 0, smart DMA 980, high-speed DMA 990, interrupt controller 8 0 0, serial interface 8 1 〇, bus control unit (BCU) 60, A / D converter 830, D / A converter 840, input port 850, output port 860, I / O port 870, and connect them Various buses 92, 94, 96, 98, various pins 890, etc. The above-mentioned C P U 2 0 has a storage stack pointer special register SP to perform the interpretation and execution of the above-mentioned various storage stack pointer special commands. The CPU 20 has the above-mentioned structure, and is used as a command reading means, a command reading means, and a method for implementing various commands. This paper size applies the Chinese National Standard (CNS) Λ4 specification (210X 297 mm). (Fill in this page again) -5 Printed by the Consumers Cooperative of the Central Bureau of Standards of the Ministry of Economics -26- 541496 kl R7 V. Invention Description f4). The microcomputer of the present invention can be applied to, for example, peripheral devices such as personal computers such as list machines, and various electronic devices such as portable devices. In this way, an information processing circuit with a simple structure capable of high-speed processing can be built in, and an inexpensive and high-performance electronic device can be provided. In addition, the present invention is not limited to those described in the above embodiments, and can be implemented in various modifications. For example, in the above-mentioned embodiment, the case where the present invention is applied to the c P U of the R I S C type is described as an example, and c P U of other forms such as the CPU of the C I SC type can also be widely applied. (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs This paper size applies to the Chinese National Standard (CNS) Λ4 specification (210X297 mm) -27-