TW429623B - EEPROM structure with metal electrode plate coupling capacitor - Google Patents

EEPROM structure with metal electrode plate coupling capacitor

Info

Publication number
TW429623B
TW429623B TW88114061A TW88114061A TW429623B TW 429623 B TW429623 B TW 429623B TW 88114061 A TW88114061 A TW 88114061A TW 88114061 A TW88114061 A TW 88114061A TW 429623 B TW429623 B TW 429623B
Authority
TW
Taiwan
Prior art keywords
oxide layer
coupling capacitor
tunneling
electrode plate
region
Prior art date
Application number
TW88114061A
Other languages
Chinese (zh)
Inventor
Chung-Rung Lin
Shin-Ming Chen
Original Assignee
Taiwan Semiconductor Mfg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg filed Critical Taiwan Semiconductor Mfg
Priority to TW88114061A priority Critical patent/TW429623B/en
Application granted granted Critical
Publication of TW429623B publication Critical patent/TW429623B/en

Links

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  • Non-Volatile Memory (AREA)

Abstract

This invention provides a kind of EEPROM structure with metal electrode plate coupling capacitor that includes the following parts: a semiconductor substrate, which has a pair of isolation regions used to define active region on the substrate; an impurity doped region in semiconductor substrate, which is used as charge tunneling region and is next to one of the isolation regions. The first oxide layer is formed on semiconductor substrate, in which a tunneling contact hole is formed inside the first oxide layer. A polysilicon floating-gate that is on top of the first oxide layer is connected with the tunneling region through the tunneling oxide layer and is used to define a pair of source/drain regions on the active region. The second oxide layer is used to cover polysilicon floating-gate and the rest part of the first oxide layer. An MIM coupling capacitor is formed on the second oxide layer and in the third oxide layer. A dielectric layer is used to connect the bottom capacitor metal layer of MIM with the polysilicon floating gate.
TW88114061A 1999-08-17 1999-08-17 EEPROM structure with metal electrode plate coupling capacitor TW429623B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW88114061A TW429623B (en) 1999-08-17 1999-08-17 EEPROM structure with metal electrode plate coupling capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW88114061A TW429623B (en) 1999-08-17 1999-08-17 EEPROM structure with metal electrode plate coupling capacitor

Publications (1)

Publication Number Publication Date
TW429623B true TW429623B (en) 2001-04-11

Family

ID=21641947

Family Applications (1)

Application Number Title Priority Date Filing Date
TW88114061A TW429623B (en) 1999-08-17 1999-08-17 EEPROM structure with metal electrode plate coupling capacitor

Country Status (1)

Country Link
TW (1) TW429623B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102881692A (en) * 2011-07-12 2013-01-16 剑桥硅无线电有限公司 Single poly non-volatile memory cells

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102881692A (en) * 2011-07-12 2013-01-16 剑桥硅无线电有限公司 Single poly non-volatile memory cells
CN102881692B (en) * 2011-07-12 2016-11-02 高通技术国际有限公司 Non-volatile memory cell

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Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MK4A Expiration of patent term of an invention patent