TW359878B - Structure of stacked gate memory cell and production process therefor - Google Patents

Abstract

A structure of stacked gate memory cell and a production process therefor, which comprises: implanting a deep diffusion well in a semiconductor substrate; implanting a second diffusion well in the deep diffusion well; implanting a source/drain diffusion region in the second diffusion well thereby forming a MOS transistor; depositing a tunneling oxide layer on the upper surface of the substrate on a channel region between the source/drain; depositing a polysilicon gate on the tunneling oxide layer on the channel region; depositing an insulation layer on the surface of the semiconductor substrate; forming a stack capacitor on the MOS transistor. The stack capacitor has an insulation layer of polysilicon first shield and connects with the gate through an opening in the insulation layer via a shorted plug. The gate and the first shield will form a floating gate of the MOS transistor. A capacitive dielectric layer is deposited on the first shield, and a polysilicon second shield is deposited on the capacitive dielectric layer. The second shield will form a control gate of the MOS transistor.