JPH11214548A - Structure of stacked gate memory cell and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain a holding time similar to an EEPROMs, a flash memory cells or a DRAM cells and a comparatively long program erasing time by forming a tunnel oxide film structure of stacked gate memory cells. SOLUTION: A source diffusion region 265 and a second diffusion well 215 are connected to a source control voltage generator Vs , and a drain diffusion region 255 is connected to a drain control voltage generator Vd . Further, an upper plate electrode 250 of a capacitor which is a control gate of MOS transistors is connected to a word line voltage generator Vwordd , and a deep N-well diffusion region 210 is connected to a deep diffusion voltage generator Vnw1 . The source control voltage generator Vs , the drain control voltage generator Vd , the wordline voltage generator Vword , and the deep diffusion voltage generator Vnw1 are regulated and used for controlling a program, an erasion and a detection of digital data inside stacked gate memory cells.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a memory cell (memory cell).
The present invention relates to the structure of a memory cell, and more particularly to the structure of a memory cell and a method of manufacturing the same, and relates to an electrically erasable programmable read only memory (Electrically Erasable Programmable
retention time (re
The present invention relates to a structure of a stacked gate memory cell having a retention time and a write / erase time close to that of a dynamic random access memory (DRAM) and a method of manufacturing the same.

[0002]

2. Description of the Related Art DRAM cells and DRAM arrays (ar
The structure and manufacturing method of rays are well known in the art. FIG.
(A), the structure of a known high-density memory cell is composed of a transistor M ₁ for controlling the on-off charge, a capacitor C for storing charge. In FIG. 1 (b), N transistor M ₁ is made in triplicate wells
MOS. Deep N well 1 in P-type substrate 10
5 are formed. The deep N-well 15, when forming a field oxide film 25 of silicon selective oxidation (Loc al O xidation of S ilicon = LOCOS), is formed in the opening portion. A shallow P well 20 is formed in a deep N well 15. The gate of the transistor M ₁ is an NMOS 35
Is, there is formed a conductive material, for example, an insulating gate oxide film 32 with disposing the polysilicon material over the channel region 37 between the drain 30 and source 40 in the transistor M ₁ is an NMOS by patterning To form

A dielectric film 50 is located on the N ⁺ drain 30 in the transistor M ₁ , on which a conductive metal 45 interconnecting a biasing voltage source of the substrate 10 is disposed. To form the capacitor C. This capacitor C will be described later. For the capacitor C with a special structure, refer to “The Evolution Of DRA
M Cell Technology "by El-Kareh et al., Solid State
See Technology, May 1997, pp. 89-101.
Minimum storage capacitance of memory cell (storage capacitanc
In order to maintain e) at about 30-40 fF (femto farad), there was a need to improve these DRAM cell structures by complex semiconductor manufacturing processes. Note that PM
For DRAM cells employing OS transistors,
Since it can be constituted by the opposite polarity and procedure, it will not be described again.

In the prior art, a power supply voltage source is typically provided for the deep N-well 15.
Ource) V _cc (ie, the highest potential on the chip) was applied, and a substrate biasing voltage source V _ss (ie, the lowest voltage on the chip) was applied to the P-well 20. The substrate bias voltage source V _ss lower than the ground voltage (i.e., negative potential) With had reduced the leakage current (Leakage current) passing through the transistor M _1. If there is a charge in the capacitor C, the logic value is “1”,
If there is no charge, the logic value is “0”. And N ⁺ drain 30 in the capacitor C and the transistor M ₁ is connected, N ⁺ source 40 is connected to the bit line V _bit, and controlled the reading and writing of DRAM cells in the bit line V _bit. MOS transistor M ₁ of the gate 35 and the word line V _word is connected, it was used in the selection of the DRAM cell.

An erasable read-only memory (Erasable P)
rogrammable Read Only Memory (EPROM) or flash memory cell (flash memory cell)
As with the cell, the manufacturing method and its structure are known. In FIG. 2 (a), EPROM or flash memory cell is constructed on the MOS transistor M _1. The gate of the MOS transistor M ₁ and the capacitor C
Are coupled to each other, and also to the channel _{Cch of the} capacitor C. The gates of the MOS transistor M ₁ and the capacitor C have a floating gate structure.
And, a control voltage source (control voltage source) for the top plate of the capacitor C and the word line V _word.
e) and are connected. The upper plate of the capacitor C is a control gate (control) of the MOS transistor.
gate). Briefly represents the potential of the floating gate (i.e., the gate of the MOS transistor M _1), the following equation 1. Where γ is the coupling ratio of the control gate.

[0006]

V _fg = V _word + C / (C + C _ch ) = V
+ Γ

A flash memory cell and an EPROM
Although similar to cells, flash memory cells have a thin tunneling oxide, so that they can be electrically erased.

Referring to FIG. 2B, an EPROM or a flash memory cell is formed in a P-type substrate 110.
The deep N-well 115 has a low
When the S insulating film is formed, it is formed in the opening. A shallow P well 120 is formed in a deep N well 115. N ⁺ drain 130 and N ⁺ source 1 in shallow P well 120
40 are formed. Then, a relatively thin gate oxide film 132 is grown on the surface of the substrate 110. Typically, the thin gate oxide 132 of the flash memory cell has a thickness of about 90-120 °, and the thin gate oxide 132 of the EPROM has a thickness of about 150-250 °. The thin gate oxide film 132 of the flash memory cell promotes the passage of electrons during an erase cycle, and is therefore called a tunnel oxide film as described later. A floating gate 135 of polysilicon is formed on a channel region 137 between the drain 130 and the source 140. A dielectric film 134 is arranged on the floating gate 135 to separate it from the control gate 139 which is the second polysilicon. Next, P ⁺ is diffused into the P-type substrate 110 to provide a low resistance path from the terminal to the P-type substrate 110. This contact and the substrate voltage generator (substrate volt
age generator) V _ss is connected. Many EPR
In an OM or a flash memory, the substrate voltage generator V _ss is usually set to a ground reference potential (0 V). Also, the source 140 and a source control voltage generator (source con
and trol voltage generator) V _s is connected. The control gate 139 and the word line control voltage source V _word are connected. N ⁺ drain 130 and bit line voltage source _Vbit are connected.

According to conventional operation, an EPROM or flash memory cell is provided with a word line control voltage source generator V
Writing was performed by setting the _word to a relatively high negative voltage (-10 V). The bit line control voltage generator V _bit was set to a relatively high positive voltage (6 V). Source control voltage generator V _s had been set to the ground reference potential (0V). With such a voltage, hot electrons (hot ellipse) are generated in the channel region 137 near the drain 130.
ectrons), and these hot electrons have sufficient energy and are accelerated through tunnel oxide 132 and are trapped in floating gate 135. The captured electrons raise the threshold voltage of the memory cell by 3-5 volts compared to the control gate of the memory cell. Writing is performed by a change in threshold voltage caused by the captured hot electrons.
This writing method is commonly referred to as "channel hot electron" writing.

As another writing method, there is a Fowler-Nordheim type tunnel effect, and writing is performed by setting a word line control voltage generator V _word to a relatively high positive voltage (15 V). . Bit line control voltage generator V _bit and source control voltage generator V _s is
It was set to the ground reference potential (0 V). In this manner, an electric field was formed through the tunnel oxide film 132, and the magnitude was about 10 MV / cm. At this time, electrons penetrated from the drain 130 and the source 140 and the channel region 137 to the floating gate 135, and these hot electrons made the threshold voltage of the memory cell higher than the power supply voltage source _Vcc . In general, the time of the Fowler-Nordheim tunnel effect was greater than 1 msec.

In FIG. 2B, an EPROM or a flash memory cell includes a word line control voltage generator V _word.
To generate a positive voltage (approximately equal to _Vcc ) to perform electronic erasure. Source control voltage generator V _s had been set to a negative power supply voltage source (-V _cc). In this situation, a strong electric field was generated at a location where the source passed through the tunnel oxide film near the floating gate overlapping region 142. The electrons in the floating gate 135 were guided to the source 140 by the mechanism of the Fowler-Nordheim tunnel effect. The EPROM cell performs erasing by applying ultraviolet rays to the cell array. It is necessary to take a sufficient irradiation time, and the electrons appearing in the floating gate 135 can escape from the floating gate 135 only after acquiring sufficient energy from ultraviolet rays. The write / erase time of the DRAM cell is about 10 ^-7 sec, and the data retention time is about 100 to 1000 msec. After this time, if the data is not refreshed or restored, the leakage current of the capacitor C shown in FIG. 1A increases, causing data loss. The write / erase time of the EPROM or flash memory cell is about 10 msec, and the data retention time is about 10 years. At present, the trend of science and technology has made the tunnel oxide film 132 thinner and thinner, and the leakage current inside the tunnel oxide film 132 shortens the holding time.

No. 5,598,357 (No.
ble), a two-element nonvolatile memory cell was disclosed. This memory cell comprised a series of planar and vertical FETs. The floating gate of a vertical FET is a standard trench capacitor (eg, BE
a trench conductor consisting of l-Kareh et al.). The function of the control gate was performed by the buried N-well. Then, reading of the memory cells has been carried out by detecting the V _T of the vertical FET.

US Pat. No. 5,386,567 (Ac
ovic et al), Transistor nonvolatile RAM
A cell was disclosed in which the RAM cell was provided with two layers of floating gates, and when power was interrupted, the contents of the capacitors were transferred to the floating gates. The first layer floating gate and the storage node (storage) of the capacitor are formed by the tunnel oxide film.
node) to cause electron tunneling between the floating gate and the capacitor.

Note that the nonvolatile RAM cell has the following four types of operation procedures. (1) RAM, (2) Transfer (tran
sfer), (3) non-volatile storage, (4) recall (recal
l) / Erase. When power is interrupted, the RAM cell is in a transfer mode, transferring data from the charge storage node to the floating gate. When power is removed, the RAM cells operate in a non-volatile mode. When power is restored, the data is recalled and placed on the storage node and erased from the floating gate.

[0015]

The problem to be solved by the present invention is that a conventional stacked gate memory cell is
That is, it does not have a holding time comparable to an EPROM or a flash memory, and does not have a writing / erasing time comparable to a DRAM. Further, a complicated manufacturing process is required to maintain the minimum storage capacitance of the memory cell.

Accordingly, a first object of the present invention is to provide an EPR
It is to provide a stacked gate memory cell with a retention time equal to the OM or flash memory cell. A second object of the present invention is to provide a stacked gate memory cell having a write / erase time equal to that of a DRAM cell.

[0017]

In order to solve the above-mentioned problems and achieve a desired object, a structure of a stacked gate memory cell according to the present invention and a method of manufacturing the same are provided in a semiconductor substrate. Implanting a deep diffusion well and interconnecting the deep diffusion well and the deep diffusion voltage generator; implanting a second diffusion well of the second conductivity type in the deep diffusion well. ,
Implanting a drain diffusion region of the first conductivity type in the second diffusion well and interconnecting the drain diffusion region and the bit line voltage generator; one channel length from the drain diffusion region in the second diffusion well; Implanting a source diffusion region of the second conductivity type at a distance position of, and interconnecting the source diffusion region with the source control voltage generator while limiting the source diffusion region to the second diffusion well; Depositing a tunnel oxide film on the upper surface of the substrate to make the channel length the length of the channel region between the drain diffusion region and the source diffusion region. Forming a MOS transistor comprising depositing a gate comprising:
Depositing an insulating film on the upper surface of the semiconductor substrate, providing a plurality of openings, interconnecting the openings with the second diffusion well, the source diffusion region, and the gate; Depositing a first plate electrode comprising a first plate electrode, the first plate electrode interconnecting the insulating film with a gate through one of the plurality of openings by means of a shorting plug; Forming a floating gate of a MOS transistor with an electrode, depositing a capacitor dielectric film on a first plate electrode, depositing a second plate electrode made of a third polysilicon material on the capacitor dielectric film, Connecting the plate electrode to a word line voltage generator to form the control gate of the MOS transistor Forming a stacked capacitor comprising the steps of:

[0018]

The source diffusion region and the second diffusion well are connected to a source control voltage generator, and the drain diffusion region is connected to a bit line voltage generator. The upper plate electrode of the capacitor, which is the control gate of the MOS transistor, is connected to the word line voltage generator. The deep N-well diffusion region and the deep diffusion voltage generator are connected. Source control voltage generator, bit line voltage generator, word line voltage generator,
A deep diffusion voltage generator is used to program, erase, and delete digital data inside the stacked gate memory cell after adjustment.
Used to control sensing.

A plurality of stacked gate memory cells are
Arranged in an array of rows and columns, and through a source control voltage generator, a bit line voltage generator, a word line voltage generator, a deep diffusion voltage generator, a sense amplifier, and peripheral circuitry, Forming an integrated circuit memory. The sense amplifier detects digital data existing inside the stacked gate memory cell. Peripheral circuits control the source control voltage generator, bit line voltage generator, word line voltage generator, deep diffusion voltage generator, and sense amplifier.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below with reference to the drawings. 3 to 5, a field oxide film 220 is grown on the surface of the semiconductor substrate 210 (FIG. 4a), and three stacked gate memory cell regions (FIG. 3) are formed in openings between the field oxide films 220.
Is patterned. An N-type material of the first conductivity type is injected into the opening to form a deep P well 210. Then, the P well 215 is formed by implanting a P-type material of the second conductivity type using a mask in one region in the deep P well 210. A plurality of regions in the P well 215 are masked, and an N-type material of the first conductivity type is implanted to form an N ⁺ drain diffusion region 255 and an N ⁺ source diffusion region 265. Using a mask in one region near the N ⁺ source diffusion region 265, a P-type material of the second conductivity type is injected, and a P ⁺ contact 275 (FIG. 4B) is formed in the P well 215. Then, an insulating material film, for example, a silicon dioxide film or an oxidized silicon nitride film is grown on the surface of the semiconductor substrate 210 and on the upper surface of the channel 260 between the N ⁺ drain diffusion region 255 and the N ⁺ source diffusion region 265. This insulating material film becomes the tunnel oxide film 225 of the stacked gate memory cell. A first polysilicon P ₁ film is deposited on this tunnel oxide film 225 to form a gate 230. The gate transistor 230, the N ⁺ drain diffusion region 255, and the N ⁺ source diffusion region 265 allow the MOS transistor M ₁ shown in FIG.
Is composed. Next, an insulating film 285, for example, silicon dioxide, is deposited on the surface of the gate 230 and the remaining portion of the semiconductor substrate 210. After forming a plurality of contact holes (referring to the contact holes of the plug 235) on the insulating film 285 by lithography and oxide etching, a second polysilicon P ₂ film is deposited and etched to form a plug (P ₂ plug). 235 are formed. A third polysilicon P ₃ film 240 is deposited on the P ₂ plug 235.
Lower plate electrode 2 in the third polysilicon P ₃ film 240 is first plate electrode of the capacitor C shown in FIG. 5
40 are formed. In this manner, the floating gates of the stacked gate memory cell is constituted by a gate 230 and P ₂ plug 235 and lower plate electrode 240, the charge required to hold the digital data in the stacked gate memory cell accumulate.

4 and 5, a thin insulating film is deposited on the third polysilicon P ₃ film 240 to form a capacitor dielectric film 245 of the capacitor C. A fourth polysilicon P ₄ film 250 is deposited on the capacitor dielectric film 245 to form an upper plate electrode 250 which is a second plate electrode of the capacitor C, and the upper plate electrode 250 is connected to the control gate of the memory cell M ₁ . 250
And The deep diffusion voltage generator V _nw1 is then _{interconnected} with the deep N-well 210 to provide the necessary voltage biasing for the stacked gate memory cells and other circuits on the semiconductor substrate 210. The deep N-well 210 is typically connected to a deep diffused voltage generator _Vnw1 , _{thereby attaining} a positive power supply voltage source ( _Vcc ) level.

In FIG. 4, a P-well diffusion voltage generator V
_pwl is interconnected with P-well diffusion region 215. P-well diffusion region 215 via metal film 270 (FIG. 4b)
And the N ⁺ source diffusion region 265 are integrally fixed. P
Well diffusion region 215 and N ⁺ source diffusion region 265
And P ⁺ contacts 275 are both interconnected with a P-well diffusion voltage generator V _pwl (ie, V _s
= V _pwl ). Each row in the stacked gate memory cell array forms a P-well diffusion region 215. P
The well diffusion voltage generator _Vpwl can be individually applied to each row in the stacked gate memory cell array. Further, the N ⁺ drain diffusion region 255 and the drain control voltage generator _Vd are connected. In the stacked gate memory cell structure according to the present invention, the bit line voltage generator V _bit is used as the drain control voltage generator V _d, and the word line is connected to the fourth polysilicon P ₄ film 250. Power generator V _word .

By the way, those skilled in the art will understand that a conventional DRAM cell can be manufactured by the above-described manufacturing process of a stacked gate memory cell. In fact, the stacked gate memory cell and the conventional DRAM cell can be simultaneously formed on one integrated circuit chip.

FIG. 6 shows four stacked gate memory cells CELL11, CELL12, CELL21, CELL22. The first stacked gate memory cells CELL11 and CELL12 are controlled by a word line voltage generator V _word1 . Form a column, stacked gate memory cells CE
LL21 and CELL22 form a second column controlled by word line voltage generator V _word2 . Stacked gate memory cells CELL11 and CELL21, the bit line voltage generator V to form a first row that is controlled by _bit1, the second controlled by the bit line voltage generator V _bit2 in stacked gate memory cells CELL12 and CELL22 Form a row.

In FIG. 7, when programming the logic value "1" to the memory cell CELL11 (ie, injecting electrons into the floating gate of the memory cell CELL11), the bit line voltage generator V _bit1 (ie, the drain) The control voltage generator V _{d (} hereinafter the same) is set to the level of the negative power supply voltage source (−V _cc ). The word line voltage generator V _word1 has a positive power supply voltage source (+
V _cc ). Source control voltage generator V
_s is set to the level of the positive power supply voltage source (-V _cc).

When the bit line voltage generator V _bit1 and the source control voltage generator V _s are changed to the level of the power supply voltage source (-V _cc ), the N ⁺ drain diffusion region 255, the N ⁺ source diffusion region 265 and the P ⁺ Well diffusion region 2
A power supply voltage source having a negative voltage level of 15 (−
V _cc ). When the word line voltage generator V _word1 is set to the level of the positive power supply voltage source (+ V _cc ), the fourth polysilicon P ₄ film (upper plate of the capacitor C) 250 is connected to the positive power supply voltage source (V _cc ). Level. In such a situation, the distance between the fourth polysilicon P ₄ film 250 and the N ⁺
Well diffusion region 215 and N ⁺ source diffusion region 265
In between, the electric field expands. This expansion of the electric field causes the Fowler-Nordheim tunnel effect, which causes electrons e ⁻ to move to the floating gate 230 through the tunnel oxide film 225. Bit line voltage generator V
_bit1 (= V _d) and the word line voltage generator V _word1 and source control voltage generator V _s is a ground reference potential (0V)
When returning to the level, these electrons e ⁻ are trapped in the floating gate 230. In this manner, the threshold voltage V _T of the memory cell M ₁ shown in FIG. 5 is changed. When reading is performed, the threshold voltage _VT is changed by detecting a logic value “1” by a sense amplifier outside the stacked gate memory cell array.

The programming of the logic value "0" to the stacked gate memory cell array is performed by erasing a single memory cell. Non-volatile memory The term "program" refers to putting electrons into the floating gate. "Programming" of a logic value "1" or "0" is completed by programming and erasing, respectively. For a typical flash memory or EPROM, first, the entire array is erased to a logic value "0", and then the logic value "1" is set only for the array.
Is "written" or "programmed". EPROM
With regard to, since a single memory cell has program and erase capabilities, writing of a logic value “1” or “0” is performed for each memory cell.

The non-selective memory cell is formed by a combination of the bit line voltage generator V _bit1 (= V _d ), the word line voltage generator V _word1 and the level setting of the source control voltage generator V _s. , And programming is performed by suppressing non-selective memory cells at an arbitrary voltage set in Table 1 below for each memory cell.

[0029]

[Table 1]

When programming an entire column of stacked gate memory cells, a word line voltage generator V _word connected in the column direction is placed at the level of a power supply voltage source (V _cc ). Bit line voltage generator V _bit (= V _d) and a source control voltage generator V _s which is connected to each memory cell in the column direction, if when the memory cell becomes a logic value "1" by the program, negative Power supply voltage source (-
V _cc ) level, and if the memory cell becomes a logic value “0” by programming, it is placed at the level of the ground reference potential (0 V). When programming is performed for the entire row, the bit line voltage generator V in the row direction is used.
_bit and source control voltage generator V _s by the negative power supply voltage source in each row direction of the memory cell is placed in (-V _cc) level. The word line voltage generator V _word of each memory cell in the row direction is placed at the level of the power supply voltage source (V _cc ) and becomes a logic value “1” by a program or the level of the ground reference potential (0 V). And becomes a logic value “0” by the program.

Referring to FIG. 8, the erasure of a memory cell or the removal of any electrons from the floating gate will be described. First, when erasing a stacked gate memory cell, the word line power generator V _word1 uses a negative power supply voltage source ( -V _cc ) level. Bit line voltage generator V _bit1 and source control voltage generator V _s11 are placed at the level of the power supply voltage source (V _cc ). The bit line voltage generator V _bit1 (= V _d ), the word line power generator V _word1 and the source control voltage generator V _s11 are connected to the fourth polysilicon P4 film (upper plate of the capacitor C) 250 and N ⁺
The drain diffusion region 255;
An electric field is formed between P well 215 and N ⁺ drain diffusion region 265. Electrons e ⁻ are trapped in the floating gate 230 by the electric field of the tunnel oxide film 225, and are transferred to the P well 215, the N ⁺ drain diffusion region 255, and the N ⁺ source diffusion region 265 via the tunnel oxide film 225 by the Fowler-Nordheim tunnel effect. Relocate. Therefore, any electron e ⁻ trapped in the floating gate 230 can be erased. To remove the electrons e ⁻ in the floating gate 230,
To righting the threshold voltage V _T of the memory cell M _1.

The memory cells that have not been erased have their own bit line voltage generator V _bit, word line voltage generator V _word, and source control voltage generator V _s, and have the voltage levels shown in Table 2 below. Is set.

[0033]

[Table 2]

These voltage levels are set so that the memory cells that have not been erased cause the Fowler-Nordheim tunnel effect due to the lack of the electric field inside the tunnel oxide film.

To erase the entire memory cell in the column direction, the word line voltage generator V _word in the column direction is set at the level of the negative power supply voltage source (−V _cc ), and the bit line voltage generator V _bit and the source control voltage generator are generated. connect the vessel V _s in each memory cell in the column direction, erasing and with positive power supply voltage source (V _cc) level. Further, erasing in the entire row direction is performed by all word line voltage generators V connected to each memory cell in the row direction.
_word a negative power supply voltage source (-V _cc) placed level, the row direction of the bit line voltage generator V _bit (= V _d) and a source control voltage generator V _s a positive power supply voltage source (V _cc ) Set to level and erase. Then, erasing the entire array places the word line voltage generator V _word at the negative power supply voltage source (-V _cc ) level, and all bit line voltage generators V _bit (= V _d ) and source control voltage generation erasing the vessel V _s positive power supply voltage source placed (V _{c c)} levels.

In FIG. 8B, digital data stored in an array of stacked gate memory cells is supplied to a source control voltage generator _Vs11 by a power supply voltage source (0
V) Read at level. The word line voltage generator V _word1 is _placed at the positive power supply voltage source (V _cc ) level, and the bit line voltage generator V _bit1 (= V _d ) is pre-charged to halve the power supply voltage source (V _cc / 2) Put it on the level. If a logic value "0" is erased or programmed is stacked gate memory cell CELL11 If, MOS and the threshold voltage V _T of the memory cell is lowered
The transistor M ₁ is turned on (conducting). At this time, a sense amplifier (not shown) connected to the bit line detects the signal and changes the logic value to “0”. However, if the case where the stacked gate memory cell CELL11 becomes a logic value "1" is programmed, the threshold voltage V _T of the memory cell rises to the MOS transistor M ₁ off (non-conducting). In this situation, since the voltage (V _cc / 2) appearing on the bit line is not changed, the sense amplifier connected to the bit line detects it and becomes a logic value "1". The control of the set values for the bit line voltage generator V _bit and the word line voltage generator V _{word, the} source control voltage generator V _s and the sense amplifier is performed by an external peripheral circuit connected to an array of stacked gate memory cells. Performed by

"High Endurance Ultra-Thin Tunnel Oxi
de For Dynamic Memory ", C. Wann and C. Hu, Proceedi
In ngs of IEDM, IEEE, 1995, p.867, it is described that an ultra-thin tunnel oxide film causes a very high-speed Fowler-Nordheim tunnel effect when a memory cell is programmed or erased. Therefore, if the thickness of the tunnel oxide film according to the present invention is about 60 to 70 °,
The program / erase time is in the range of about 10 to 100 ns. The stacked gate memory cell structure according to the present invention is similar to that disclosed by El-Kareh et al., Each having a large capacitance and having a high coupling ratio (γ = about 0.95). The control gate coupling ratio (γ) is obtained by dividing the capacitor C from the control gate to the floating gate by the total capacitance (C _tot ) measured at the floating gate, and C _tot =
C + C _ch + other stray capacitanc
e). C _ch is control gate 2
30 and the capacitance between channel 260 (FIG. 4b). Therefore, the coupling ratio can be expressed by the following Equation 2.

[0038]

Γ = C / C _tot = C / (C + C _ch )

In the stacked gate memory cell according to the present invention, the value of the capacitor C is about 30 fF, and the capacitance between the floating gate 230 and the channel 260 is about 1 fF. 97
It is. When a bias voltage is applied to the control gate, the control of the floating gate potential can be simplified if the coupling ratio (γ) is large. The floating gate potential (V _fg ) can be expressed by the following Equation 3. In the equation, Q is the net charge of the floating gate (net el
ectron charge).

[0040]

V _fg = γV _word + (1−γ) V _pwl + Q /
C _tot V _word + Q / C _tot

[0041] If there exists a negative charge on the floating gate 230, a V _fg = V _T. The threshold voltage of the word line voltage generator V _word is expressed by the following equation (4).

[0042]

## EQU4 ## V _word = V _T + C / C _tot

The above-mentioned thin tunnel oxide film 225 (about 60
Å70 °), at a _Vcc operating voltage of 5V, its thickness is sufficient to avoid long term (one month or more) data retention.

The tunnel oxide film structure of the stacked gate memory cell according to the present invention can provide the same retention time as the EEPROM and a relatively long program / erase time. Alternatively, a program having a relatively short holding time similar to that of a DRAM but having a relatively high
An erasure time can be provided. The holding time is E
Although shorter than EPROM (about 10 years), DRAM (about 2 years)
00ms). DRAMs and EEPROMs are similar, are useful as a data storage method, and have excellent write characteristics even at low power. In particular, short periods of time (about 1
Months), the accumulated data becomes non-volatile.

[0045] In FIG. 9, when explaining the program operation and timing control for write time, first 9, as shown in (a), the source control voltage generator during program operation start V _s and P-well diffusion voltage generator V
_pwl becomes negative power supply voltage source (-V _cc) level and the bit line voltage generator V _bit negative power supply voltage source (-V _cc) level at the same time, the force supplied to the word line voltage generator V _word It is set to the voltage source ( _Vcc ) level. In other words, once the channel is reversed, the source control voltage generator V _s and P-well diffusion voltage generator V _pwl a negative power supply voltage source becomes (-V _cc) level and the word line voltage generator V _word plus When the power supply voltage source (V _cc ) level is reached, the bit line voltage generator V _bit enters a high resistance state.

The thickness of the tunnel oxide film is relatively thick (about 1
00Å), the programming time of the stacked gate memory cell becomes longer than 10 msec. However, when the thickness of the tunnel oxide film is small (about 60 to 70 °), the programming time of the stacked gate memory cell becomes shorter than 10 nsec.

[0047] In FIG. 9 (b), the erase operation, when the program operation starts, the source control voltage generator V _s and P
The well diffusion voltage generator V _pwl is at the level of the positive power supply voltage source (+ V _cc ), and the bit line voltage generator V _bit is at the same time as the level of the positive power supply voltage source (+ V _cc ). the _word negative force supply voltage source and (-V _cc) level. That is, once the source control voltage generator V _s and the P-well diffusion voltage generator V _pwl are at the power supply voltage source (+ V _cc ) level, the bit line voltage generator V _bit goes into a high resistance state and the P-well When a small forward bias voltage is applied to the junction between the bit line and the bit line, the bit line voltage generator V _bit causes the power supply voltage source (+ V
_cc ) clamped to the level.

As described above, the present invention has been disclosed by the preferred embodiments. However, as will be easily understood by those skilled in the art, appropriate changes and modifications can be made within the technical idea of the present invention. Therefore, the scope of patent protection must be determined based on the claims and their equivalents.

[0049]

As described above, the stacked gate memory cell according to the present invention can provide the same retention time as the EEPROM and a relatively long program / erase time due to its tunnel oxide film structure. Alternatively, it has a relatively short holding time similar to a DRAM,
A relatively fast program / erase time can be provided. Its retention time is shorter than EEPROM (about 10 years) but longer than DRAM (about 200 ms). Also,
It has excellent write characteristics even at low power. In particular, in a short time (about one month) when the power supply voltage source is deficient, the accumulated data becomes non-volatile. Therefore, the industrial use value is high.

[Brief description of the drawings]

FIG. 1A is a circuit diagram illustrating a DRAM according to a conventional technique, and FIG. 1B is a cross-sectional view illustrating the semiconductor device.

FIG. 2A is a circuit diagram illustrating an EEPROM according to the related art, and FIG. 2B is a cross-sectional view illustrating the semiconductor device.

FIG. 3 is a plan view showing a stacked gate memory cell according to the present invention.

FIG. 4A is a cross-sectional view showing a stacked gate memory cell taken along the line 4A-4A 'in FIG. 3, and FIG. 4B is a cross-sectional view taken along the line 4B-4B' in FIG. FIG. 9 is a cross-sectional view showing the displayed stacked gate memory cell.

FIG. 5 is a circuit diagram showing a stacked gate memory cell according to the present invention.

FIG. 6 is a circuit diagram showing a stacked gate memory cell array according to the present invention.

FIG. 7A is a cross-sectional view showing a state in which a logic value “1” is programmed in the stacked gate memory cell according to the present invention. FIG. 7B is a sectional view showing a state in which the logic value “1” is programmed. FIG. 4 is a circuit diagram showing a state in which the operation is performed.

FIG. 8A is a cross-sectional view showing a state where an erase operation is performed in the stacked gate memory cell according to the present invention, and FIG. 8B is a circuit diagram showing a state where the erase operation is performed.

FIG. 9A is a timing chart showing a program cycle of the stacked gate memory cell according to the present invention, and FIG. 9B is a timing chart showing an erase cycle.

[Explanation of symbols]

210 Semiconductor substrate (deep diffusion well) 215 P well (second diffusion well) 220 Field oxide film 225 Tunnel oxide film 230 Gate (floating gate) 235 Plug (P ₂ plug / short plug) 240 Lower plate electrode (third polysilicon) P ₃ film / first plate electrode) 245 capacitor dielectric layer 250 a control gate (fourth polysilicon P ₄
255 N ⁺ drain diffusion region (drain diffusion region) 260 channel (channel region) 265 N ⁺ source diffusion region (source diffusion region) 285 insulating film V _bit bit line voltage generator V _word word line voltage Generator V _nwl N well diffusion voltage generator (deep diffusion voltage generator) V _pwl P well diffusion voltage generator V _s source control voltage generator V _d drain control voltage generator

Claims (23)

[Claims] 1. A deep diffusion well of a first conductivity type which is implanted in a semiconductor substrate and interconnects with a deep diffusion voltage generator, and a second implant which is implanted in the deep diffusion well. (C) a MOS transistor, wherein the MOS transistor is formed by injecting the first conductivity type material into the second diffusion well and interconnected with a bit line voltage generator; And a region formed by injecting the second conductivity type material into the second diffusion well, located at a distance of one channel length from the drain diffusion region and interconnecting with a source control voltage generator. A source diffusion region; and a tunnel acid disposed on the semiconductor substrate in the channel region, wherein the length of the channel is the length of the channel region between the drain diffusion region and the source diffusion region. A MOS transistor comprising: a first polysilicon material disposed on the tunnel oxide film on the upper surface of the channel region; and a plurality of MOS transistors located on the semiconductor substrate. An insulating film provided with an opening to interconnect with the second diffusion well, the drain diffusion region, the source diffusion region, and the gate; and (e) a stacked capacitor, which is deposited on the insulating film and short-circuited. The insulating film is interconnected with the gate through one of the plurality of openings in the insulating film through a plug, and the MOS is connected together with the gate.
A first plate electrode made of a second polysilicon material forming a floating gate of the transistor; a capacitor dielectric film disposed on the first plate electrode; a word line voltage generator disposed on the capacitor dielectric film A stacked capacitor comprising: a second plate electrode made of a third polysilicon material interconnected with the second transistor and forming a control gate of the MOS transistor; and a stacked capacitor comprising: Structure. 2. (a) A plurality of stacked gate memory cells are arranged as an array, wherein the array is a plurality of rows and a plurality of columns, and each stacked gate memory cell is located in a semiconductor substrate. A first conductivity type deep diffusion well implanted into the deep diffusion well; a second conductivity type second diffusion well implanted inside the deep diffusion well; and a first conductivity type material in the second diffusion well. A drain diffusion region implanted into the second diffusion well and formed by injecting the second conductivity type material into the second diffusion well, and located at a distance of one channel length from the drain diffusion region; A source diffusion region defined in a diffusion well, and a channel disposed on an upper surface of the semiconductor substrate in a channel region, wherein a length of the channel is a length between the drain diffusion region and the source diffusion region. And a first oxide film located on the tunnel oxide film on the upper surface of the channel region.
MO composed of a gate made of a polysilicon film and
An S transistor, which is located on the semiconductor substrate and has a plurality of openings, wherein these openings are interconnected with the second diffusion well, the drain diffusion region, the source diffusion region, and the gate. An insulating film, deposited on the insulating film, penetrating through one of the plurality of openings in the insulating film through a short-circuit plug, interconnected with the gate, and the MOS together with the gate;
A first plate electrode made of a second polysilicon material forming a floating gate of the transistor;
A second capacitor dielectric film disposed on the plate electrode and a second polysilicon material disposed on the capacitor dielectric film and interconnected with a word line voltage generator to form a control gate of the MOS transistor; A plurality of stacked memory cells comprising: a stacked capacitor comprising: a plate electrode; and (b) a plurality of stacked memory cells each arranged in a column direction of the array of the stacked gate memory cells. A plurality of word line voltage generators connected to the second plate electrode of each stacked capacitor in the stacked gate memory cell; and (c) each connected to the drain diffusion region of the stacked gate memory cell. A plurality of bit line voltage generators arranged in a row direction of said array of said stacked gate memory cells (D) a deep diffusion voltage generator connected to a deep diffusion well of each of the stacked gate memory cells; and (e) each being connected to the source diffusion region, and A plurality of source control voltage generators connected to the diffusion well and each stacked gate memory cell being arranged in one row direction of the plurality of rows; A plurality of sense gates connected to the drain diffusion region, wherein each stacked gate memory cell is arranged in one row direction among the plurality of rows and detects digital data stored in each stacked gate memory cell. (G) each connected to the plurality of word line voltage generators; connected to the plurality of bit line voltage generators; Connected to the pressure generator, connected to the plurality of source control power generator, connected with said plurality of sense amplifiers,
And a plurality of peripheral circuits for controlling programming, erasing, and detection of the plurality of stacked gate memory cells. 3. A method comprising: (a) implanting a deep diffusion well of a first conductivity type in a semiconductor substrate and interconnecting the deep diffusion well and a deep diffusion voltage generator; and (b) the deep diffusion. Implanting a second diffusion well of the second conductivity type in the well; and (c) forming a MOS transistor, wherein a drain diffusion region of the first conductivity type is implanted in the second diffusion well. Interconnecting the drain diffusion region and the bit line voltage generator; and a second conductivity type source diffusion region located at a distance of one channel length from the drain diffusion region in the second diffusion well. Implanting and limiting to within the second diffusion well and interconnecting the source diffusion region and a source control voltage generator; and Depositing a tunnel oxide film on the surface to make the channel length the length of the channel region between the drain diffusion region and the source diffusion region; and Depositing a gate made of a first polysilicon material; and forming a MOS transistor comprising: (d) depositing an insulating film on the upper surface of the semiconductor substrate and providing a plurality of openings; Interconnecting the opening with the second diffusion well, the source diffusion region, and the gate; and (e) forming a stacked capacitor, wherein a second capacitor made of a second polysilicon material is formed on the insulating film. One plate electrode is deposited, and the first plate electrode is connected to one of the plurality of openings by the short-circuit plug. Forming a floating gate of said MOS transistor with said gate and said first plate electrode, interconnecting said gate with said first plate electrode; depositing a capacitor dielectric film on said first plate electrode; Depositing a second plate electrode made of a third polysilicon material on the dielectric film, connecting the second plate electrode to a word line voltage generator,
A method of manufacturing a stacked gate memory cell, comprising: forming a control gate of a transistor; and forming a stacked capacitor including: 4. The structure of a stacked gate memory cell according to claim 1, wherein the deep diffusion voltage generator is a power supply voltage source, and a method of manufacturing the same. 5. The stacked gate memory cell of claim 1, wherein the retention time is substantially longer than that of a DRAM.
4. The structure of a stacked gate memory cell according to claim 3, and a method of manufacturing the same. 6. The structure of a stacked gate memory cell according to claim 5, wherein said holding time is longer than 200 ms. 7. The structure of a stacked gate memory cell according to claim 1, wherein the retention time is shorter than that of an EEPROM. 8. The structure of a stacked gate memory cell according to claim 7, wherein said retention time is shorter than 10 years. 9. The program time is about 10 ns to 10 ns.
The structure of the stacked gate memory cell according to any one of claims 1 to 3, which is in the range of ms, and a manufacturing method thereof. 10. The structure of a stacked gate memory cell according to claim 1, wherein the erase time is in a range of about 10 ns to 10 ms. 11. The structure of a stacked gate memory cell according to claim 1, wherein said memory cell is a DRAM cell, and a method of manufacturing the same. 12. The structure of a stacked gate memory cell according to claim 1, wherein said memory cell is an EEPROM cell, and a method of manufacturing the same. 13. The method according to claim 1, wherein the thickness of the tunnel oxide film is about 60.
The structure of a stacked gate memory cell according to any one of claims 1 to 3, and a manufacturing method thereof, wherein the angle is up to 70 °. 14. The method according to claim 1, wherein the thickness of the tunnel oxide film is about 10
The structure of a stacked gate memory cell according to any one of claims 1 to 3, and a method of manufacturing the same, wherein 0 °. 15. The method according to claim 15, wherein the coupling ratio of the memory cells is about 0.9.
The structure of the stacked gate memory cell according to any one of claims 1 to 3, and a manufacturing method thereof. 16. The method according to claim 16, wherein the logic value of the memory cell is set to "1" by programming the bit line voltage generator to the negative power supply voltage source level and the word line voltage generator to the positive power supply voltage. 2. The method according to claim 1, wherein the power source voltage level is set to be negative, the source control voltage generator is set to the negative power supply voltage source level, and the deep diffusion voltage generator is set to the positive power supply voltage source level. 4. The structure of a stacked gate memory cell according to claim 3, and a method of manufacturing the same. 17. The method according to claim 17, wherein the logic value of the memory cell is set to "0" by programming, the bit line voltage generator is set to a ground reference potential, the word line voltage generator is set to the positive power supply voltage source level, 2. The method of claim 1, wherein the source control voltage generator is at the negative power supply voltage source level and the deep diffusion voltage generator is at the positive power supply voltage source level.
4. The structure of a stacked gate memory cell according to claim 3, and a method of manufacturing the same. 18. The method of claim 17, wherein the erasing in the memory cell comprises: setting the word line voltage generator to the negative power supply voltage source level; setting the bit line voltage generator to the positive power supply voltage source level; 4. The method according to claim 1, wherein the voltage generator is at the negative power supply voltage level and the deep diffusion voltage generator is at the positive power supply voltage level.
A structure of a stacked gate memory cell according to any one of claims 1 to 4, and a method of manufacturing the same. 19. The program for a row of the plurality of stacked gate memory cells may include simultaneously setting the bit line voltage generator to the negative power supply voltage source level and setting the word line voltage generator to the positive power supply voltage. The supply voltage source level is programmed in the row of the plurality of stacked gate memory cells to a logic value “1”, and the word line voltage generator is set to the ground reference potential level to set the plurality of stacked gate memory cells. Programming in the row of gate memory cells to a logic value "0", the source control voltage generator at the negative power supply voltage source level, and the deep diffusion voltage generator at the positive power supply voltage source level; The structure of the stacked gate memory cell according to claim 2 or 4, wherein 20. A program for a column of said plurality of stacked gate memory cells, wherein said bit line voltage generator is simultaneously set to said negative power supply voltage source level. And the word line voltage generator is set to the ground reference potential level, and the program in the column of the plurality of stacked gate memory cells is performed to set the logic value to "0". And the source control voltage generator being at the negative power supply voltage source level and the deep diffusion voltage generator being at the positive power supply voltage source level.
5. The structure of the stacked gate memory cell according to claim 4. 21. Erasing a row of the plurality of stacked gate memory cells causes all of the plurality of bit line power generators to be at the negative power supply voltage source level;
And connecting the plurality of stacked gate memory cells in the row to the plurality of stacked gate memory cells in the row and setting the bit line power generator in the row to the positive power supply voltage source level. 5. A stack according to claim 2 or claim 4, wherein the source control voltage generator of the cell is at the positive power supply voltage source level and the deep diffusion voltage generator is at the positive power supply voltage source level. Gate memory cell structure. 22. Erasing a column of the plurality of stacked gate memory cells causes the plurality of bit line power generators to be at the negative power supply voltage source level and the plurality of stacks in the row. Connected to the gate memory cells, all of the plurality of bit line power generators of the plurality of stacked gate memory cells are at the positive power supply voltage source level, and connected to the column, and all of the plurality of stacked gate memory cells are connected to the column. The plurality of source control voltage generators of a stacked gate memory cell being at the positive power supply voltage source level and connected to the column, and the deep diffusion voltage generator being at the positive power supply voltage source level The structure of the stacked gate memory cell according to claim 2 or 4, wherein 23. An erase operation on the array of the plurality of stacked gate memory cells causes the plurality of bit line power generators of the plurality of stacked gate memory cell arrays to have a negative power supply voltage source level. Wherein all of the plurality of word line power generators of the array are at the positive power supply voltage source level, and all of the plurality of source control voltage generators of the array are at the positive power supply voltage source level; The structure of a stacked gate memory cell according to claim 2 or 4, wherein the deep diffusion voltage generator is at the positive power supply voltage source level.