TW426985B - Landing via of semiconductor wafer - Google Patents

Abstract

This invention provides a kind of landing via fabricated in a semiconductor wafer. The semiconductor wafer surface includes a substrate and a dielectric layer. The landing via includes the followings: a plug hole, which is installed in the dielectric layer and punches through this dielectric layer until reaching the substrate surface; a conduction layer, which is installed in the plug hole and contacts with the substrate surface; and a protection layer, which is installed on the upper end of this plug hole and surrounds the periphery of the conduction layer top portion. The landing via of this invention can be used to increase the alignment tolerance of the following process and avoid the etching of dielectric layer which is caused by the following etch process on the upper opening of the plug hole.

Description

4269 8 5_ 5. Description of the invention (i) The present invention provides a via via made in a semiconductor wafer, especially a via via with a protective structure. Background Description The memory cell of a dynamic random access memory is mainly composed of a metal-oxide semiconductor (MOS) transistor, a capacitor, and a contact plug. The transfer channel is used in a contact plug as a node contact to smoothly connect the MOS transistor to the capacitor. With the reduction in the size design of semiconductor devices, it becomes very difficult to make smaller transfer channels without affecting the performance of the M0S transistor. Therefore, how to improve the structure of the transfer channel and thereby improve the yield of the process has become An important issue in semiconductor manufacturing. Please refer to FIG. 1, which is a schematic cross-sectional view of a conventional transfer channel 24. It is known that the switching channel 24 formed in a semiconductor wafer 10 is used as an electrical connection between a transistor and other components. The semiconductor wafer 10 includes a substrate 12 composed of single crystal silicon, an M0S transistor 2 2 disposed on the substrate 12, and a dielectric composed of silicon dioxide (Si02). The layer 20 is disposed on the substrate 12 and covers the entire MOS transistor 22 to avoid a short circuit between the transistor 22 and other components. The transfer channel 24 includes a plug hole 26 penetrating the dielectric layer 20 to the surface of the substrate 12, and a conductive layer 28 is disposed in the plug hole 26 and is in contact with the surface of the substrate 12. Conductive layer

V. Description of the invention ug). 2 8 rt, using & Tian Yi doped polycrystalline silicon (doped as—polycrystalline silicon plug (ρ 〇1 y P1 please refer to Figure 2 and Figure 3, Figure 2 and Figure 3 are Figure 1 transfer channel 2 4 of, Schematic cross-sectional view of the method. Known manufacturing method of the transfer channel 24. First-a lithography process 'forms a photoresist layer 23 on the semiconductor wafer 10' and a hole 25 is defined thereon to define a plug hole 26. And the position is small. Then an anisotropic (anis 〇tr 〇pic) etching process is performed, and the dielectric layer 20 is etched vertically downward along the hole 25 to form a plug hole 26, as shown in FIG. After the photoresist layer 23 is completely removed, a doped polycrystalline silicon layer 27 is deposited on the surface of the semiconductor wafer 10 by a thin film deposition process (thin fnm deposition), and the doped polycrystalline silicon layer 27 is completely filled. The plug hole 2 6 ′ is shown in FIG. 3. Finally, an etching process is performed to remove the polycrystalline silicon layer 28 covering the surface of the dielectric layer 20, leaving only the polycrystalline silicon layer 27 inside the plug hole 26 as the plug hole 26. The conductive layer 28 completes the production of the transfer channel 24 shown in Fig. 1. The plug hole 2 of the transfer channel 24 The size of 6 is limited by the size of the transistor 22. As the size of the transistor 22 is getting smaller, the size of the plug hole 2 6 is getting smaller. Therefore, it is not easy in the subsequent yellow light process. The pattern of the subsequent film is aligned with the plug hole 26, and the tolerance (a 1 ignmentt ο 1 erance) of the alignment in the post-production process is reduced. For example, the pattern of the electrode contact cannot be aligned with the active area. Therefore, the transistor 22 cannot form a good electrical connection with other components.

4269, V. Description of the invention ¢ 3) Please refer to 24. Figure 4 is a schematic diagram of a dielectric layer 29 formed in a square shape on the transfer channel 24 shown in Figure 1. An electrode contact may be formed above the switching channel 24 so that the switching channel 24 can be brought into contact with a conductive layer to be formed subsequently, so that the transistor 22 can be electrically connected to other components. First, another dielectric layer 29 mainly composed of silicon dioxide is deposited on the dielectric layer 20 as an insulating layer between subsequent components or metal lines. The portion of the dielectric layer 29 above the opening of the via 24 is then removed by an etching process to make electrode contacts. In the etching process of the dielectric layer 29, by adjusting the etching selection ratio, the #etching rate of silicon dioxide can be increased. The crystal engraving rate is 51 higher. Therefore, when the dielectric layer 29 is touched at the transition When the portion above the opening of the channel 24 is formed, the surface of the conductive layer 28 made of polycrystalline silicon will become the end point of the etching to prevent the etching from proceeding downward. In contrast, for the dielectric layers 20 and 29 which are of similar material (both are composed of silicon dioxide), after the etching reaches the bottom of the dielectric layer 29, the dielectric layer 2 may be etched downwards. 0. Therefore, the dielectric layer 20 located around the opening at the upper end of the plug hole 26 is prone to over etching, and the structure of the transfer channel 24 is destroyed. When the over-etching reaches a certain depth, it may cause a short circuit between the conductive layer 28 or the subsequently-produced components and the MOS transistor 22, and even damage the structure of the MOS transistor 22, thereby affecting the yield of the entire process. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a transfer channel with a protective layer structure to increase the tolerance of alignment in subsequent processes and achieve

Page 6 4269 85 Explanation of the 5 'invention (4) Purpose of protecting the dielectric layer. In a preferred embodiment of the present invention, the surface of the semiconductor wafer includes a substrate, a dielectric layer, and a via. The transfer channel includes a plug hole disposed in the dielectric layer and penetrating the dielectric layer up to the substrate surface, a conductive layer is provided in the plug hole and is in contact with the substrate surface, and _ 二 _ protection A layer is disposed on the upper end of the plug hole and surrounds the top of the conductive layer. The switching channel of the present invention expands the area of the opening at the upper end of the plug hole, thereby improving the accuracy of alignment in subsequent processes. In addition, the protective layer can protect the dielectric layer around the opening at the upper end of the transfer path from the subsequent etching process. Therefore, the excessive etching of the dielectric layer can be avoided, thereby protecting the structure of the MOS transistor. Brief description of the diagrams. First is a schematic cross-sectional view of a conventional transfer channel. Figures 2 and 3 are schematic cross-sectional views of the manufacturing method of the first transfer channel. FIG. 4 is a schematic diagram of forming a second dielectric layer over the transition channel shown in FIG. FIG. 5 is a schematic cross-sectional view of a transfer channel according to the present invention. FIG. 6 is a schematic cross-sectional view of forming the plug hole shown in FIG. 5. FIG. 7 is a schematic cross-sectional view of the doped polycrystalline silicon layer shown in FIG. 5.

4269 B b 5. Description of the invention (5) Figure. FIG. 8 is a schematic cross-sectional view of forming the conductive layer shown in FIG. 5. FIG. 9 is a schematic cross-sectional view of the annular shallow pit shown in FIG. 5. FIG. 10 is a schematic cross-sectional view of the silicon nitride layer shown in FIG. 5. Description of symbols in the illustration 10 Semiconductor wafer 12 Substrate 20 Dielectric layer 22 MOS transistor 23 Photoresist layer 24 Transfer channel 25 Hole 26 Plug hole 27 Doped polycrystalline silicon layer 28 Conductive layer 29 Dielectric layer 30 Semiconductor wafer 32 Substrate 40 Dielectric layer 42 MOS transistor 43 Photoresist layer 44 Transfer channel 45 Doped polycrystalline silicon layer 46 Plug hole 47 Hole 48 Conductive layer 50 Shallow annular pit 52 Silicon nitride layer 54 Protective layer For a detailed description of the invention, please refer to the figure Fifth, FIG. 5 is a schematic cross-sectional view of the transfer channel 44 of the present invention. The present invention is a transition channel 4269 8 5 fabricated in a semiconductor wafer 30 5. Invention description (6) 44. The surface of the semiconductor wafer 30 includes a substrate 32 composed of single crystal silicon, a MOS transistor 42 is disposed on the substrate 32, and a dielectric layer 40 composed of silicon dioxide is disposed on the substrate 32 and covers the entire MOS. The transistor 42 is used to avoid a short circuit between the transistor 42 and other components. The via 44 of the present invention includes a plug hole 46 having a columnar structure provided in the dielectric layer 40 and penetrating the dielectric layer 40 to the surface of the substrate 32. A conductive layer 48 made of doped polycrystalline silicon is provided on the The plug hole 46 is in contact with the surface of the substrate 42 and serves as a polycrystalline stone plug, and a protective layer 54 composed of si 1 ic η nitride (SJ) is provided in the plug hole. The upper end of 46 surrounds the top of the conductive layer 48, and is used to protect the dielectric layer 40 at the upper end of the plug hole 46. The diameter of the opening at the upper end of the plug hole 46 is larger than the diameter of the columnar structure to form a circular shallow pit 50. For expanding the area of the upper end of the plug hole, please refer to FIGS. 6 to 8. 6 is a schematic cross-sectional view of forming the plug hole 46 shown in FIG. 5, FIG. 7 is a cross-sectional schematic view of forming the doped polycrystalline silicon layer 4 5 shown in FIG. 5, and FIG. 8 is a conductive layer 4 8 shown in FIG. 5. Schematic cross-section. As shown in FIG. 6, the manufacturing method of the transfer channel 44 of the present invention first performs a yellow light process, forming a photoresist layer 43 on the semiconductor wafer 30, and a hole 4 7 is defined on the semiconductor wafer 30 to define the position of the plug hole 46. With size. Then, an anisotropic etching process is performed, and the dielectric layer 40 is etched vertically downward along the hole 47 to form a plug hole 46. Then the photoresist layer 43 is completely removed. As shown in FIG. 7, a doped polycrystalline silicon layer 45 is deposited on the surface of the semiconductor wafer 30 by a thin film deposition process to completely fill the plug hole 46. As shown in Figure 8,

V. Description of the invention (7) An etching process is performed to remove the polycrystalline silicon layer 45 covering the surface of the dielectric layer 40, leaving only the polycrystalline silicon layer 45 in the plug hole 4 6 as the conductive layer 48 to complete the polycrystalline silicon plug. Fabrication 8 Please refer to FIG. 9 and FIG. 10. FIG. 9 is a schematic cross-sectional view of forming the ring-shaped shallow pit 50 in FIG. 5, and FIG. 10 is a schematic cross-sectional view of forming the silicon nitride layer 52 in FIG. As shown in FIG. 9, after the fabrication of the polycrystalline silicon plug is completed, a wet, wetetching process is performed, and hydrofluoric acid (HF) is diluted by adding water at a ratio of 10: 1 to the dielectric layer. Wet etching is performed at 40 to form a circular shallow pit 50 at the upper end opening of the plug hole 46, which is used to expand the area of the upper end of the plug hole 46. As shown in FIG. 10, a second thin film deposition process is performed next, and a silicon nitride layer 52 is deposited on the surface of the dielectric layer 40 and the annular shallow pit 50. As shown in FIG. 5, an anisotropic etching process is finally performed to remove the silicon nitride layer 52 on the surface of the dielectric layer 40 and the conductive layer 48, and at the junction of the annular shallow pit 50 and the dielectric film 40 A protective layer 54 is formed similar to a spacer structure, and the protective layer 54 surrounds the top of the conductive layer 48 to protect the dielectric layer 40 at the upper end of the plug hole 46. The transfer channel 44 of the present invention is characterized in that it includes a ring-shaped shallow pit 50 with a large opening area and a protective layer 54 that can protect the dielectric layer 40. As the ring-shaped shallow pit 50 increases the opening area of the upper end of the plug hole 46, the tolerance of the alignment can be increased in the subsequent process, so that the pattern of the subsequent film can be aligned with the transfer channel 44. Taking this embodiment as an example, the protective layer 5 4 on each side can increase the alignment tolerance of 0.02 / zm, and the entire transfer channel 44 can be increased by 0.04.

P. 10 b 4269 V. Specify the tolerance of alignment (8). In addition, the switching channel 44 of the present invention uses the protective layer 54 as the end point of the engraving to prevent the dielectric layer 40 adjacent to the ring-shaped shallow pit 50 from being etched by the subsequent etching process, thereby avoiding affecting the transistor 42 provided in the dielectric layer order. Therefore, the via 44 of the present invention can improve the alignment accuracy in subsequent processes, and protect the dielectric layer 40 'next to the ring-shaped shallow pit 50, thereby improving the yield of the semiconductor process. Compared with the conventional transfer channel 24, the transfer channel of the present invention includes a ring-shaped shallow pit 50 provided at the upper opening of the plug hole 46, and a protective layer 54 provided in the ring pit 50 and surrounding the top of the conductive hole 48. around. The annular shallow pit 50 can expand the area of the opening at the upper end of the plug hole 46, so that it can improve the alignment ratio in subsequent processes. In addition, the protective layer 54 can protect the “upper opening of the transition channel” = the dielectric layer 40 from being eroded by the subsequent etching process, so that excessive etching of the dielectric layer can be avoided, thereby protecting the structure of the MOS transistor. Please apply The BN issue of the book is specifically based on the issue of the book? The examples should be Shi Jieshi 'The Jiajin repair and the Minghua version are the only descriptions of the book. The scope is covered by the scope and scope.

Claims (1)

4269 8 5 VI. Scope of patent application 1. A landing via fabricated in a semiconductor wafer. The surface of the semiconductor wafer includes a substrate, and a dielectric layer is disposed on the substrate. The transfer channel includes:-a plug hole provided in the dielectric layer and penetrating the dielectric layer to the surface of the substrate; a conductive layer provided in the plug hole and opposite to the surface of the substrate Contact; and a protective layer, which is disposed at the upper end of the plug hole and surrounds the top of the conductive layer to protect the dielectric layer at the upper end of the plug hole. 2. For example, the Lufa method of the scope of patent application, wherein the plug hole is a columnar structure, and the diameter at the upper end opening is larger than the diameter of the columnar structure, which is used to expand the upper hole of the plug hole. Area. 3. As for the method in the first scope of the patent application, it is claimed that the plug hole is used to form a contact plug or a via plug. 4. For the diners applying for item 2 of the patent scope, wherein the protective layer is provided at the opening at the upper end of the plug hole and around the top of the conductive layer to protect the dielectric at the upper end of the plug hole. Floor. 5. The method according to item 1 of the patent application scope, wherein the dielectric layer is composed of silicon dioxide (2). Page 12 ^^ 69 8 5 Scope of patent application 6. As stated in the scope of patent application No. 1 by nitrogen 4 silicon nitride, S The protective layer is formed to prevent the dielectric layer at the upper opening of the plug hole from being invaded by subsequent etching (e t c h i n g) process. Wherein, the conductive layer is composed of ο η), and is used for 7. As described in item 1 of the scope of patent application, a doped poly is a doped poly (polyped). 8. A surface of a conductive wafer and at least one surface of a substrate, a conductive layer and a protective layer surrounding the conductive plug in a semiconductor wafer. The half includes a substrate and a dielectric layer. It is provided on the substrate, and a plug hole is provided in the dielectric layer and penetrates the dielectric layer until the conductive plug includes:, is provided in the plug hole and is in contact with the surface of the substrate; and is provided in the The upper end of the plug hole surrounds the top of the conductive layer to protect the dielectric layer at the opening of the upper end of the plug hole. 9. As described in item 8 of the scope of patent application, the plug hole is a columnar structure, and the upper end The diameter of the opening is larger than the diameter of the columnar structure, and is used to expand the area of the upper opening of the plug hole. Wherein the conductive plug 10. As in the scope of patent application No. 8 ~ Page 13 6. Scope of patent application The hole is a contact plug or a via plug. , Where the dielectric layer is; minus ‘12. As in item 8 of the scope of patent application, $ is composed of silicon dioxide (SiO2). 13. As described in item 8 of the scope of patent application, wherein the protective layer is composed of silicon nitride (Si Ν) to prevent the dielectric layer at the opening at the upper end of the plug hole from being invaded by silver in the subsequent money engraving process. 14. As described in item 8 of the scope of patent application, wherein the conductive layer is composed of a doped polycrystalline sand. Page M