:/006 :/006 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（/) 本發明是有關於一種電腦控制系統，且特別是有關於 一種藉由積體兀件電子介面（integrated device · e 1 e c t r ο n i c s 1 1+ DE)來程式化週邊快問唯讀記億體 (peripheral flash read-only memoi’Y，flash ROM)的系 統的使用方法。 最近電腦工業的發展極爲快速，因而使電腦的周邊硬 體元件也相對的不斷發展。隨著電腦業的迅速發展，電腦 的軟體也相對的不斷在發展，如此使得用以控制週邊元件 的韌體資料（data)/指令（code)也必須不斷的更新。一般 而言韌體指令會儲存在快閃唯讀記憶體中。因此，電腦系 統需要可以迅速且方便的將快閃唯讀記憶體程式化而更 新韌體指令/資料的方法。 目前電腦系統常使用幾種方法來讀取存在快閃唯讀記 憶體中的韌體指令。在美國專利第5603056號專利中所揭 露的是一種將用以控制硬碟驅動裝置（hard d1Sk dnve， HDD)的控制程式與一種再寫入程式一起儲存在電性可抹 除可程式記憶體（electrically eras.able programmable read only memory，EEPROM)的控制程式。在輸入再寫入 模式的時候，硬碟驅動裝置中的中央處理器 (central procemng unU，CPU)會將快閃電性可抹除可程式記憶 體中的控制程式存入隨機存取記憶體（random access memory，RAM)中。中央處理器會將電性可抹除可程式記憶 體中的資料抹除並重新將隨機存取記憶體中的再寫入程 式重新存入電性可抹除可程式記憶體中。中央處理器會由 4 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 裳-----ί 訂·--—--I —^ 4 2 5 21 vtJ'. d^o c / 0 0 6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（i) 主電腦（h 〇 st c 〇 m p u t e r)中得到一個新的控制程式並將其 裝到電性可抹除可程式記憶體中。中央處理器對電性可抹 除可程式記憶體的抹除與新控制程式的讀取是根據存在 隨機存取記憶底中的再寫入程式而進行的。傳統的方式 中，是將小電腦系統介面（sma 1 1 compu t e s y s ΐ em surface，SCSI)連接器或是 ΑΤΑ (AT attachment)連接器 作爲輸出/入介面，並將其中連接器未定義的接腳作爲與 主電腦之間的序列連接（s e r i a 1 c omm un i c a t i ο η)。由於所 使用的介面並非普遍使用的介面，因此這個方法無法普遍 的應用於不同類型的電腦的主機板上。其他的方法，例如 美國專利第5408624號與第5729683號專利中所揭露的方 法，則是非常複雜，同時也僅能應用於部分的系統中。 習知的系統中包括應用積體元件電子介面來更新儲存 在快閃唯讀記憶體中的韌體指令。由於一般的積體元件電 子介面常被用以連接不同的周邊元件，因此相容性便較 局° 唯讀光碟機（compact-disk read-onl y-memory，CDR0M) 爲電腦中的基本配備。第1圖係用以說明例如唯讀光碟機 這樣的周邊配備3其中，電腦系統包括一個微處理器 (mocroprocessor)lOO’用以作爲操作所有元件，如唯讀 光碟機的伺服器（servo)l〇2與解碼器（decoder)104的控 制益。伺服游10 2耦(接光碟10 6 ’用以讀取光碟1 〇 6上的 資料。韌體指令包括如控制程式 '再寫入程式與其他儲存 在快閃唯讀記憶體108中的資料。韌體指令提供了處理器 1〇〇的執行架構。唯讀光碟機藉由積體元件電子介面/匯流 (請先閲讀背面之注意事項再填寫本頁>: / 006: / 006 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the Invention (/) The present invention relates to a computer control system, and in particular, to an electronic interface through integrated components ( integrated device · e 1 ectr ο nics 1 1 + DE) to program the peripheral flash read-only memoi'Y (flash ROM) system. The recent rapid development of the computer industry has resulted in relatively continuous development of computer peripheral hardware components. With the rapid development of the computer industry, the software of the computer is also constantly developing, so that the firmware data / code used to control peripheral components must also be constantly updated. In general, firmware instructions are stored in flash read-only memory. Therefore, computer systems need a way to quickly and easily program flash-only memory to update firmware instructions / data. Computer systems currently use several methods to read firmware instructions stored in flash read-only memory. Disclosed in U.S. Patent No. 5,603,056 is a control program for controlling a hard disk drive (hard d1Sk dnve, HDD) stored in an electrically erasable programmable memory together with a rewrite program ( electrically eras.able programmable read only memory (EEPROM). In the input rewrite mode, the central processing unit (central procng unU, CPU) in the hard disk drive device stores the control program in the fast lightning erasable programmable memory into random access memory (random access memory, RAM). The central processing unit erases the data in the electrically erasable programmable memory and re-stores the rewrite procedure in the random access memory into the electrically erasable programmable memory. The central processor will be based on 4 paper sizes applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (Please read the precautions on the back before filling out this page). --I — ^ 4 2 5 21 vtJ '. D ^ oc / 0 0 6 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (i) Obtained from the main computer (h 〇st c 〇mputer) A new control program and install it in electrically erasable programmable memory. The erasing of the electrically erasable programmable memory by the central processing unit and the reading of the new control program are performed according to the rewriting program stored in the random access memory. In the traditional method, a small computer system interface (sma 1 1 compu tesys ΐ em surface (SCSI) connector or AT attachment (AT attachment) connector is used as the input / output interface, and the undefined pins of the connector are used. As a serial connection to the host computer (seria 1 c omm un icati ο η). Since the interface used is not a commonly used interface, this method cannot be universally applied to motherboards of different types of computers. Other methods, such as those disclosed in U.S. Patent Nos. 5,408,624 and 5,297,683, are very complex and can only be applied to some systems. The conventional system includes the use of integrated component electronic interfaces to update the firmware instructions stored in flash ROM. Since the general electronic interface of integrated components is often used to connect different peripheral components, compatibility is relatively limited. Compact-disk read-on-memory (CDR0M) is the basic equipment in computers. Figure 1 is used to illustrate peripheral equipment such as a CD-ROM. 3 Among them, the computer system includes a microprocessor 100 'as a server for operating all components, such as a CD-ROM. 〇2 and the decoder (decoder) 104 control benefits. Servo tour 10 2 is coupled (connected to the disc 10 6 ′ to read the data on the disc 10). The firmware instructions include, for example, a control program, a rewrite program, and other data stored in the flash read-only memory 108. The firmware instructions provide the execution architecture of the processor 100. The read-only optical drive uses the integrated component electronic interface / confluence (please read the precautions on the back before filling this page>
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7 4252twf.doc/006 ΐνζβ-e6、- 五、發明說明（>) 排（bus)連接主電腦11〇。主電腦則會提供一個要更新到快 閃唯讀記憶體108的韌體指令，而微處理器100則係用以 程式化唯讀記憶體108。 然而，更新的程式係藉由週邊元件與微處理器100才 得以完成。傳統的方法麻煩的地方便在於因爲韌體指令在 系統發展的過程中需要經常被更新，即使是在產品已經到 達最終使用者的手上也是一樣。 本發明在此提出一種用於電腦系統中的方法，可以透 過對應重新定義（redefine)的ΑΤΑ的工作檔案（task file) 的積體元件電子介面，來程式化通常用以儲存韌體指令的 快閃唯讀記憶體。快閃唯讀記憶體可以直接由主電腦而被 程式化，不需要經由週邊元件。 本發明並提供一個快閃控制器，可以直接透過積體元 件電子介面連接主電腦，並直接程式化.快閃唯讀記憶體。 且快閃控制器獨立於硬體元件的形式。 本發明中的用以程式化週邊快閃記憶體的方法包括在 主電腦要求（request)程式化或是更新快閃唯讀記憶體中 的韌體指令時，抑制快閃唯讀記憶體對其他資料的存取。 此時在主電腦中的幾個ΑΤΑ工作檔案會被重新定義，其 中，AT/V工作檔案通常會被依照ΑΤΑ的規格來定義，並常 被作爲主電腦與積體元件電子週邊元件之間的暫存器級 (register-level)的連接介面。主電腦中的韌體指令會經 由被例如主電腦重新定義的積體元件電子介面傳送，並經 由例如快閃控制器的程式控制器來寫入快閃唯讀記憶 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------- *---I---^ i — ϊ — — ? ^ I (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7 4252twf.doc / 006 ΐνζβ-e6,-V. Description of the invention (&); The bus is connected to the host computer 110. The host computer provides a firmware instruction to update to the flash read-only memory 108, and the microprocessor 100 is used to program the read-only memory 108. However, the updated program is completed by the peripheral components and the microprocessor 100. The traditional method is cumbersome and convenient because the firmware instructions need to be updated frequently during the development of the system, even when the product has reached the end user. The present invention proposes a method for a computer system, which can be programmed through a component element electronic interface corresponding to a redefined ATA task file to program the fast-received firmware instructions. Flash read memory. The flash read-only memory can be programmed directly from the host computer without the need for peripheral components. The invention also provides a flash controller, which can be directly connected to the host computer through the electronic interface of the integrated component and directly programmed. The flash-read-only memory. And the flash controller is independent of the form of the hardware components. The method for programming peripheral flash memory in the present invention includes inhibiting the flash read-only memory from being used by other hosts when the host computer requests to program or update the firmware instructions in the flash read-only memory. Data access. At this time, several ATAA working files in the host computer will be redefined. Among them, AT / V working files are usually defined in accordance with ATAA specifications, and are often used as the interface between the host computer and the electronic peripheral components of the integrated component. Register-level connection interface. The firmware instructions in the host computer are transmitted through the electronic interface of the integrated component redefined by, for example, the host computer, and written into the flash read-only memory through a program controller such as a flash controller. The paper dimensions are applicable to Chinese national standards (CNS) A4 specification (210 X 297 mm) ----------- * --- I --- ^ i — ϊ — —? ^ I (Please read the notes on the back before filling (This page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs
4252t^f^J oc/006 A7 B7 五、發明說明（y) 體。快閃控制器會解譯積體元件電子介面的動作1並提出 讀/寫快閃唯讀記億體的循環。快閃控制器提供一個軟體 方法、-個硬體方法，或是混用軟體與硬體的方法來程式 化快閃唯讀記憶體。在軟體方法中，韌體指令係透過快閃 控制器直接輸入快閃唯讀記憶體的。在硬體方法中，若是 一個要求需要一個以上的快閃記憶體循環，則是使用一個 緩衝器（buffer)，例如隨機存取記憶體來儲存韌體的指 令。然後，再透過快閃控制器將存在緩衝器中的韌體指令 寫入快閃控制器。 本發明並提出一種用以程式化週邊快閃記憶體的系 統1其中包括主電腦、積體元件電子介面、快閃控制器、 快閃唯讀記憶體與一個微處理器。其中快閃控制器透過積 體元件電子介面而耦接主電腦。快閃唯讀記億體與微處理 器也均耦接快閃控制器。當系統輸入快閃唯讀記憶體程式 化模式時，積體元件電子介面與主電腦之間的工作檔案便 會被主電腦重新定義，並由快閃控制器解碼，使主電腦所 發出的韌體程式經由快閃控制器而寫入快閃唯讀記憶體 中。在快閃唯讀記憶體已完全被程式化之後，工作檔案會 回覆爲原來的原始定義。微處理器係用以在快閃唯讀記憶 體的程式化模式中，使其他對快閃唯讀記億體中的存取步 驟無效。若是主電腦的要求中同時需要數個快閃唯讀記憶 體的程式化循環，韌體則可暫時性的儲存於隨機存取記憶 體之類的暫存器中，然後再透過快閃控制器寫入快閃唯讀 記憶體中。由於軟體方法可能會佔據積體元件電子介面相 7 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) I---- I 訂· I - ---- 經濟部智慧財產局員工消費合作杜印製 dl C / Ο Ο 6 dl C / Ο Ο 6 經濟部智慧財產局員工消費合作社印製 102 :伺服器 106 :光碟機 110、208 :主電腦 204 :快閃控制器 五、發明說明（ί) 當多的時間’而導致接下來的其他動作的延遲（delay)， 因此更新韌體的指令時用硬體方法可能會較佳，特別是在 更新大的韌體指令時。 爲讓本發明之上述和其他目的、特徵 '和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 圖式之簡單說明： 第1圖繪示的是習知的具有週邊唯讀光碟機的系統的 方塊圖，其中唯讀光碟機係由一個儲存在快閃唯讀記憶體 中的韌體指令所控制； 第2圖繪示的是根據本發明的較佳實施例的用以程式 化快閃唯讀記憶體的電腦系統的方塊圖，其中快閃唯讀記 憶體係用以儲存韌體指令，以便控制週邊元件； 第3圖繪示本發明的較佳實施例的用以產生軟體循環 的工作檔案中的幾個控制位元訊號的波形的時序圖；以及 第4圖繪示本發明的較佳實施例的用以產生軟體循環 的工作檔案中的幾個控制位元訊號的波形的時序圖。 圖示標號說明 100 ' 200 :微處理器 104 :解碼器 108、202 :快閃唯讀記憶體 112、206 :隨機存取記憶體 實施洌 用以控制主電腦中的周邊元件韌體指令通常會儲存於 本紙張又度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先間讀背面之注意事項再填寫本頁) 裝 i — — — — — — 訂·! ίι-崎，4252t ^ f ^ J oc / 006 A7 B7 V. Description of the invention (y). The flash controller will interpret action 1 of the electronic interface of the integrated component and propose a cycle of reading / writing the flash-only memory. The flash controller provides a software method, a hardware method, or a combination of software and hardware to program the flash read-only memory. In the software method, the firmware instruction is directly input into the flash read-only memory through the flash controller. In the hardware method, if a request requires more than one flash memory cycle, a buffer, such as random access memory, is used to store the firmware instructions. Then, the firmware instructions stored in the buffer are written into the flash controller through the flash controller. The present invention also proposes a system 1 for programming peripheral flash memory, which includes a host computer, an integrated component electronic interface, a flash controller, a flash read-only memory, and a microprocessor. The flash controller is coupled to the host computer through the electronic interface of the integrated component. Flash read-only memory and microprocessor are also coupled to the flash controller. When the system enters the flash read-only memory programming mode, the working file between the electronic interface of the integrated component and the host computer will be redefined by the host computer and decoded by the flash controller. The program is written into the flash read-only memory via the flash controller. After the flash read-only memory is completely stylized, the working file will be returned to the original definition. The microprocessor is used to disable other access steps in the flash read-only memory in the programming mode of the flash read-only memory. If the host computer requires a number of flash read-only memory program loops at the same time, the firmware can be temporarily stored in a register such as random access memory, and then passed through the flash controller Write to flash read-only memory. Because the software method may occupy the electronic interface phase of the integrated component 7 This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) (Please read the precautions on the back before filling this page) I ---- Order I · I----- Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for Consumer Cooperative Printing dl C / Ο Ο 6 dl C / Ο Ο 6 Printed by the Employees' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 102: Server 106: Optical Disc Drive 110, 208: Host computer 204: Flash controller V. Description of the invention (ί) When too much time 'causes other actions to be delayed (delay), the hardware method may be used to update the firmware instructions Better, especially when updating large firmware instructions. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings for detailed description as follows: Brief description of the drawings: FIG. 1 Shows a block diagram of a conventional system with a peripheral read-only optical drive, where the read-only optical drive is controlled by a firmware instruction stored in flash read-only memory; Figure 2 shows the A block diagram of a computer system for programming flash read-only memory according to a preferred embodiment of the present invention, wherein the flash read-only memory system is used to store firmware instructions to control peripheral components; FIG. 3 shows A timing chart of waveforms of several control bit signals in a working file for generating a software loop in a preferred embodiment of the present invention; and FIG. 4 illustrates a preferred embodiment of the present invention for generating a software loop in a software loop. Timing diagram of the waveforms of several control bit signals in the working file. Description of icons: 100 '200: Microprocessor 104: Decoder 108, 202: Flash read-only memory 112, 206: Random access memory implementation. The firmware commands used to control peripheral components in the host computer usually Stored on this paper is also applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) (please read the precautions on the back before filling out this page) Pack i — — — — — — Order ·! Ίι- 崎,
經濟部智慧財產局員工消費合作社印製 五、發明說明（(ί ) 快閃唯讀記憶體中’並因電腦軟體的快速發展而需要經常 更新α然而傳統用以更新韌體的方法並不方便，且僅能適 用於部分系統中。 由於積體元件電子介面常被用於週邊元件中而作爲與 主電腦之間的聯繫’本發明提供—個使用快閃控制器來再 解碼（re-interpret)所有積體元件電子匯流排的動作，並 以一個讀/寫快閃唯讀記憶體循環來直接程式化快閃唯讀 記憶體的系統。 第2圖繪示的是一個根據本發明的較佳實施例的用以 程式化快閃唯讀記憶體的電腦系統的方塊圖，其中快閃唯 讀記憶體通常係用以儲存控制週邊元件用的韌體指令。元 件系統中包括微處理器200、快閃唯讀記憶體202,以及 快閃控制器204。本系統可以透過一個積體元件電子介面 來連接主電腦208。本系統中更包括一個隨機存取記憶 體’用以作爲緩衝器。快閃控制器會透過一個積體元件電 子介面連接至主電腦208，快閃唯讀記憶體202與微處理 器200則連接快閃控制器204。隨機存取記憶體206也可 以連接快閃控制器204。接下來將會說明，本系統可以在 軟體循換與硬體循環中執行。在系統於硬體循環中操作時 需要隨機存取記憶體206來作爲暫存器，其中硬體循環的 一個要求便需要有幾個快閃唯讀記憶體循環來更.新快閃 唯讀記憶體202。 當系統輸入快閃唯讀記憶體程式化模式時，積體元件 電介面與主電腦208之間的工作檔案便會被重新定義， 9 (請先閱讀背面之注意事項再填寫本頁) 4^4----— I I I 訂---------. 本紙張尺度適用中國國家標準（CNS)A4規格（210x 297公釐) A7 B7 4252iwi'.cioc/006 五、發明説明（） 使主電腦中的韌體程式經由快閃控制器2 0 4而寫入快閃唯 讀記億體202中。工作檔案可定義於例如ΑΤΑ規格中’並 用以作爲暫存器級的連接介面。在快閃唯讀記憶體202完 全程式化之前，微處理器2 0 0會停止對快閃唯讀記憶體2 0 2 的存取的動作，以避免與匯流排的連接。一般而言，在快 閃唯讀記億體202完全程式化之後，快閃控制器204會使 快閃唯讀記憶體程式化的功能無效，並使所有的積體元件 電子介面的動作回到其原先的設定，使其在普通的模式下 來驅動耦接微處理器200的周邊元件，如第1圖中的唯讀 光碟機。 不論主電腦208在什麼時候作出程式化快閃唯讀記憶 體202的要求，主電腦208會先寫入一個積體元件電子傳 送規格指令（vendo]_-specific IDE command)來通知元件 系統。然後快閃控制器204便會轉移接下來的積體元件電 子的動作至快閃唯讀記憶體循環中，以便作程式化的動 作。在程式化結束時，主電腦208會再寫入另一個積體元 件電子傳送規格指令，以便通知系統，或是重新啓動系 統。然後，系統便會回到正常的模式。 所有由快閃控制器204發出的快閃唯讀記憶體循環均 可以分割爲兩個部分。一個叫做軟體循環，另一個叫硬體 循環，且兩個都可以提供讀與寫的功能。在軟體循環中， 主電腦208會直接控制快閃唯讀記憶體202的快閃接腳的 狀態’以便產生用以讀/寫快閃唯讀記憶體202的適當波 形。在軟體循環中，ΑΤΑ工作檔案中的四個暫存器CTL、 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） ----------— f ---I I I I 訂-------- (諳先閱讀背面之注意事項再填寫本頁) * --- I: 經濟部智慧財產局員工消費合作社印製 A1¾¾¾ d^>( /006 A7 B7 i、發明說明（<?) DBUS、ABUSLOW以及ABUSHIGHTC的狀態會被再定義成如表 格1的情形。 名稱 7 6 5 4 3 2 1 0 CS# CTL _ 一 編 _ DRV OE# WR# DBUS DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQO ABUSL0W A7 A6 A4 A4 A3 A2 A1 AO ABUSHIGH A15 A14 A13 A12 All A10 A9 A8 先 閱 讀 背 面 之 注 意 事 項 再 填 寫 本 頁 裝 所有快閃唯讀記憶體202的接腳，像是64Kx8的快閃 唯讀記憶體，均可對應這四個暫存器的位元（bU)，因此 若是使用其他大小尺寸的快閃唯讀記憶體也還是可以對 應連接。如此使主電腦208可以可以寫入資料快閃唯讀記 憶體來設定或是淸除接腳中的設定，並隨意的建立讀/寫 循環的波形。接腳的狀態也可以藉由主電腦208來讀取暫 存器的方式得到。例如在CTL暫存器中的Bi t3中，DRV便 是被定義成可以使主電腦208決定是否要驅動資料匯流 (data bus)。這是因爲快閃唯讀記憶體資料匯流通常是雙 向的，如此可以避免匯流排的連接。 接著所顯示的是主電腦208係如何程式化四個暫存 器，以產生具有如第3圖中波形的軟體讀取循環。 //假設所有的快閃唯讀記億體的相關接腳均暫時不會 闬到， //即 cs#=高（high)，oe#=高（high)，wr#=高（high)， 訂 經濟部智慧財產局員工消費合作社印製 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） u 0(4()0 6 A7 B7 / /程式化所欲讀取位址 //程式化所欲讀取位址 / /維持c s # //維持wr# 〇等候快閃唯讀記憶體的存取時間 ReadBackData = read_DBUS; write_CTL (8’bF6); //抹除 oe# wr】te_CTL (8’bF7); //抹除 cs# 接下來所介紹的是近似的主電腦208程式化這四個暫 存器，以產生具有第4圖中波形的軟體讀取循環的程序。 //假設所有的快閃唯讀記憶體相關接腳均暫時不會用 到 //即 cs#=高（high)，oe#=高（high)，wi.#=高（high) 且 經濟部智慧財產局員工消費合作社印製 五、發明說明（Ϋ ) 且 η資料接腳浮置。 wri te_ABUSL0W(8，bX)〇 ; wr 1 te_ABUSHIGH(8’bXX); wri te_CTL (8’bF6); writ e_CTL (85bF4); //程式化所欲讀取位址 //程式化所欲讀取位址 / /維持c s # / /維持w r # //程式化所欲寫入的資料 //設定DRV並開始驅動 (請先閱讀背面之注意事項再填寫本頁) //所有的接腳均浮置。 wri te_ABUSL0W(8’bXX); wri te_ABUSHIGH(8’bXX); Wi-i te_CTL (8，bF6); wi-ite_CTL (8，bF4); write_DBUS (8’bXX) write_CTL (85bFC); 資料匯流 12 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（π) write_CTL (8’bFE); // 抹除 wr# wi-i te_CTL (8’bF6) ; //淸除 DRV 與浮置資料 匯流 \νι· ί t e_CTL ( 8’bF7) ; //抹除 cs# 其中，快閃唯讀記憶體可提供不同用途的快閃傳送規 格指令。例如快閃傳送規格指令便可用於整快晶片的抹 除、軟體寫入保護等。快閃傳送規格指令常藉由讀/寫特 定資料至特定的位址而形成。由於軟體循環具有較大的彈 性，因此對主電腦208提出快閃傳送規格指令很有用。快 閃傳送規格指令中亦包括確定所欲動作，如此可以確定快 閃唯讀記憶體202正位於程式化的狀態。 在上述的敘述中，快閃唯讀記憶體202的程式化係藉 由軟體循環來達成。在第2圖中的隨機存取記憶體206並 非必要。在本發明中，軟體循環只是一個選擇，即使應用 軟體來程式化快閃唯讀記憶體202具有其優點所在，但本 發明在此仍舊再提出一個硬體方法。在本發明中，軟體方 法在程式化快閃唯讀記憶體202的程式化的過程中會佔用 掉積體元件電子介面相當多的時間，因此若是韌體指令需 要被更新的部分很大的話，就必須花費很久的時間，因而 造成接下來其他積體元件電子的活動的速度變慢，而使系 統的效能變差。接下來將介紹硬體方法以便解決這個問 題。硬體方法在有需要傳輸的量大時可以提供一個效率較 佳的方法。 在第2圖中的硬體循環中，韌體指令會經由兩個步驟 (請•先閱讀背面之注意事項再填寫本頁) — I — It — — --------- 本纸張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐）Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs V. Invention Description ((ί) Flash ROM) and need to be updated frequently due to the rapid development of computer software α However, the traditional method of updating firmware is not convenient , And can only be used in some systems. Because integrated component electronic interfaces are often used in peripheral components as a connection with the host computer, the present invention provides a flash controller to re-interpret (re-interpret ) The actions of the electronic buses of all integrated components, and a read / write flash read-only memory cycle to directly program the flash read-only memory system. Figure 2 illustrates a preferred method according to the present invention. A block diagram of a computer system for programming flash read-only memory according to an embodiment. The flash read-only memory is generally used to store firmware instructions for controlling peripheral components. The component system includes a microprocessor 200, Flash read-only memory 202 and flash controller 204. The system can be connected to the host computer 208 through an integrated component electronic interface. The system also includes a random access memory 'Used as a buffer. The flash controller is connected to the host computer 208 through an integrated component electronic interface, and the flash read-only memory 202 and the microprocessor 200 are connected to the flash controller 204. Random access memory 206 can also be connected to the flash controller 204. Next, it will be explained that the system can be executed in software cycle and hardware cycle. When the system operates in the hardware cycle, the random access memory 206 is required as a register. One of the requirements of the hardware cycle requires several flash read-only memory cycles to be updated. The new flash read-only memory 202. When the system enters the flash read-only memory programming mode, the integrated device electrical interface and the host The working files between computers 208 will be redefined, 9 (Please read the notes on the back before filling this page) 4 ^ 4 ----— III Order ---------. This paper size Applicable to China National Standard (CNS) A4 specification (210x 297 mm) A7 B7 4252iwi'.cioc / 006 V. Description of the invention () The firmware program in the host computer is written into the flash memory via the flash controller 2 0 4 Only read the record in the body 202. The work file can be defined in the example In the ATFA specification, it is also used as a register-level connection interface. Before the flash ROM 202 is fully programmed, the microprocessor 2 0 will stop accessing the flash ROM 2 0 2 Action to avoid connection with the bus. Generally speaking, after the flash read-only memory 202 is fully programmed, the flash controller 204 will invalidate the flash read-only memory programming function and make all The action of the electronic interface of the integrated component returns to its original setting, so that it drives peripheral components coupled to the microprocessor 200 in a normal mode, such as the CD-ROM drive in Figure 1. No matter what the host computer 208 is in At the time, a request for the programmed flash read-only memory 202 is made, and the host computer 208 first writes a vendo_-specific IDE command of the integrated component to notify the component system. The flash controller 204 then transfers the actions of the next integrated component electronics to the flash read-only memory cycle for programmed operation. At the end of the programming, the host computer 208 writes another integrated component electronic transmission specification instruction to notify the system or restart the system. The system will then return to normal mode. All flash read-only memory cycles issued by the flash controller 204 can be divided into two parts. One is called a software loop, the other is called a hardware loop, and both can provide read and write functions. In the software cycle, the host computer 208 directly controls the state of the flash pins of the flash read-only memory 202 'in order to generate an appropriate waveform for reading / writing the flash read-only memory 202. In the software cycle, the four temporary registers CTL in the ΑΤΑ working file and the paper size are applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) ------------ f- -IIII Order ---- (谙 Please read the notes on the back before filling this page) * --- I: Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs A1¾¾¾ d ^ > (/ 006 A7 B7 i. Description of the invention (<?) The status of DBUS, ABUSLOW and ABUSHIGHTC will be redefined as the situation in Table 1. Name 7 6 5 4 3 2 1 0 CS # CTL _ 1st_ DRV OE # WR # DBUS DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQO ABUSL0W A7 A6 A4 A4 A3 A2 A2 The 64Kx8 flash read-only memory can correspond to the bits (bU) of these four registers, so if you use other sizes of flash read-only memory, it can still be connected. In this way, the host computer 208 can Can write data to flash read-only memory to set or delete settings in pins, and freely Create a read / write cycle waveform. The state of the pins can also be obtained by reading the register from the host computer 208. For example, in Bi t3 in the CTL register, DRV is defined to enable the master The computer 208 decides whether to drive the data bus. This is because the flash read-only memory data bus is usually two-way, so the connection of the bus can be avoided. The following shows how the host computer 208 is programmed. Register to generate a software read cycle with the waveform shown in Figure 3. // Assume that all the relevant pins of the flash-only read-only memory will not be temporarily found, // ie cs # = 高(High), oe # = high (high), wr # = high (high), order printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, the paper size is applicable to China National Standard (CNS) A4 (210 X 297 mm) ) U 0 (4 () 0 6 A7 B7 // programmed read address // programmed read address // maintain cs # // maintain wr # 〇 wait for flash read-only memory Access time ReadBackData = read_DBUS; write_CTL (8'bF6); // Erase oe # wr] te_CTL (8'bF7); // Erase cs # Connect Introduced to the host computer 208 is approximately four programmable registers temporarily, the software has to generate a fourth waveform of FIG read cycle of the routine. // Assume that all flash read-only memory related pins will not be used temporarily // that is, cs # = high (high), oe # = high (high), wi. # = High (high) and the Ministry of Economic Affairs Printed by the Intellectual Property Bureau's Consumer Cooperatives V. Invention Description (Ϋ) and η data pins are floating. wri te_ABUSL0W (8, bX) 〇; wr 1 te_ABUSHIGH (8'bXX); wri te_CTL (8'bF6); writ e_CTL (85bF4); // program the desired address // program the desired address Address // maintain cs # /// maintenance wr # // program the data to be written // set DRV and start driving (please read the precautions on the back before filling this page) // all pins are floating Home. wri te_ABUSL0W (8'bXX); wri te_ABUSHIGH (8'bXX); Wi-i te_CTL (8, bF6); wi-ite_CTL (8, bF4); write_DBUS (8'bXX) write_CTL (85bFC); Data collection 12 books Paper size applies to China National Standard (CNS) A4 (210 X 297 mm) B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (π) write_CTL (8'bFE); // 擦除 wr # wi -i te_CTL (8'bF6); // Delete DRV and floating data confluence \ νι · ί t e_CTL (8'bF7); // Erase cs # Among them, the flash read-only memory can provide different purposes Flash transmission specification instruction. For example, the flash transfer specification command can be used for erasing the whole chip, software write protection, etc. Flash transfer specifications are often formed by reading / writing specific data to a specific address. Because the software loop has greater flexibility, it is useful to provide a flash transfer specification command to the host computer 208. The flash transmission specification instruction also includes determining a desired action, so that it can be determined that the flash read-only memory 202 is in a programmed state. In the above description, the programming of the flash read-only memory 202 is achieved by a software loop. The random access memory 206 in Fig. 2 is not necessary. In the present invention, software looping is only an option. Even if the use of software to program the flash ROM 202 has its advantages, the present invention still proposes a hardware method. In the present invention, the software method occupies a considerable amount of time during the programming of the program flash ROM 202. Therefore, if the part of the firmware instruction that needs to be updated is large, It must take a long time, which causes the subsequent activity of other integrated component electronics to slow down, which makes the system's performance worse. The hardware method is introduced next to solve this problem. The hardware method can provide a more efficient method when the amount of transmission required is large. In the hardware loop in Figure 2, the firmware instruction goes through two steps (Please read the precautions on the back before filling this page) — I — It — — --------- This paper Standards apply to China National Standard (CNS) A4 (210 X 297 mm)
A f-do.c/006 A7 B7 ______ 經濟部智慧財產局員工消費合作社印製 备明說明（/f) 來轉移至快閃唯讀記憶體202。舉例來說，在硬體寫入循 環中’第一步驟是主電腦208藉由快閃控制器204寫入像 是韌體指令的資料進入快閃唯讀記憶體206。此時隨機存 取記億體係用以作爲緩衝器。快閃控制器204接著在第二 步驟中’會將隨機存取記億體206中的緩衝器中的資料移 轉入快閃唯讀記憶體202。在硬體讀取循環中，第一步驟 則是由快閃控制器204讀取快閃唯讀記憶體202中的資料 並存入隨機存取記憶體206，然後在第二步驟中再由主電 腦208讀取隨機存取記憶體206中的資料。 兩個積體元件電子傳送規格指令會分別被硬體讀取循 環與硬體寫入循環定義，第2表中繪示的是在ΑΤΑ工作檔 案中的三個暫存器的使用情形。 第2表 名稱 7 6 5 4 3 2 Ί： 資料 資料埠 長度 L7 L6 L5 L4 L3 L2 L1 LQ 指令/狀態 BSY - - - DRQ - 當主電腦欲啓動硬體寫入循環時，會先啓動積體元件電子 硬體寫入指令，這是積體元件電子傳送規格指令之一。在 系統接收到這個指令之後，會如第2表中所示的設定緊急 狀態時所用的BSY位元，並淸除有資料需求時所用的DRQ 位元，以準備由主電腦208中傳送資料。只要一準備好， 本紙張尺度適用中0國家標準（CNS)A4規格（210 X 297公釐） -------- —--- --------訂--I------$ {請¾閱讀背面之注意事項再填寫本頁) A B7 D c / 0 0 6 2¾ 3、石. A7 五、發明說明（p) BSY位元便會被淸除，DRQ位元也會被設定。當主電腦208 紀錄下STATUS暫存器時，若結果爲BSY位元已淸除，DRQ 位元已設定，主電腦208便會開始將資料寫入DATA暫存 器，使資料經由快閃控制器204而存入隨機存取記憶體 206 當系統接收到被定義於LENGTH暫存器中的位元的資 料時，便會再次淸除DRQ位元並設定BSY位元，以便通知 主電腦可以停止輸出資料。然後快閃控制器204會自動的 開始輸出後續的寫入循環，並將存在隨機存取記憶體206 中的資料送入快閃唯讀記憶體202。只要資料的轉移結 束，元件系統便會淸除BSY位元並結束硬體寫入循環。値 得注意的是，主電腦208在啓動積體元件電子硬體寫入指 令前，需要給在工作檔案中作爲啓動位址的用途的 ADDRL(ABUSLOW)暫存器與 ADDRH(ABUSHIGH)暫存器一個起 始値才能作用。丨夬閃控制器204可以在每一次成功的資料 轉移後使位址增加。 經濟部智慧財產局員工消費合作杜印製 .(請先閲讀背面之注意事項再填寫本頁) H"·-* 相似的，當主電腦208與啓動硬體讀取循環時，首先 也是要啓動積體元件電子硬體讀取指令這個積體元件電 子規格限制指令中的一個指令，使元件系統設定BSY位元 並淸除DRQ位元，然後再開始輸出讀取循環至快閃唯讀記 憶體202，並儲存由快閃唯讀記憶體202得到的資料進入 隨機存取記憶體206中。LENGTH暫存器可決定要傳輸的資 料的位元的數量。在上述動作結束之後，元件系統會淸除 BSY位元並設定DRQ位元，以便要求主電腦208由DATA暫 存計讀取存在隨機存取記憶體206中的資料。在主電腦208 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 4 26孖毛'、1(|〇。/0〇6 87 五、發明說明（G) 讀取所有的資料之後，元件系統便會淸除BSY位元並設定 DRQ位元。如此便完成了硬體讀取循環。値得注意的是， 主電腦208在積體元件電子硬體讀取循環指令發出前，需 要給被當成起始位址的ADDRL暫存器與ADDRH暫存器一個 起始値才能作用。快閃控制器204可以在每一次成功的資 料轉移後使起始値的位址增加。 綜上所述，本發明的架構中，當系統輸入快閃唯讀記 憶體程式化模式時，會增加了四個積體元件電子傳送規格 指令，並重新定義了 ΑΤΑ工作檔案中的五個暫存器。下歹tj 的部份爲新增的指令，包括： • PROGRAMMING_FLASH_ON，用以將系統切換至快閃唯 讀記憶體程式化模式； • PROGRAMMING_FLASH_OFF，用以將系統切離快閃唯讀 記憶體程式化模式； • HARDWAREJRITE，用以觸發寫入循環；以及 • HARDWARE_READ，用以觸發讀取循環。 其中的最後兩項僅適用於硬體循環。所有的ΑΤΑ工作檔 案以及其位於快閃唯讀記憶體程式化模式中的定義則均 列於第3表中，其中所定義的包括LENGTH、CTL、DBUS、 ABUSLOW以及ABUSHIGH五個暫存器。 (請先閒讀背面之注意事項再填寫本頁) iw 裝----A f-do.c / 006 A7 B7 ______ Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (/ f) to transfer to the flash read-only memory 202. For example, the first step in the hardware write cycle is that the host computer 208 writes data like firmware instructions into the flash read-only memory 206 through the flash controller 204. At this time, the random access system is used as a buffer. The flash controller 204 then transfers the data in the buffer in the random access memory 206 to the flash read-only memory 202 in a second step. In the hardware read cycle, the first step is to read the data in the flash read-only memory 202 by the flash controller 204 and store it in the random access memory 206. Then in the second step, the host The computer 208 reads the data in the random access memory 206. The two integrated component electronic transmission specifications will be defined by the hardware read cycle and the hardware write cycle, respectively. Table 2 shows the usage of the three registers in the ATAA work file. Table 2 Name 7 6 5 4 3 2 Ί: Data Port Length L7 L6 L5 L4 L3 L2 L1 LQ Command / Status BSY---DRQ-When the host computer wants to start the hardware write cycle, it will start the block first Component electronic hardware write instruction, this is one of the integrated component electronic transfer specification instructions. After the system receives this command, it sets the BSY bit used in the emergency state as shown in Table 2 and removes the DRQ bit used when there is a data demand in preparation for the data to be transmitted from the host computer 208. As soon as it is ready, this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -------- ------- -------- Order --I- ----- $ {Please read the notes on the back and fill in this page again) A B7 D c / 0 0 6 2¾ 3. Shi. A7 V. Description of the invention (p) The BSY bit will be eliminated, DRQ Bits are also set. When the host computer 208 records the STATUS register, if the result is that the BSY bit has been deleted and the DRQ bit has been set, the host computer 208 will start writing data to the DATA register, allowing the data to pass the flash controller. 204 and stored in random access memory 206 When the system receives the data of the bit defined in the LENGTH register, it will delete the DRQ bit and set the BSY bit again to notify the host computer that the output can be stopped data. Then the flash controller 204 automatically starts outputting subsequent write cycles, and sends the data stored in the random access memory 206 to the flash read-only memory 202. As soon as the data transfer ends, the component system will erase the BSY bit and end the hardware write cycle. It should be noted that the host computer 208 needs to give the ADDRL (ABUSLOW) register and the ADDRH (ABUSHIGH) register used as the startup address in the work file before starting the electronic component write instruction of the integrated component. A starter can only work. The flash controller 204 can increase the address after each successful data transfer. Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs for consumer cooperation. (Please read the precautions on the back before filling out this page) H " ·-* Similarly, when the host computer 208 and the hardware read cycle are started, the first thing is to start Integrated component electronic hardware read instruction This instruction of the integrated component electronic specification limit instruction enables the component system to set the BSY bit and delete the DRQ bit, and then starts the output read cycle to flash read-only memory. 202, and stores the data obtained from the flash read-only memory 202 into the random access memory 206. The LENGTH register determines the number of bits of data to be transmitted. After the above actions are completed, the component system will delete the BSY bit and set the DRQ bit, in order to request the host computer 208 to read the data stored in the random access memory 206 from the DATA register. The paper size of the main computer 208 applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economy 4 26 孖 毛 ', 1 (| 〇. / 0〇6 87 5 Explanation of the invention (G) After reading all the data, the component system will delete the BSY bit and set the DRQ bit. This completes the hardware reading cycle. It should be noted that the host computer 208 is in the integrated state. Before the component electronic hardware read cycle instruction is issued, the ADDRL register and the ADDRH register that are used as the start address need to be initialized. The flash controller 204 can be used after each successful data transfer. Increase the address of the initial frame. In summary, in the framework of the present invention, when the system enters the flash read-only memory programming mode, four integrated component electronic transmission specification instructions are added and redefined. The five registers in the ΑΤΑ working file are added. The following tj sections are newly added instructions, including: • PROGRAMMING_FLASH_ON, used to switch the system to flash read-only memory stylized mode; • PROGRAMMING_FLASH_OFF, used to will The system cuts off the flash read-only memory stylized mode; • HARDWAREJRITE to trigger the write cycle; and • HARDWARE_READ to trigger the read cycle. The last two items are only applicable to the hardware cycle. All ΑΤΑ working files And its definition in flash read-only memory stylized mode is listed in Table 3, which includes five registers: LENGTH, CTL, DBUS, ABUSLOW, and ABUSHIGH. (Please read the back first. (Notes to fill in this page) iw equipment ----
If n <. HI .^1 d I » 1 6 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Ψ 經濟部智慧財產局員工消費合作社印製 .uoc/006 A7 B7 五、發明說明（Y) 名稱 說明 DATA “資料埠”。用以作爲資料埠，其定義與在A T A 中的規定相同。 LENGTH “移轉長度”。此暫存器會限制硬體循環中所 計算的移轉位元量。 CTL “控制”相對應於快閃唯讀記憶體的接腳 c s #、w 1· #、以及0 e #。主電腦可以利用本暫 存器來控制接腳的狀態。 DBUS “資料匯流”相對應快閃唯讀記憶體中的資 料匯流的接腳，主電腦可以利用本暫存器 來控制接腳的狀態。 ABUSLOW “位址匯流低（Address Bus Low)”相對應快 閃唯讀記憶體中位址匯流低位元數的接 腳。主電腦能利用本暫存器來控制接腳的 狀態。 ABUSHIGH “位址匯流高（Address Bus High) ”相對應 快閃唯讀記憶體中位址匯流低高位元數的 接腳。主電腦能利用本暫存器來控制接腳 的狀態。 DRIVE SELECT “驅動選擇”。主電腦可寫入本暫存器以便選 擇積體元件電子元件。其定義與在A T A 中的設定相同。 CO匪AND/ STATUS “指令/狀態”。主電腦藉由可以寫入本暫存 器’以便發出A T A指令，並藉由讀取本 暫存器而得知元件的狀態。其定義與在A T A中的設定相同。 17 本纸張又度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 閱 讀 背 意If n <. HI. ^ 1 d I »1 6 This paper size applies to China National Standard (CNS) A4 (210 X 297 mm) 印 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Uoc / 006 A7 B7 5. Description of the invention (Y) Name Description DATA "data port". Used as a data port, the definition is the same as that specified in A T A. LENGTH "Migration Length". This register limits the amount of shift bits calculated in the hardware loop. The CTL "control" corresponds to the pins cs #, w 1 · #, and 0 e # of the flash read-only memory. The host computer can use this register to control the state of the pins. The DBUS “data confluence” corresponds to the data confluence pins in the flash read-only memory. The host computer can use this register to control the state of the pins. ABUSLOW “Address Bus Low” corresponds to the pin of the address bus low bit in the flash ROM. The host computer can use this register to control the state of the pins. ABUSHIGH "Address Bus High" Corresponds to the pin number of the address bus in the flash read-only memory. The host computer can use this register to control the state of the pins. DRIVE SELECT. The host computer can write to this register to select the integrated component electronic components. Its definition is the same as the setting in A T A. COBAND AND STATUS. The host computer can write to this register to issue the AT command, and read the register to know the status of the components. Its definition is the same as the setting in A T A. 17 This paper is again compatible with the Chinese National Standard (CNS) A4 (210 X 297 mm). Please read it first.
項 再 填 ί裝 頁I I 訂 A7 B7 A252\w 1\doc/006 五、發明說明（6) 在本發明中的這項實施例中，快閃唯讀記憶體202可 以直接被程式化而更新1舉例來說，透過積體元件電子介 面所使用的韌體指令可以僅需透過重新定義積體元件電 子介面所使用的ΑΤΑ工作檔案中的幾個暫存器而被重新定 義。而不需要先經過週邊元件。程式化的過程可以由硬體 方法或是軟體方法，甚至兩者混合使用來達成。軟體方法 中包括-個主電腦經由重新定義的ΑΤΑ工作檔案直接讀取 或是寫入快閃唯讀記憶體的步驟。 硬體方法中資料在主電腦與快閃唯讀記憶體中的移轉 包括兩個步驟。首先儲存於緩衝器中，例如隨機存取記憶 體，然後再將隨機存取記憶體中的資料寫入快閃唯讀記憶 體而形成一個寫入循環，或是由主電腦讀取。在資料暫時 性的儲存於隨機存取記憶體中後，積體元件電子介面會被 釋放，以便其他的資料可以繼續使用。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 (請先間讀背面之注意事項再填寫本頁) 1 -iTeJI I n 1 > 經濟部智慧財產局員工消費合作社印製 本紙張尺度遶用t國國家標準（CNS)A4規格（210 x 297公釐）Refill the item II. Order II A7 B7 A252 \ w 1 \ doc / 006 5. Description of the invention (6) In this embodiment of the present invention, the flash read-only memory 202 can be directly programmed and updated 1 For example, the firmware instructions used by the integrated component electronic interface can be redefined only by redefining a few registers in the ATAA working file used by the integrated component electronic interface. There is no need to go through peripheral components first. The stylized process can be achieved by hardware method or software method, or even a mixture of the two. The software method includes the steps of a host computer directly reading or writing to the flash read-only memory via the redefined ATP working file. The transfer of data between the host computer and flash read-only memory in the hardware method involves two steps. It is first stored in a buffer, such as random access memory, and then the data in the random access memory is written into the flash read-only memory to form a write cycle, or it can be read by the host computer. After the data is temporarily stored in the random access memory, the electronic interface of the integrated component will be released, so that other data can continue to be used. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. (Please read the precautions on the back before filling in this page) 1 -iTeJI I n 1 > Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs, this paper uses national standards (CNS) A4 specifications (210 x 297) Mm)