TW425705B - Manufacturing method of capacitor structure - Google Patents

Abstract

This invention relates to the manufacturing method of forming capacitor structure for DRAM device. The capacitance value stated above can be increased by using capacitance dielectric layer with high dielectric constant and by using the HSG layer as the top surface of storage node electrode. This invention has the characteristic of using HSG TiN layer as part of the storage node structure such that the surface area of storage node electrode can be increased and the capacitance value can be increased.

Description

_ 4 2 5 7 0 5 ____ V. Description of the Invention (1) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for applying dynamic random access memory (Dynami (; Rand () m

Access Memory (DRAM) devices are used to form capacitor structures with high surface area. Micro-miniaturization of semiconductor devices ^ 丨 ^ “-" "^^" ..., or the ability to fabricate semiconductor devices with sub-micron characteristics (sub-mi cron) features' makes DRAM device density reach or exceed 256 Mbyte. However With the shrinking of the critical DRAM feature size, in order to accommodate the required density, it becomes more difficult to achieve critical DRAM parameters, such as electrical capacity. Take DRAM Cells as an example, using stacked capacitors ( Stacked Capacitor Configuration) will be limited by the size of the Transfer Gate Transistor below. The capacitance provided by the stacked capacitor structure of a DRAM device is a function of the thickness of the capacitor dielectric layer and is also the capacitance A function of area. Since reducing the thickness of the capacitor dielectric layer is a trend, the direction of improvement has been to increase the capacity of the DRAM by increasing the area of the capacitor, while still limiting it by reducing the size of the switching gate transistor. Without increasing the size of the stacked capacitor structure, one of the methods to increase the surface area of the capacitor is to store the electrode structure at the storage node. No. Electrode Structure) uses a hemisphericai grained (HSG) silicon layer as the top surface area. The silicon layer can provide a continuous concave and convex structure, which can increase the surface area, thereby increasing the capacitance of the stacked capacitor structure. For example, U.S. Patent No. 5, 61 8, 747, the inventor Lou 'discloses the detailed manufacturing process of forming a stacked capacitor structure with HSG stone layers Λ 25 7 Ο 5 V. Description of the invention (2) process. However, it is related to the silicon material Compared with high dielectric constant dielectric layer and electrode materials such as Titanium Nitride (TiN), it is easier to have compatibility. High dielectric constant dielectric layer refers to other materials such as oxidation Silicon 'can provide more capacitance at the same thickness. Materials such as Barium Strontium T i tana te (BST)' Lead Zirconate Titanate (LZT), and tantalum Oxide). The present invention will describe a process that uses T i N as part of the capacitor structure to form a capacitor structure. In addition, compared with the process of manufacturing a smooth TiN layer, the present invention will provide the formation of HSG Π The process of the layer can increase the surface area and thus increase the capacitance. Taking US Patent No. 5,612, 558 as an example of 'inventor Harshfield', it describes the use of titanium nitride as the Underlying Seed Layer to form a hemispherical crystal A method for manufacturing a granular silicon layer. However, this conventional technique does not use an HSG TiN layer as a surface layer for a storage power-saving electrode structure. Therefore, it is an object of the present invention to manufacture a capacitor structure which can increase the surface area in a kDRAM device. Another object of the present invention is to form an HSG TiN layer and use the HSG T i N layer as a top surface layer of a storage node electrode. Another object of the present invention is to use an HSG TiN layer as a capacitor electrode (UPper Electrode) or a cell panel electrode (ceu Plate Electrode). Another object of the present invention is to use tantalum oxide (Ta205) as a capacitor. For the dielectric layer, HSG TiN is used as the capacitor electrode.

-_Λ257〇5_ 5. Description of the invention (3) To achieve the above-mentioned object, the present invention provides a method for forming an HSG TiN layer, which can be used as a structure of part of a DR AM capacitor, and can increase the surface area of the capacitor. Firstly, the following conversion gate electrode is provided on a semiconductor substrate. The body of the following conversion gate transistor includes a thin gate insulating layer: a polycrystalline silicon gate structure, and a semiconductor substrate. Next, a source layer and a drain region are deposited, and then an insulating layer is deposited. Then, a storage node contact hole is formed in the insulating layer, and the surfaces of the source and drain regions are exposed. A first polycrystalline silicon layer is deposited on the insulating layer to completely fill the storage node contact opening, and then, a bottom portion of the storage node electrode structure is formed by a patterning process. Low pressure chemical vapor deposition

Pressure Chemical Vapor Deposition (LPCVD) is at the bottom of the storage node electrode structure below: a hemispherical grain ^ HSG TiN layer is formed, and then a capacitor dielectric layer is formed. The second example is tantalum oxide (TVIII), silicon oxide, silicon oxide, or nitrogen on the oxide layer ^ silicon layer (〇XidiZed Silicon Nitride on 0xide), and then deposit a titanium nitride layer, and then deposit a second polycrystalline silicon layer Figure Z—Multi-crystalline silicon layer and titanium nitride layer to form the upper layer of DRAM capacitor structure, or saponin panel electrode. Let the above and other objects, features, and advantages of the present invention become clearer & 1 μ & amp The following is a detailed description of a preferred embodiment, and in conjunction with the attached drawings, detailed description of Tian § brother is as follows: Brief description of the diagram:

Figures 1 through 5 show the main section of the fabrication of a DRAM device with an STC structure.

425705 V. Description of the invention (4) The layer ′ can increase the surface area, and the HSG TiN layer is in direct contact with the capacitor dielectric layer. Explanation of symbols: ° 1: p-type semiconductor substrate; _ 2: field oxide region; 3. gate insulating layer; 4: compound silicon gate structure; 5. lightly doped source and drain region; 6: insulation interval Materials; 7: heavily doped source and drain regions; 8: third insulating layer; 9: storage node contact opening; I 0 · polycrystalline stone is popular; II: HSG TiN layer; 12: capacitor dielectric layer 13. TiN layer, composite layer; 14: storage node capacitor structure; and 20: cover insulation layer. Example: The method for forming a DRAM element proposed by the present invention will be described in detail below. The formed DRAM element has a partial structure with a HSG TiN layer as a bottom capacitor electrode (Bottom Capacitor Electrode), which can increase the surface area. Increase electric capacity. The switching gate transistor system used in the DRW element of the present invention is an N-channel element. However, the capacitor structure with increased surface area of the present invention can also be applied to P-channel switching idler transistors.

Page 7 425 7 05 5. In the description of the invention (5) ○ Please refer to FIG. 1 to provide a semiconductor substrate 1 having a p-type, a crystal plane of < 100 >, and a single crystal. Field Oxide (F0X) 2 can be used as a barrier. The formation of the field oxidation zone 2 is briefly explained: thermal oxidation is performed in an oxygen vapor environment ′ ′ at a temperature of 850 to 1050 ° C, and the thickness formed is about 3000 to 5000 angstroms. In order to prevent the formation of the field oxide region 2 in a subsequent element region on the surface of the substrate, a silicon nitride-silicon oxide layer is used as a patterned oxidation resistant mask. After the field oxide region 2 is formed, the silicon nitride layer is coated with a hot phosphoric acid solution, and a buffered hydrofluoric acid solution is used on the silicon oxide layer to remove the oxidation barrier mask. After a series of wet cleaning, the gate insulation layer 3 made of silicon oxide is formed at a temperature of about 85 to 1050 at a temperature of between 85 and 1050, and the thickness is about 50 to 200. Aye. Next, using a low-pressure chemical vapor deposition (LpcvD) method, a polycrystalline spar layer 4 is deposited at a temperature of about 500 to 700 C, with a thickness of about 15,000 to 4000 angstroms. The polycrystalline silicon layer 4 can be formed from the inside and ion-implanted with arsenic or phosphorus ions. The implantation energy is about 30 to 80] ^ ¥, and the implantation dose is about 1E13 to 1E16 at 0ms / cm2. 'Alternatively, the in-situ doping process can be used to form by mixing arsenic or phosphorus with silane. Then, LPCVD or plasma enhanced chemical vapor deposition (Plasma

Enhanced Chemical Vapor Deposition (PECVD) procedure to form a first oxide oxide layer 20 'as a Cap Insulator Layer, with a thickness of about 600 to 15,000 Angstroms. Perform the micro-view of the conventional technology & engraving with reactive ion (ReactiVe inn Etching, rie) 425705 5 'invention description ¢ 6) procedure to form a polycrystalline silicon gate structure 4 with a cover insulating layer 20, As shown in Figure ι. Among them, the RIE process uses CHh as an etchant for the silicon oxide layer 20 and C 12 as the etch agent for the polycrystalline spar layer 4. Then, Plasma Oxygen Ashing and thorough wet cleaning are used. Remove the photoresist. Then, phosphorus ion implantation is performed at an implantation energy of 20 to 50 KeV and an implantation dose of about 1E13 to 1E14 at 0ms / cm2 to form a lightly doped source and drain region 5. Then, using the LPCVD or PECVD process 'at a temperature of 400 to 700 1, a second insulating layer made of oxidized stone' is deposited to a thickness of about 15 0 to 4 0 0 Angstroms, followed by cHF3 as an etchant. Insulator Spacer 6 is formed on the polycrystalline silicon gate structure 4. Next, the implantation energy is 30 to 10 OKeV 'and the implantation dose is about ΙΕ14 to 5Ε16 atoms / cm2, and the clock ion implantation' is performed to form a heavily doped source and drain region 7. These programs are structured as shown in FIG. Then, by a LPCVD or PECVD process, a third insulating layer 8 ′ composed of silicon oxide or borophosphosilicate glass (BPSG) is deposited at a temperature of about 700 to 800 ° 0, and the thickness is about Between 3000 and 6000 Angstroms. Then, the third insulating layer 8 is subjected to a Planarization process using Chemical Mechanical Polishing (CMP) to form a flatter surface ′ to facilitate subsequent deposition and patterning processes. The above-mentioned deposition and planarization procedures are also shown in FIG. As shown in Fig. 2, through the conventional lithography technology and the RIE process using CHF3 as the etching agent (5) and the invention description (7) agent, the third insulating layer 8 is 9 and the heavily doped source and drain are exposed. The polar area becomes ashing of the storage node contact openings and thorough wet cleaning to remove the photoresistance = the surface. Then, in the plasma oxygen sequence, at a temperature of about 500 to 70 (rc, = .f), the LPCVD process is about 100 to 8000 angstroms. The thickness of the silicon layer or arsenic ions is formed by ion implantation. I is formed by intrinsic ions and is doped in situ with phosphorus. II is formed by adding phosphorus or U to the dual-crystal silicon layer. The following conversion dipole region 7 contacts. With the anisotropic RiE program of the conventional technique Γ, the program can form a polycrystalline stone profile as shown in Figure 2 (Polys Mountain C 〇n ShaPe) 10. Next, the bottom is wet-cleaned to remove the photoresist. ^ ^ ^ Next, the key hemispherical grain (hsg) vaporized titanium (TiN) layer 11 is deposited 'as shown in FIG. 3'. Using the LPCVD program 'at a temperature of 35 to 700 ° C' and a pressure of 5 to 40 torr and a deposition time of 30 to 15 () seconds, the HSG TiN layer 11 is formed to a thickness of about 200. To 800 angstroms. In the process of forming HSG TiN layer 11 by LPCVD, the components used are dragon 3 with a flow of 50 to 100 seem, flow of 10 to 70, and Nz of flow of 2000 to 4000 seem The HSG TiN layer 11 has an uneven surface area that is approximately twice as large as the conventional smooth TiN surface area. When the hsg TiN layer 11 is subsequently patterned, a storage node electrode can be formed, which includes an HSG T i N layer 11 The top of the composition and the bottom of the polycrystalline silicon profile 10.

_ 4 25 7 0 5 V. Description of the invention (8) Then 'as shown in Figure 4', a layer of the same thickness as the silicon oxide is deposited by the Metal Organic Chemical Vapor Deposition (MOCVD) procedure. The capacitor dielectric layer 12 is made of tantalum oxide (Taj5) and has a thickness of about 15 to 35 angstroms. The τ & 205 layer 12 can be directly deposited on the HSG TiN layer 11. Other dielectric materials with the same thickness of 40 to 100 angstroms, such as silicon oxide, silicon nitride, nitrogen oxide (Nitride_xide, NO), and 0N0, can also be directly applied to the HSG TiN layer 11. Next, as shown in FIG. 4 to FIG. 5, the upper electrode of the DRAM capacitor structure or the formation process of the cell panel structure is performed. One of the steps for forming the upper electrode structure is to use LPCVD or plasma vapor deposition (Piasma Vapor).

Deposition (PVD) procedure to form another TiN layer 13 with a thickness of about 200 to 1,500 angstroms. The TiN layer 13 can be used as an HSG-shaped TiN layer, or the TiN layer 13 can form a smoother surface due to the coarse bond of the surface of the HSG TiN layer 11 as a storage node electrode to meet the demand for capacitance. Another step includes forming a composite layer as the upper electrode structure. The composite layer 13 includes a TiN layer, or HSG TiN layer, with a thickness of about 2000 to 1000 Angstroms' and a polycrystalline layer overlying it. Silicon layer with a thickness of about 500 to 2000 Angstroms. As shown in Figure 4. If the required thickness of the polycrystalline silicon electrode is about 500 to 2000 angstroms', it is not necessary to use the underlying TiN layer. Next, the upper electrode layer 13, the capacitor dielectric layer 12, and the HSG TiN layer 11 are patterned by lithography and anisotropic RIE procedures, where (: 12 is Ding et al. And polycrystalline silicon etchant) At the same time, it is also the etchant of the capacitor dielectric layer 12. The photoresist is removed by the plasma oxygen ashing and thorough wet cleaning procedures. The storage node capacitor structure 14 is shown in FIG. 5.

425705 V. Description of the Invention (9) Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes without departing from the spirit and scope of the present invention. And retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Page 12

Claims (1)

a Zb (y 06 '_Please patent scope — 1 · In a DRAM device with a capacitor structure, the above method is used for the heart of a semiconductor substrate, and includes the following steps: Provide a gate electrode below the switching gate electrode The gate insulating sound upper transistor includes a silicon gate structure having a day-to-day silicon gate structure in the semiconductor substrate, and an insulating layer is deposited on the source and drain regions. A storage rib K is formed in the above insulating layer. The top surface of the Bai source and drain regions · 'touch the opening' and expose the above on the top surface of the above-mentioned insulating layer, a storage node structure is formed in the mouth /, and the storage node is in contact with the open node. The upper s = silicon profile in the contact opening 'And in contact with the above-mentioned bottom compound crystal silicon wheels, the insulating layer which is covered by the outline of the crystal silicon has not yet been deposited on the bottom compound plates by HSG τ from & A capacitor dielectric is deposited on the HSG T1N layer; a layer is formed on the capacitor dielectric layer. A photoresist is formed on the above electrode layer; θ is patterned using the photoresist as a mask. The upper electrode layer of the capacitor structure; the upper electrode layer is formed with the above photoresist as a mask, and the capacitor dielectric layer is patterned, and the photoresist is used as a mask to pattern the storage node mine The HSG TiN layer is traced to form the HSG TiN wheel 2b on the silicon profile of the above-mentioned bottom-to-day silicon. The manufacturing method as described in item No. of the scope of patent application, the above-mentioned bottom Fuyang silicon wheel gallery system The LPCVD process is used to form a crystalline silicon layer with a thickness of about 10,000 to 8000 Angstroms on page 13 of 425705. The patented compound silicon layer is formed by an anisotropic RIE process using C 12 as an etchant. Spar profile. 3. The manufacturing method described in item 1 of the scope of patent application, wherein the HSG TiN layer is LPCVD, at a temperature of 350 to 700 ° C, a pressure of 5 to 40 torr, and a deposition time of 35. It is deposited under 150 seconds and has a thickness of about 100 to 800 angstroms. The above LPCVD procedure uses NH3 with a flow of 50 to 150 seem, TiCl4 with a flow of 10 to 70 seem, and N2 with a flow of 2000 to 4000 seem. 4. The system described in item 1 of the scope of patent application The manufacturing method, wherein the capacitor dielectric layer is a Tads layer, is deposited with a thickness of 15 to 35 angstroms using the MOCVD procedure, and has the same thickness as that of silicon oxide. 5. The manufacturing method according to item 1 of the scope of patent application, wherein The capacitor dielectric layer is selected from the following material groups, including silicon oxide, silicon nitride, N0 (nitrogen oxide), or όνο, where the capacitor dielectric layer has a thickness of about 100 Angstroms and is the same thickness as that of silicon oxide . 6. The manufacturing method as described in the item of the scope of the patent application, wherein the upper electrode layer is an HSG TiN layer 'is deposited using a LpcVD process to have a thickness of ^ 200 to 1 500 Angstroms, or the upper electrode layer is a TiN layer The system is deposited to form a smooth surface with a thickness of about 2000 to 15,000 Angstroms. 7. The manufacturer as described in item 丨 of the patent application, wherein the upper electrode layer is a polycrystalline hair layer, and the thickness of the CVD is about 500 to 2000 angstroms. There are many ways 425705 6. Patented HSG TiN, or a TiN layer with a smooth surface, and a polycrystalline silicon layer with a thickness of 500 to 2000 Angstroms. 9. The manufacturing method according to item 1 of the scope of the patent application, wherein the upper electrode structure uses Cl2 as an etchant for the above-mentioned polycrystalline silicon layer, Cl2 as the silver etching agent for the above-mentioned HSG TiN layer, and Cl2 as the above The # dielectric of the capacitor dielectric layer is formed by an anisotropic RIE process. Page 15