TW432640B - High density DRAM device for simultaneously forming capacitor electrode board and metal contact structure - Google Patents

Abstract

A manufacturing method for DRAM device which is characterized for simultaneously forming capacitor electrode board to produce stack-type capacitor structure and forming the metal layer contact structure and word line contact structure. The process is characterized for depositing a barrier layer and a capping tungsten layer on the storage node, and the depositing process can completely fill up the metal layer contact opening and the word line contact opening. The method uses an anisotropic RIE procedure to conduct the pattern definition procedure so as to remove the undesired portion of the tungsten layer and barrier layer and form the capacitor electrode board, metal layer contact structure and word line contact structure which all comprise the tungsten layer and barrier layer that are all produced with a single deposition procedure and a single pattern definition procedure.

Description

r F4 32 6 4 0. V. Description of the Invention (i) [Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for simultaneously forming a capacitor plate using the same process steps. The method for constructing and constructing the metal layer contact window is suitable for a dynamic random access memory (DRAM) device. [Know-how] The semiconductor industry is constantly striving to improve the efficiency of semiconductor devices. On the other hand, it is also striving to reduce the production costs of the same semiconductor devices. The ability of components to be microplasticized or to fabricate semiconductor devices with submicron feature sizes has enabled the above-mentioned goals to take into account both performance and production costs. As a result of gradually reducing the capacitance and resistivity using smaller feature sizes, semiconductor devices, such as dynamic random access memory (DRAM) devices manufactured using sub-micron technology, can achieve their performance enhancement goals. In addition, smaller wafers can be obtained using sub-micron feature sizes, so more wafers can be accommodated on a limited size substrate area, thereby reducing the production cost of DRAM wafers. In addition to reducing production costs through miniaturization technology, DRAM production costs can be further reduced by simplifying process steps. For example, if a structure that conventionally had to be divided into several steps can be formed in a single process step, the production cost of a DRAM device can be effectively reduced. The present invention will introduce a process, SMP, to utilize the same process steps to simultaneously form a capacitor plate and a metal layer contact window. In the conventional technology, for example, the United States, No. 5, 5 97, 75 4 of Lou et al. Is a DRAM device with a multilayer capacitor structure, which has a polycrystalline silicon capacitor plate and a metal layer contact window structure. However, The Xi

Γ f4 32 6 4 ο 5. Description of the invention ¢ 2) Forming the capacitor electrode and metal layer contact The technology does not integrate the window in a single process step as in the present invention. [Summary of the Invention] In view of this, an object of the present invention is to provide a dynamic random access memory (DRAM) device, which includes a stacked capacitor (STC) structure and a metal layer contact window structure. Another object of the present invention is to provide a single process step to simultaneously form a capacitor plate ' of a stacked capacitor (STC) structure and a metal layer window structure. Yet another object of the present invention is to simultaneously form a capacitor plate including a tungsten layer on a titanium nitride barrier layer, and to form a "tungsten-titanium nitride" metal layer contact window structure, which is located in a contact opening in a semiconductor substrate ( via hole) on the exposed area = > According to the present invention, a process for manufacturing a high-density chirped device is disclosed, in which a capacitor plate with a laminated valley device (STC) structure and a metal layer contact window structure use the same Material and formed in the same step. A polycide gate structure and a silicon nitride spacer are formed on a thin gate insulating layer. The polycide gate structure includes polycrystalline silicon and tungsten silicide thereon. Covered with silicon. When the source and drain regions are formed in a region between the semiconductor gate structure in the semiconductor substrate, a polycrystalline silicon contact plug is disposed in the contact opening of the first insulating layer, wherein the polycrystalline silicon contact The plug is in contact with the source and non-electrode regions. Form a polycide bit line structure, including polycrystalline silicon and tungsten silicide above it.

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5. Description of the invention (3) In the contact opening of the second insulating layer, the polycrystalline silicon pad layer serving as a bit line contact window is connected to contact the source and drain regions of the semiconductor substrate. A storage point contact opening is opened in the third insulating layer and the second insulating layer to expose the upper surface of the polycrystalline silicon contact pad for contacting the source and drain regions of the semiconductor substrate. Second, a polycrystalline silicon storage point covered with a capacitor dielectric layer is formed in the storage point contact opening. Next, a first contact opening 'is opened in the third insulating layer, the second insulating layer, and the first insulating layer to expose the source and drain regions D of the semiconductor substrate, and the third insulating layer, the second insulating layer, A second contact opening is opened in a region of the first insulating layer and the silicon nitride layer above the plycide gate structure to expose the upper surface of the p0yc heart gate structure. A titanium nitride layer and a tungsten layer are deposited on the storage point structure and completely fill the first contact opening and the second contact opening. A pattern of a tungsten layer and a titanium nitride layer is defined to form a capacitor plate on a storage point structure at the same time, a base contact window is configured in a first contact opening, and a word line contact window is configured in a second contact opening. [Brief description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, several preferred embodiments are given below in conjunction with the accompanying drawings to make a detailed description as follows: Section 1 Figures 12 through 12 are cross-sectional views showing the main steps used to fabricate a high-density DRAM device. 'It uses the same steps to form a capacitor plate with STC structure and a metal layer contact window structure for high-density heart cells. in. iHmai i ^ h C: \ path \ 0516-4067-e.ptd ^ asr F4326 4 〇 5. Description of the invention (4) [Detailed description of the preferred embodiment] Now, the method for forming a high-density DRAM memory cell will be described in detail. It is characterized in that it can form a capacitor electrode plate with a STC structure and a metal layer contact window structure at the same time. An N-channel element for a transfer transistor system used in the DRAM device of the present invention. However, this process of simultaneously forming a capacitor plate with a STC structure and a metal layer contact window structure can also be applied to a DRAM device including a P-channel transfer transistor. Referring to Fig. 1, a P-type semiconductor substrate 1 having a single crystal orientation of <100> is used. Field One Oxidation (FOX) Zone 2 is used for isolation. In short, it is in an oxygen environment and the temperature is between 850 and 1050. (: Under the conditions, a thermal oxidation process is performed to form a field oxidation region 2 having a thickness of 30,000 to 50,000 angstroms. A silicon nitride-silicon oxide material with a defined pattern is used to prevent the oxidation reaction from blocking the mask. The FOX region 2 grows to a region where the semiconductor substrate 1 will be used to fabricate components later. After the FOX region 2 is grown, the surface silicon nitride layer is treated with a hot phosphoric acid solution and the underlying silicon oxide layer is treated with an argon fluoride solution. Remove the above-mentioned oxidation reaction blocking mask. After a series of cleaning, the silicon dioxide gate insulation is thermally hardened to a thickness of 50 to 200 angstroms in an oxygen environment at a temperature of 850 to 1050 ° C. Layer 3. Second, at a temperature between 500 and 700. (: conditions, a low-pressure chemical vapor deposition (LpcvD) procedure is used to deposit a polycrystalline silicon layer having a thickness of 50 to 2000 angstroms. 4. This polycrystalline silicon The layer can be grown separately and then implanted by arsenic or phosphorus ions for doping. Its energy is between 30 and 80 KeV, and the dose is between 1 xl0u to! Xl016 atoms / cra2; Add Arsenic or Phosphorus to SiMethane (In-situ dop i ng) prepared program. Next to

r F4 326 4 ^ V. Description of the invention (5) LPCVD process deposits a first tungsten silicide layer with a thickness between 500 and 2000 angstroms 5 'and then deposits it by LPCVD or plasma enhanced chemical vapor deposition (PECVD) deposition process. The first siliconized silicon cap layer 6 having a thickness of 600 to 1500 angstroms ^ using conventional optical lithography and reactive ion etching (RIE) procedures (using CF 4 as an etchant for the first silicon nitride layer 6 'to tungsten silicide The layer 5 and the polycrystalline silicon layer 4 use c 12 as an etchant) to form a polycide structure 10 ′ (tungsten silicide-polycrystalline silicon structure), which is covered with a first nitride layer 6 as shown in FIG. 1. The photoresist layer is removed by an oxygen plasma treatment and a fine wet cleaning step. Secondly, a lightly doped source and drain region 7 ′ is formed by a phosphorus ion implantation procedure, and the implantation energy is between 20 and 50 KeV, and the dose is between ΐχΐιι3 and ix 1014 atoms / cm2. Then at a temperature between 400 and 700. (: Under the conditions, LPCVD or PECVD procedures are performed to deposit a second nitride layer with a thickness of 1500 to 4000 Angstroms. Then an anisotropic RIE procedure is performed using CF4 as a money etcher for polycide gates. A gasified silicon spacer (3? 306): 8 is formed on the side wall of the structure 10. In this way, the mouth 0170: 1 (16 gate structure 10 can be the first silicon nitride layer 6 and silicon nitride The gap wall 8 is completely covered. Then, a heavily doped source electrode and a non-electrode region 9 are formed by a rubidium ion implantation procedure, the implantation energy is between 20 to 100 KeV, and the dose is between 1X1014 to 5xi〇i6at〇ms / cm2. The results are shown in Figure 2. The first insulating layer of silicon oxide material with a thickness of 3000 to 8000 angstroms is deposited by LPCVD or PECVD at a temperature of 400 to 800 ° C. 1 1 'Next, a chemical mechanical polishing (CMP) process is performed to planarize the first insulating layer 11 to produce a flat surface. The first insulating layer 11 is sequentially subjected to photoresist patterns 12 as a mask. Traditional optical lithography

C: \ path \ 0516-4067-e. Ptd page 8 r 32 6 4 η ___ 5. Description of the invention (6) and anisotropic RIE process using CHF3 as an etchant, and the first insulating layer A self-aligned contact window (SAC) opening 13 and a SAC opening 14 are opened in 11 so as to expose the heavily doped source and drain regions 9 between the pOiCide gate structure 10 covered with nitride stone. surface. The result is shown in Figure 3. 'SAC opening 1 3 will be used for contact between subsequent bit lines and source and drain regions' while SAC opening 1 4 will be used for STC structure and source and drain regions Contact. The photoresist layer was removed by an oxygen plasma treatment and a careful wet cleaning step. Then, a conductive polycrystalline silicon contact plug 16 is formed, as shown in FIG. 4. The step of forming the polycrystalline silicon contact plug 14 is to first deposit a polycrystalline silicon layer according to the LPCVD process. 〇OO-3000 angstroms, the polycrystalline silicon layer can be doped during an in-situ deposition process, or a polycrystalline silicon layer is deposited separately and then doped with a crushing or ion implantation process. Miscellaneous; Next, an anisotropic rie procedure using Cl? As an etchant, or a CMP procedure is used to make a pattern. The above-mentioned anisotropic r 丨 E procedure for removing unnecessary portions of the polycrystalline silicon layer on the surface of the first insulating layer 11 is continued to form a recessed polycrystalline chip contact plug 16 ′, which is lower than the first insulating layer 11. The upper surface, as shown in Figure 4. At a temperature of 65 to 75 ° C, a second insulating layer 17 of silicon oxide material is deposited by a LPCVD or PECVD process to a thickness of 2000 to 4,000 angstroms. The second insulating layer 17 may be BPSG Or PSG layer, which is prepared by combining 卩} ^ 3 with B2He or only adding phs separately to tetraethoxysilicone (te0s). The second insulating layer 17 is used Photoresist pattern 18 as a traditional optical lithography process for masks' and anisotropy using CHF3 as an etchant

C: \ path \ 0516-4067-e. Ptd page 9 r W4 32 β-V. Description of the invention (7) The RIE procedure is used to form the contact window opening 19, which is exposed in the SA (: opening 3 and used to communicate with The upper surface of the polycrystalline silicon contact plug 16 for subsequent bit line contact is as shown in Figure 5. After the photoresist pattern 18 is removed again by oxygen plasma treatment and careful wet cleaning steps, fabrication is performed. The step of constructing the polycide bit line 22. First, a polycrystalline silicon layer 20 having a thickness of 500 to 200 angstroms is deposited by the lpCVD process. Again, the polycrystalline silicon layer may be formed by applying arsenic or The dish is added to the stone sintering and doped during a simultaneous deposition process, or a polycrystalline silicon layer is deposited separately and then doped with an arsenic or phosphorus ion implantation process. Next, it is deposited using the LPCVD process Another tungsten sulfide layer 21 having a thickness of 50 to 2000 angstroms. 1. An optical lithography process and an anisotropic RIE process using CHf3 as an etchant are performed to form a poiycide (tungsten silicide). -Polycrystalline silicon stack) bit line structure 22 'as shown in Figure -6. Through contact with the complex aa chip in the SAC opening 1 3 16 Direct contact, pOlyCide bit line structure 22 can be in contact with the source and drain regions below. Oxygen plasma treatment and careful wet cleaning steps are performed again to remove the above definition P 01 yc 丨 de Photoresist pattern 18 of the mask of the bit line structure 22. At a temperature of 400 to 80 ° (under conditions, a PECVD or LPCVD process is used to deposit a third insulating layer of silicon oxide material with a thickness of 2000 to 4000 angstroms). Layer 23 'followed by a CMP process to planarize the upper surface of the third insulating layer layer 23. Next, a photoresist pattern 24 is formed as an etching mask, and an anisotropic process using CHF3 as an etchant is performed. A storage point contact opening 25 is formed in the third insulating layer 23 and the second insulating layer 17 to expose the contact openings 25 located in the SAC opening 14 for providing subsequent STC structures in contact with the source and drain regions. The upper surface of the polycrystalline silicon contact plug 16 is as shown in FIG.

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After the oxygen plasma treatment and careful wet cleaning steps of the container dielectric layer 27 of the photoresist pattern 24 are performed, the two steps of manufacturing the polycrystalline silicon storage point electrode are performed. To borrow a stored electrode 26, the LPCO program is first set to a degree between _ and 120 °. Angstrom, to completely fill the polycrystalite layer in the deposition process can be carried out by firing with ❹㈣f. Then, perform optical lithography and use. 2 An anisotropic RIE process as an etchant to form a polycrystalline silicon storage point electrode 26. After removing the photoresist pattern η used to define the polycrystalite storage point electrode 26 with an oxygen plasma treatment and a careful wet cleaning step, a high dielectric constant layer 27 is deposited by an RF sputtering process. On the polycrystalline silicon storage point electrode 26, for example, Ta205, the thickness is between 50 and 200 Angstroms. The capacitor dielectric layer 27 may also be formed by chemical vapor deposition (cvd) or plasma vapor deposition (PVD). ) A layer of barium strontium titanate deposited by procedures, having a thickness between 50 and 200 angstroms. A RI program using ci24HBr as an etchant is performed to remove the unnecessary portion of the capacitor dielectric layer 27 on the surface of the third insulating layer 23 to obtain a polycrystalline silicon storage point electrode 26 covered with the capacitor dielectric layer 27, such as Shown in Figure 8. (When the unnecessary capacitor dielectric layer 27 is removed from the surface of the third insulating layer 23, the capacitor dielectric layer 27 covering the polycrystalline silicon storage point electrode 26 is protected with a photoresist.) Next, a photoresist is used. The pattern 28 is used as a mask to perform an anisotropic RIE process and make a word line contact in the third insulating layer 2 3, the second insulating layer 1 7, the first insulating layer 11, and the silicon nitride capping layer 6. Opening 29 to expose polycide

C: \ path \ 0516-4067-e. Ptd page 11 F4 3 2 P 4-V. Description of the invention (9) The upper surface of the gate structure 10. The same procedure is performed to open a metal layer contact opening 30 'in the third insulating layer 23, the second insulating layer 17 and the first insulating layer 1 丨 to expose an area of the semiconductor substrate 1. The anisotropic RIE process uses CHFs as an etchant. The above process steps are shown in Figure 9. After removing the above-mentioned photoresist pattern 28 by using an oxygen treatment and a careful wet cleaning step, a so-called SPM process is performed, that is, a structure of a contact window of a capacitor plate and a metal layer is formed at the same time. First, a barrier layer 31 is deposited to a thickness of between 100 angstroms and 100 angstroms. The barrier layer 31 may be a titanium nitride layer or a tungsten nitride layer deposited by a radio frequency sputtering process. Secondly, a tungsten layer 32 having a thickness of 1000 to 5000 angstroms is deposited by LPCVD or radio frequency key bonding procedures to completely fill the word line contact openings 29 and metal layer contact openings 30, as shown in FIG. 10 By. Secondly, optical lithography and RIE procedures using ci as a money engraving agent are performed on the crane layer 32 and the barrier layer 31 to form a capacitor plate structure of the STC structure 33. It includes the crane layer 32 and the barrier layer 31 and is covered in a package. The storage point electrode is covered with a capacitor dielectric layer. The same optical lithography and RIE procedures can be used to form the word line contact window structure 34 and the metal layer contact window structure 35 at the same time. The ability to completely fill the word line contact openings 29 and the metal layer contact openings 30 with the metal layer promotes the purpose of simultaneously defining the capacitor plate, the word line contact window structure, and the metal layer contact window structure. RIE removes portions of the tungsten layer 32 and the barrier layer 31 on the surface of the third insulating layer 23 that are not covered by the mask. The photoresist pattern was removed again using an oxygen plasma treatment and a careful wet cleaning step. The results are shown in Figure 11.

C: \ path \ 0516-4067-e * ptd page 12 32 6 V. Description of the invention (ίο) Figure 12 shows the production of the metal interconnecting wire structure 38, which makes some contact with the metal layer contact window structure. A PECVD or LPCVD process is used to deposit a fourth insulating layer 36 having a thickness between 2 000 and 10,000 Angstroms, and a C Mp process is performed.

Flattening process. Optical lithography and a β J E procedure using C as an etchant are performed to form the opening 37 of the contact window, exposing the upper surface of the metal layer contact window structure 35. After the photoresist pattern used to form the contact window opening 37 is removed by an oxygen plasma treatment and a careful wet cleaning step, an aluminum layer having a thickness of 2000 to 5000 angstroms is deposited by a radio frequency sputtering process. Contains about 0 to 3.2% copper content. Optical lithography and a Rig procedure using ci2 as a nicking agent is performed to form a metal interconnect wire structure 38, as shown in FIG. The photoresist pattern was removed again using an oxygen plasma treatment and a careful wet cleaning step. Although the present invention has been disclosed as above with several preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be as defined in the attached patent application park.

Claims (1)

f &gt; 4 326 4 0___ 6. Application for Patent Scope 1. A method for simultaneously manufacturing a capacitor plate, a word line contact window structure, and a metal layer contact window structure of a multilayer capacitor structure is applicable to a DRAM device, which The method includes the following steps: setting a plurality of transfer transistors on a semiconductor substrate, each including a polycide gate structure formed on a gate insulating layer; and a source and drain region formed on the semiconductor; On the area of the substrate that is not covered by the polycrystalline silicide gate structure; the polycrystalline silicon contact plug is located in the contact opening ^ uuu α iupl ug y yjs ^ ^ ^ The contact plug is located between the complex silicide gate structure and the transfer transistor, and the complex silicon contact plug is in contact with the source and drain regions of the transfer transistor. Surface; 乂 exposes the complex The top surface of the crystalline silicon contact plug is contacted with the crystalline silicon contact plug; the contact opening is formed to form a capacitor dielectric layer in the second composite insulating layer. On the electrode A metal layer of a semiconductor substrate is contacted in a third composite insulating layer. A complex silicide structure is formed. The character line contacts the upper surface of the capacitor dielectric layer; The metal layer: a second barrier layer covering the sidewall and bottom of Θ u on the sidewall and bottom of the storage braille line contact opening and the σ π to be exposed to be exposed "醪 4 R d R_____ VI. Patent application scope Deposit a tungsten layer on the barrier layer 'to completely fill the metal layer contact opening and the word line contact opening; and define the town layer and the barrier layer. Patterning to form the capacitor plate on the capacitor dielectric layer of the storage point electrode, forming the word line contact window structure in the word line contact opening, and forming the metal in the metal layer contact opening Layer contact window construction. 2. The method according to item 1 of the scope of patent application, wherein the step of forming the polycrystalline silicon contact plug is firstly depositing a polycrystalline fragment layer with a thickness of 1 to 3000 angstroms by the LPCVD procedure. The silicon layer can be doped during an in-situ deposition process, or doped with an arsenic or phosphorus ion implantation process and then 'anisotropic' RIE process using Clg as an etchant to remove the first An unnecessary portion above an insulating layer, or a CMP program, removes unnecessary portions of the polycrystalline silicon layer, and defines the pattern of the polycrystalline silicon layer. 3. The method according to item 1 of the scope of patent application, wherein the storage point contact opening is opened in the first composite insulating layer by using an anisotropic r I e program using CHF3 as a money engraving agent, wherein The first composite insulating layer includes: a third silicon oxide insulating layer deposited by the LPCVD or PECVD process, the thickness of which is between 2000 and 5000 angstroms; and a second silicon oxide insulating layer deposited by the LPCVD or PECVD process, the thickness of which is Between 200 and 4000 Angstroms. 4. The method according to item 1 of the scope of the patent application, wherein the storage point electrode is made of an N-type polycrystalline stone layer 'which is deposited to a thickness of 4,000 to 12,000 angstroms using the LPCVD process' and is co-located Simultaneous doping during the deposition process and then using an anisotropic R e process with C 12 as an etchant C: \ path \ 0516-4067-e. Ptd page 15 32 6 4 η 6. Scope of patent application Make patterns. 5. The method according to item 1 of the scope of patent application, wherein the material of the capacitor dielectric layer is Ta205, which is deposited using a radio frequency sputtering process and has a thickness of 50 to 200 angstroms. 6_ The method according to item 1 of the patent application, wherein the material of the capacitor dielectric layer is bariuin strontium titanate, which is deposited using a CVD or PVD process, and the thickness is between 50 and 50. To 200 angstrom. The method according to item 1 of the patent application range, wherein the metal layer contact opening is opened in the second composite insulating layer using an anisotropic RIE process using CHF3 as an etchant. Wherein the second composite insulating layer includes: the third insulating layer; the second insulating layer; and a first silicon oxide insulating layer deposited by LPCVD or! ^^!) Procedure, the thickness of which is between 300 and 8 〇〇〇〇〇. The method described in the scope of the first patent application, wherein the word line contact openings using a non-isotropic κ E program using CHF3 as an etchant in the third composite insulating layer Opened, wherein the first composite insulating layer includes: the third insulating layer; the second insulating layer; the upper half of the first insulating layer 'has a thickness ranging from 2000 to 8000 angstroms; The thickness of the silicon nitride layer on the object gate structure is between 1 and 10 3〇〇〇 billion to Egypt. 9. The method according to item 1 of the scope of patent application, wherein the material of the barrier layer is titanium nitride, which is deposited using a radio frequency sputtering process, and has a thickness of 100 to 100 angstroms. 10. The method as described in claim 1, wherein the barrier layer Γ 14 32 6 4 η 6. The material for patent application is tungsten nitride 'which is deposited by RF sputtering process and its thickness is between 100 and 100 Angstroms. 11. The method according to item 1 of the scope of the patent application, wherein the tungsten layer is deposited using LPCVD or radio frequency sputtering procedures, and has a thickness of about 500 Angstroms. 12. The method as described in the item of the scope of patent application, wherein the pattern of the tungsten layer and the barrier layer is defined by an anisotropic RIE program using C12 as a post-etching agent, and is used to simultaneously form The capacitor plate, the metal layer contact opening, and the word line constructor. 13. A method for manufacturing a DRAM device on a semiconductor substrate, wherein a capacitor plate of a multilayer capacitor structure, a word line contact opening, and a metal layer contact opening are all formed by a single deposition process and a single pattern definition process. It is formed and includes the following steps: # J set a plurality of transfer transistors on the semiconductor substrate, each including a polycrystalline silicide gate structure covered with a silicon nitride, formed on a gate insulating layer, and a source And a drain region formed on a region of the semiconductor substrate between the nitrided polysilicon gate structures; depositing a first insulating layer; planarizing the first insulating layer; forming Self-align the contact openings in the first insulating layer to access the first source and drain regions' and to the second source and drain regions; deposit a first polycrystalline silicon layer to completely fill The self-aligned contact removes the first polycrystalline silicon layer on the surface of the first insulating layer to form C. \ path \ 0516'4067_e, ptd Page 17 Alignment within the contact opening α; The polycrystalite in the mouth contacts the recess of the plug, the height of the surface; the mouth leads to the plug located at the first source and drain regions ; The pattern of the first polycrystalline stone layer is configured in the bit line contact window, which is located in the second insulating layer to open an upper surface of a storage point contact contact plug, which is located in the first pattern In order to expose the storage point contact opening on the storage point contact opening; a second insulating layer, t ′ and an area of the first insulating layer to expose the semiconducting semiconductor substrate; 6. Patent application scope for polycrystalline silicon A contact plug is deposited on the self-aligning contact to deposit a second insulating layer below the first insulating layer; a first polycrystalline silicon contact plug is opened above the first insulating layer to deposit a second A polysilicon layer is deposited with a tungsten silicide layer; a third insulating layer is deposited above the polysilicon contact plug defined by defining the tungsten silicide layer and the element wire contact opening; and planarizing the third insulating layer at The third insulating layer and the opening 'to expose the second Crystalline silicon source and drain regions; depositing a third polycrystalline silicon layer to define a storage point electrode in the third polycrystalline silicon layer; forming a capacitor dielectric layer on the third insulating layer, the opening A metal layer contacts the opening on the third insulating layer, the second insulating layer, and the first insulating layer. C: \ path \ 0516-4067-e. Ptd page 18 Miao 4 3264 〇 6. Half of the patent application scope, and a word line contact opening is made in a silicon nitride layer to expose the silicon nitride The upper surface of the clad polysilicon gate structure; a barrier layer is deposited on the capacitor dielectric layer, the storage point electrode, the surface exposed by the metal layer contact opening, and the surface exposed by the daughter wire contact opening Depositing a tungsten layer on the barrier layer to completely fill the metal layer contact opening and the word line contact opening; and defining a pattern of the tungsten layer and the barrier layer to form the stacked type simultaneously A capacitor plate of a capacitor structure, the metal layer contact window structure in the metal layer contact opening, and the character line contact window structure in the character line contact opening. 14. The method according to item 13 of the scope of patent application, wherein the material of the first insulating layer is silicon oxide * which is deposited by a LPCVD or PECVD process to a thickness of 300,000 to 80,000 Angstroms, and The CMP process is used for planarization. 15_ The method as described in item 13 of the patent application, wherein the first polycrystalline silicon layer used to fabricate the polycrystalline silicon contact plug is deposited by the LPCVD process and has a thickness between 1000 to 3000 angstroms, and adding arsenic or phosphorus to the in-situ dopant in the silicon methane environment during the deposition process, or first depositing the first polycrystalline silicon layer and then performing an arsenic or phosphorus ion implantation process to Doping. 16. The method according to item 13 of the patent application, wherein the material of the second insulating layer is silicon oxide, which is deposited using a LPCVD or PECVD process, and has a thickness ranging from 200 to 4000 angstroms. C: \ path \ 0516-4067-e. Ptd page 19 "鼷 4 32 6 4 ο 6. Patent application scope 1 7 'Method as described in item 13 of the patent application scope', which is used to make the bit The second polycrystalline silicon layer of the line contact window structure is deposited by the LPCVD process to a thickness of 5000 to 2000 Angstroms, and is added by a silicon dioxide environment during the isotopic deposition process. N-type doping, or first depositing the second compound; the layer is then doped with a god or ion implantation procedure to perform doping. 18. The method according to item 13 of the scope of patent application 'wherein The tungsten wire silicide layer of the bit line contact window is deposited using the LPCVD process, and its thickness is between 500 and 2000 angstroms. 19_ The method according to item 13 of the patent application scope, wherein the third insulating layer The material is silicon oxide, which is deposited by a PECVD or LPCVD process to a thickness of between 200 and 4000 angstroms, and is planarized by a CMP process. 20. The method according to item 13 of the scope of patent application, wherein The third polycrystalline silicon layer used to make the storage point electrode is deposited by the LPCVD process. 'Its thickness is in the range of 4000 to 12000 Angstroms, and N-type doping is performed by adding arsenic or phosphorus in a silicic acid environment during the isotopic deposition process. 21_ The method according to item 13 of the patent application scope, wherein The material of the capacitor dielectric layer is Ta205, which is deposited using a radio frequency sputtering process and has a thickness of 50 to 200 angstroms. 22. The method according to item 13 of the patent application scope, wherein The material is barium lithium titanate, which is deposited using CVD or PVD procedures. Its thickness is between 50 and 200 angstroms. 23. The method according to item 13 of the patent application scope, wherein the barrier C: \ path \ 0516-4067-e. Ptd Page 20t Fermentation 4326 4 ο 6. The scope of the patent application layer is made of titanium nitride, which is deposited using RF sputtering process. Its thickness is between 100 and 1 0 0 0 Angstroms. The thickness of the tungsten layer is between 24, and the method described in item 13 of the patent application range, wherein the material of the barrier layer is tungsten nitride, which is deposited using a radio frequency sputtering process, and the thickness is between 100 and 100. 100 Angstroms. 25. The method described in item 3 of the patent application range is deposited by using the LPCVD process or the radio frequency Tibetan forging process from 1 to 5000 angstroms. 26. The method as described in item η of the scope of patent application. Cavity, -------- Anisotropic r I Ε program using C12 as an etchant to define the pattern of the tungsten layer and the barrier layer And used to form the capacitor plate, the metal layer contact opening, and the word line structure at the same time. C: \ path \ 0516-4067-e, ptd p. 21