TW425696B - Semiconductor memory device having capacitor encapsulated with multiple layers and method of manfacturing the same - Google Patents

Semiconductor memory device having capacitor encapsulated with multiple layers and method of manfacturing the same Download PDF

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Publication number
TW425696B
TW425696B TW088115902A TW88115902A TW425696B TW 425696 B TW425696 B TW 425696B TW 088115902 A TW088115902 A TW 088115902A TW 88115902 A TW88115902 A TW 88115902A TW 425696 B TW425696 B TW 425696B
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Taiwan
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layer
capacitor
barrier
dielectric
scope
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TW088115902A
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Chinese (zh)
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Yong-Tak Lee
Hag-Ju Cho
Yeong-Kwan Kim
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/7687—Thin films associated with contacts of capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3192—Multilayer coating

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A semiconductor memory device having a capacitor which is encapsulated with multiple layers, and a method for manufacturing the same. The capacitor of the semiconductor memory device is covered with the multi-layered encapsulating layer. The encapsulating layer includes at least a blocking layer and a capacitor protection layer. The blocking layer is formed of a material layer capable of preventing a capacitor dielectric layer from volatilizing and/or capable of preventing a reaction between a material layer under the blocking layer and the capacitor protection layer. The capacitor protection layer is formed of a material capable of preventing diffusion of hydrogen into a capacitor dielectric layer. The encapsulating layer can prevent deterioration of the capacitor dielectric layer during an interlayer dielectric (ILD) process, an intermetal dielectric (IMD) process and a passivation process.

Description

4 25 6 96 A7 經濟部智慧財產局員工消費合作杜印製 五、發明説明（丨） 本發明之背景 本發明之領域 本發明係有關於一種半導體記憶裝置及其製法，更特 別地是，有關於一種具有多層包封電容器的半導體記憶裝 置及其製法。 相關技藝之說明 近來，在半導體記憶裝置的領域中，極大的.注意力係 集中於一種形成具有鐵電材料之電容介電層的方法。此乃 因在非揮發性半導體裝置中，鐵電性材料的殘留極性(pr)與 已廣泛使用之形成數位記憶裝置的基本之二元記憶觀念相 符。目前，有二種主要的鐵電材料在使用：PZT (Pb(Zr，Ti)03)以及 SBT (SrBi2Ta209” 然而，在形成具有一鐵電材料的半導體記憶裝置的電 容介電層中，嚴重的問題之一係鐵電材料的鐵電特性在形 成電容器後之半導體記憶裝置整合製程進行期間f化。亦 艮P，在一中間層介電質(ILD)製程、一介金屬介電質(IMD) 製程以及一鈍化製程期間（在電容器形成後進行）所產生 之污染物（特別是氫）將劣化Pr，其係鐵電材料的鐵電特 性之一。 例如，在進行ILD製程以形成一諸如氧化矽層之ILD 層的狀況中，在一普通的鐵電電容器形成於一半導體基板 上後，該電容介電層可能劣化。亦即，在氧化矽層藉電漿 輔助化學氣相沈積法而形成的ILD製程中，係使用一含有 3 ___ 本紙張尺度適用中圉國家標準（CNS ) A4規格（2IOX297公釐） ----------^------ΐτ------^ {請先聞讀背面之注意事項再填Κ入V頁) 425696 A7 B7 五、發明説明（> ) 矽烷(SiH4)與氧（02)的反應氣體。順帶一提的，氫係來自於 藉矽烷與氧氣反應之ILD製程的副產物。所產生的氫直接 擴散入該電容介電層，而造成該電容介電層的劣化。所產 生的氫亦包含於該ILD層中，並逐漸地擴散至電容器之介 電層中，因而在後續的整合製程中以及半導體記憶裝置的 操作中使得電容介電層劣化。所以，該電容介電層的Pr降 低，而使得一半導體記憶裝置的可靠度降低。在最差的狀 況中，該電容介電層的h降低造成電容介電層之鐵電特性 的喪失。 因此，爲解決這些問題，一種傳統的半導體記憶裝置 製法已採用一種在電容器形成後將電容器以一單一絕緣層 包封的方法。然而，.單一絕__緣層無法有赛地避免氫所造成 之電容介電層劣化。例如，美國專利第_5J22，175號揭示 一種以一氧化矽層、一摻雜的氧化矽層或一氮化矽層包封 一電容器之方法，以解決氫擴散而劣化電容介電層的問題 杜衣 訂 線 (請先閱讀背面之注意事項再填广V頁) 經濟部智慧財產局員工消費合作社印製 本發明之槪要 本發明之一目的係提供一種具有以多層包封之電容器 的半導體記憶裝置。 本發明之另一個目的係提供一種半導體裝置製法，藉 此，一電容器可在形成電容器之後的半導體裝置整合製程 期間得到保護。 在本發明之一特性中，係提供一半導體記憶裝置，其 4 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐} 經濟部智慧財產局員工消費合作社印製 425696 A7 —____B7____ 五、發明説明（4 ) 中該裝置包含具有一下電極、一上電極以及一置於上下電 極間之電容介電層的電容器，一形成於該電容器上之多層 包封層、一形成於該多層包封層上的介電層、一上電極金 屬接觸（穿經該介電層而與上電極接觸）以及一下電極金 屬接觸（穿經該介電層而與下電極接觸）。 該包封層包含至少一阻絕層以及一電容器保護層，且 該阻絕層係位於該電容器保護層下方。 該阻絕層可以是能避免該電容介電層揮發和/或避免一 材料層(其形成於該阻絕層下方）與該電容器保護層反應之 材料所形成的一材料層。該阻絕層最好爲一 Ti〇2層、一 Ta205 層、一BaTi03 層、一 SrTi03 層、一 Bi4Ti30丨2 層、 一 PbTi03 層、一Si〇2 層、一 SiN 層、一(Ba，Sr)Ti03 層' 一(卩1?，1^)(21'，7^)03層、一 Pb(Zr，Ti)03層或一SrBi2Ta209 層 。該阻絕層的厚度可爲50-1500埃。該阻絕層可爲在400-600°C之氧氣氣氛中退火的一材料層。 該電容器保護層可以是能避免氫擴散進入電容介電層 的材料所形成的一材料層。該電容器保護層最好爲一 Ti〇2 層、一Ta205 層、一a1203 層、一BaTi03 層、一 SrTi〇3 層 、一Bi4Ti3012 層、一pbTi03 層、一Si02 層、一SiN 層' 一（Ba，Sr)Ti03 層、—（Pb，La)(Zr，Ti)03 層、—Pb(Zr，Ti)〇3 層或一 SrBi^aiO9層。該電容器保護層最好可與阻絕層的 材料相異。該電容器保護層的厚度可爲5〇_15〇〇埃。該電 容器保護層可爲在400-600t：之氧氣氣氛中退火的一材料層 〇 5 本紙張尺度適^中國國家標準（CNS > Μ規格（210X29^^^5 -— I I I Ϊ — I — Ε "•訂 I . I 線 (請先閲讀背面之注意事項再填广本頁) 經濟部智慧財產局員工消費合作社印製 425696 A7 _____B7 五、發明説明（屮） 在本發明的另一特性中，係提供—種製造半導體記憶 裝置的方法，其包含的步驟有：形成具有一下電極、一上 電極以及一置於上下電極間之電容介電層的電容器於一半 導體基板上的步驟’以及形成一包封層而以多層覆蓋電容 器的步驟。本發明的另一特性，可更包含形成一介電層於 該包封層上的步驟》 圖式之簡要說明 本發明之上述目的與優點將藉由參考附圖詳細說明其 較佳實施例而變得更淸楚，其中： 圖1至圖5係舉例說明根據本發明之較佳實施例，一 種具有多層包封電容器的半導體記憶裝置之製法的剖面圖 ， 圖6與圖7係舉例說明該後續整合製程之剖面圖，其 係於將該電容器以多層包封後進行，有助於瞭解根據本發 明之製造半導體記憶裝置的方法所形成之包封層的功能； 圖8係舉例說明根據本發明之另一較佳實施例，一種 具有多層包封電容器的半導體記憶裝置之製法的剖面圖； 圖9與圖1〇分別顯示一電容器之電容介電層遲滯曲線 與該電容器之漏電流特性的圖形，其係以根據本發明之方 法所製造的樣品C1來測試； 圖Π與圖12分別顯示遲滯曲線與阻障接觸電阻的圖 形’其係以根據本發明方法所製造的樣品C1與由不同方 法所製作之各具有一單一包封層的樣品C2與C3來測試。 6 ----------^------1T------0 (請先閱讀背面之注意事項再填f.本頁) I紙張尺度適用V國國家標準（CNS7八^格（210X297公釐） 425696 經濟部智慧財產局員工消費合作杜印製 A7 __B7_ 五、發明説明（< ) 較佳實施例之說明 本發明現將參考附圖而更完整地說明，其中所示係本 發明的較佳實施例，係有關於一種具有多層包封電容器的 半導體記憶裝置及其製法。然而，本發明可以多種不同形 式實施，而不應認爲僅限於在此所示的實施例，而所提供 的這些實施例將使得本揭示更透徹與完整，並將本發明之 觀念完整地傳遞予熟習本技藝之人士。在圖式中，誇大諸 層與區域的厚度以便淸楚表示。亦應瞭解的是，當一層稱 爲在另一層或基板「上」時，其可能直接在該層或基板上 ，或者可能於其間存在中間層。在參考圖1至圖4以及圖 8說明之本發明的實施例中，一半導體記憶裝置的電容器 係以一電容器在位元線上(COB)的構造來形成。然而，本 發明亦可應用於電容器以一電容器在位元線下（CUB)的構 造來形成的狀況。 實施例1 參考圖1，一隔離層101形成於一半導體基板1〇〇上 ，以定義一主動區，其次形成一電晶體於該主動區中β該 隔離層101可藉一般的方法形成，例如藉矽的局部氧化 (LOCOS)製程。該電晶體可爲具有一閘電極105 (具有側 壁間隔物103與形成於其下的一閘極絕緣層1〇4)、一汲 極區106與一源極區107的場效應電晶體。 其次’一位元線Π0係以一般的方法形成。亦即’形 成一第一介電層108，且一導電插塞109 (其與電晶體的汲 7 本紙張尺度適用中國國家標準（CNS ) A4规格（210X297公釐） ---------装------1T------0 (請先閏讀背面之注意事項再填f本頁) A7 4 6 9 6 -----------B7 _ 五、發明説明（L ) 極區1〇6接觸）形成於該第一介電層108中。其次，該位 元線110形成於該導電插塞109上，而一第二介電層112 形成於該位元線Π0上。 第一與第二介電層108和112可爲氧化矽層、氮氧化 砂層、硼矽酸鹽玻璃(BSG)層、磷矽酸鹽玻璃(PSG)層、硼 磷矽酸鹽玻璃(BPSG)層、四乙基正矽酸鹽(TEOS)層、臭氧 (〇3)-TEOS層、電漿輔助(PE)-TEOS層、未摻雜的矽酸鹽 铍璃(1^0)層或上述諸層的複合層。該第一與第二介電層 和112可藉由一般的方法形成，例如藉低壓化學氣相 沈積法(LPCVD)或電漿輔助化學氣相沈積法(PECVD)。 其次，進行一光蝕印製程而形成一接觸孔Π4於該第 〜與第二介電層108和112中，其曝露出電晶體的源極區 1〇7。 參考圖2，該接觸孔Π4藉由一般的方法塡充以一導 電材料，而形成一接觸插塞1丨6。例如’塡充該接觸孔114 的導電層係藉濺鍍法形成於半導體基板100的整個表面上 ’並藉化學機械拋光法而平坦化至與第二介電層U2的頂 面有實質相同的水平，而形成該接觸插塞116於該接觸孔 114中。該導電層可爲一摻雜了雜質的複晶矽層、一鎢(W) 層、〜iS(Ta)層、一釕(Ru)層、一銀(Ir)層、一餓（〇s)層、 —鉑(Pt)層、一矽化鎢(WSi)層、一氮化鎢(WN)層或上述諸 層的〜複合層。 之後，形成一阻障層118於該第二介電層及接觸 插塞1丨6上。該阻障層118避免氧在熱處理期間(諸如在阻 __ 8 _ 本紙張尺度適用中国國家標準（CNS ) A4規格（2I0X297公釐） .~^IiT------線 (請先閱讀背面之注項再填 V頁) 翅濟部智慧財產局員工消費合作社印製 425696 Α7 Β7 五、發明説明（q ) 障層118形成後在氧氣氣氛下進行的退火製程)擴散進入該 接觸插塞。該阻障層118亦增加第二介電層Π2與接觸插 塞116和後續製程中要形成之一下導電層120之間的黏著 性。 該阻障層118可爲一鈦(Ti)層、一 Ta層、一W層、 —鎳(Ni)層、一鉻(Cr)層、一lr層、一 Ru層或上述諸層的 —複合層。該阻障層118亦可爲Ti、Ta、W、Ni、Cr、Ir 或Ru的氮化層、溴化物層、碳化層或砍化物層或上述諸 層的一複合層。阻障層118可爲一個二元或三元的化合物 所形成。該二元的化合物可爲一 Ti-Al化合物或一 Ta-Al 化合物。該三元的化合物可爲一 Ti-Si-N化合物、一 Ti-B-N化合物、—Ta-Si-N化合物、一 Ta-B-N化合物、一 Ta-A1-N化合物、一 w_B-N化合物或一 W-Si-N化合物◊霞阻 障層Π8最好由一個雙層所形成，該雙層包含：可增強阻 障層118與其他層（諸如第二介電層1Π)間之黏著性的 材料層以及可避免〇2擴散進入接觸插塞116的一材料層 。例如’阻障層118可爲一 Ti層與一 Ir層依序堆疊之雙 層。在此，該Ti層的主要功能係增強第二介電層112與接 觸插塞116和阻障層118之間的黏著性，而該Ir層的主要 功能爲避免02擴散進入接觸插塞116。 另一方面，該阻障層118可形成至50-2〇00埃的厚度 。例如，在阻障層118形成爲一 Ti層與一 ΙΓ層之雙層狀 況中’該Ti層可形成至10-200埃的厚度，而該lr層可形 成至40-1800埃的厚度。在本實施例中，阻障層118係使 9 裝— {請先閱讀背面之注意事項再填V本頁) -ΤΓ 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國圉家標準（CNS ) Μ規格（210X297公釐） 經濟部智慧財產局員工消費合作社印製 425696 A7 _ B7 _ 五、發明説明（s ) 用濺鍍法形成一 Ti層與Ir層的雙層，使得阻障層118包 含厚度5〇埃的Ti層以及厚度1100埃的Ir層。 參考圖3，形成一下導電層120於阻障層118上。該 下導電層120可以一般的方法形成，諸如濺鍍法。該下導 電層120係由一金屬層、一金屬氧化物層或上述二層的一 複合層所形成。該金屬層可爲一 Pt層、一 Ir層、一Ru層 、一鍺(Rh)層、一Os層或一鈀(Pd)層。該金屬氧化物層可 爲一Ru02 層、一Ir02 層、一(Ca,Sr)Ru〇3 層或一 LaSrCo〇3 層。例如，該下導電層可由一雙層所形成，其中一 Ir02層 與一Pt層係以濺鍍法依序堆疊。在此，該ίΓ〇2層與Pt層 將於後續刻劃圖案成一電容器下電極。另一方面，該Ir02 層提供介電層122 (在後續製程中形成）而有氧原子。例 如’在一PZT層於後續製程中形成爲一介電層122的狀況 中，即使當氧原子離開該PZT層時，該Ir02層可再次供給 氧到ΡΖΤ層。所以，該Ir〇2層可避免因該ΡΖΤ層的氧氣 出氣(outgassing)而使得ΡΖΤ層劣化。該Pt層造成介電層 122的晶體成長，其中該Pt層係於一後續製程中形成並協 助該介電層122均勻地成長。 該下導電層120可形成至500-3500埃的厚度。在下導 電層120形成爲一 Ir〇2層與一 Pt層之雙層的狀況中，該 Ir〇2層可形成至10(M000埃的厚度，而該Pt層可形成至 400-2500埃的厚度。在本實施例中，該較低導電層120係 由一 Ir02層與一Pt層之雙層所形成，使得該Ir02層具有 500埃的厚度，而該Pt層具有1500埃的厚度。 10 本紙張尺度適用中國國家標隼（CNS ) A4規格ί 2I0X297公釐） ---------1------，訂------.^ (請先閱讀背面之注$項再填Γ.本頁) 經濟部智慧財產局員工消費合作社印製 ι A 2 5 6 9 6 A7 ____B7___ 五、發明説明（i]) 其次，形成一介電層122於該下導電層120上。該介 電層 122 可爲一Ti〇2 層、一 Ta2〇3 層' —AI2O3 層、一 BaTi03 層 ' —SrTi03 層、一Bi4Ti3Ol2 層、一 PbTi03 層、 一 Si〇2 層' —SiN 層、一（Ba，Sr)Ti03 層、一 (Pb，La)(Zr，Ti)03 層、一Pb(Zr,Ti)03 層、一 SrBi2Ta209 層或 上述諸層的一複合層。該介電層122可以一般的方法形成 。使用於形成該介電層122的方法係依據選擇何種材料以 形成該介電層122而決定。例如，可採用一溶膠-凝膠製程 ，以形成PZT層的介電層U2。另一方面，該介電層122 的厚度可形成至500-3000埃。在本發明的實施例中，藉溶 膠-凝膠法形成厚度爲2000埃的PZT層做爲介電層122。 在形成介電層122後，在600_9〇0°C的〇2氣氛中進行 一退火製程。其次，該介電層122係以該退火製程而緻密 ，使得後續形成之電容器的電容量增加，並改良電容器的 漏電流特性。再者，因爲該退火製程係於氧氣氣氛中進行 ，所以氧可以擴散進入接觸插塞Π6。然而，氧進入接觸 插塞116的擴散可因阻障層118形成於接觸插塞116上而 阻絕。 之後，一上導電層124形成於該介電層122上。該上 導電層124可以諸如濺鍍法等一般的方法形成。該上導電 層124係由一金屬層、一金屬氧化物層或上述二層的一複 合層所形成。該金屬層可爲一 Pt層、一11層'一 Ru層、 一 Rh層、一 Os層或一 Pd層。該金屬氧化物層可爲一 Ru〇2 層、一 Ir〇2 層、一·(CaJORuO;層或一 LaSrCoO;層。 11 本紙張尺度適用中國國家標準（CNS) A4規格（2】OX 297公釐） I I 裝 I I I I I I 訂 I I I I 線 (請先閱讀背面之注意事項再填Γ本頁) 425696 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明説明（\〇 ) 例如，該上導電層U4可由一雙層所形成（使用濺鍍法） ，其中一 ϊγ〇2層與一 Ir層係依序地堆疊。該Ir02層與Ir 層稍後刻劃圖案成一電容器上電極。在此，該上導電層 124的Ir02層提供氧給介電層122,以避免該介電層122 因氧氣出氣而劣化。該上導電層124可形成至500-3000埃 的厚度。例如，在上導電層124以一Ir〇2層與一 lr層之雙 層所形成的狀況中，該Ir02層可形成至100-1000埃的厚度 ，而該Ir層可形成至400-2000埃的厚度。在本發明的實 施例中，該上導電層124可以濺鍍法形成爲一：[r〇2層與/ Ir層的雙層，其中該Ir02層與Ir層的厚度分別爲300埃興 1200 埃。 參考圖4A，阻障層II8、下導電層120、介電層I22 與上導電層I24被刻劃圖案以形成一下電極120’、一電容 介電層I22’與一上電極I24，。該下導電層12〇、介黧艨 I22與上導電層I24可藉由進行一道、二道或更多道光鋏 印製程而刻劃出圖案。在電容器C藉二道光蝕印製程而蘀 得的狀況中，該上導電層124刻劃圖案成上電極124’，然 後該介電層122與下導電層120刻劃圖案成電容介電礞 I22’與下電極U0，。在電容器C藉三道光蝕印製程而獾 得的狀況中，該上導電層124、介電層122與下導電層I20 藉分離的光蝕印製程刻劃出圖案。 參考圖4B與圖4C，在進行二道或三道光飩印製程而 形成電容器C的狀況中，該電容器C側壁具有一階梯狀劍 面’而與圖4A所示不同。圖4B與圖4C分別表示藉進行 12 表紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） ---------聲tr# (請先閲讀背面之注意事項再填 :425 6 96 A7 B7 五、發明説明（丨（） 二道與三道光蝕印製程而獲得之電容器c ° (請先閲讀背面之注意事項再填f.本頁) 另一方面，一中間層介電質(ILD)製程、一介金屬介電 質(IMD)製程以及一鈍化製程通常在電容器C形成後進行 。然而，電容介電層122’的介電特性可能會爲氫基氣體所 劣化，例如氫氣、氫離子或包含這些製程期間所產生之氫 原子的氣體化合物。因此，本發明提供一功能性層，其係 於電容器C形成後形成，其可保護該電容器C不爲諸如氫 基氣體等外在環境所影響。本發明所提供之功能性層係一 建構成多層的包封層(EL)，以覆蓋該電容器C。 下列條件最好必須藉一多層的EL滿足，以保護該電 容器C不爲外在環境所影響。首先，該電容介電層122’的 劣化必須藉EL而避免。例如，在電容介電層122’以諸如 PZT等鐵電材料所形成的狀況中，該鐵電材料的揮發在後 續整合製程中必須避免。此乃因該電容器C可能劣化，使 得後續形成之半導體記憶裝置的可靠度因電容介電層122’ 的揮發而降低至一極限値。第二，該EL層必須不與電容 介電層122’反應。第三，氫基氣體在後續整合製程中進入 電容介電層122’的擴散必須爲該EL所阻絕。 在根據本發明之EL的形成中，一阻絕層與一電容器 保護層皆包含於該EL中。該電容器保護層的主要功能係 避免該氫基氣體在後續的整合製程中擴散進入該電容介電 層122’ °形成於該電容器保護層下方之阻絕層，則避免形 成於阻絕層下之一材料層與電容器保護層間的反應，和/或 避免電容介電層122’的揮發。阻絕層與電容器保護層的主 ____13 本纸張尺度適用中國國家檁準（CNS ) 2】_〇><297公着) 425696 A7 經濟部智慧財產局員工消費合作社印製 五、發明説明（丨>) 要功能係彼此相異，然而，所有上述的功能皆可藉由建構 成EL的該雙層組合而完全進行。該阻絕層與電容器保護 層在EL本身形成中或電容器C形成後所進行之整合製程 中執行個別的功能。阻絕層與電容器保護層的這些功能將 說明如下。 在一 EL形成爲一多層（諸如三層）的狀況中，該EL 藉由依序堆疊一阻絕層、一緩衝層以及一電容器保護層， 而形成至該EL可覆蓋該電容器C的程度。在一 EL形成爲 一雙層的狀況中，一阻絕層以及一電容器保護層係依序堆 疊而覆蓋電容器C。形成EL的材料層數目以及EL的構造 可以改變。堆疊以完成該EL的材料層數目係取決於EL形 成製程中的經濟因素等等。 如圖5所示，一 EL在本發明的實施例中形成爲雙層 。首先，形成一覆蓋該電容器C的阻絕層126。考慮該阻 絕層126所需產生的效果，而選擇用以形成該阻絕層126 的材料。該阻絕層126最好由一 Ti02層、一Ta205層、一 BaTi03 層、一SrTiO；}層、一 Bi4Ti3〇i2 層、一 PbTi〇3 層、 —Si02 層、一 SiN 層 '一（Ba，Sr)Ti03 層、一 (卩13，1^)(21*,71)03層、一 Pb(Zr，Ti)〇3 層或一 SrBi2Ta209層所 形成。最好選擇不會與後續形成之電容器保護層128反應 的材料來形成該阻絕層126。再者，因爲該阻絕層126用 以避免電容介電層122’的揮發，所以使用於形成該阻絕層 126的材料係根據使用於形成該電容介電層122’的材料而 決定。在本實施例中，該電容介電層122’係由一PZT層所 _____14_ 本紙張尺度遄用中國國家棵準（CNS }八4規格（210X297公釐） ^"^ (請先聞讀背面之注意事項再^^枣頁) 425696 經濟部智慧財產局員工消骨合作社印製 A7 ___B7_ 五、發明説明（\々） 形成，而該阻絕層係由一Ti〇2層所組成。當然，該PZT 層與該们02層彼此不會反應。再者，該阻絕層126的厚度 係根據阻絕層126的功能以及選擇做爲阻絕層126之材料 層的物理與化學性質而決定。阻絕層126最好形成至50-1500埃的厚度。 另一方面，用於形成阻絕層126的方法係根據用以形 成該阻絕層126的材料而改變。此乃因形成阻絕層126的 方法可根據選擇做爲阻絕層126之材料（由上述材料中選 擇）而改變。該阻絕層126最好藉化學氣相沈積法(CVD) 、物理氣相沈積法(PVD)、灑鍍法 '原子層沈積法(ALD)或 雷射剝離法而形成。例如，當一 1^02層使用爲阻絕層126 時，選擇濺鍍法以形成阻絕層126。其他的方法亦可使用 於形成Ti〇2層的阻絕層126。在使用一Si02層以形成阻絕 層126的狀況中，最好不要使用CVD法。此乃因CVD法 在形成Si02層期間包含諸如氫氣等氫基氣體。 例如，在藉濺鍍法形成一 Ti02層之阻絕層126的狀況 中，使用鈦爲靶材、使用氬氣做爲一濺鍍氣體，而使用氧 氣做爲一反應氣體。在使用DC濺鍍設備以形成該阻絕層 126的狀況中，其製程條件可設定如下。施加於DC濺鍍 設備的功率可爲l-6kW’腔室的溫度可設定爲25-700°C， 而該腔室的壓力可調整至l-5mT〇rr。再者，氬氣與氧氣的 流速可維持在8-14 seem。 在本發明的實施例中’阻絕層126係使用DC濺鍍設 備而形成，其製程條件爲功率6kW ’腔室溫度630°C，腔 15 本紙張尺度適用中ΐ固家標隼（CNS ) ( 210父297公着~) " t------IT------.^ (請先閱讀背面之注意事項再填f 4頁) 425696 A7 B7 seem 在形成如上述的阻絕層I26後，形成電容器保维層 I28以覆蓋該阻絕層U6。考慮該電容器保護層所^產 生的效果，而選擇用以形成該電容器保護層128的材 。該電容器保護層128最好可由一 Ti02層、 一 Al2〇3 層、一BaTi〇3 層 ' —SrTi〇3 層、〜 五、發明説明Uk) 室壓力lmTorr，氬氣流速1〇 sccm以及氧氣流速ι〇 層、 Β“Τί3〇12 層 、一PbTi03 層、一Si02 層、一 SiN 層、〜(Ba Sr)Ti〇3 層 、—(Pb，La)(Zr，Ti)03 層、—Pb(Zr，Ti)03 層或〜SrBi2Ta2〇9 層所形成。在此，使用爲電容器保護層128的材料^係根9 據用於形成電容介電層I22’與阻絕層U6的材料層而選擇 。例如，選擇可與阻絕層U6反應之一材料靥做爲該電容 器保護層128係非所要的。再者，該電容器保護層最 好由與阻絕層126相異的材料層所形成。在本實施例中， 使用一Al2〇3層以形成該電容器保護層128。 考慮該電容器保護層128的功能以及選擇做爲電容器 保護層128之材料層的物理與化學性質，而決定電容器保 護層128的厚度。該電容器保護層128最好形成至5〇_ 5000埃的厚度。而該電容器保護層128形成至50-1500埃 的厚度則更佳。當電容器保護層128的厚度超過15〇0埃時 ，該電容器保護層128可使用做爲一 ILD層，如此稍後無 須進行ILD製程。 用於形成該電容器保護層128的方法基於與形成阻絕 層126相同理由，其可根據選擇做爲該電容器保護層128 16 本紙張仏適财國國家標準（CNS )八4麟（2JOX 297公着） ----------装--------ST------^ (請先閲讀背面之注意事項再填V,本頁) 經濟部智慧財產局員工消費合作社印製 425696 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明説明（丨<) 的材料層（由上述材料選擇）而改變。該電容器保護層 128最好藉CVD法、PVD法、濺鑛法、ALD法或雷射剝 離法而形成。 然而，基於下列優點，該電容器保護層128最好藉 ALD法形成。亦即，該ALd法係在低溫進行。再者，藉 ALD法所形成之電容器保護層在物理與化學性質上皆 相當穩定，而可改良電容器保護層128的上述功能。再者 ’因爲電容器保護層128係藉重複堆疊單一原子層而形成 ，所以該電容器保護層128的厚度可精確地控制。而且， 無論電容器保護層128將形成於其上的表面形貌有多複雜 ，該電容器保護層128皆可形成，使得該電容器保護層 128具有100%的梯級覆蓋性。 當根據本發明之實施例的電容器保護層128以ALD法 形成一A1203層時，一鋁來源氣體係脈衝輸送至裝載於 ALD設備之腔室中的半導體基板上表面。三甲基鋁(TMA) 、氫化二甲基鋁(DAMH)、二甲基乙基胺鋁(DMEAA)、三 異丁基鋁(ΤΙΒΑ)或這些氣體的複合氣體可使用爲該鋁來源 氣體。脈衝輸送的鋁來源氣體係化學性或物理性地吸附於 整個半導體基板的上表面。其次，在移除殘留於腔室中的 鋁來源氣體後，該半導體基板的上表面係以一第一鈍氣淸 洗，而移除物理性地吸附在該半導體基板上表面的鋁來源 氣體。該第一鈍氣可爲氬氣、氮氣、Ν2〇氣體或這些氣體 的複合氣體。其次，一氧來源氣體脈衝輸送至該半導體基 板的上表面。該氧來源氣體可爲Η20氣體、Ν20氣體、03 17 (請先閲讀背面之注意事項再填V‘本買)4 25 6 96 A7 Consumption cooperation by employees of the Intellectual Property Bureau of the Ministry of Economic Affairs. Du V. Description of the invention (丨) BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor memory device and a method for manufacturing the same. More specifically, there are The invention relates to a semiconductor memory device having a multilayer encapsulated capacitor and a manufacturing method thereof. Description of Related Art Recently, in the field of semiconductor memory devices, great attention has been focused on a method of forming a capacitor dielectric layer having a ferroelectric material. This is because in non-volatile semiconductor devices, the residual polarity (pr) of ferroelectric materials is consistent with the basic binary memory concept that has been widely used to form digital memory devices. At present, there are two main ferroelectric materials in use: PZT (Pb (Zr, Ti) 03) and SBT (SrBi2Ta209 ". However, in the formation of a capacitor dielectric layer of a semiconductor memory device with a ferroelectric material, serious One of the problems is that the ferroelectric properties of ferroelectric materials are changed during the integration process of the semiconductor memory device after the capacitor is formed. Also, P, an intermediate layer dielectric (ILD) process, a dielectric metal dielectric (IMD) Pollutants (especially hydrogen) generated during the process and a passivation process (after the capacitor is formed) will degrade Pr, which is one of the ferroelectric properties of ferroelectric materials. For example, the ILD process is performed to form a material such as oxidation In the state of the ILD layer of the silicon layer, after a common ferroelectric capacitor is formed on a semiconductor substrate, the capacitor dielectric layer may be deteriorated. That is, the silicon oxide layer is formed by a plasma-assisted chemical vapor deposition method. In the ILD manufacturing process, a paper containing 3 ___ is used in this paper. It is applicable to the China National Standard (CNS) A4 specification (2IOX297 mm) ---------- ^ ------ ΐτ --- --- ^ {Please read the notes on the back first and then fill in V ) 425696 A7 B7 V. Description of the invention (>) Reaction gas of silane (SiH4) and oxygen (02). Incidentally, hydrogen is a by-product of the ILD process by the reaction of silane and oxygen. The hydrogen produced Diffusion into the capacitor dielectric layer directly, resulting in the degradation of the capacitor dielectric layer. The generated hydrogen is also contained in the ILD layer and gradually diffuses into the capacitor's dielectric layer, so in the subsequent integration process And the operation of the semiconductor memory device degrades the capacitor dielectric layer. Therefore, Pr of the capacitor dielectric layer is reduced, which reduces the reliability of a semiconductor memory device. In the worst case, the h of the capacitor dielectric layer is Reduce the loss of the ferroelectric characteristics of the capacitor dielectric layer. Therefore, in order to solve these problems, a conventional semiconductor memory device manufacturing method has adopted a method of encapsulating a capacitor with a single insulating layer after the capacitor is formed. However, the single The insulating layer cannot prevent the deterioration of the capacitor dielectric layer caused by hydrogen. For example, US Patent No. 5J22,175 discloses a silicon oxide layer, a doped oxide Layer or a silicon nitride layer to encapsulate a capacitor to solve the problem of hydrogen diffusion and deterioration of the capacitor dielectric layer. Du Yiding (please read the precautions on the back before filling in page V). Staff of the Intellectual Property Bureau of the Ministry of Economic Affairs Summary of the invention printed by a consumer cooperative. It is an object of the present invention to provide a semiconductor memory device having a capacitor encapsulated in multiple layers. Another object of the present invention is to provide a method for manufacturing a semiconductor device, whereby a capacitor can be formed in The semiconductor device after the capacitor is protected during the integration process. In one feature of the present invention, a semiconductor memory device is provided, the 4 paper sizes of which are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) Intellectual Property Bureau of the Ministry of Economic Affairs Printed by an employee consumer cooperative 425696 A7 —____ B7____ 5. In the description of the invention (4), the device includes a capacitor having a lower electrode, an upper electrode, and a capacitive dielectric layer placed between the upper and lower electrodes, and a multilayer formed on the capacitor. An encapsulation layer, a dielectric layer formed on the multilayer encapsulation layer, and an upper electrode metal contact (through The dielectric layer is in contact with the upper electrode) and a lower metal electrode in contact (via through the dielectric layer in contact with the lower electrode). The encapsulation layer includes at least one barrier layer and a capacitor protection layer, and the barrier layer is located under the capacitor protection layer. The barrier layer may be a material layer formed of a material capable of preventing the capacitor dielectric layer from volatilizing and / or preventing a material layer (which is formed under the barrier layer) from reacting with the capacitor protective layer. The barrier layer is preferably a Ti02 layer, a Ta205 layer, a BaTi03 layer, an SrTi03 layer, a Bi4Ti30 丨 2 layer, a PbTi03 layer, a Si02 layer, a SiN layer, and a (Ba, Sr) layer. Ti03 layer '-(卩 1 ?, 1 ^) (21', 7 ^) 03 layer, a Pb (Zr, Ti) 03 layer or a SrBi2Ta209 layer. The thickness of the barrier layer may be 50-1500 Angstroms. The barrier layer may be a material layer annealed in an oxygen atmosphere at 400-600 ° C. The capacitor protective layer may be a material layer formed of a material capable of preventing hydrogen from diffusing into the capacitor dielectric layer. The capacitor protective layer is preferably a Ti02 layer, a Ta205 layer, an a1203 layer, a BaTi03 layer, an SrTi03 layer, a Bi4Ti3012 layer, a pbTi03 layer, a Si02 layer, and a SiN layer. , Sr) Ti03 layer,-(Pb, La) (Zr, Ti) 03 layer, -Pb (Zr, Ti) 03 layer, or a SrBi ^ aiO9 layer. The capacitor protective layer is preferably different from the material of the barrier layer. The thickness of the capacitor protective layer may be 50-1500 Angstroms. The capacitor protective layer may be a material layer annealed in an oxygen atmosphere of 400-600t: The paper size is ^ China National Standard (CNS > M specification (210X29 ^^^ 5--III Ϊ-I-Ε " • Order the I. I line (please read the notes on the back before filling out this page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 425696 A7 _____B7 V. Description of the invention (屮) In another feature of the invention The invention provides a method for manufacturing a semiconductor memory device, which includes the steps of forming a capacitor having a lower electrode, an upper electrode, and a capacitive dielectric layer disposed between the upper and lower electrodes on a semiconductor substrate, and forming the capacitor. A step of encapsulating a layer and covering the capacitor with multiple layers. Another feature of the present invention may further include the step of forming a dielectric layer on the encapsulating layer. It is made even more detailed by describing its preferred embodiments in detail with reference to the accompanying drawings, in which: FIGS. 1 to 5 illustrate a preferred embodiment of the present invention. A cross-sectional view of a method of manufacturing a conductive memory device. FIGS. 6 and 7 are cross-sectional views illustrating the subsequent integration process, which is performed after the capacitor is encapsulated in multiple layers, which is helpful for understanding the manufacturing of a semiconductor memory device according to the present invention. The function of the encapsulation layer formed by the method shown in FIG. 8 is a cross-sectional view illustrating a method of manufacturing a semiconductor memory device with a multilayer encapsulation capacitor according to another preferred embodiment of the present invention; FIG. 9 and FIG. 10 are respectively A graph showing a hysteresis curve of a capacitor dielectric layer and a leakage current characteristic of the capacitor, which is tested with a sample C1 manufactured according to the method of the present invention; FIG. Π and FIG. 12 respectively show a hysteresis curve and a barrier contact resistance The pattern 'is tested with sample C1 made according to the method of the present invention and samples C2 and C3 each having a single encapsulation layer made by different methods. 6 ---------- ^- ----- 1T ------ 0 (Please read the notes on the back before filling f. This page) I Paper size is applicable to national standard V (CNS7 octave (210X297 mm)) 425696 Wisdom of the Ministry of Economic Affairs Consumption Cooperation of Employees of Property Bureau A7 __B7_ V. Description of the preferred embodiment The invention will now be described more fully with reference to the accompanying drawings, in which the preferred embodiment of the invention is shown, and a capacitor with multilayer encapsulation is shown. Semiconductor memory device and manufacturing method thereof. However, the present invention can be implemented in many different forms and should not be considered limited to the embodiments shown here, and the embodiments provided will make this disclosure more thorough and complete, and The concept of the present invention is completely passed on to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for easy expression. It should also be understood that when a layer is referred to as being "on" another layer or substrate In this case, it may be directly on the layer or the substrate, or there may be an intermediate layer therebetween. In the embodiment of the present invention described with reference to Figs. 1 to 4 and 8, a capacitor of a semiconductor memory device is formed by a capacitor on a bit line (COB) structure. However, the present invention can also be applied to a situation in which a capacitor is formed by a capacitor under the bit line (CUB) structure. Embodiment 1 Referring to FIG. 1, an isolation layer 101 is formed on a semiconductor substrate 100 to define an active region, and then a transistor is formed in the active region. The isolation layer 101 can be formed by a general method, for example, By the local oxidation of silicon (LOCOS) process. The transistor may be a field effect transistor having a gate electrode 105 (having side wall spacers 103 and a gate insulating layer 104 formed thereunder), a drain region 106 and a source region 107. Secondly, the one-bit line Π0 is formed by a general method. That is, a first dielectric layer 108 is formed, and a conductive plug 109 (which is connected to the transistor 7) The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) ------- --Install ------ 1T ------ 0 (Please read the precautions on the back before filling this page) A7 4 6 9 6 ----------- B7 _ 5. Description of the Invention (L) (106) contact region is formed in the first dielectric layer 108. Second, the bit line 110 is formed on the conductive plug 109, and a second dielectric layer 112 is formed on the bit line Π0. The first and second dielectric layers 108 and 112 may be a silicon oxide layer, a oxynitride sand layer, a borosilicate glass (BSG) layer, a phosphosilicate glass (PSG) layer, and a borophosphosilicate glass (BPSG). Layer, tetraethyl orthosilicate (TEOS) layer, ozone (〇3) -TEOS layer, plasma assisted (PE) -TEOS layer, undoped silicate beryllium glass (1 ^ 0) layer or the above Composite layers of layers. The first and second dielectric layers 112 can be formed by a general method, such as by low pressure chemical vapor deposition (LPCVD) or plasma assisted chemical vapor deposition (PECVD). Next, a photolithography process is performed to form a contact hole Π4 in the first and second dielectric layers 108 and 112, which exposes the source region 107 of the transistor. Referring to FIG. 2, the contact hole Π4 is filled with a conductive material by a general method to form a contact plug 1 丨 6. For example, 'the conductive layer filling the contact hole 114 is formed on the entire surface of the semiconductor substrate 100 by a sputtering method' and planarized to a substantially same surface as the top surface of the second dielectric layer U2 by a chemical mechanical polishing method. The contact plug 116 is horizontally formed in the contact hole 114. The conductive layer may be an impurity-doped polycrystalline silicon layer, a tungsten (W) layer, a ~ iS (Ta) layer, a ruthenium (Ru) layer, a silver (Ir) layer, and a starvation (〇s) Layer, a platinum (Pt) layer, a tungsten silicide (WSi) layer, a tungsten nitride (WN) layer, or a composite layer of the foregoing layers. After that, a barrier layer 118 is formed on the second dielectric layer and the contact plugs 1 and 6. The barrier layer 118 avoids oxygen during heat treatment (such as in resisting __ 8 _ This paper size applies Chinese National Standard (CNS) A4 specification (2I0X297 mm). ~ ^ IiT ------ line (please read first Remarks on the back page are refilled on page V.) Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 425696 Α7 Β7 V. Description of the invention (q) Annealing process in the oxygen atmosphere after barrier layer 118 is formed) diffuses into the contact plug . The barrier layer 118 also increases the adhesion between the second dielectric layer Π2 and the contact plug 116 and a lower conductive layer 120 to be formed in a subsequent process. The barrier layer 118 may be a titanium (Ti) layer, a Ta layer, a W layer, a nickel (Ni) layer, a chromium (Cr) layer, a lr layer, a Ru layer, or a combination of the above-mentioned layers. Floor. The barrier layer 118 may also be a nitride layer, a bromide layer, a carbide layer, or a chopper layer of Ti, Ta, W, Ni, Cr, Ir, or Ru, or a composite layer thereof. The barrier layer 118 may be formed of a binary or ternary compound. The binary compound may be a Ti-Al compound or a Ta-Al compound. The ternary compound may be a Ti-Si-N compound, a Ti-BN compound, a -Ta-Si-N compound, a Ta-BN compound, a Ta-A1-N compound, a w_B-N compound, or a The W-Si-N compound Haxia barrier layer Π8 is preferably formed of a double layer, which includes: a material that can enhance the adhesion between the barrier layer 118 and other layers (such as the second dielectric layer 1Π) Layer and a layer of material that prevents O 2 from diffusing into the contact plug 116. For example, the barrier layer 118 may be a double layer in which a Ti layer and an Ir layer are sequentially stacked. Here, the main function of the Ti layer is to enhance the adhesion between the second dielectric layer 112 and the contact plug 116 and the barrier layer 118, and the main function of the Ir layer is to prevent 02 from diffusing into the contact plug 116. On the other hand, the barrier layer 118 may be formed to a thickness of 50 to 200 Angstroms. For example, in the case where the barrier layer 118 is formed as a double layer of a Ti layer and an IΓ layer, the Ti layer may be formed to a thickness of 10 to 200 angstroms, and the lr layer may be formed to a thickness of 40 to 1800 angstroms. In this embodiment, the barrier layer 118 is made of 9 pieces — {Please read the notes on the back before filling the V page) -ΤΓ Printed on paper standards of the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs. CNS) M size (210X297 mm) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 425696 A7 _ B7 _ V. Description of the invention (s) A double layer of Ti layer and Ir layer is formed by sputtering to make the barrier layer 118 includes a Ti layer having a thickness of 50 Angstroms and an Ir layer having a thickness of 1100 Angstroms. Referring to FIG. 3, a lower conductive layer 120 is formed on the barrier layer 118. The lower conductive layer 120 may be formed by a general method such as a sputtering method. The lower conductive layer 120 is formed of a metal layer, a metal oxide layer, or a composite layer of the above two layers. The metal layer may be a Pt layer, an Ir layer, a Ru layer, a germanium (Rh) layer, an Os layer, or a palladium (Pd) layer. The metal oxide layer may be a Ru02 layer, an Ir02 layer, a (Ca, Sr) RuO3 layer, or a LaSrCoO3 layer. For example, the lower conductive layer may be formed of a double layer, in which an Ir02 layer and a Pt layer are sequentially stacked by a sputtering method. Here, the Γ02 layer and the Pt layer will be patterned into a capacitor lower electrode in the subsequent scribing. On the other hand, the Ir02 layer provides a dielectric layer 122 (formed in a subsequent process) and has oxygen atoms. For example, in a state where a PZT layer is formed as a dielectric layer 122 in a subsequent process, even when oxygen atoms leave the PZT layer, the Ir02 layer can supply oxygen to the PZT layer again. Therefore, the Ir02 layer can prevent the PZT layer from being deteriorated due to oxygen outgassing of the PZT layer. The Pt layer causes the crystal growth of the dielectric layer 122, wherein the Pt layer is formed in a subsequent process and assists the dielectric layer 122 to grow uniformly. The lower conductive layer 120 may be formed to a thickness of 500-3500 Angstroms. In a case where the lower conductive layer 120 is formed as a double layer of an Ir02 layer and a Pt layer, the Ir02 layer may be formed to a thickness of 10 (M000 Angstroms, and the Pt layer may be formed to a thickness of 400-2500 Angstroms). In this embodiment, the lower conductive layer 120 is formed of a double layer of an Ir02 layer and a Pt layer, so that the Ir02 layer has a thickness of 500 Angstroms and the Pt layer has a thickness of 1500 Angstroms. Paper size is applicable to China National Standard (CNS) A4 specifications ί 2I0X297 mm) --------- 1 ------, order ------. ^ (Please read the note on the back first $ Item refill Γ. This page) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A 2 5 6 9 6 A7 ____B7___ V. Description of the Invention (i)) Next, a dielectric layer 122 is formed on the lower conductive layer 120 on. The dielectric layer 122 may be a Ti02 layer, a Ta203 layer, an AI2O3 layer, a BaTi03 layer, a SrTi03 layer, a Bi4Ti3Ol2 layer, a PbTi03 layer, a Si02 layer, a SiN layer, and a Si02 layer. (Ba, Sr) Ti03 layer, one (Pb, La) (Zr, Ti) 03 layer, one Pb (Zr, Ti) 03 layer, one SrBi2Ta209 layer or a composite layer of the above-mentioned layers. The dielectric layer 122 can be formed by a general method. The method used to form the dielectric layer 122 is determined based on which materials are selected to form the dielectric layer 122. For example, a sol-gel process can be used to form the dielectric layer U2 of the PZT layer. On the other hand, the thickness of the dielectric layer 122 may be formed to 500-3000 Angstroms. In the embodiment of the present invention, as the dielectric layer 122, a PZT layer having a thickness of 2000 angstroms is formed by a sol-gel method. After the dielectric layer 122 is formed, an annealing process is performed in a 0 2 atmosphere at 600-900 ° C. Secondly, the dielectric layer 122 is compacted by the annealing process, which increases the capacitance of the capacitors formed later and improves the leakage current characteristics of the capacitors. Furthermore, because the annealing process is performed in an oxygen atmosphere, oxygen can diffuse into the contact plug Π6. However, the diffusion of oxygen into the contact plug 116 may be blocked by the formation of the barrier layer 118 on the contact plug 116. After that, an upper conductive layer 124 is formed on the dielectric layer 122. The upper conductive layer 124 can be formed by a general method such as a sputtering method. The upper conductive layer 124 is formed of a metal layer, a metal oxide layer, or a composite layer of the above two layers. The metal layer may be a Pt layer, an 11 layer, a Ru layer, a Rh layer, an Os layer, or a Pd layer. The metal oxide layer can be a Ru0 2 layer, an Ir 0 2 layer, a (CaJORuO; layer, or a LaSrCoO; layer.) 11 This paper size applies to China National Standard (CNS) A4 specifications (2) OX 297 Ii) II package IIIIII order IIII line (please read the precautions on the back before filling this page) 425696 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (\ 〇) For example, the upper conductive layer U4 It can be formed by a double layer (using the sputtering method), in which a γ〇2 layer and an Ir layer are sequentially stacked. The Ir02 layer and the Ir layer are later patterned into a capacitor upper electrode. Here, the upper electrode The Ir02 layer of the conductive layer 124 provides oxygen to the dielectric layer 122 to prevent the dielectric layer 122 from being deteriorated by oxygen outgassing. The upper conductive layer 124 may be formed to a thickness of 500-3000 angstroms. In a situation where a double layer of an Ir02 layer and an lr layer is formed, the Ir02 layer can be formed to a thickness of 100-1000 angstroms, and the Ir layer can be formed to a thickness of 400-2000 angstroms. In the implementation of the present invention In an example, the upper conductive layer 124 can be formed into one by sputtering: [r02 layer and / ir layer The thickness of the Ir02 layer and the Ir layer are 300 Angstroms and 1200 Angstroms, respectively. Referring to FIG. 4A, the barrier layer II8, the lower conductive layer 120, the dielectric layer I22, and the upper conductive layer I24 are patterned to form The lower electrode 120 ', a capacitor dielectric layer I22', and an upper electrode I24. The lower conductive layer 120, the dielectric I22, and the upper conductive layer I24 can be subjected to one, two, or more photolithographic processes. The pattern is scribed. In the condition obtained by capacitor C through two photolithographic printing processes, the upper conductive layer 124 is scribed into an upper electrode 124 ', and then the dielectric layer 122 and the lower conductive layer 120 are scribed. Capacitive dielectric 礞 I22 'and lower electrode U0. In the condition that capacitor C is obtained by three photoetching processes, the upper conductive layer 124, dielectric layer 122, and lower conductive layer I20 are printed by separate photoetching. 4B and FIG. 4C, in a case where a capacitor C is formed by performing two or three photo-printing processes, the sidewall of the capacitor C has a stepped sword surface, which is different from that shown in FIG. 4A. Fig. 4B and Fig. 4C respectively show that the paper size of 12 sheets is subject to Chinese national standards ( CNS) A4 specification (210X297 mm) --------- Sound tr # (Please read the notes on the back before filling in: 425 6 96 A7 B7 V. Description of the invention (丨 () Two and three lights The capacitor c ° obtained by the etching process (please read the precautions on the back before filling f. This page) On the other hand, an intermediate layer dielectric (ILD) process, a dielectric metal dielectric (IMD) process, and a The passivation process is usually performed after the capacitor C is formed. However, the dielectric properties of the capacitor dielectric layer 122 'may be deteriorated by hydrogen-based gases, such as hydrogen, hydrogen ions, or gas compounds containing hydrogen atoms generated during these processes. Therefore, the present invention provides a functional layer, which is formed after the capacitor C is formed, which can protect the capacitor C from the external environment such as a hydrogen-based gas. The functional layer provided by the present invention is a multilayer encapsulation layer (EL) to cover the capacitor C. The following conditions must preferably be met by a multilayer EL to protect the capacitor C from the external environment. First, the deterioration of the capacitor dielectric layer 122 'must be avoided by EL. For example, in the case where the capacitor dielectric layer 122 'is formed of a ferroelectric material such as PZT, volatilization of the ferroelectric material must be avoided in a subsequent integration process. This is because the capacitor C may be deteriorated, so that the reliability of the semiconductor memory device to be formed later is reduced to a limit 因 due to the volatilization of the capacitor dielectric layer 122 '. Second, the EL layer must not react with the capacitor dielectric layer 122 '. Third, the diffusion of the hydrogen-based gas into the capacitive dielectric layer 122 'in the subsequent integration process must be blocked by the EL. In the formation of the EL according to the present invention, a barrier layer and a capacitor protective layer are included in the EL. The main function of the protective layer of the capacitor is to prevent the hydrogen-based gas from diffusing into the capacitive dielectric layer 122 ′ in the subsequent integration process. A barrier layer formed under the protective layer of the capacitor is prevented from forming a material under the barrier layer. Reaction between the layer and the capacitor protective layer, and / or avoid volatilization of the capacitor dielectric layer 122 '. The master of the barrier layer and the capacitor protective layer __13 This paper size is applicable to the Chinese National Standard (CNS) 2] _〇 > < 297 (publication) 425696 A7 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (丨 >) The functional systems are different from each other, however, all the above-mentioned functions can be completely performed by constructing the two-layer combination constituting the EL. The barrier layer and the capacitor protective layer perform individual functions in the integration process performed during the formation of the EL itself or the capacitor C. These functions of the barrier and capacitor protection layers will be described below. In a state where an EL is formed into a multilayer (such as three layers), the EL is formed to the extent that the EL can cover the capacitor C by sequentially stacking a barrier layer, a buffer layer, and a capacitor protection layer. In a state where an EL is formed as a double layer, a barrier layer and a capacitor protective layer are sequentially stacked to cover the capacitor C. The number of material layers forming the EL and the structure of the EL can be changed. The number of material layers stacked to complete the EL depends on economic factors in the EL formation process and so on. As shown in FIG. 5, an EL is formed as a double layer in the embodiment of the present invention. First, a blocking layer 126 is formed to cover the capacitor C. In consideration of the effect required by the barrier layer 126, a material for forming the barrier layer 126 is selected. The barrier layer 126 is preferably composed of a Ti02 layer, a Ta205 layer, a BaTi03 layer, and an SrTiO;} layer, a Bi4Ti3oi2 layer, a PbTi03 layer, a -Si02 layer, and a SiN layer 'a (Ba, Sr ) Ti03 layer, a (卩 13,1 ^) (21 *, 71) 03 layer, a Pb (Zr, Ti) 〇3 layer or a SrBi2Ta209 layer. It is preferable to select a material that does not react with the capacitor protection layer 128 to be formed later to form the barrier layer 126. Furthermore, since the barrier layer 126 is used to prevent the capacitor dielectric layer 122 'from evaporating, the material used to form the barrier layer 126 is determined according to the material used to form the capacitor dielectric layer 122'. In this embodiment, the capacitor dielectric layer 122 'is made of a PZT layer. _____14_ This paper size is based on the Chinese National Standard (CNS) 8-4 (210X297 mm) ^ " ^ (Please read first Note on the back again ^^ Date page) 425696 Printed by A7 _B7_, an employee bone-eliminating cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. The invention description (\ 々) is formed, and the barrier layer is composed of a Ti02 layer. Of course, The PZT layer and the 02 layer do not react with each other. Furthermore, the thickness of the barrier layer 126 is determined according to the function of the barrier layer 126 and the physical and chemical properties of the material layer selected as the barrier layer 126. The barrier layer 126 It is preferably formed to a thickness of 50 to 1500 angstroms. On the other hand, the method for forming the barrier layer 126 varies depending on the material used to form the barrier layer 126. This is because the method for forming the barrier layer 126 can be selected according to choice It is changed for the material of the barrier layer 126 (selected from the above materials). The barrier layer 126 is preferably a chemical vapor deposition method (CVD), a physical vapor deposition method (PVD), a sputtering method, an atomic layer deposition method ( ALD) or laser lift-off method. For example, when a 1 ^ 0 When two layers are used as the barrier layer 126, a sputtering method is selected to form the barrier layer 126. Other methods can also be used to form the barrier layer 126 of the Ti02 layer. In the case where a SiO2 layer is used to form the barrier layer 126, It is better not to use the CVD method. This is because the CVD method includes a hydrogen-based gas such as hydrogen during the formation of the SiO 2 layer. For example, in the case where a barrier layer 126 of a TiO 2 layer is formed by sputtering, titanium is used as a target, Argon gas is used as a sputtering gas, and oxygen is used as a reaction gas. In the case of using a DC sputtering equipment to form the barrier layer 126, the process conditions can be set as follows. The power applied to the DC sputtering equipment The temperature of the chamber which can be l-6kW 'can be set to 25-700 ° C, and the pressure of the chamber can be adjusted to l-5mTrr. Furthermore, the flow rate of argon and oxygen can be maintained at 8-14 seem In the embodiment of the present invention, the 'barrier layer 126 is formed using DC sputtering equipment, and its process conditions are 6kW'. The temperature of the chamber is 630 ° C, and the chamber is 15. The paper size is applicable to the Chinese solid standard (CNS). (210 father and 297 public works) " t ------ IT ------. ^ (Please read the back first (Note 4) Please fill in f4) 425696 A7 B7 seem After forming the barrier layer I26 as described above, a capacitor retaining layer I28 is formed to cover the barrier layer U6. Considering the effect of the capacitor protection layer, choose to use The material forming the capacitor protective layer 128. The capacitor protective layer 128 is preferably composed of a Ti02 layer, an Al203 layer, and a BaTi0 layer'-SrTi03 layer, ~ V. Description of the invention Uk) Chamber pressure lmTorr, Ar gas flow rate of 10 sccm and oxygen flow rate of 10 layers, Β "Τί 3012 layer, a PbTi03 layer, a Si02 layer, a SiN layer, ~ (Ba Sr) TiO3 layer,-(Pb, La) (Zr , Ti) 03 layer, -Pb (Zr, Ti) 03 layer or ~ SrBi2Ta203 layer. Here, the material used as the capacitor protection layer 128 is selected based on the material layers used to form the capacitor dielectric layer I22 'and the barrier layer U6. For example, it is not desirable to select a material that can react with the barrier layer U6 as the capacitor protection layer 128. Furthermore, the capacitor protective layer is preferably formed of a material layer different from the barrier layer 126. In this embodiment, an Al203 layer is used to form the capacitor protection layer 128. The thickness of the capacitor protective layer 128 is determined by considering the function of the capacitor protective layer 128 and the physical and chemical properties of the capacitor protective layer 128 selected as the material layer. The capacitor protective layer 128 is preferably formed to a thickness of 50-5000 angstroms. The capacitor protection layer 128 is more preferably formed to a thickness of 50 to 1500 angstroms. When the thickness of the capacitor protection layer 128 exceeds 150,000 angstroms, the capacitor protection layer 128 can be used as an ILD layer, so that the ILD process is not required later. The method for forming the capacitor protective layer 128 is based on the same reasons as the formation of the barrier layer 126, and it can be selected as the capacitor protective layer 128. ) ---------- Equipment -------- ST ------ ^ (Please read the precautions on the back before filling in V, this page) Staff Consumption of Intellectual Property Bureau, Ministry of Economic Affairs Printed by the cooperative 425696 Α7 Β7 Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. The material layer of the invention description (丨 <) was changed. The capacitor protective layer 128 is preferably formed by a CVD method, a PVD method, a sputtering method, an ALD method, or a laser lift-off method. However, the capacitor protection layer 128 is preferably formed by the ALD method based on the following advantages. That is, the ALd method is performed at a low temperature. Furthermore, the capacitor protective layer formed by the ALD method is quite stable in both physical and chemical properties, and the above-mentioned functions of the capacitor protective layer 128 can be improved. Furthermore, because the capacitor protective layer 128 is formed by repeatedly stacking a single atomic layer, the thickness of the capacitor protective layer 128 can be precisely controlled. Moreover, no matter how complicated the surface morphology of the capacitor protection layer 128 is, the capacitor protection layer 128 can be formed, so that the capacitor protection layer 128 has 100% step coverage. When the capacitor protective layer 128 according to the embodiment of the present invention forms an A1203 layer by the ALD method, an aluminum source gas system is pulsed to the upper surface of the semiconductor substrate loaded in the chamber of the ALD device. Trimethyl aluminum (TMA), dimethyl aluminum hydride (DAMH), dimethyl ethyl aluminum (DMEAA), triisobutyl aluminum (TIBA) or a composite gas of these gases can be used as the aluminum source gas. The pulsed aluminum source gas system is chemically or physically adsorbed on the entire upper surface of the semiconductor substrate. Second, after the aluminum source gas remaining in the chamber is removed, the upper surface of the semiconductor substrate is rinsed with a first inert gas to remove the aluminum source gas physically adsorbed on the upper surface of the semiconductor substrate. The first inert gas may be argon, nitrogen, N2O gas, or a combination of these gases. Second, an oxygen source gas is pulsed to the upper surface of the semiconductor substrate. The oxygen source gas can be Η20 gas, Ν20 gas, 03 17 (please read the precautions on the back before filling V ’this purchase)

Je 本纸俵尺度適用中國國家標準（CNS ) Α4規格（210 X 297公釐） 經濟部智慧財產局MK工消費合作社印製 425 b ^ ϋ Α7 __Β7 五、發明説明（t t ) 氣體或這些氣體的複合氣體。該鋁來源氣體與該氧來源氣 體的反應僅發生於鋁來源氣體已化學性地吸附的半導體基 板上表面，如此形成一單一原子層薄膜。然後，在殘留的 氧來源氣體由腔室移除後，使用一第二鈍氣（由上述鈍氣 中選擇）以淸洗，而移除已物理性地吸附在半導體基板上 表面的氧來源氣體。此一單一原子層薄膜的形成稱爲ALD 法的一個循環。重複預定循環數目的該ALD法，直至電容 器保護層128達到諸如100埃的預定厚度爲止。 藉ALD法形成Al2〇3層之電容器保護層128的較佳製 程條件如下。亦即，鋁來源氣體的脈衝輸送時間可爲0.1_2 秒。用於移除物理性吸附之鋁來源氣體的第一鈍氣的淸洗 時間可爲0.1-10秒。再者，氧來源氣體的脈衝輸送時間可 爲0.1-20秒。用於移除物理性吸附之氧來源氣體的第二鈍 氣的淸洗時間可爲〇·1，20秒。在本發明的實施例中，鋁來 源氣體的脈衝輸送時間設定爲1秒，用於移除物理性吸附 之鋁來源氣體的第一鈍氣的淸洗時間設定爲5秒，氧來源 氣體的脈衝輸送時間設定爲〇·2秒，而用於移除物理性吸 附之氧來源氣體的第二鈍氣的淸洗時間設定爲6秒，以藉 ALD法形成該電容器保護層128。 再者，爲進一步改良該EL的功能，一視需要的退火 製程可於形成阻絕層126和/或電容器保護層128後進行。 詳言之，在阻絕層126形成後，可在氧氣氣氛下進行一退 火製程，以增加阻絕層126的絕緣特性。該退火製程最好 在600°C或更低溫下進行。此乃因爲當阻絕層126在諸如 本紙張尺度適用中國國家樣率（CNS )八4規格（2丨0X297公釐） ----------M--------iT------線 {請先鬩讀背面之注意事項再填-w本頁) 425 6 9 6 經濟部智慧財產局員工消費合作杜印製 A7 ____B7 五、發明説明（\f|) 600°C或更高的溫度下進行退火時，氧可能擴散進入接觸插 塞116，而造成阻障接觸電阻的增加。該退火製程最好在 400-600°C的溫度下進行。 在電容器保護層12S形成後’〜視需要的退火製程可 於氧氣氣氛下進行’最好在600°C或更低的溫度下進行， 以增加電容器保護層1〗8的絕緣特性。該退火製程最好在 400-600°C的溫度下進行。 . 在特定狀況下’在600t：或更高溫的高溫退火製程可 於電容器保護層U8形成後進行。此乃因爲接觸插塞ι16 因完成的EL而對氧擴散可能不敏感^在採用ALD以外的 方法來形成電容器保護層I28的狀況中，一高溫退火製程 最好可在電容器保護層128形成後進行。根據電容器保護 層128的形成法，此係有關於電容器保護層128的化學與 物理穩定性。詳言之’藉ALD法所形成的電容器保護層 128較藉其他方法所形成的電容器保護層128更爲穩定。 該ALD法的優點允許電容保護層128無須進行高溫退火製 程就有效用。然而，在以ALD以外的方法形成電容器保護 層128的狀況中，該電容器絕緣層122’的絕緣特性須藉由 一 600°C或更高溫的高溫退火製程來提升。特別地是，在 退火製程未於阻絕層126形成後進行，且電容器保護層 128藉ALD以外的方法而形成的狀況中，最好進行一 600 。(：或更高溫的退火製程。當然，在電容器保護層128藉 ALD法形成的狀況中’也可以進行高溫退火製程。其次， 因爲藉ALD法形成的電容器保護層128相當穩定’所以在 19 ^ΐτ-^— (請先閲讀背面之注意事項再填V,.本頁) 本紙張尺度適用中國國家標準（CNS ) Α4規格（210Χ297公釐） 425696 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明) 退火製程期間擴散進入接觸插塞16的氧可以可靠地避免， 因而更增加電容器保護層128的退火製程中的製程邊際。 藉由上述的EL覆蓋電容器C ’則可避免後續整合製 程中之電容介電層122’的劣化，其將詳細說明如下。 參考圖6，在形成EL後進行ILD製程。亦即，形成 一第三介電層130於整個半導體基板1〇〇表面。該第三介 電層130可爲氧化矽層、氮氧化矽層' BSG層、PSG層、 BPSG 層、TEOS 層、〇3-TEOS 層 ' PE-TEOS 層、USG 層 或上述諸層的複合層。 在以CVD法形成氧化矽層的第三介電層130的狀況 中，係使用含有矽烷氣體(SiH4)與氧氣(02)的反應氣體。順 帶一提的，來自於矽烷氣體與氧氣反應所產生的氫可能會 劣化電容介電層122’。然而，因爲根據本發明之電容器C 係以具有雙層構造的EL所覆蓋，所以在ILD製程期間擴 散進入電容器C的氫可根本地阻絕。特別地是，該EL的 電容器保護層128對於氫擴散阻絕有所貢獻。阻絕層126 對於避免氫氣擴散有所貢獻，雖然其貢獻不必大於電容器 保護層128。 之後，進行一金屬化製程。亦即，藉一般的方法，將 該第三介電層130、電容器保護層128以及阻絕層126刻 劃出圖案，以形成曝露出電容器C部份上電極124’的接觸 孔132。該第三介電層130可藉氟基溼式或乾式蝕刻而刻 劃出圖案。再者，該電容器保護層128與阻絕層126可藉 反應性離子蝕刻法，在氬氣與四氟化碳氣氛中刻劃出圖案 ______20 ^紙張尺度適用中國國家標準( CNsl Μ規格（210X297公釐） ---------^----.--1Τ------^ (請先閲讀背面之注意事項再填f本頁) 經濟部智慧財產局員工消費合作社印製 425696 五、發明説明（j) 。在接觸孔132形成後，形成一上電極金屬接觸134。在 接觸孔132形成後，可進行一回復退火製程。該回復退火 製程可在諸如450-500°C溫度的氧氣氣氛中進行。一下電極 金屬接觸（未示於圖6中）可與上電極金屬接觸134同時 形成。 參考圖7，在形成上電極金屬接觸Π4後，進行一 IMD製程，以形成一 IMD層136。例如，該IMD層136 可藉旋塗法形成一旋塗式玻璃(SOG)層。其次，藉一鈍化 製程形成一鈍化層138。該鈍化層138係以PECVD法形成 氧化矽層或氮氧化矽層β氫可在IMD層136與鈍化層138 的形成期間產生（如在ILD製程一般），而擴散進入電容 器C。然而，電容器保護層128阻絕氫擴散進入電容器C 。所以，電容器C在IMD與鈍化製程中的劣化可避免。如 上所述，該阻絕層126亦可阻絕氫擴散進入電容器C達某 種程度。 如參考圖6與圖7的說明，當ILD、IMD與鈍化製程 在覆蓋以EL的電容器C上進行時，氫侵襲所造成之電容 介電層122’的劣化可避免。 實施例2 本發明的第二個實施例至接觸插塞116形成爲止，皆 以與第一個實施例相同的方式進行。參考圖8，一阻障層 與一下導電層係以一般的方法（諸如濺鍍法）依序形成於 第二介電層112與接觸插塞116上可使用爲阻障層與下 21 本紙浪尺度適用中國國家標準（CNS ) Α4規格（2丨0X297公釐） ^ ^.?1.^. (請先閲讀背面之注意事項再填Γ本頁) 4 25 6 96 經濟部智慧財產局員工消費合作社印製 A7 _ B7 _ 五、發明説明（〆） 導電層之材料層的種類以及這些層的厚度’係與第一個實 施例相同。其次，將該下導電層與阻障層以光蝕印製程刻 劃圖案，以產生一阻障層圖案140與一下電極142。 接著，藉諸如PECVD法等一般的方法，將一第三介 電層144形成於整個半導體基板100表面。可使用爲第三 介電層144之材料層的種類以及這些層的厚度，係與第一 個實施例中所形成的第一介電層108 (圖1)相同。其次， 藉光蝕印製程形成一開口 146,且間隔物148形成於開口 146的二側壁。可用以形成間隔物148之材料層的種類， 係與用以形成第一個實施例的阻絕層126 (圖7)相同。爲 形成該間隔物148, 一介電層沈積於整個半導體基板表面 上，然後進行非等向性蝕刻。 之後，藉諸如溶膠-凝膠法等一般的方法，將開口 146 以一電容介電層150塡充。在電容介電層150形成後，可 以如第一個實施例一般進行一退火製程。可使用爲電容介 電層150之材料層的種類係與第一個實施例相同。形成一 上電極152於該電容介電層150上。爲形成該上電極152 ，一上導電層係以諸如灑鍍法等一般方法形成於整個半導 體基板表面上，然後以光蝕印製程刻劃出圖案。 其次，形成一 EL，其覆蓋電容介電層150曝露出的上 表面以及上電極152。該EL可形成爲一多層’其至少包含 一阻絕層154以及一電容器保護層156。該EL在第二個實 施例中形成爲雙層。亦即，該阻絕層154與電容器保護層 係依序堆疊於整個半導體基板表面上。在形成該阻絕 _____22 ____ 本紙^尺度適用中國國家標準（CNS] A4規格（21 〇X 297公H " ¾------IT------,^ (請先閲讀背面之注意事項再填V.本頁) 經濟部智慧財產局員工消費合作社印製 4 2b 6 9 6 A7 B7 五、發明説明（>/ ) 層154和/或該電容器保護層156後，可視需要進行如第一 個實施例中的退火製程。可使用爲阻絕層154與電容器保 護層156之材料層的種類以及這些材料層的厚度，係與第 一個實施例相同。 在形成EL後，依序進行一 ILD製程、—金屬化製程 、一 IMD製程以及一鈍化製程，以形成一第四介電層158 、一上電極金屬接觸160、一下電極金屬接觸（未示於圖 中）' 一 IMD層162以及一鈍化層164。因爲這些製程係 於電容器C以EL覆蓋後進行，所以爲氫侵襲所造成之電 容介電層150的劣化可避免於本發明的第二個實施例中。 根據本發明較佳實施例之一半導體記憶裝置，已在說 明半導體記憶裝置的製法時揭示，因而未提供其細節說明 。以下，具有一雙層構造之EL的效果（亦即避免ILD製 程、IMD製程及類似期間所產生的氫基氣體造成電容器C 的劣化），將藉下列實驗性實例說明。 爲了探討該雙層EL的效果，樣品C1係於後述條件下 形成。然後，電容器的極化程度與漏電流係於將-5至5伏 特的電壓施加於樣品C1的電容器時量測。該結果係表示 於圖9與圖10中。 樣品C1係以下述製程製造。首先，形成一鐵電電容 器於一半導體基板上。該電容器的面積爲1.44Xi(r0Cm2, 而一電容介電層係以2000埃厚的PZT所形成。電容器的 上電極係一 Ir層與一 Ir02層的雙層，而這些層的厚度分別 爲1200埃與300埃。電容器的下電極亦爲一 Pt層與一 ____ 23___ 本紙張尺度逋^中國國家標準)"八4規格（210X2W公瘦Ί I---------^------ΐτ------^ (請先閱讀背面之注意事項再4.V.冬頁) 4^5696 A7 B7 五、發明说明（>^Je This paper scale is applicable to China National Standard (CNS) A4 specifications (210 X 297 mm) Printed by the MK Industrial Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 425 b ^ ϋ Α7 __Β7 V. Description of the invention (tt) Gases or these gases Compound gas. The reaction between the aluminum source gas and the oxygen source gas occurs only on the surface of the semiconductor substrate on which the aluminum source gas has been chemically adsorbed, thus forming a single atomic layer thin film. Then, after the residual oxygen source gas is removed from the chamber, a second passivation gas (selected from the above passivation gases) is used for rinsing to remove the oxygen source gas that has been physically adsorbed on the upper surface of the semiconductor substrate . The formation of such a single atomic layer thin film is called a cycle of the ALD method. This ALD method is repeated for a predetermined number of cycles until the capacitor protective layer 128 reaches a predetermined thickness, such as 100 angstroms. The preferred process conditions for forming the Al203 capacitor protection layer 128 by the ALD method are as follows. That is, the pulse delivery time of the aluminum source gas may be 0.1_2 seconds. The scrub time of the first inert gas for removing the physically adsorbed aluminum source gas may be 0.1-10 seconds. Furthermore, the pulse delivery time of the oxygen source gas may be 0.1 to 20 seconds. The rinsing time of the second inert gas for removing the physically adsorbed oxygen source gas may be 0.120 seconds. In the embodiment of the present invention, the pulse delivery time of the aluminum source gas is set to 1 second, and the cleaning time of the first passivation gas for removing the physically adsorbed aluminum source gas is set to 5 seconds. The pulse of the oxygen source gas is The transfer time is set to 0.2 seconds, and the rinsing time of the second passivation gas for removing the physically adsorbed oxygen source gas is set to 6 seconds to form the capacitor protective layer 128 by the ALD method. Furthermore, in order to further improve the function of the EL, an optional annealing process may be performed after forming the barrier layer 126 and / or the capacitor protective layer 128. In detail, after the barrier layer 126 is formed, an annealing process may be performed in an oxygen atmosphere to increase the insulation characteristics of the barrier layer 126. This annealing process is preferably performed at 600 ° C or lower. This is because when the barrier layer 126 applies the Chinese National Sample Rate (CNS) 8-4 specification (2 丨 0X297 mm) such as this paper size ---------- M -------- iT ------ Line {Please read the precautions on the back before filling -w page) 425 6 9 6 Consumer Cooperation of Intellectual Property Bureau of the Ministry of Economic Affairs Du printed A7 ____B7 V. Invention Description (\ f |) 600 When annealing is performed at a temperature of ° C or higher, oxygen may diffuse into the contact plug 116, causing an increase in barrier contact resistance. The annealing process is preferably performed at a temperature of 400-600 ° C. After the capacitor protective layer 12S is formed, the optional annealing process can be performed in an oxygen atmosphere, and preferably at a temperature of 600 ° C or lower to increase the insulation characteristics of the capacitor protective layer 1? 8. The annealing process is preferably performed at a temperature of 400-600 ° C. Under certain conditions, a high temperature annealing process at 600t: or higher temperature may be performed after the capacitor protective layer U8 is formed. This is because the contact plug 16 may not be sensitive to oxygen diffusion due to the completed EL ^ In the case of using a method other than ALD to form the capacitor protective layer I28, a high temperature annealing process may be performed after the capacitor protective layer 128 is formed. . According to the formation method of the capacitor protective layer 128, it is related to the chemical and physical stability of the capacitor protective layer 128. In detail, the capacitor protective layer 128 formed by the ALD method is more stable than the capacitor protective layer 128 formed by other methods. The advantages of the ALD method allow the capacitor protective layer 128 to be effectively used without a high-temperature annealing process. However, in the case where the capacitor protective layer 128 is formed by a method other than ALD, the insulation characteristics of the capacitor insulating layer 122 'must be improved by a high-temperature annealing process at 600 ° C or higher. In particular, in a state where the annealing process is not performed after the barrier layer 126 is formed, and the capacitor protective layer 128 is formed by a method other than ALD, it is preferably performed at 600. (: Or higher temperature annealing process. Of course, in the case where the capacitor protection layer 128 is formed by the ALD method, a high temperature annealing process can also be performed. Second, because the capacitor protection layer 128 formed by the ALD method is quite stable, so it is 19 ^ ΐτ-^ — (Please read the notes on the back before filling in V ,. This page) This paper size is applicable to China National Standard (CNS) Α4 size (210 × 297 mm) 425696 Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 V. Description of the invention) Oxygen diffused into the contact plug 16 during the annealing process can be reliably avoided, thereby further increasing the process margin in the annealing process of the capacitor protective layer 128. With the above-mentioned EL cover capacitor C ', the deterioration of the capacitor dielectric layer 122' in the subsequent integration process can be avoided, which will be described in detail below. Referring to FIG. 6, an ILD process is performed after the EL is formed. That is, a third dielectric layer 130 is formed on the entire surface of the semiconductor substrate 100. The third dielectric layer 130 may be a silicon oxide layer, a silicon oxynitride layer, a BSG layer, a PSG layer, a BPSG layer, a TEOS layer, a 0-TEOS layer, a PE-TEOS layer, a USG layer, or a composite layer of the foregoing layers. . In the case where the third dielectric layer 130 of the silicon oxide layer is formed by the CVD method, a reaction gas containing a silane gas (SiH4) and oxygen (02) is used. Incidentally, the hydrogen generated from the reaction of silane gas and oxygen may degrade the capacitor dielectric layer 122 '. However, since the capacitor C according to the present invention is covered with an EL having a double-layered structure, the hydrogen that diffuses into the capacitor C during the ILD process can be completely blocked. In particular, the capacitor protective layer 128 of the EL contributes to hydrogen diffusion barrier. The barrier layer 126 contributes to avoiding hydrogen diffusion, although its contribution need not be greater than that of the capacitor protective layer 128. After that, a metallization process is performed. That is, the third dielectric layer 130, the capacitor protective layer 128, and the barrier layer 126 are patterned by a general method to form a contact hole 132 that exposes the upper electrode 124 'of the capacitor C portion. The third dielectric layer 130 can be patterned by fluorine-based wet or dry etching. Furthermore, the capacitor protective layer 128 and the barrier layer 126 can be patterned in an argon and carbon tetrafluoride atmosphere by reactive ion etching. ______20 ^ The paper size is applicable to Chinese national standards (CNsl Μ specifications (210X297) (Li) --------- ^ ----.-- 1Τ ------ ^ (Please read the precautions on the back before filling in this page) Manufacturing 425696 V. Description of the invention (j). After the contact hole 132 is formed, an upper electrode metal contact 134 is formed. After the contact hole 132 is formed, a recovery annealing process may be performed. The recovery annealing process may be performed at, for example, 450-500 ° It is performed in an oxygen atmosphere at a temperature of C. The lower electrode metal contact (not shown in FIG. 6) may be formed simultaneously with the upper electrode metal contact 134. Referring to FIG. 7, after forming the upper electrode metal contact Π4, an IMD process is performed to form An IMD layer 136. For example, the IMD layer 136 can be formed into a spin-on-glass (SOG) layer by spin coating. Secondly, a passivation layer 138 can be formed by a passivation process. The passivation layer 138 is formed of silicon oxide by a PECVD method. Layer or silicon oxynitride layer β hydrogen may be formed between the IMD layer 136 and the passivation layer 138. During the production process (as in the ILD process), it diffuses into capacitor C. However, the capacitor protective layer 128 prevents hydrogen from diffusing into capacitor C. Therefore, the deterioration of capacitor C in the IMD and passivation process can be avoided. As described above, this The barrier layer 126 can also prevent hydrogen from diffusing into the capacitor C to some extent. As described with reference to FIGS. 6 and 7, when the ILD, IMD, and passivation processes are performed on the capacitor C covered with EL, the capacitance caused by hydrogen attack Deterioration of the dielectric layer 122 'can be avoided. Embodiment 2 The second embodiment of the present invention is performed in the same manner as the first embodiment until the contact plug 116 is formed. Referring to FIG. 8, a barrier layer The following conductive layer is sequentially formed on the second dielectric layer 112 and the contact plug 116 by a general method (such as sputtering method). It can be used as a barrier layer and the lower layer. This paper applies the Chinese National Standard (CNS). Α4 Specifications (2 丨 0X297mm) ^ ^.? 1. ^. (Please read the notes on the back before filling this page) 4 25 6 96 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 _ B7 _ 5 、 Explanation of invention (〆) The types of material layers and the thickness of these layers are the same as in the first embodiment. Second, the lower conductive layer and the barrier layer are patterned by a photolithographic printing process to generate a barrier layer pattern 140 and Lower the electrode 142. Next, a third dielectric layer 144 is formed on the entire surface of the semiconductor substrate 100 by a general method such as a PECVD method. The types of material layers used as the third dielectric layer 144 and the thickness of these layers can be used. Is the same as the first dielectric layer 108 (FIG. 1) formed in the first embodiment. Second, an opening 146 is formed by a photolithography process, and spacers 148 are formed on two sidewalls of the opening 146. The types of material layers that can be used to form the spacer 148 are the same as those used to form the barrier layer 126 (FIG. 7) of the first embodiment. To form the spacer 148, a dielectric layer is deposited on the entire surface of the semiconductor substrate and then anisotropically etched. Thereafter, the opening 146 is filled with a capacitive dielectric layer 150 by a general method such as a sol-gel method. After the capacitor dielectric layer 150 is formed, an annealing process may be performed as in the first embodiment. The types of material layers that can be used as the capacitor dielectric layer 150 are the same as those of the first embodiment. An upper electrode 152 is formed on the capacitor dielectric layer 150. To form the upper electrode 152, an upper conductive layer is formed on the entire surface of the semiconductor substrate by a general method such as a sputtering method, and then a pattern is scribed by a photolithography process. Next, an EL is formed to cover the exposed upper surface of the capacitor dielectric layer 150 and the upper electrode 152. The EL may be formed as a multi-layer ' including at least a barrier layer 154 and a capacitor protection layer 156. The EL is formed as a double layer in the second embodiment. That is, the barrier layer 154 and the capacitor protective layer are sequentially stacked on the entire surface of the semiconductor substrate. In the formation of this barrier _____22 ____ This paper ^ standard applies Chinese National Standards (CNS) A4 specifications (21 〇X 297 公 H " ¾ ------ IT ------, ^ (Please read the back Note for refilling V. This page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2b 6 9 6 A7 B7 V. Description of the invention (&); /) After the layer 154 and / or the capacitor protective layer 156, it can be performed as needed Like the annealing process in the first embodiment, the types of material layers that can be used as the barrier layer 154 and the capacitor protection layer 156 and the thickness of these material layers are the same as those in the first embodiment. After forming the EL, sequentially Perform an ILD process, a metallization process, an IMD process, and a passivation process to form a fourth dielectric layer 158, an upper electrode metal contact 160, a lower electrode metal contact (not shown in the figure) 'an IMD layer 162 and a passivation layer 164. Since these processes are performed after the capacitor C is covered with EL, the deterioration of the capacitor dielectric layer 150 caused by hydrogen attack can be avoided in the second embodiment of the present invention. According to the present invention A semiconductor memory device according to a preferred embodiment, It was disclosed in the description of the manufacturing method of the semiconductor memory device, so no detailed description is provided. In the following, the effect of EL with a two-layer structure (that is, avoiding the hydrogen-based gas generated in the ILD process, IMD process, and the like from causing the capacitor C Deterioration) will be illustrated by the following experimental examples. In order to explore the effect of the double-layer EL, sample C1 was formed under the conditions described below. Then, the degree of polarization and leakage current of the capacitor was applied by a voltage of -5 to 5 volts Measured on the capacitor of sample C1. The results are shown in Figure 9 and Figure 10. Sample C1 is manufactured by the following process. First, a ferroelectric capacitor is formed on a semiconductor substrate. The area of the capacitor is 1.44Xi ( r0Cm2, and a capacitor dielectric layer is formed of 2000 angstroms thick PZT. The upper electrode of the capacitor is a double layer of an Ir layer and an Ir02 layer, and the thickness of these layers is 1200 angstroms and 300 angstroms respectively. The electrode is also a Pt layer and a __ 23___ this paper size (^ Chinese national standard) " 8 4 specifications (210X2W male thin) I --------- ^ ------ ΐτ-- ---- ^ (Please read the notes on the back before 4 .V. Winter page) 4 ^ 5696 A7 B7 V. Description of the invention (> ^

Ir02層的雙層’而這些層的厚度分別爲1500埃與500埃。 其次，一 EL形成爲一雙層。亦即，藉濺鍍法形成厚 度爲1000埃的Ti〇2層做爲一阻絕層，並於45〇°C的氧氣氣 氛中退火3〇分鐘。其次’藉ALD法形成摩度爲120埃的 Al2〇3做爲一電容器保護層。 之後，進行該ILD製程（氫來源氣體在此期間產生） ，而形成一介電層於整個半導體基板表面上’然後形成部 份曝露出上下電極的—接觸孔。爲了將接觸孔形成期間所 産生的損傷復原’該樣品C1係於450°C的氧氣氣氛中退火 30分鐘。其次’形成—上電極金屬接觸以及一下電極金屬 接觸。 參考圖9，可由約25eC/cm2的殘留極化値看出，其 幾乎與起始水平相當，所以該電容介電層並未被形成Ti02 與Al2〇3層的EL後所進行的ILD製程劣化。該結果證實 EL可避免電容介電層的劣化。 參考圖10，可看出該電容器的漏電流在1-4伏特的電 壓下約爲安培。亦即，可以確定的是：該電容器的漏 電流在該半導體記憶裝置的操作電壓範圍中表現出穩定的 分布。由此結果，亦可總結：該EL避免了電容介電層的 劣化。 製造樣品C2與C3以跟樣品C1對照。爲便於進行比 較，Ti〇2與αι2ο3層（分別形成做爲阻絕層與電容器保護 層）藉與形成樣品C1相同的方法，分別形成爲樣品C2與 C3的一單獨EL。亦即，樣品C2的EL係以濺鑛法形成， 24 本紙張尺度適用中國國家揉準（CNS ) Α4規格（210X297公釐） f請先閲讀背面之注意事項再填νϊ 裝· 訂 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員X消費合作杜印製 4 b 9 6 4 25 6 9 6 A7 B7 '*' " 、w, 11 '— 五、發明説明（4) 而樣品C3的EL係以ALD法形成》 詳言之，爲製造該樣品C2與樣品C3，一電容器形成 製程在與樣品C1相同的條件下進行，而形成一電容器於 一半導體基板上。然後，一 EL形成爲單層。樣品C2與 C3的各單層EL係於下列條件下形成。 在樣品C2的狀況中，該EL藉濺鍍法形成厚度爲 1000埃的一 Ti02層。其次，在650°C的氧氣氣氛中進行30 分鐘的退火，以強化該EL的絕緣特性。在此，相較於樣 品C1之阻絕層的形成，該退火溫度更高。 在樣品C3的狀況中，該EL藉ALD法形成厚度爲 120埃的一 AI2O3層°在此，分別使用A1(CH4)3以及H2O 氣體做爲鋁來源氣體以及氧來源氣體。然而，該EL並未 進行退火。 其次，以與樣品C1相同的方法，在樣品C2與C3上 進行一 ILD與金屬化製程，以形成一下電極金屬接觸與一 上電極金屬接觸。然後，樣品C2與C3的極化程度在電壓 改變下量測，如同樣品C1的狀況，而產生遲滯曲線（各 以圖11的C2與C3標示）。樣品C1的遲滯曲線（以C1 標示）亦示於圖U中。 再者，由樣品Cl、C2與C3各選擇I2個晶粒，並量 測阻障接觸電阻。結果示於圖I2中。在圖12中，樣品C1 、C2與C3的阻障電阻各以Cl、C2與C3標示。 如圖11所示，樣品C2之遲滯曲線面積小於樣品C1 。相對於樣品C1，此意味樣品C2的電容介電層的鐵電特 ___25__ 本纸張尺度適用中國國家榡準（CNS ) A4規格1 2]〇X297公釐） ' ----------¢----—1T------^ (請先閱讀背面之注意事項再填广本頁) 經濟部智慧財產局員工消費合作社印製 425696 A7 B7 五、發明説明（<) 性在ILD製程中劣化。再者，由樣品C3的殘留極化値（ 幾乎爲零）來看，樣品C3的電容介電層的鐵電特性幾乎 完全劣化。由這些結果，可作成下列結論。 第一，樣品C2的EL (丁丨02層）可在ILD製程中阻絕 氫的擴散。然而，相較於樣品ci (具有Ti〇2與ai2o3的雙 層EL)的狀況，該阻絕效果相當弱。 第二，樣品C1之阻絕層（Ti02層）的退火溫度低於 樣品C2之EL ( Ti02層）》因此’相較於樣品C2的EL ’ 樣品C1的阻絕層的絕緣特性較差。然而，即使相較於樣 品C2而言樣品C1的絕緣特性差，但樣品C1阻絕氫的效 果佳》此意味阻絕氫擴散的功能主要藉樣品1的電容器保 護層進行。 第三，該EL的絕緣特性可在單層EL形成後’藉在 60(TC或更高溫的高溫退火改良（如樣品C2的狀況）°然 而，爲氫侵襲所造成之電容器劣化的問題無法完全爲該單 層EL所解決。 第四，樣品C3中的電容介電層劣化與用於形成該EL (Al2〇3層）的方法有關。亦即，劣化的原因來自於使用 H20氣體做爲氧來源氣體。同時，在樣品C1的狀況中’ 該電容器保護層係於阻絕層形成後才形成。亦即’因爲該 電容器係以阻絕層覆蓋’所以H20氣體可在藉ALD法形 成電容器保護層（A1203層）中用做氧來源氣體’而不會劣 化該電容介電層。 如圖12所示，樣品C1的阻障接觸電阻較樣品3爲低 26____ 本紙張尺度適用中國囷家標準（CNS > A4規格（2丨0><297公釐） _ J ' I I ί ^ 1. 線— (請先閱讀背面之注意事項再填/ Λ頁) 經濟部智慧財產局員工消費合作社印製 4 25 6 9 6 A7 _____B7_ 五 '發明説明（y<) 。再者，樣品C2的阻障接觸電阻增加至約1ΜΩ或更高的 程度。下列的結論可由圖12的結果獲得。 第一，樣品C1之阻絕層形成中的退火溫度450°c，係 低於樣品C2之EL形成中的退火溫度60(TC。亦即，樣品 C2之阻障接觸電阻的增加，係由於EL高溫退火時氧擴散 進入該接觸插塞所造成。_ 第二，樣品C3的EL ( A1203層）較樣品C2的EL ( Ti〇2層）更能有效地避免氧擴散。雖然樣品C3的EL與樣 品C1的電容器保護層形成的條件相同，但樣品C1的EL 具有較佳的阻絕氧擴散能力。因此，阻絕氧擴散的效果可 藉由形成雙層的EL而改良。 藉由根據本發明之半導體記憶裝置的製法，以EL覆 蓋電容器，而使得電容器不受外在環境影響。亦即，可避 免由於整合製程（其係於電容器形成後進行）期間之氫侵 襲所造成的電容介電層劣化。 雖然本發明已特別地揭示並參考其較佳實施例作說明 ，惟熟習本技藝之人士將瞭解：可於不違背如所附申請專 利範圍所定義之本發明的精神與範疇下，做出各種形式上 與細節的改變β 27 ^------II------^ (請先閲讀背面之注意事項再填4頁) 本紙張尺度適用令國國家標準（CNS ) Α4規格（210Χ297公釐），The double layer of the Ir02 layer 'and the thicknesses of these layers are 1500 angstroms and 500 angstroms, respectively. Second, an EL is formed as a double layer. That is, a Ti02 layer having a thickness of 1000 angstroms was formed as a barrier layer by a sputtering method, and was annealed in an oxygen atmosphere at 45 ° C for 30 minutes. Secondly, Al2O3 with 120 angstroms was formed as a protective layer for the capacitor by the ALD method. After that, the ILD process is performed (a hydrogen source gas is generated during this period), and a dielectric layer is formed on the entire surface of the semiconductor substrate ', and then a contact hole partially exposing the upper and lower electrodes is formed. In order to recover the damage generated during the formation of the contact hole, the sample C1 was annealed in an oxygen atmosphere at 450 ° C for 30 minutes. Second 'formation-upper electrode metal contact and lower electrode metal contact. Referring to FIG. 9, it can be seen from the residual polarization of about 25eC / cm2 that it is almost equivalent to the initial level, so the capacitor dielectric layer has not been degraded by the ILD process performed after the formation of the EL of the Ti02 and Al203 layers. . This result confirms that EL prevents deterioration of the capacitor dielectric layer. Referring to Fig. 10, it can be seen that the leakage current of the capacitor is about amperes at a voltage of 1-4 volts. That is, it can be confirmed that the leakage current of the capacitor shows a stable distribution in the operating voltage range of the semiconductor memory device. From this result, it can also be concluded that the EL prevents deterioration of the capacitor dielectric layer. Samples C2 and C3 were made to compare with sample C1. In order to facilitate the comparison, the Ti0 2 and α 2 3 layers (formed as a barrier layer and a capacitor protection layer, respectively) are formed as a separate EL of samples C2 and C3 by the same method as that of the sample C1. That is, the EL of sample C2 is formed by the splatter method. 24 paper sizes are applicable to the Chinese National Standard (CNS) A4 specification (210X297 mm) f Please read the precautions on the back before filling. Ϊ Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, printed by the Intellectual Property Bureau of the Ministry of Economic Affairs, and printed by the Consumer Cooperative Department of the Ministry of Economic Affairs. 4 b 9 6 4 25 6 9 6 A7 B7 '*' ", w, 11 '— 5. Description of the invention (4) and sample C3 The EL is formed by the ALD method. In detail, in order to manufacture the samples C2 and C3, a capacitor formation process is performed under the same conditions as the sample C1, and a capacitor is formed on a semiconductor substrate. Then, an EL is formed as a single layer. The single-layer ELs of samples C2 and C3 were formed under the following conditions. In the case of sample C2, the EL was formed into a Ti02 layer with a thickness of 1000 angstroms by sputtering. Next, annealing was performed in an oxygen atmosphere at 650 ° C for 30 minutes to strengthen the insulation characteristics of the EL. Here, the annealing temperature is higher than the formation of the barrier layer of the sample C1. In the condition of sample C3, the EL formed an AI2O3 layer with a thickness of 120 angstroms by the ALD method. Here, A1 (CH4) 3 and H2O gas were used as the aluminum source gas and the oxygen source gas, respectively. However, the EL was not annealed. Next, an ILD and metallization process was performed on samples C2 and C3 in the same way as sample C1 to form a lower electrode metal contact and an upper electrode metal contact. Then, the degree of polarization of samples C2 and C3 was measured under a change in voltage, as in the case of sample C1, and a hysteresis curve was generated (each indicated by C2 and C3 in Figure 11). The hysteresis curve (labeled C1) for sample C1 is also shown in Figure U. Furthermore, I2 grains were selected from each of the samples Cl, C2 and C3, and the barrier contact resistance was measured. The results are shown in Figure I2. In FIG. 12, the barrier resistances of the samples C1, C2, and C3 are each indicated by Cl, C2, and C3. As shown in FIG. 11, the area of the hysteresis curve of the sample C2 is smaller than that of the sample C1. Relative to sample C1, this means that the ferroelectric characteristics of the capacitor dielectric layer of sample C2 ___25__ This paper size is applicable to China National Standard (CNS) A4 specifications 1 2] 〇297mm) '------- --- ¢ ----— 1T ------ ^ (Please read the notes on the back before filling out this page) Printed by the Intellectual Property Bureau Staff Consumer Cooperatives of the Ministry of Economic Affairs 425696 A7 B7 V. Invention Description (<) Deterioration in ILD process. Furthermore, from the residual polarization 値 (almost zero) of sample C3, the ferroelectric characteristics of the capacitor dielectric layer of sample C3 were almost completely degraded. From these results, the following conclusions can be made. First, the EL (layer 02) of sample C2 can block the diffusion of hydrogen during the ILD process. However, compared to the condition of the sample ci (a two-layer EL with Ti02 and ai2o3), the blocking effect is quite weak. Second, the annealing temperature of the barrier layer (Ti02 layer) of sample C1 is lower than the EL (layer of Ti02) of sample C2. Therefore, ‘compared to the EL of sample C2’, the insulation characteristics of the barrier layer of sample C1 are poor. However, even though sample C1 has poor insulation characteristics compared to sample C2, sample C1 has a good effect of blocking hydrogen. This means that the function of blocking hydrogen diffusion is mainly performed by the capacitor protective layer of sample 1. Thirdly, the insulation characteristics of the EL can be improved by 60 ° C or higher temperature annealing (such as the condition of sample C2) after the formation of the single-layer EL. However, the problem of capacitor degradation due to hydrogen attack cannot be completely solved. Solved by this single-layer EL. Fourth, the deterioration of the capacitor dielectric layer in sample C3 is related to the method used to form the EL (Al203 layer). That is, the cause of the deterioration comes from the use of H20 gas as oxygen Source gas. At the same time, in the condition of sample C1, the capacitor protective layer was formed after the barrier layer was formed. That is, because the capacitor is covered with a barrier layer, H20 gas can form a capacitor protective layer by the ALD method ( A1203 layer) is used as an oxygen source gas' without deteriorating the capacitor dielectric layer. As shown in Figure 12, the barrier contact resistance of sample C1 is lower than that of sample 3 26 __ This paper size is in accordance with Chinese standards (CNS > A4 specification (2 丨 0 > < 297 mm) _ J 'II ί ^ 1. Thread — (Please read the notes on the back before filling / page Λ) Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 25 6 9 6 A7 _____B7_ Five 'invention description y <). Furthermore, the barrier contact resistance of sample C2 was increased to about 1 MΩ or higher. The following conclusions can be obtained from the results of Fig. 12. First, the annealing temperature in the formation of the barrier layer of sample C1 is 450 ° c. Is lower than the annealing temperature of 60 ° C. in the EL formation of sample C2. That is, the increase in the barrier contact resistance of sample C2 is due to the diffusion of oxygen into the contact plug during high temperature annealing of EL._ Second, The EL of the sample C3 (layer A1203) is more effective in avoiding oxygen diffusion than the EL of the sample C2 (layer Ti02). Although the conditions for forming the capacitor protective layer of the sample C3 and sample C1 are the same, the EL of the sample C1 has Better ability to block oxygen diffusion. Therefore, the effect of blocking oxygen diffusion can be improved by forming a double-layer EL. By manufacturing the semiconductor memory device according to the present invention, the capacitor is covered with EL so that the capacitor is not subject to external Environmental impact. That is, the deterioration of the capacitor dielectric layer due to hydrogen attack during the integration process (which is performed after the capacitor is formed) can be avoided. Although the present invention has been specifically disclosed and referenced to its preferred embodiments, However, those skilled in the art will understand that various changes in form and detail can be made without departing from the spirit and scope of the invention as defined by the scope of the appended patents. Β 27 ^ ------ II ------ ^ (Please read the precautions on the back before filling in 4 pages) This paper size applies the national standard (CNS) Α4 specification (210 × 297 mm),

Claims (1)

經濟部智慧財產.局員工消費合作社印製 4 2 5 6 9 6 as B8 C8 D8 六、申請專利範圍 1. 一種半導體記憶裝置的製法，其包含： 形成一電容器於一半導體基扳中，該電容器具有一下 電極、一上電極以及一置於上下電極間之電容介電層；以 及 形成一包封層而以多層覆蓋電容器。 2. 如申請專利範圍第1項之製法，其中該包封層包含 至少一阻絕層與一電容器保護層。 3. 如申請專利範圍第2項之製法，其更包含在形成包 封層後形成一介電層於該包封層上的步驟。 4. 如申請專利範圍第2項之製法，其中該包封層爲一 雙層，且形成該包封層的步驟包含： 形成該阻絕層以覆蓋電容器；以及 形成該電容器保護層以覆蓋阻絕層。 5. 如申請專利範圍第2項之製法，其中該阻絕層係由 可避免形成於該阻絕層下方之一材料層與電容器保護層間 產生反應的一材料所形成，而該電容器保護層係由可避免 氫擴散進入電容介電層之一材料所形成。 6. 如申請專利範圍第2項之製法，其中該阻絕層係由 可避免該電容介電層揮發的一材料所形成，而該電容器保 護層係由可避免氫擴散進入電容介電層之一材料所形成。 7. 如申請專利範圍第2項之製法，其中該阻絕層係由 可避免該電容介電層揮發並可避免形成於該阻絕層下方之 一材料層與電容器保護層間產生反應的一材料所形成，而 該電容器保護層係由可避免氫擴散進入電容介電層之一材 1 ^訂 線 (請先閲讀背面之注$項再填V頁) 本紙張足度適用t國國家揉丰（CNS ) A4規格（210X297公* ) 4 2 5 6 9 6 A8 B8 CS _ D8 六、申請專利範圍 料所形成。 8·如申請專利範圍第2項之製法，其中該電容器保護 層係以原子層沈積法形成。 9.如申請專利範圍第2項之製法，其更包含在形成阻 絕層後將具有阻絕層的所得構造在400-600°C的氧氣氣氛中 退火的步驟。 10_如申請專利範圍第2項之製法，其更包含在形成電 容器保護層後將具有電容器保護層的所得構造在400-600°C 的氧氣氣氛中退火的步驟。 Π.如申請專利範圍第2項之製法，其中該阻絕層係由 —Ti〇2 層 ' —Ta205 層、一 BaTi〇3 層、一SrTi03 層、一 Bi4Ti30.i2 層、一 PbliOi 層、一 Si02 層、一 SiN 層、一 (Ba，Sr)Ti03 層、一(Pb，La)(Zr，Ti)03 層、一 Pb(Zr，Ti)03 層 或一 SrBi2Ta2〇9層所形成。 I2·如申請專利範圍第2項之製法，其中該電容器保護 層係由一 Ti〇2 層、一 Ta2〇5 層、一' AI2O3 層、一BaTi〇3 層 、一 SrTi〇3 層、—BiJisOu 層、一PbTi03 層、一 Si〇2 層 、一 SiN 層、一(Ba，Sr)Ti03 層' —(Pb，La)(Zr，Ti)〇3 層、一 Pb(Zr，Ti)〇3層或—SrBi2Ta2〇9層所形成，且由與該阻絕層 相異的一材料層所形成。 13·如申請專利範圍第2項之製法，其中各阻絕層與電 容器保護層形成50-1500埃的厚度。 M·—種半導體記憶裝置，其包含： 一電容器，其具有一下電極、一上電極以及一置於上 ____ _2_ 本紙浪尺度適用中國躅家襟率（CNS > A4现格（210X297公釐） --------¾.II (請先聞讀背面之注意事項再填V )頁) . 線 經濟部智慧財產！>5員工消費合作社印製 425696 A8 B8 C8 D8 〜---- 以及 六、申請專利範圍 下電極間之電容介電層； 一多層包封層’其係形成於該電容器上； 一介電層，其係形成於該多層包封層上； 一上電極金屬接觸，其穿經該介電層而與上電極接觸 下電極金屬接觸，其穿經該介電層而與下飕極接觸 15. 如申請專利範圍第I4項之半導體記憶裝鹰，其中 該包封層包含至少一阻絕層與一電容器保護層，而該阻絕 層形成於電容器保護層下方。 ~ 16. 如申請專利範圍第I5項之半導體記憶裝霞，其中 該包封層爲雙層，且該阻絕層覆蓋電容器，而該電容^保 護層覆蓋阻絕層。 Π·如申請專利範圍第1S項之半導體記憶裝霞，其中 該阻絕層係由可避免形成於該阻絕層下方之一材料層與電 容器保護層間產生反應的一材料所形成，而該電容器保護 層係由可避免氫擴散進入電容介電層之一材料所形成。 1S.如申請專利範圍第I5項之半導體記憶裝釐，其中 該阻絕層係由可避免該電容介電層揮發的一材料所形成， 而該電容器保護層係由可避免氫擴散進入電容介電層之一 材料所形成。 I9·如申請專利範圍第15項之半導體記憶裝置，其中 該阻絕層係由可避免該電容介電層揮發並可避免形成於該 阻絕層下方之一*材料層與電容器保護層間產生反應的一材 良紙張適用*^國1|家揉準（CNS ) A规( 2IOX25»7公釐 -------¾----I--1T------^ (請先W讀背面之注意事項再洗 4頁) 經濟部智慧財A局員工消費合作社印製 425 6 96 AS s —___—_ D8 六、申請專利範圍 料所形成，而該電容器保護層係由可避免氫擴散進入電容 介電層之一材料所形成。 2〇.如申請專利範圍第15項之半導體記憶裝置，其中 該阻絕層係於400-60CTC的氧氣氣氛中退火。 21. 如申請專利範圍第I5項之半導體記憶裝置，其中 該電容器保護層係於400-600°C的氧氣氣氛中退火。 22. 如申請專利範圍第15項之半導體記憶裝置，其中 該電容器保護層係以原子層沈積法形成。 23. 如申請專利範圍第15項之半導體記憶裝置，其中 其中各阻絕層與電容器保護層的厚度形成爲5(M500埃。 24. 如申請專利範圍第15項之半導體記憶裝置，其中 該阻絕層係由一Ti02層、一 Ta205層、一BaTi03層、一 SrTi03層、一 Bi4Ti3012層、一PbTi〇3層、一 3丨02層、一 SiN 層、一（Ba，Sr)Ti03 層、一（Pb，La)(Zr，Ti)03 層、一 Pb(Zr，Ti)03 層或一 SrBi2Ta209 層所形成。 25. 如申請專利範圍第15項之半導體記憶裝置，其中 該電容器保護層係由一 Ti〇2層、一Ta205層、一Al2〇3層 、一 BaTi03層 ' —SrTi03層、一；^41^3012層、一 PbTi03 層、一Si〇2 層、一 SiN 層、〜（Ba，Sr)Ti〇3 層、一 (Pb，La)(Zr，Ti)〇3 層、一 Pb(Zr，Ti)〇3 層或—SrBi2Ta2〇9 層所 形成，且由與該阻絕層相異的一材料層所形成。 26. —種半導體記憶裝置，其包含： 一電容器，其具有一下電極、〜上電極以及一置於上 下電極間之電容介電層； 4 义張尺度適用國家標¥ ( CNS ) A4规格^210X297公方- fπ------.ii (請先閲讀背面之注意事項再填 4頁) 經濟部智慧財產局員工消費合作社印製 425696 A8 B8 C8 D8 六、申請專利範圍 一阻絕層，其覆蓋電容器，並由一 ΤΚ)2層、一 Ta205 層、一 BaTiCh 層、一 SrTi〇3 層、一 Bi4Ti3〇n 層、一 PbTi03 層、一Si〇2 層、一SiN 層、一(Ba，Sr)Ti03 層、一 (Pb，La)(Zr，Ti)03 層、一 Pb(Zr，Ti)03 層和一 SrBi2Ta209 層組 成的族群中選擇的一材料層所形成； 一電容器保護層，其覆蓋該阻絕層，並由一Ti〇2層、 一 Ta2〇5 層、一Al2〇3 層、一 BaTi〇3 層、一 SrTi〇3 層、一 Bi4Ti3012 層、一PbTi03 層、一 Si02 層、一SiN 層、一 (Ba，Sr)Ti〇3 層、一(Pb，La)(Zr，Ti)〇3 層 ' —Pb(Zr，Ti)〇3 層 和一 SrBi2Ta209層組成的族群中選擇的一材料層所形成； 一上電極金屬接觸，其穿經該阻絕層與電容器保護層 而與上電極接觸；以及 一下電極金屬接觸，其穿經該阻絕層與電容器保護層 而與下電極接觸。 ---------^------ΐτ------^ (請先閲讀背面之注意事項再填' _ΐ ) 經濟部智慧財產局員工消費合作社印製 5 本紙張尺度適用中國國家橾準（CNS M4说格（210X297公着)Printed by the Intellectual Property of the Ministry of Economic Affairs and the Consumer Cooperative of the Bureau 4 2 5 6 9 6 as B8 C8 D8 VI. Application for Patent Scope 1. A method for manufacturing a semiconductor memory device, comprising: forming a capacitor in a semiconductor substrate, the capacitor It has a lower electrode, an upper electrode, and a capacitor dielectric layer disposed between the upper and lower electrodes; and an encapsulation layer is formed to cover the capacitor with multiple layers. 2. The manufacturing method according to item 1 of the patent application scope, wherein the encapsulation layer includes at least a barrier layer and a capacitor protection layer. 3. If the method of applying for the second item of the patent scope further comprises the step of forming a dielectric layer on the encapsulating layer after forming the encapsulating layer. 4. The manufacturing method according to item 2 of the application, wherein the encapsulation layer is a double layer, and the steps of forming the encapsulation layer include: forming the barrier layer to cover the capacitor; and forming the capacitor protection layer to cover the barrier layer . 5. For the manufacturing method according to item 2 of the scope of patent application, wherein the barrier layer is formed of a material that can prevent a reaction between a material layer formed below the barrier layer and the capacitor protection layer, and the capacitor protection layer is made of Prevents hydrogen from diffusing into one of the materials of the capacitor dielectric layer. 6. For the manufacturing method according to item 2 of the patent application, wherein the barrier layer is formed of a material that can prevent the capacitor dielectric layer from volatilizing, and the capacitor protective layer is made of one of the capacitor dielectric layers that can prevent hydrogen from diffusing into the capacitor dielectric layer. Material. 7. The manufacturing method according to item 2 of the scope of patent application, wherein the barrier layer is formed of a material that can prevent the capacitor dielectric layer from volatilizing and prevent a reaction between a material layer formed below the barrier layer and the capacitor protection layer. The protective layer of the capacitor is made of a material that can prevent the diffusion of hydrogen into the dielectric layer of the capacitor. ^ Ordering (please read the note on the back and then fill in page V) This paper is adequate for countries in China (CNS) ) A4 size (210X297 male *) 4 2 5 6 9 6 A8 B8 CS _ D8 6. The scope of patent application is formed. 8. The manufacturing method according to item 2 of the patent application range, wherein the capacitor protective layer is formed by an atomic layer deposition method. 9. The manufacturing method according to item 2 of the patent application scope, further comprising the step of annealing the obtained structure having the barrier layer in an oxygen atmosphere at 400-600 ° C after the barrier layer is formed. 10_ The manufacturing method according to item 2 of the scope of patent application, further comprising the step of annealing the resulting structure having the capacitor protective layer in an oxygen atmosphere at 400-600 ° C after the capacitor protective layer is formed. Π. The manufacturing method according to item 2 of the scope of the patent application, wherein the barrier layer is composed of a Ti02 layer, a Ta205 layer, a BaTi03 layer, an SrTi03 layer, a Bi4Ti30.i2 layer, a PbliOi layer, and a Si02 layer. Layer, a SiN layer, a (Ba, Sr) Ti03 layer, a (Pb, La) (Zr, Ti) 03 layer, a Pb (Zr, Ti) 03 layer, or a SrBi2Ta209 layer. I2. The manufacturing method of item 2 in the scope of the patent application, wherein the capacitor protection layer is composed of a Ti02 layer, a Ta205 layer, an AI2O3 layer, a BaTi03 layer, a SrTi03 layer, and BiJisOu. Layer, a PbTi03 layer, a Si02 layer, a SiN layer, a (Ba, Sr) Ti03 layer '-(Pb, La) (Zr, Ti) 03 layer, a Pb (Zr, Ti) 03 layer Or -SrBi2Ta2O9 layer, and is formed of a material layer different from the barrier layer. 13. The manufacturing method according to item 2 of the scope of patent application, wherein each barrier layer and the capacitor protective layer are formed to a thickness of 50-1500 angstroms. M · —A semiconductor memory device comprising: a capacitor having a lower electrode, an upper electrode, and an upper electrode ____ _2_ This paper wave scale is applicable to China ’s family rate (CNS > A4 now standard (210X297 mm) ) -------- ¾.II (please read the notes on the back before filling in the V) page). Intellectual Property of the Ministry of Online Economy! > Printed by 5 employee consumer cooperatives 425696 A8 B8 C8 D8 ~ ---- and 6. Capacitive dielectric layer between electrodes under the scope of patent application; a multilayer encapsulation layer 'formed on the capacitor; a dielectric An electrical layer is formed on the multilayer encapsulation layer; an upper electrode metal contact passes through the dielectric layer to contact the upper electrode and a lower electrode metal contacts passes through the dielectric layer to contact the lower electrode. 15. The semiconductor memory device of claim I4, wherein the encapsulation layer includes at least a barrier layer and a capacitor protection layer, and the barrier layer is formed under the capacitor protection layer. ~ 16. For example, the semiconductor memory device X1 in the scope of application for patent, wherein the encapsulation layer is double-layer, the barrier layer covers the capacitor, and the capacitor ^ protection layer covers the barrier layer. Π · Semiconductor memory device according to the scope of application for patent No. 1S, wherein the barrier layer is formed of a material that can prevent a reaction between a material layer formed below the barrier layer and the capacitor protective layer, and the capacitor protective layer It is formed of a material that prevents hydrogen from diffusing into the capacitive dielectric layer. 1S. The semiconductor memory device according to item I5 of the patent application scope, wherein the barrier layer is formed of a material that can prevent the capacitor dielectric layer from volatilizing, and the capacitor protective layer is formed of a capacitor that prevents hydrogen from diffusing into the capacitor dielectric. One of the layers is formed of a material. I9. The semiconductor memory device according to item 15 of the application, wherein the barrier layer is a layer that prevents the capacitor dielectric layer from volatilizing and prevents formation of one of the layers below the barrier layer. Cailiang paper is applicable * ^ Country 1 | China Standard (CNS) A Regulation (2IOX25 »7mm ------- ¾ ---- I--1T ------ ^ (please first W Read the precautions on the back and then wash 4 pages) Printed by the Consumer Finance Cooperative of the Bureau of Intellectual Property A of the Ministry of Economic Affairs 425 6 96 AS s —___—_ D8 6. The scope of patent application is formed, and the protective layer of the capacitor is made of avoidable hydrogen Diffusion into one of the materials of the capacitor dielectric layer. 20. The semiconductor memory device according to item 15 of the patent application range, wherein the barrier layer is annealed in an oxygen atmosphere of 400-60CTC. 21. If the patent application range is I5 Item of the semiconductor memory device, wherein the capacitor protective layer is annealed in an oxygen atmosphere at 400-600 ° C. 22. For example, the semiconductor memory device of the scope of application for patent item 15, wherein the capacitor protective layer is formed by an atomic layer deposition method 23. For the semi-conductor of the scope of patent application No. 15 A memory device in which the thickness of each barrier layer and the protective layer of the capacitor is formed to 5 (M500 angstroms. 24. For example, the semiconductor memory device of the scope of application for patent No. 15, wherein the barrier layer is a Ti02 layer, a Ta205 layer, BaTi03 layer, one SrTi03 layer, one Bi4Ti3012 layer, one PbTi03 layer, one 3 丨 02 layer, one SiN layer, one (Ba, Sr) Ti03 layer, one (Pb, La) (Zr, Ti) 03 layer, A layer of Pb (Zr, Ti) 03 or a layer of SrBi2Ta209. 25. For example, the semiconductor memory device under the scope of application for patent No. 15, wherein the capacitor protection layer is composed of a Ti02 layer, a Ta205 layer, and an Al2〇. 3 layers, one BaTi03 layer '-SrTi03 layer, one; ^ 41 ^ 3012 layer, one PbTi03 layer, one Si02 layer, one SiN layer, ~ (Ba, Sr) Ti03 layer, one (Pb, La) (Zr, Ti) 〇3 layer, a Pb (Zr, Ti) 〇3 layer, or -SrBi2Ta2O9 layer, and is formed of a material layer different from the barrier layer. 26. A semiconductor memory device , Which includes: a capacitor having a lower electrode, an upper electrode, and a capacitive dielectric layer placed between the upper and lower electrodes; With national standard ¥ (CNS) A4 size ^ 210X297cm-fπ ------. Ii (Please read the notes on the back before filling in 4 pages) Printed by the Intellectual Property Bureau Staff Consumer Cooperative of the Ministry of Economic Affairs 425696 A8 B8 C8 D8 VI. Patent application scope-A barrier layer that covers the capacitor and consists of a TK2 layer, a Ta205 layer, a BaTiCh layer, an SrTi03 layer, a Bi4Ti3ON layer, a PbTi03 layer, and a Si〇2 A material selected from the group consisting of a layer, a SiN layer, a (Ba, Sr) Ti03 layer, a (Pb, La) (Zr, Ti) 03 layer, a Pb (Zr, Ti) 03 layer, and a SrBi2Ta209 layer A capacitor protection layer covering the barrier layer, and consisting of a Ti02 layer, a Ta205 layer, an Al203 layer, a BaTi03 layer, an SrTi03 layer, and a Bi4Ti3012 layer , A PbTi03 layer, a Si02 layer, a SiN layer, a (Ba, Sr) Ti03 layer, a (Pb, La) (Zr, Ti) 03 layer '-a Pb (Zr, Ti) 03 layer, and Formed by a material layer selected from the group consisting of an SrBi2Ta209 layer; an upper electrode metal contact which passes through the barrier layer and the capacitor protective layer to contact the upper electrode; and Metal contact electrode, through which the capacitor through the barrier layer and the protective layer in contact with the lower electrode. --------- ^ ------ ΐτ ------ ^ (Please read the notes on the back before filling in '_ΐ) 5 papers printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs Standards apply to Chinese national standards (CNS M4 grid (210X297))
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