TW424319B - System and method for limiting charge-pump internal node voltage - Google Patents

Abstract

This invention relates to a charge-pump that can limit the internal node voltage to decrease the junction breakdown possibility. This charge-pump includes the first pump circuit, the second pump circuit, the first clamp circuit and the second clamp circuit. When the voltage of a well region reaches the first predetermined critical point, the first clamp circuit provides a current path from the well region to the output terminal to limit the voltage of well region. The second clamp circuit restricts a node voltage and the electric charge is redistributed from this node to the well region. The second clamp circuit is designed to provide a conducting path from this node to output terminal when the node voltage reaches the second predetermined critical point. Each one of the pump circuits can include a logic circuit. Depending on the difference of external supply voltage, the logic circuit is designed to be able to decrease the rising rate of capacitor node when the external supply voltage is relatively large. This logic circuit can also change the voltage difference between the capacitor node and the external supply voltage in order to decrease the relative voltage between the capacitor node and the external supply voltage. These characteristics also are useful to reduce the junction breakdown possibility of charge-pump.

Description

424319 V. Description of the invention (1) Field of the invention The present invention relates to an integrated circuit charge pump, in particular to an integrated circuit charge pump having a circuit that can limit the potential of its internal node. BACKGROUND OF THE INVENTION Certain integrated circuits (meaning wafers) require different potential supply voltages. These supply voltages can be generated directly in the wafer by incorporating a voltage generator into the wafer. For a supply voltage generated in a chip that is higher than the external supply voltage, a charge pump is usually used as the voltage generator. Figure 1 is a block diagram of a conventional integrated circuit charge pump 10, which is used to generate a supply voltage vh which is higher than the external supply voltage. The charge pump 10 includes a main pump stage (MPS) '-a well pump stage (WPS) 13 and two P-channel transistors pi4 and P15 as channel gates MPS 11 And WPS 13 are respectively connected to a VDD supply bus and a ground bus to receive power from an external power supply providing a supply voltage VDD. In addition, MPS 11 and WPS 13 are connected via a control line 16 to receive n (η represents an integer greater than zero) pump control signals ^ Mps 丨 丨 and liver $ a. The output terminals are connected to the p-channel transistor P14 and? Source of 15. The gates of the P-channel transistors P14 and P15 are connected to a connection 18 to receive a pump-up control signal PMPBST. When PMPBST is triggered (meaning a logic low potential in this embodiment), it has a pull-up potential (meaning a potential higher than the normal VDD potential) and is used to control the transmission from the Mps n & wps 13 output terminal Charge. The drain of the p-channel transistor P14 is connected to the output terminal 19 * The drain of the P-channel transistor P15 is connected to the well region of the p-channel transistor p14. In this example, p

P. 5 4243

The channel transistor P14 is constructed in the β-well region. As is well known in semiconductor technology, the well region must maintain a potential (hen) higher than or equal to the highest potential of the source or drain of the p-channel transistor. In order to make the transistor work normally. However, due to the fluctuation of the load current, the potential at% of the output terminal 9 (ie, the drain of the p-channel transistor P14) is sometimes higher than the output of Mps η (the source of the p-channel transistor P1 4). ) Potential. In addition, the potential of the source of the transistor p4 may also be lower than the potential of Vh. Therefore, it is not helpful to simply connect the well region to the source or non-pole of the p-channel transistor P14. To deal with this problem, the charge pump 10 uses WPS 13 to maintain the potential of the transistor at a preset potential greater than the highest potential in the source or sink of the P-channel transistor P14. Those who are familiar with this technology are familiar with the capacitance value and leakage current of the well region of the P-channel transistor P1 5 are usually small '. Therefore, the potential of the source of the p-channel transistor p 1 5 will always be greater than or equal to the potential of the well region. Therefore, connecting the drain of the p-channel transistor P15 to a well region can effectively maintain the potential of the well region at or higher than the potential of the source and the drain of the p-channel transistor P15. In order to maintain the supply voltage Vh at the desired potential, traditionally, a control circuit (not shown) provides a pump circuit signal on the connection 16 so that MPS11 and WPS13 transfer the charge to the p-channel transistor P14, respectively. And P15. Pump up the signal PMPBST as a control P channel transistor P14 and? 15 to transfer the charge from the MPS11 and WPS13 to the well 19 of the wheel outlet 19 and the P-channel transistor 14 respectively. More specifically, when MPS11 and WPS13 connected to the sources of p-channel transistors P14 and P15 are charging their pump capacitors, P-channel transistors P14 and P15 are turned off. In particular, Mpsil and WPS13 increase their corresponding output voltage to

V. Description of the invention (3) Supply potential. This is usually done by charging a capacitor in the pump stage such that the first terminal is at the zero potential point and the second terminal is externally supplied with the voltage potential. After that, the pumping stage raises the potential of the first terminal, so at least, at the beginning, the potential of the second terminal is increased to a potential higher than that of the external power supply. ’'T one one ^ 々 像 %% ^ rh jui ^ The potential is the same as or higher than the potentials of the source and non-poles of P14 and P15

V When MPS11 and WPS13 have increased the source potentials of the P-channel transistors pi4 and P15, the PMPBST signal turns on the P-channel transistors P14 and pi5 so that the charge can be redistributed from the pump capacitors of MPSU and WPS1 3 to the p-channel, respectively. The source of the electric aa body P14 and P15, and the well area to the channel exit 19 and p channel, respectively. With this method, the charge pump 10 generates a supply voltage and maintains well. However, if the potential of the well region of the P-channel transistor P14 is too high, the chance of the joint surface in the well device to collapse will increase. The external power supply voltage is still large for the M-test test order. This problem is caused by the charge pump. Therefore, there is a need to control the internal node power of the invention. The purpose of the invention is to provide a charging circuit that can control the internal node voltage. The characteristics are a first circuit and a second clamping circuit. According to the present invention, its special circuit is reached by the potential in the 丼 region, and the preset electric circuit is set. The present invention has the following features: the current path restricts the well area. The first clamping circuit is at a first node. The invention reduces the probability of collapse of the joint surface in the charge pump. The embodiment in the middle of the month includes a first pump circuit; a second pump power ^^ 88111980 V. Description of the invention (4) The bit reaches a second pre-execution w ^ ------ " conductive Path to limit — the point to the output is redistributed to the well [potential and the charge is opened by the first node. Restricting the well area and the point where the point is connected to the device in the well area can reduce the potential of the joints of the present invention. The pump circuit and a capacitor temporary charge pump include a logic circuit. The circuit is based on external characteristics. One of the characteristics is that the capacitor node in the logic is powered by a pump circuit. The shore voltage is relatively high. This feature is suitable for low-speed external power supply: outside the voltage rise rate, the capacitor node is external; when the supply is quite large, Li I. This feature is suitable for reducing the external supply voltage when the external supply voltage becomes another. The potential of the capacitive node becomes another mechanism to reduce the probability of rupture at the joint. The diagram shows the block diagram of the charging circuit of the old integrated circuit using the conduction gate of the p-channel transistor. FIG. 2 is a block diagram of an integrated circuit charge pump with internal node voltage control in an embodiment of the present invention. Fig. 3 is a circuit diagram of the integrated circuit charge pump for completing the block diagram in Fig. 2. Fig. 4 is an operation timing chart of the integrated circuit charge pump in Fig. 3. DETAILED DESCRIPTION FIG. 2 is a block diagram depicting an integrated circuit charge pump 20. in accordance with

05ib-4535TW? 2-pic Page 8 42 > 43f 9 _ V. Description of the invention (5) '~ In one embodiment of the present invention, the charge pump 20 includes an internal node voltage limiting control. For the sake of clarity, elements having the same or similar functions or structures in each figure are given the same reference numerals. Except that-the main pump stage (MPS) 21 with the main burn control circuit (MBC) 22 and the well pump stage (WPS) 23 with the well burn control circuit (WBC) 24 are different from the MPS1 1 (Figure 1) and WPS13C (Figure 1), the charge pump 20 is similar to the charge pump 10 (Figure 1). In addition, the charging pump 20 of this embodiment includes a clamping circuit 25 and a clamping circuit 26. The charging fruit 20 is assembled as follows. The MPS21 receives a pump control signal 'via the connection 16 like the charge pump 10 (Fig. 1). In this embodiment, 1 ^ [22 and * ^ 321 receive a burn-in pump control signal BPMP via the connection 27. The output of MPS21 is connected to the source of P-channel transistor P1 4 via a point N20. The gate connection of the p-channel transistor p 1 4 receives the pump-up signal PMPBST. The drain (ie, output terminal 19) of the channel transistor P14 is connected to one end of the clamp circuit 25. The other end of the clamp circuit 25 is connected to the N-well region of the transistor P14 and the drain of the transistor P15. WPS23 is also connected to charge pump 10 (Figure 1) to receive the pump control signal through connection 16. In this embodiment, WBC24 of WPS23 is connected via a connection 28 to receive a well pumping control signal WBIC. The output of WPS23 is connected to the source of P-channel transistor pi5 via a node N22. The gate of the p-channel transistor P15 receives the pump-up signal PMPBST via a connection. The drain of the P-channel transistor P15 is connected to the N-well region of the transistor p14 and the drain of the transistor P15. The clamp circuit 26 is connected between the node N22 and the output terminal 19. The operation of the charge pump 20 is as follows. In normal mode operation, BPMP and

4243 1 9 V. Description of the invention (6) WBIC signal makes MBC22 and WBC24 enter normal mode. When the mbC22 is in the normal mode, it performs internal operations with the remaining circuits of the MPS21 to use the method like MPS11 (Figure 1) to cause the MPS21 to raise the potential of the node N20 in response to the pump control signal received from the connection 16. When MPS21 raises the potential of node N20, the 'P-channel transistor P14 allows the charge to be redistributed from node N20 to output terminal 19 in response to the PMPBST signal. The potential of the control signal ′ ^ is maintained at a desired potential by appropriately triggering the control signal. h Similarly, in normal mode, the remaining circuits of WBC24 and WPS23 perform internal operations to use methods such as ffMPS13 (Figure 1) to make WBC23 raise the potential of node N22 in response to the pump control signal received from the connection 6 . When W ^ S24 raises the potential of node N22, the p-channel transistor pi5 allows the charge from

Node N22 is reassigned to the well area of p-channel transistor pi4 in response to the pMpBST signal. By this method, the potential of VweI1 is maintained at a potential equal to or greater than the v-point N 2 0. 1 According to the present invention, the clamp circuits 25 and 26 are used to limit the electric potential of the ¥ and the knowledge point N22 to prevent the joints in the device connected to the p-channel transistor pi4 well area from collapsing. The clamping circuit 25 is designed to limit the U potential by providing a path from the P-channel transistor P14 to the wheel-out when the Vweil potential reaches the ―predicted critical voltage‖. For example, "2" can be used-its positive electrode is electrically connected to the p-channel circuit v-one-to avoid Γ. Because the potential of Vwen is limited to a potential that is higher than the threshold voltage of the t 极 -pole body, the junction surface in the device connected to the well: ^ 4 well zone is prevented from collapsing. Similarly, fine tap,, φ. λ, the sweet thorn circuit 26 is designed to reach the potential at the node N22—

Α9ά1 ^ ί V. Description of the invention (7) --------- When presetting the threshold voltage, by referring to the potential of the limit node N22 from the knowledge point N22 to the output terminal 19 For example, the clamp circuit 26 bis; 6 I is connected to the point N22 and its negative electrode is electrically connected to the output terminal 19 ^. Therefore, the potential of the node N22 is limited to a potential of a value of ρ Ί -¾ Φ a, which is higher than the threshold voltage of a polar body, which is used to transfer the charge to the electric channel P of the P channel. 1 4 I Γ5 " + 4 * jtL Λ- rsr ^ a Λ The pull-up voltage of well 14 prevents the joint in the device connected to the channel aafP14 well area from collapsing. In the burn-in mode, the external supply voltage VDD of this embodiment is increased by about 4.5 volts during the burn-in test, but as known to those skilled in the art, the burn-in voltage is technology-related. Because Mps21 and liver §23 provide the pull-up amounts at N2 0 and N22, which are usually related to the external supply voltage v⑽, in the burn-in mode, the rise of nodes N20 and N22 will usually be greater than in normal mode. Therefore, although the clamp circuits 25 and 26 help and limit the potential of v, these clamp circuits cannot prevent the high potential of the external voltage when the burn-in mode is enabled. MPS21 and WPS23 increase the potential of nodes N20 and N22 to these fairly high The potential. Since it takes a certain amount of time to transfer charges from nodes N20 and N22 to the well area of wheel 19 and P channel transistor p14, if nodes N20 and N22 rise faster than the charge is redistributed through transistor pi4 & pi5 Compared with the source of the transistor P14 & P15, the high voltage growth at the nodes N20 and N22 will cause the junction in the device connected to the p-channel transistor pi4 well area to collapse. According to the present invention 'MBC22 and WBC24 are designed to reduce the ascent rate of nodes N20 and N22 during the burn-in mode. In the burn-in mode, when MpS2l and WPS23 are pulled up_points N20 and N22, reducing the rising rate helps to provide electricity

Page 11 4243 1 8 Five 'Explanation of the invention (8)' -------- --- How much time is redistributed from these nodes to the output end and the P-channel transistor ^ P14 well area. As a result, the highest potentials of the nodes N20 and N22 are lowered, which reduces the probability of a joint collapse in a device connected to the nodes N20 and N22. The more refined 疋 'WBC24 not only reduces the rise rate, it can also be designed to limit the pull-up potential of node N22 during the burn-in mode. MBC22 and ffBC24 are described below with reference to Figure 3 only. Fig. 3 is a schematic diagram depicting the charge pump 20 (Fig. 2). In this embodiment, MPS21 uses n-channel transistors 20, MN21, MN24, and P-channel transistors P20, P21, and a capacitor. . To be done. The p-channel transistor pH is also used as MBC22. The connection of MPS21 is as follows. The source, gate, and end of the N-channel transistor MN20 are connected to the VDD supply bus, connection 16], and node N20, respectively. The connection line 61 is a unit line for connection line 16 (Fig. 1) for transmitting the pump control signal. In this embodiment, ^ is connected to transmit a pre-boost fs to break PREBST. When the node N20 is precharged, the PREBST signal is selectively triggered or idled, which will be described in detail below. When the signal PREBST is triggered, it will have a potential higher than the external supply voltage VDD. The N-channel transistor MN21 is connected as a diode, with the positive pole connected to the vdd supply bus and the negative pole fast connected to the node N20. Capacitor C20 is connected between nodes N2 0 and N21. The source, gate, and drain of the P-channel transistor P20 are connected to the VDD supply bus, connection 162, and node N21. The connection 162 is a unit line of connection 16 (Fig. 1), and is used for transmitting the pump control signal. In this embodiment, the 'connection 162 transmits a pump signal PMP. Lifting node N20

Page 12 4243 1 9 V. In the description of the invention (9), the PMP signal is selectively triggered to a logic high level, which will be described in detail below. The source, gate, and drain of the P-channel transistor P2 1 are connected to the VDD supply bus, connection 27, and node N21. The connection 27 is connected to receive the burn-in pump signal BPMP and the signal BPMP is selectively triggered or idled when the node N20 rises, and is idle in the burn-in mode, which will be described in detail below. The source, gate, and drain of the N-channel transistor MN24 are connected to the ground bus, the connection 163, and the node N21. The connection 163 is a unit line of the connection 16 for transmitting a pump control signal. In this embodiment, the connection 1 transmits a pre-capaci tor signal PRECAP. The PRECAP signal is selectively triggered or idled when the node N20 rises, as will be explained in detail below. WPS23 includes an N-channel transistor MN25, MN26, MN28, MN29 and

P-channel transistors P23, P25 and a capacitor C21. The connection of WPS23 is as follows. The N-channel transistor MN25 has its pole, gate, and drain connected to the VDD supply bus, connection 16 !, and node N22, respectively. The N-channel transistor MN26 is connected as a diode ', whose positive terminal is connected to the VDD supply bus and the negative terminal is connected to the node N22. Electricity C21 is connected between nodes N22 and N24. The source, gate and drain of the P-channel transistor P23 are connected to the VDD supply bus, connection i 6 and node N23, respectively. The source and gate of the 2 P-channel transistor p 2 5 are connected to node N23, connection 28, and node N24, respectively. Connection 28 is a unit line of connection 28, which is used to transmit the burn-in control signal in the well area. In this embodiment, connection 28m is connected to receive a burn-in control signal TBURN and the signal TBURN is in normal mode.

4243ί ^ V. Description of the Invention (ίο) Idle ’which is triggered during the burn-in mode, will be described in detail below. The source, gate, and non-poles of the N-channel transistor MN28 are connected to the ground bus, connection 16a, and node N24, respectively. The source, gate, and drain of the N-channel transistor MN29 are connected to point N24, line 282, and point N23, respectively. The connection 282 is a unit line of the connection 28 and is connected to transmit a normal mode pump signal. The PMPN signal is triggered in the burn-in mode and idle in the normal mode, which will be described in detail below. In another embodiment, the 'TBURN and PMPN signals are the same signal. In addition, the PMPN signal may also be a reverse signal of the PMP signal. In addition, the charge pump 20 includes a P-channel transistor P26 and N-channel transistor MN23, MN27, and MN30. The channel transistor P26 is connected as a diode, the positive electrode of which is connected to the well region of the P-channel transistor P14, and the negative electrode is connected to Output terminal 19. Therefore, the 'diode-connected' ρ channel transistor ρ26 limits the potential of ^ chuan to a threshold voltage (ie, about, +) above a Vh potential. The ν channel transistors MN23, MN27, and MN30 are also connected as diodes. In particular, the anode of the 'diode-connected N-channel transistor Zhao MN23 is connected to the VDD supply bus and the anode is connected to the output terminal 19. Therefore, the diode-connected N-channel transistor MN23 causes the potential Vh of the output terminal 19 to rise to a potential (ie, VDI) _Vtn) which is lower than the VDD external supply voltage by a critical voltage value. The anode of the diode-connected N-channel transistor MN27 is connected to the VDD supply bus and its anode is connected to the region of the P-channel transistor P14. Therefore, the ν-channel transistor MN27 is used to raise the veell to a potential lower than the external supply voltage vdd by a critical voltage value (ie, VDD-Vtn). Diode-connected transistor questions 23 and MN2 7 increase the source voltage at power-on to help ensure correct

Page 14 424319 V. Description of the invention (11) Start. The diode-connected N-channel transistor) has a positive pole connected to node N22 and a negative pole connected to output terminal 19. Therefore, the N-channel transistor MN30 limits the potential of the node N22 to a potential higher than the vh potential by a threshold voltage value. FIG. 4 is a timing diagram illustrating the operation of the charge pump 20. The potential of the pmpbsT signal is represented by a waveform 40. As shown in waveform 40, the PMPBST signal is actually a clock signal when its high potential is equal to the pull-up potential. The potential of the PREBST signal is represented by waveform 41, which is also a periodic signal with a high potential being a pull-up potential ^ The high potential state of the PREBST signal is slightly delayed and is shorter than the high potential state of the PMPBST signal. The potential state completely covers the high potential state of the PREBST signal. The potential of the PRECAP signal is represented by waveform 42, except that the high potential of the PRECAP signal is equal to the normal potential (that is, approximately the same as the external supply voltage) ', which is approximately the same as the PREBST signal. The PMP signal is represented by waveform 43 'as a periodic signal with no pull-up potential. The time of the high potential state of the waveform 43 is longer than the time of the high potential state of the waveforms 41 and 42. In addition, the high-potential state of waveform 43 starts at about the same time as the high-potential state of the PMPBST signal, but is shorter than the PMPBST signal. Therefore, the high-potential state of waveform 40 completely covers the high-potential state of waveform 43, as well as the high-potential state of waveforms 41 and 42.

The potentials at nodes N20 to N22 and N24 are represented by waveforms 45, 44, 47, and 46, respectively. The waveforms 44 to 47 during the operation of the charge pump 20 (Fig. 3) are as follows. BPMP is represented by waveform 48 and is approximately equal to the PMP signal in the normal mode. However, the BPMP signal is idle in the burn-in mode. V. Explanation of the invention (12) Therefore, the waveform 48 in the figure shows that there is a low potential D pmpn and TBURN signal in the burn-in mode by the waveforms 49 and 50. In normal mode, waveforms 49 and 50 remain high. On the contrary, in the burn-in mode, the waveforms 49 and 50 remain at a low level. In addition, the PMpN signal may be a reverse signal of the pmp signal. As mentioned earlier, the waveforms 40 to 43 and 48 to 50 are provided by a control circuit (not shown). Those skilled in the art of integrated circuit technology can make such a control circuit without additional research after reading the description of the present invention. Please refer to FIG. 3 and FIG. 4. The operation of this embodiment of the charge pump 20 is as follows. In the normal startup mode, the N-channel transistors MN21, MN23, MN26 and MN27 pre-charge the well area of node N20, output 19, node N22, and P-channel transistor P14 to a threshold voltage lower than the external supply voltage VDD Value of potential. In addition, the PMPN and TBURN signals are at a low potential, so the N-channel transistor MN29 is turned off and the p-channel transistor p25 is turned on. As for the sections sN2 {) and N22 ′, the initial pre-charging is displayed on the rising edges 45! And 47 of the waveforms 45 and 47. Then as pjjpBSTj ·! Is at the pull-up potential, the pREBST signal is pushed up to a pull-up potential, as shown by rising edge 41. As a result, the p-channel transistors P14 and P15 are turned off and the N-channel transistors MN20 and MN25 pull the potentials of the nodes N20 and N22 to the potentials of the external supply voltage, respectively. The “full pull” (fuU_rail puu_up) of the potentials of nodes mo and N22 is shown on the rising edge segments 452 and 472. The PRECAPk number is triggered at the rising edge 41, as shown by the rising edge 42 of the waveform 42]. In response to the high potential of the PRECAp signal, the n-channel transistors MN24 and MN28 are turned on ', thus pulling down the potentials of the nodes N2m and ㈣ 彳, respectively. Then the PREBST and PRECAP signals are idle, as shown in the falling edge. V. Invention Description (13) 412 and 4 22. After the low potentials of the PREBST and PRECAP signals turn off the n-channel transistors MN20, MN24, MN25, and MN28, the control circuit (not shown in the figure) idles the PMP and BPMP, as shown in the falling edge 43t below. As mentioned before, the PMP and BPMP signals are the same in normal mode. The low potential of the PMP and BPMP signals turns on the p-channel transistors P2 0, P23, and P21 ′, thus pulling up the potentials of nodes N21 and N23, as shown by rising edges 44] and 46 !. In addition, since the pjjPN and TBURN signals are at a low potential ', the N-channel transistor MN29 is turned off and the p-channel transistor p25 is turned on. As a result, the potentials of the “卽 points N 2 0 and N 2 2 are pulled up via the capacitors c 2 0 and c 2 1, respectively” as shown in the rising edge segments 453 and 4 73. P-channel transistors P20 and P21 provide two parallel rising paths to directly pull up the potential of node N2i. Since the P-channel transistor is used as a pull-up device, the potential of node N20 can be pulled up to a capacitor and charged to this potential plus. When the PMP signal is idle, the potential of node N22 is pulled up by a slightly different method. The P-channel transistors P23 and P25 provide a single rising path to pull up the potential of node N24. Furthermore, since the p-channel transistor is used as a rising device, the potential of the node N22 can be pulled up to the aforementioned potential plus VDI). Then the 'PMPBST signal is interlaced' as shown by the falling edge 40m. The low potential of the PJiPBST signal turns on the p-channel transistor pi4 and? 15 so that electricity can be immediately redistributed to points N20 and N22 to the output terminal 9 and the p-channel electric crystal P14 well area. Then the PMPBST, PMP and BPMP signals are switched to high potentials' as shown by rising edges 402, 432 and 482. PMPBST, PMP and BPMP 1 Lu closed the P-channel transistors P14, P15, P20, P23 and P21. This cycle follows the rising edge of the PREBST and PRECAP signals next-straight on page 17 V. Description of the invention (⑷ *-duplicate. Relatively, in the burn-in mode, the control circuit (not shown) provides f The BPMP signal held at a high potential. As a result, the p-channel body P21 and P25 are turned off, and the N-channel transistor _29 is turned on. The signal of 2 is also provided in the same manner as in the normal mode, so the pump 20 ( Figure 4) The operation mode in the burn mode is the same as in the positive f mode except for the following description. Because the P-channel transistor P21 is turned off in the burn-in mode, only the channel transistor P20 is used to pull up The potential of node N21. Therefore, compared with the normal mode operation, C20 is pulled at a lower rate in the positive f mode operation. The operation of the p-channel transistor P20 and P21 raises the capacitance C2. In the burn-in mode, only the transistor P20 is used to pull up the capacitor C20., = Is turned on at the N-channel transistor view 9 and? The channel transistor m is' electrical !! Via the P-channel transistor P23 Crystal_ to pull up. But 疋, in the P channel transistor P23 and 25 Under normal = pull-up comparison, the N-channel transistor simply limits the pull-up of node N24 to a threshold voltage value 5 which is lower than the external supply voltage VDD. ΓΛ The reduced pull-up on node N 2 4 is not only reduced. It can increase the potential of node N22, and also reduce the rise rate of capacitor C2l. For example, the decrease in the “capacitance” and ⑶ rise rate in the “entry mode” effectively reduces the connection to the P14 well in the P-channel transistor. The machine for the breakdown of the joint surface The above-mentioned embodiment of the internal voltage limiting control mechanism of the charging pump is only on page 18 --- 5 'Description of the Invention (15)' --- This is an explanation of the main principles of the present invention, not the Restricting the present invention ^ For those who are familiar with integrated circuit technology after reading the present invention, two examples are made of different MBC22, OC24 and clamp circuits 25, 26. ^ ^ can be M ^ C22, WBC24 and clamp circuits %, 26 can also be designed to provide unique, I boundary points and rising rates. Therefore, although the present invention has been disclosed as above with the preferred embodiment, it is prepared without departing from the spirit and scope of the present invention. Can be changed and retouched slightly.

Claims (1)

S2d319 VI. Application for patent scope 1. A charge pump formed in or on a semiconductor substrate ^ The charge pump includes: / 'The output power consumption of the first and first pumps is combined to enable the first device Critical 2. The switcher switches the Le-Fu-pu circuit 'has an output end and a shape-shifter on a well area' The well area has a conductivity different from that of the substrate. The circuit is coupled to receive an external supply voltage, where the first A group of calculations can make the output terminal have a potential higher than the external power supply voltage;% £ The second pump circuit has a-second switcher, which receives the external supply voltage, wherein the-蜇, # ^ Use electricity _, — $ Pu circuit is set up, the well area has a potential higher than or equal to the output voltage, and the first clamping circuit is coupled to the output terminal and 誃% 131 · 'and the clamping circuit is It is designed to provide a current path from the well area to the end of the wheel at the midpoint of φ A ^ well area of the well area. . Including a P-channel formed in an N-well area, wherein the pole of the first P-channel transistor is light-coupled to the charge as described in item 1 of the scope: the second is coupled to the output terminal and An internal node a ,,, _, the second clamp is designed to provide a current path from the internal node to the output terminal when the potential of the internal node reaches a second preset critical point. ‘The charge pump as described in item 3 of the scope of patent application’, wherein the first preset critical point is an electric instrument, and the first preset critical point is lower than the second critical point. The charging system according to item 3 of the scope of patent application, wherein the second Control circuit When the circuit is activated, 4. and the second preset HI Page 20 —---------, 'Scope of patent application ▲ The device has a first terminal and a second terminal, the' terminal is closed in the 3 Haijing area and the second terminal is coupled To the internal node. 6. The charge pump according to item 3 of the scope of patent application, wherein the first and second clamping circuits each have a diode. The charge pump according to item 5 of the scope of the patent application, wherein the first sweet circuit includes an N-channel transistor with a first threshold voltage and the second sweet circuit includes a second threshold voltage. Which? Channel transistor 'The first critical voltage value is greater than the second critical voltage ^^ 8.-A method for limiting the potential of an internal node of a charge pump The charge pump has a well area and a first and a second operation mode, the The M pump is coupled to a supply bus 'the supply bus is connected to receive an external supply voltage' The charge pump is designed to provide an output voltage whose voltage value is greater than the value of the external supply voltage, the charge pump is also designed So that the well area has a potential and the potential value is greater than the potential value of the output voltage 'the potential value of the external supply voltage in the first operation mode is less than the potential value in the second operation mode' The method includes : Increasing the potential of the first internal node of the charge pump at a first rate in the first operating mode, the potential of the output voltage being related to the potential of the first internal node; in the second operating mode The potential of the first internal node of the charge pump is increased at a second rate, and the first and second rates are different. 9. The method according to item 8 of the scope of patent application, wherein increasing the potential of the first internal node of the charge pump at a first rate includes: enabling a first switch to be selectively turned on in the first operation mode versus Page 21 42431® ^ • ^^^^ Patent Scope Hehui Group reported that 'the first switch is coupled to the first internal node and the supply travelling farming; and a first switch is selectively turned on and off in the first operation mode' the second switch Is coupled to the first internal node and the supply line. 10. The method according to item 9 of the scope of patent application, wherein the first node is selectively coupled to an output of the charge pump via a first capacitor. 11. The method as described in claim 10, wherein the first capacitor is coupled to the output terminal using a -p channel transistor. 12. The method according to item 8 of the scope of patent application, wherein increasing the potential of the first internal node multiplied by the charging at a second rate includes: enabling the first switch to selectively turn on and off in the second operating mode. shut down; ' The closing during the process includes: the switcher in the second operation mode asks for the potential of the second internal node of the charge pump to rise at a third rate in the first operation mode as described in item 8 of the patent range The potential is related to the potential of the second internal node; ^, in the second operation mode, the electric standing of the second internal node of the charge pump rises at a fourth rate, the third and fourth rates Is different. Section 14 · The method described in item 13 of the scope of application 'where the potential of the second internal point rises to the same potential as the external supply voltage in the first operating mode, and in the second operating mode Rose to that external supply 4243ί ^ 6. Scope of patent application The potential value of the voltage is small. 1 5. The method as described in item 13 of the scope of patent application, wherein increasing the potential of the second internal node of the charge pump at a third rate includes: enabling a third switch to be selective in the first operating mode Ground on and off, the third switch is coupled to the supply bus and a third internal node of the charge pump; and a fourth switch is turned on throughout the first operation mode, the fourth switch A router is coupled to the second and third internal nodes. 16. The method as described in item 15 of the scope of patent application, wherein increasing the potential of the second internal node at the fourth rate includes: causing the third switch to selectively turn on and off in the second operating mode. Close; enable a fifth switch to be turned on throughout the second operation mode, and the fifth is coupled to the second and third internal H. 1 The method described in item 16 of the patent scope; including: closing the fifth switch during the entire operation of the first operation mode; closing the fourth switch during the entire operation of the second operation mode. 18. The method according to item 13 of the scope of patent application, wherein the second internal node is selectively coupled to the well area via a second capacitor. 19. The method according to item 18 of the scope of patent application, wherein a P-channel transistor is used to couple the second capacitor to the well area. 2 0. A charge pump formed in or on a semiconductor substrate having a first conductivity, the charge pump has a first operation mode and a second operation mode, the charge pump includes: 4M§ fq on page 23 6. Apply for a patent ^ ~~~ an output; a first node; a first switch coupled to the output and the first node, the switch is formed in a well area And above, the well region is formed in the substrate and has a second conductivity which is different from the first conductivity, wherein the first switch is designed to be selectively at the first node and the output A conductive path is formed between the terminals; a supply bus is connected to receive an external supply voltage, the external supply voltage having a voltage value greater than that in the first operation mode in the second operation mode; and a first pump circuit, Coupling to the first node and the supply bus', wherein the first pump circuit is designed to selectively increase the potential of the first node to a potential that is greater than the potential of the external supply voltage. It is further designed to increase the potential of the first node at a first rate in the first operation mode and increase the potential of the second node in the second operation mode: In the first Apply for charging or include a second node as described in item 20 of the patent scope; a second cut 3B second switch is closed to the well area and the second node 'where the place is formed-twilight% leaf It is possible to select a second gang between the second node and the well area; the grinding point, which enables the second circuit to be coupled to the supply bus and the second section ~ the pump circuit is designed to be able to Make one of the second nodes electrical I page 24. 6. The scope of patent application rises to a potential that is greater in value than the external supply voltage. The second pump circuit is further designed in the first operating mode. The potential of the second node is increased at a third rate and the potential of the second node is increased at a fourth rate in the second operation mode, which is different from the fourth rate 0 2 2. The charge pump described in claim 20, wherein the first pump circuit includes: a third switch coupled to the supply bus and a third node, wherein the third switch is designed to Can be selectively turned off or on in the first operation mode; A fourth switch is coupled to the third node and the supply bus, wherein the fourth switch is designed to be selectively synchronized with the third switch in the first operation mode or to be selectively turned off or Enemy_: 2 3: ¾ ^ The charging described in item 22 of the patent scope includes a first capacitive coupling to the first node and the third node. 24. The charge pump according to item 22 of the scope of patent application, wherein the first, third and fourth switches are P-channel transistors. 2 5. The charge pump according to item 21 of the scope of patent application, wherein the second pump circuit is designed to increase the potential of the second node to a level equal to the external supply voltage in the first operation mode And the potential of the second node in the second operating mode rises to a value smaller than the external supply voltage. 26. The charge pump according to item 21 of the scope of patent application, wherein the second pump circuit includes: Page 25 ΑΓ: t3 t 9ίαΐί_ VI. Patent application scope A fifth switch coupled to the supply bus and a fourth node, wherein the fifth switch is designed to be selectable in the first operating mode Ground is turned off or on; and a sixth switch is coupled to the fourth and a fifth node, wherein the sixth cutting skin is designed to be turned on in the first operation mode. The charge-second capacitor described in item 26 of the patent scope is coupled to the second and fourth nodes. 2 8. The charge pump according to item 26 of the scope of patent application, wherein the second charge pump further includes a seventh switch coupled to the fourth and fifth nodes, and the second charge pump is also designed to make the The seventh switch is turned on throughout the second operation mode. _ 2 9. The charge pump as described in item 28 of the scope of patent application, wherein the second pump circuit is also designed to cause the seventh switch to be turned off during the entire process of the first operation mode and to enable the sixth switch The switch is turned off throughout the second operation mode. 30. The charge pump according to item 28 in the scope of patent application, wherein the second, fourth and sixth switches are P-channel transistors, and the seventh switch is an N-channel transistor. Page 26 ^ 243 ^ f 9 Ν'-: 1. '\, the scope of the patent application converter is formed by nature, the second device is designed as a conductive path; a supply voltage should have the potential of the first group in the formula- In and above a well area 'The well area has conductivity different from the first conductivity, and there may be a second conductivity between the first node and the output terminal where the first switch is selectively formed—to choose In the electrical operation mode of the first voltage, the second operating mode rate is not changed. The bus' connection receives a value in the first; and the device, coupled AE clothing = Q to the first node and the potential of the node rises. To one bit, where the first-pump device is set to the potential of the first node to rise at a second rate in the first-speed mode, the first external supply voltage is greater than that in the first external operation mode. The operation mode of the supply bus is greater than the external supply and is counted as the first operation rate increases and the The speed and the first, second, and second switching places form a lead, a second band, and a selectively connected supply voltage. An operating mode is the charging node described in item 31 of the second range of the second operating rate. And the second device is designed to be connected to the second node and the electrical path; and the pump device is coupled to the supply busbar to raise the potential of the second node to a potential of one, where In the two pumps, the potential of the second node rises at a fourth rate in a first mode, the same as Includes two nodes, where the well interval selectivity and the second node are numerically greater than the outer and are designed to rise at the third rate and the third rate and the Page 27 f§ VI. Patent Application Range 33. The charge pump according to item 32 of the patent application range, wherein the second pump device is designed to make the potential of the second node in the first operation mode It rises to the same potential as the external supply voltage and is lower than the external supply voltage in the second operation mode. Page 28