JP4380846B2 - Booster - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a boosting device that generates and outputs a boosted voltage higher than that of a high-voltage side of a power supply, and particularly occurs when the minimum voltage at which a semiconductor integrated circuit can operate is lowered. The present invention relates to a booster that can be suitably used to prevent a reduction in drive capability of a transmission gate.
[0002]
[Prior art]
FIG. 4 is a circuit diagram showing a configuration of a conventional booster. In the figure, 33 is a charging power source, 34 is a charging capacitor, 35 is a holding capacitor, 36 is a reference power source, and 37 and 38 are both terminals of the charging capacitor 34 alternately with the charging power source 33 or the holding capacitor 35. A pair of switching elements to be connected, 39 is a control circuit for controlling the operation of the pair of switching elements 37 and 38, and 40 is an output terminal.
[0003]
Next, the operation will be described.
First, the control circuit 39 controls the pair of switching elements 37 and 38 so that both terminals of the charge-up capacitor 34 are connected to the charge power source 33, and charges the charge-up capacitor 34 to the voltage of the charge power source 33. . Next, the control circuit 39 controls the pair of switching elements 37 and 38 so that both terminals of the charge-up capacitor 34 are connected to the holding capacitor 35, whereby the holding capacitor 35 is the same as the charge-up capacitor 34. Charge to voltage. Then, by repeating the switching operation of the pair of switching elements 37 and 38 at a predetermined cycle, the charging voltage of the holding capacitor 35 is increased by the amount of increased charge supplied to the holding capacitor 35 per unit time and the output terminal. 40 and a reduced charge amount due to natural discharge or the like are maintained at a voltage level. As a result, a boosted voltage having a level obtained by adding the charging voltage of the holding capacitor 35 and the voltage of the reference power source 36 is output from the output terminal 40.
[0004]
[Problems to be solved by the invention]
Since the conventional booster is configured as described above, it is used to prevent the drive capability of the transmission gate from being lowered when the minimum power supply voltage of the semiconductor integrated circuit is lowered. When trying to do so, there were the following problems.
[0005]
First, when the power source of the semiconductor integrated circuit is used as the charging power source 33 or the reference power source 36 in the conventional booster, the power source of such a semiconductor integrated circuit is used from the minimum power source voltage to the maximum power source voltage. A voltage in the possible power supply voltage range is supplied, and the booster device may output a voltage twice as large as this maximum power supply voltage. When such an output voltage is supplied to a transistor constituting the transmission gate, problems such as insufficient withstand voltage of the transistor occur. Therefore, when the conventional boosting device is used to prevent the drive capability of the transmission gate from being lowered, the charge-up capacitor 34 is charged using an external power source different from the power source of the semiconductor integrated circuit. As a result, an external connection terminal for connecting the external power supply to the semiconductor integrated circuit is required, which causes problems such as an increase in the number of components used and an increase in the number of external connection terminals. .
[0006]
Secondly, in the conventional boosting device, the voltage of the charging power supply 33 is stored in the charge-up capacitor 34 as it is, and this is added to the voltage of the reference power supply 36 to generate the boosted voltage. The boosted voltage causes a voltage fluctuation twice as large as these two power supply voltages, and the boosted voltage is weak against the power supply voltage fluctuation. Therefore, in order to prevent a decrease in the drive capability of the transmission gate regardless of such power supply voltage fluctuations, it is necessary to design so that the output voltage does not become insufficient regardless of the fluctuations. It is necessary to ensure a large margin, and problems such as insufficient breakdown voltage in the transmission gate transistor become more severe.
[0007]
Thirdly, as described above, in the conventional boosting device, the charge-up capacitor 34 is charged by an external power supply different from the power supply of the semiconductor integrated circuit, so that the charge-up capacitor 34 is required. Specification such as withstand voltage cannot be specified. Therefore, conventionally, the charge-up capacitor 34 used as the charge pump is generally also externally attached, and there are further problems such as an increase in the number of components used and an increase in the number of external connection terminals. End up.
[0008]
The present invention has been made to solve the above-described problems, and can generate a boosted voltage within an appropriate voltage range while being configured using elements in a semiconductor integrated circuit. It is an object of the present invention to obtain a boosting device that reduces the number of attached parts and the number of external connection terminals and does not cause a problem of insufficient withstand voltage of a transistor in a transmission gate to which an output voltage is supplied.
[0009]
[Means for Solving the Problems]
A boosting device according to the present invention is a boosting device that outputs a boosted voltage having a voltage higher than a power supply voltage from an output terminal by using an accumulated voltage accumulated in a capacitor, and charging by connecting both terminals of the capacitor to a power supply. Discharging means for electrically connecting and discharging both terminals of the capacitor after charging; and output means for connecting the low voltage side terminal of the discharged capacitor to the power source and connecting the high voltage side terminal to the output terminal Are provided.
[0010]
The booster according to the present invention includes a capacitor, a first transistor that connects one terminal of the capacitor to the high voltage side of the power supply, a second transistor that connects the other terminal of the capacitor to the low voltage side of the power supply, A plurality of diodes connected in series and a third transistor for connecting the anode of the uppermost diode to the high-voltage side of the power source, and the cathode of the lowermost diode connected to the other terminal of the capacitor A fourth transistor that connects the other terminal of the capacitor to the high-voltage side of the power supply, an output terminal, a fifth transistor that connects the one terminal of the capacitor and the output terminal, The second transistor is turned on, and then the first transistor and the third transistor are turned on. Finally those and a fourth transistor and a fifth control circuit for the transistors to an ON operation.
[0011]
In the booster according to the present invention, the diode unit includes a sixth transistor that connects an anode of a diode other than the lowermost diode to the high voltage side of the power supply, and the control circuit controls the third transistor and the sixth transistor according to the output voltage. One of the transistors is selected and turned on.
[0012]
The booster according to the present invention includes a first back gate transistor that connects the back gate of the first transistor to the high voltage side of the power source, and a second back gate transistor that connects the back gate of the fifth transistor to the high voltage side of the power source. The provided control circuit turns off the first back gate transistor and the second back gate transistor when the fourth transistor and the fifth transistor are turned on.
[0013]
The booster according to the present invention includes a seventh transistor that connects the output terminal to the high-voltage side of the power supply, and an eighth transistor that connects the output terminal to the low-voltage side of the power supply, and the control circuit turns on the fifth transistor. When not operating, the seventh transistor or the eighth transistor is turned on.
[0014]
The booster according to the present invention includes a third back gate transistor that connects the back gate of the seventh transistor to the high voltage side of the power source, and the control circuit turns on the fourth transistor and the fifth transistor when the fourth transistor and the fifth transistor are turned on. 3 The back gate transistor is turned off.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described below.
Embodiment 1 FIG.
1 is a circuit diagram showing a configuration of a booster according to Embodiment 1 of the present invention. This circuit is configured as a part of a semiconductor integrated circuit in which MOS transistors are integrated. In the figure, 1 is a high voltage side power line connected to the high voltage side of a power supply (not shown) of the semiconductor integrated circuit, 2 is a ground line connected to the low voltage side of the power source, and 3 is generally the above high voltage side power line 1. A reference voltage line 4 connected to the capacitor 4 is a capacitor, 5 is a PchMOS transistor (first transistor, charging means, discharging means) for connecting one terminal A of the capacitor 4 and the reference voltage line 3, and 6 is a capacitor 4. NchMOS transistor (second transistor, charging means) for connecting the other terminal B and the low-voltage power supply line 2, 7 is a diode (diode, discharging means) whose cathode is connected to the other terminal B of the capacitor 4, 8 Is a diode having a cathode connected to the anode of the diode 7 (diode, discharge means), and 9 is a diode connected to the anode of the diode 8. A PchMOS transistor (third transistor, discharge means) connecting the reference voltage line 3, 10 is a PchMOS transistor (sixth transistor, discharge means) connecting the anode of the diode 7 and the boost reference voltage line 3, and 11 is a boost reference. PchMOS transistor (fourth transistor, output means) for connecting the voltage line 3 and the other terminal B of the capacitor 4, 12 is an output terminal, 13 is a PchMOS transistor for connecting one terminal A of the capacitor 4 and the output terminal 12 (Fifth transistor, output means).
[0016]
Reference numeral 14 denotes a Pch MOS transistor (seventh transistor) that connects the output terminal 12 and the high-voltage power supply line 1, and 15 denotes an Nch MOS transistor (eighth transistor) that connects the output terminal 12 and the ground line 2.
[0017]
Reference numeral 16 denotes a PchMOS transistor (first back gate transistor) disposed between the back gate of the PchMOS transistor 5 and the boost reference voltage line 3, and reference numeral 17 denotes between the back gate of the PchMOS transistor 13 and the high voltage side power supply line 1. A PchMOS transistor (second back gate transistor) 18 is provided between the back gate of the PchMOS transistor 14 and the high-voltage power supply line 1 (third back gate transistor).
[0018]
Reference numeral 19 denotes a control circuit for controlling the gate voltage of these 11 MOS transistors 5, 6, 9,..., 11, 13,.
[0019]
FIG. 2 is a cross-sectional view showing the structure and electrical connection relationship of the PchMOS transistor of the semiconductor integrated circuit according to the first embodiment of the present invention. 2A shows a normal PchMOS transistor, and FIG. 2B shows the PchMOS transistor 5, the PchMOS transistor 13, and the PchMOS transistor 14. In these figures, 20 is a P (−) semiconductor substrate, 21 is an N (−) well (back gate) formed in the P (−) semiconductor substrate 20 and serves as a back gate, and 22 is this N (−). A P (+) semiconductor layer formed in the well 21, 23 is a P (+) semiconductor layer formed in the N (−) well 21 and separated from the P (+) semiconductor layer 22, and 24 is P A gate insulating layer 25 is stacked on the P (−) semiconductor substrate 20 between the (+) semiconductor layer 22 and the P (+) semiconductor layer 23, 25 is a gate electrode stacked on the gate insulating layer 24, 26 Is a source electrode stacked on the P (+) semiconductor layer 22, 27 is a drain electrode stacked on the P (+) semiconductor layer 23, and 28 connects the N (−) well 21 and the high-voltage power supply line 1. This is a back gate transistor. Note that the P (−) semiconductor substrate 20 is grounded to the ground level, and in a general PchMOS transistor, the N (−) well 21 is directly connected to the high-voltage side power supply line.
[0020]
In FIG. 5B, if the back gate transistor 28 is in the ON state, the N (−) well 21 is connected to the high voltage side power supply line 1 in the same manner as a normal PchMOS transistor. An inversion region is formed between the P (+) semiconductor layer 22 and the P (+) semiconductor layer 23 according to the applied voltage, and a current flows between the source electrode 26 and the drain electrode 27.
[0021]
Next, the operation will be described.
PchMOS transistor 16, PchMOS transistor 17 and PchMOS transistor 18 provided as back gate transistor 28 are controlled to be turned on, and PchMOS transistor 5, PchMOS transistor 13 and PchMOS transistor 14 can operate in the same manner as a normal PchMOS transistor. Then, the control circuit 19 first turns on the PchMOS transistor 5 and the NchMOS transistor 6. As a result, the voltage of the boost reference voltage line 3 and the voltage of the ground line 2 are applied to both ends of the capacitor 4, and the capacitor 4 is charged up to the voltage difference so that the one terminal A side becomes a positive side ( This is the charging process.
[0022]
Next, the control circuit 19 turns off the NchMOS transistor 6 and turns on either the PchMOS transistor 9 or the PchMOS transistor 10. When the PchMOS transistor 9 is turned on, a connection state in which two diodes 7 and 8 are connected in series is formed between the boost reference voltage line 3 and the other terminal B of the capacitor 4. The charging voltage of the capacitor 4 is lowered to the sum of the threshold values of the two diodes 7 and 8. When the PchMOS transistor 10 is turned on, a connection state is formed in which one diode 7 is connected in series between the boost reference voltage line 3 and the other terminal B of the capacitor 4. The charging voltage of 4 is reduced to the threshold voltage of the one diode 7 (discharging process).
[0023]
Finally, the control circuit 19 turns off the PchMOS transistor 5, the PchMOS transistor 9, and the PchMOS transistor 10, and turns on the PchMOS transistor 11 and the PchMOS transistor 13. As a result, the capacitor 4 charged to a voltage that is an integral multiple (here, 1 or 2) of the threshold value of the diodes 7 and 8 has its low voltage side terminal B connected to the boost reference power supply line 3 and a high voltage. The side terminal A is connected to the output terminal 12, and a voltage obtained by adding the charging voltage of the capacitor 4 to the voltage of the boost reference power supply line 3 is applied to the output terminal 12.
[0024]
At this time, the control circuit 19 turns off the Pch MOS transistor 16, the Pch MOS transistor 17, and the Pch MOS transistor 18. As a result, the voltage of the output terminal 12 is higher than the voltage of the back gate (N (−) well 21) of the PchMOS transistor 5, the PchMOS transistor 13, and the PchMOS transistor 14. The back gate (N (−) well 21) can be electrically insulated, and the gate electrode 25 to the back gate (N (−) well 21) in these transistors 5, 13, and 14. Current does not flow (output processing).
[0025]
The control circuit 19 turns on the PchMOS transistor 14 to output the voltage of the high-voltage power supply line 1 from the output terminal 12 or turns on the NchMOS transistor 15 to output the voltage of the ground line 2 from the output terminal 12. Various controls connected to the output terminal 12 can be performed by switching these three types of voltages.
[0026]
FIG. 3 is a circuit diagram showing a configuration of a transmission gate to which such a booster can be suitably applied. In the figure, 29 is an NchMOS transistor, 30 is a PchMOS transistor whose source and drain are connected to the NchMOS transistor 29, 31 is an input / output terminal to which the source is connected, and 32 is an input / output terminal to which the drain is connected. .
[0027]
For example, when a sufficient power supply voltage can be secured, the input / output can be switched by switching the voltage between the voltage of the high-voltage power supply line 1 and the voltage of the ground line 2 and switching the gate voltages of these two transistors 29 and 30. Regardless of the voltage at the terminals 31 and 32, at least one of the transistors 29 and 30 can be completely turned on to transmit the voltage from one to the other.
[0028]
Even when a sufficient voltage cannot be secured, the voltage is switched between the boosted voltage obtained by adding the charging voltage of the capacitor 4 to the voltage of the boosted reference power supply line 2 and the voltage of the ground line 3. By switching the gate voltages of the two transistors 29 and 30, no matter what the voltage of the input / output terminals 31 and 32 is, the at least one of the transistors 29 and 30 is completely turned on to change from one to the other. Voltage can be transmitted.
[0029]
Since the charging voltage of the capacitor 4 is limited to a voltage equal to or less than two diodes, the voltage level that causes a shortage of withstand voltage in the transistors 29 and 30 of the transmission gate is much higher than the conventional voltage level. Accordingly, the allowable power supply voltage range can be expanded correspondingly, and a sufficient range can be secured as the allowable power supply voltage range of the semiconductor integrated circuit.
[0030]
As described above, in the semiconductor integrated circuit that does not use the booster, the minimum power supply voltage can be reduced only within a range in which the voltage necessary for controlling the transmission gate can be secured. According to the present invention, the minimum power supply voltage can be reduced without being limited to such a circuit, and an effect of realizing an unprecedented low voltage driving semiconductor integrated circuit can be obtained.
[0031]
In addition, since the charging voltage charged to the capacitor 4 is limited to two threshold values of the diodes 7 and 8 regardless of the power supply voltage used for the charging, the capacitor 4 is charged using the power supply of the semiconductor integrated circuit. In spite of this, a stable boosted voltage can be generated. In addition, since the power source of the semiconductor integrated circuit can be used, the specification of the capacitor 4 can be specified, and the capacitor 4 is integrated with the switching transistors 5, 6, 9,. The effect that it can arrange | position in a circuit and can reduce the number of components used and the number of external connection terminals significantly is acquired.
[0032]
Next, since the diodes 7 and 8 are used to make the charging voltage of the capacitor 4 constant, the boosted voltage is not easily affected by fluctuations in the voltage of the power supply, and the voltage margin of the output voltage is reduced accordingly. As a result, it is possible to obtain an effect that the usable power supply voltage range can be secured by making the above-mentioned insufficient withstand voltage difficult to occur.
[0033]
Furthermore, the magnitude of the boosted voltage can be switched by switching the number of stages of the diodes 7 and 8, so that the shortage of the breakdown voltage of the transmission gate at the time of the high voltage of the power supply is suppressed, while the voltage at the low voltage of the power supply is suppressed. The drive capability of the transmission gate can be prevented from being lowered, and the usable power supply voltage range can be further expanded.
[0034]
Finally, back gate transistors 16,..., 18 are provided between the back gates of the Pch MOS transistor 5, the Pch MOS transistor 13, and the Pch MOS transistor 14 and the boost reference power supply line 3 or the high voltage side power supply line 1, and the control circuit 19 When the PchMOS transistor 11 and the PchMOS transistor 13 are turned on, the back gate transistors 16,..., 18 are turned off, so that the boosted voltage is higher than that of the high-voltage power supply line 1, and these transistors 5, 13 , 14 even when the threshold value of the parasitic diode between the drain and the back gate is exceeded, it is possible to prevent the current from flowing in reverse between the drain and the back gate. Small charge charge in the integrated circuit Even while using a capacitor 4, the effect capable of supplying a stable gate voltage is obtained for each transistor 29 and 30 of the transmission gate.
[0035]
【The invention's effect】
As described above, according to the present invention, in a booster device that outputs a boosted voltage having a voltage higher than the power supply voltage from the output terminal using the stored voltage stored in the capacitor, both terminals of the capacitor are connected to the power supply. Charging means for charging, discharging means for electrically connecting and discharging both terminals of the capacitor after charging, and connecting the low voltage side terminal of the capacitor after discharging to the power source and connecting the high voltage side terminal to the output terminal Output means for reducing the accumulated voltage of the capacitor by discharging, and using this, the boosted voltage can be output.
[0036]
Therefore, even if this boosted voltage is supplied to each transistor of the transmission gate when the power supply voltage is high, the breakdown voltage will not be insufficient, and if the power supply voltage is low, the shortage will be stored in the capacitor. There is an effect that the drive capability of the transmission gate can be prevented from being reduced by compensating with the voltage.
[0037]
Further, since the boosted voltage can be set regardless of the power supply voltage in this way, a desired voltage can be charged to the capacitor while using an IC power supply for a semiconductor integrated circuit as a power supply, and an external power supply is connected. It is possible to reduce the number of external connection terminals. At the same time, when an IC power supply for a semiconductor integrated circuit is used, the basic specifications such as a withstand voltage required for the capacitor can be specified. As a result, the number of external parts and the number of external connection terminals can be further reduced.
[0038]
According to the present invention, the capacitor, the first transistor that connects one terminal of the capacitor to the high voltage side of the power source, the second transistor that connects the other terminal of the capacitor to the low voltage side of the power source, and one or more A diode unit in which a diode connected in series and an anode of the uppermost diode are connected to the high voltage side of the power source, and a cathode of the lowermost diode is connected to the other terminal of the capacitor; A fourth transistor that connects the other terminal of the capacitor to the high-voltage side of the power supply, an output terminal, a fifth transistor that connects the one terminal of the capacitor and the output terminal, and first and second transistors Turn on the transistor, then turn on the first and third transistors, and finally 4 so and a transistor and a fifth transistor control circuit for the on operation, the storage voltage of the capacitor by the diode unit and discharged to a substantially constant voltage, it is possible to output a boosted voltage by using this.
[0039]
Therefore, even if this boosted voltage is supplied to each transistor of the transmission gate when the power supply voltage is high, the breakdown voltage will not be insufficient, and if the power supply voltage is low, the shortage will be stored in the capacitor. There is an effect that the drive capability of the transmission gate can be prevented from being reduced by compensating with the voltage. In particular, since the charging voltage of the capacitor is stabilized by one or a plurality of diodes connected in series, the boosted voltage is not easily affected by voltage fluctuations of the power supply, and this fluctuation margin is reduced by that much, thereby further increasing the voltage. There are effects such as lowering the voltage and expanding the allowable range of power supply.
[0040]
Further, since the boosted voltage can be set regardless of the power supply voltage in this way, a desired voltage can be charged to the capacitor while using an IC power supply for a semiconductor integrated circuit as a power supply, and an external power supply is connected. It is possible to reduce the number of external connection terminals. At the same time, when an IC power supply for a semiconductor integrated circuit is used, the basic specifications such as a withstand voltage required for the capacitor can be specified. As a result, the number of external parts and the number of external connection terminals can be further reduced.
[0041]
According to this invention, the diode unit includes the sixth transistor that connects the anode of the diode other than the lowermost diode to the high-voltage side of the power supply, and the control circuit controls the third transistor and the sixth transistor according to the output voltage. Since one of them is selected to be turned on, for example, when the power supply voltage of the semiconductor integrated circuit is high, the sixth transistor is turned on to suppress the boosted voltage, and conversely, when the power supply voltage of the semiconductor integrated circuit is low The third transistor is turned on to increase the boosted voltage, thereby preventing the transistor from having insufficient breakdown voltage at the transmission gate and preventing the drive capability of the transmission gate from being lowered at a low voltage. There is an effect that the allowable range can be expanded.
[0042]
According to the present invention, the first back gate transistor for connecting the back gate of the first transistor to the high voltage side of the power source and the second back gate transistor for connecting the back gate of the fifth transistor to the high voltage side of the power source are provided. When the control circuit turns on the fourth transistor and the fifth transistor, the first back gate transistor and the second back gate transistor are turned off, so that a voltage higher than the high voltage side of the power supply is applied to the output terminal. In spite of such a configuration, it is possible to prevent current from flowing between the drain and back gate of these transistors. Therefore, even if a capacitor having a small capacitance in the semiconductor integrated circuit is used, the output voltage can be stabilized.
[0043]
According to the present invention, the seventh transistor that connects the output terminal to the high voltage side of the power supply and the eighth transistor that connects the output terminal to the low voltage side of the power supply are provided, and the control circuit does not turn on the fifth transistor. In this case, since the seventh transistor or the eighth transistor is turned on, it is possible to output a voltage other than the boosted voltage, thereby reliably turning on / off the transistor used for the transmission gate. There is an effect that can.
[0044]
According to the present invention, the third back gate transistor for connecting the back gate of the seventh transistor to the high voltage side of the power supply is provided, and when the control circuit turns on the fourth transistor and the fifth transistor, the third back gate transistor is provided. Since the gate transistors are turned off, current flows between the drain and back gate of these transistors even though the output terminal is configured to apply a higher voltage than the high voltage side of the power supply. Can be prevented. Therefore, even if a capacitor having a small capacitance in the semiconductor integrated circuit is used, the output voltage can be stabilized.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration of a booster according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing the structure and electrical connection relationship of a PchMOS transistor of a semiconductor integrated circuit according to a first embodiment of the present invention.
FIG. 3 is a circuit diagram showing a configuration of a transmission gate to which such a booster can be suitably applied.
FIG. 4 is a circuit diagram showing a configuration of a conventional boosting device.
[Explanation of symbols]
1 high-voltage side power supply line, 2 ground line, 3 boost reference voltage line, 4 capacitor, 5 Pch MOS transistor (first transistor, charging means, discharging means), 6 Nch MOS transistor (second transistor, charging means), 7 diode (diode) , Discharge means), 8 diode (diode, discharge means), 9 Pch MOS transistor (third transistor, discharge means), 10 Pch MOS transistor (sixth transistor, discharge means), 11 Pch MOS transistor (fourth transistor, output means), 12 output terminals, 13 Pch MOS transistor (fifth transistor, output means), 14 Pch MOS transistor (seventh transistor), 15 Nch MOS transistor (eighth transistor), 16 Pch MOS transistor First back gate transistor), 17 Pch MOS transistor (second back gate transistor), 18 Pch MOS transistor (third back gate transistor), 19 control circuit, 20 P (−) semiconductor substrate, 21 N (−) well (back gate) , 22P (+) semiconductor layer, 23P (+) semiconductor layer, 24 gate insulating layer, 25 gate electrode, 26 source electrode, 27 drain electrode, 28 back gate transistor, 29 Nch MOS transistor, 30 Pch MOS transistor, 31 I / O terminal 32 Input / output terminals.

Claims (6)

In a booster that outputs a boosted voltage that is larger than the power supply voltage from the output terminal using the stored voltage stored in the capacitor,
Charging means for charging by connecting both terminals of the capacitor to a power source;
Discharging means for electrically connecting and discharging both terminals of the capacitor after charging;
A step-up device comprising: an output means for connecting a low-voltage side terminal of the capacitor after discharge to the power source and connecting the high-voltage side terminal to an output terminal. A capacitor,
A first transistor connecting one terminal of the capacitor to the high voltage side of the power supply;
A second transistor connecting the other terminal of the capacitor to the low voltage side of the power supply;
One or more diodes connected in series and a third transistor that connects the anode of the uppermost diode to the high-voltage side of the power supply, and the cathode of the lowermost diode connected to the other terminal of the capacitor Unit,
A fourth transistor connecting the other terminal of the capacitor to the high voltage side of the power supply;
An output terminal;
A fifth transistor connecting one terminal of the capacitor and the output terminal;
And a control circuit that first turns on the first transistor and the second transistor, then turns on the first transistor and the third transistor, and finally turns on the fourth transistor and the fifth transistor. The diode unit includes a sixth transistor that connects the anode of a diode other than the lowermost diode to the high voltage side of the power supply,
3. The boosting device according to claim 2, wherein the control circuit selects one of the third transistor and the sixth transistor in accordance with the output voltage to turn on. A first back gate transistor that connects the back gate of the first transistor to the high voltage side of the power source; and a second back gate transistor that connects the back gate of the fifth transistor to the high voltage side of the power source.
4. The boosting device according to claim 2, wherein when the fourth transistor and the fifth transistor are turned on, the control circuit turns off the first back gate transistor and the second back gate transistor. . A seventh transistor connecting the output terminal to the high voltage side of the power supply;
An eighth transistor for connecting the output terminal to the low voltage side of the power supply;
4. The boosting device according to claim 2, wherein the control circuit turns on the seventh transistor or the eighth transistor when the fifth transistor is not turned on. Providing a third back gate transistor for connecting the back gate of the seventh transistor to the high voltage side of the power supply;
6. The boosting device according to claim 5, wherein the control circuit turns off the third back gate transistor when turning on the fourth transistor and the fifth transistor.

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