JP2001042961A - Voltage boosting device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of external components etc., and to solve the problem of breakdown voltage deficiency of a transistor of a transmission gate by discharging a capacity having been charged, connecting the low-voltage terminal of the capacitor having been discharge to a power source, and the high-voltage terminal to an output terminal. SOLUTION: A control circuit 19 applies the voltage of a voltage boosting reference voltage line 3 and the voltage of a ground line 2 to both the ends of the capacitor 4 and charges the capacitor up to such a voltage difference that the terminal A is positive. Then diodes 7 and 8 are connected in series between the voltage boosting reference voltage line 3 and low-voltage side terminal B, so the charging voltage of the capacitor 4 drops to the sum voltage of the thresholds of the diodes 7 and 8. The capacitor 4 having been charged to a voltage which is an integral multiple of the thresholds of the diodes 7 and 8 applies an output terminal 12 with the voltage obtained by adding the charging voltage of the capacitor 4 to the voltage of the voltage boosting reference voltage line 3 by connecting the low-voltage side terminal B to the voltage boosting reference voltage line 3 and the high-voltage side terminal A to the output terminal 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boosting device for generating and outputting a boosted voltage higher than the high voltage side of a power supply, and more particularly to a boosting device for lowering the minimum operable voltage of a semiconductor integrated circuit. The present invention relates to a step-up device that can be suitably used to prevent a reduction in drive capability of a transmission gate caused by a decrease in voltage.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a configuration of a conventional booster. In the figure, 33 is a charging power source, 34 is a charge-up capacitor, 35 is a holding capacitor, 36
Is a reference power supply, and 37 and 38 are a pair of switching elements for alternately connecting both terminals of the charge-up capacitor 34 to the charge power supply 33 or the holding capacitor 35.
9 is a control circuit for controlling the operation of the pair of switching elements 37 and 38, and 40 is an output terminal.

Next, the operation will be described. Control circuit 39
First, a pair of switching elements 3 are connected so that both terminals of the charge-up capacitor 34 are connected to the charging power supply 33.
7 and 38 to control the charge-up capacitor 3
4 to the voltage of the charging power supply 33. Next, the control circuit 39 controls the pair of switching elements 37 and 38 so as to connect both terminals of the charge-up capacitor 34 to the holding capacitor 35, whereby the holding capacitor 35 is the same as the charge-up capacitor 34. Charge to voltage. By repeating the switching operation of the pair of switching elements 37 and 38 at a predetermined cycle,
The charging voltage of the holding capacitor 35 is maintained at a voltage level where the increased amount of charge supplied to the holding capacitor 35 per unit time and the decreased amount of charge due to the output terminal 40 and natural discharge are balanced. As a result, a boosted voltage of a level obtained by adding the charging voltage of the holding capacitor 35 and the voltage of the reference power supply 36 is output from the output terminal 40.

[0004]

Since the conventional booster is constructed as described above, when the minimum power supply voltage of the semiconductor integrated circuit is lowered, the transmission gate generated with the lowering of the power supply voltage is reduced. When the system is used to prevent a decrease in drive performance, there are the following problems.

First, when the power supply of the semiconductor integrated circuit is used as the charging power supply 33 or the reference power supply 36 in the conventional booster, the power supply of such a semiconductor integrated circuit is from the minimum power supply voltage to the maximum power supply voltage. Up to a usable power supply voltage range, and the booster may output twice the maximum power supply voltage. When such an output voltage is supplied to a transistor forming a transmission gate, a problem such as insufficient withstand voltage of the transistor occurs. Therefore, when the conventional booster is used to prevent the drive capability of the transmission gate from lowering, the charge-up capacitor 34 is charged using an external power supply different from the power supply of the semiconductor integrated circuit. Is generally performed, and as a result, an external connection terminal for connecting the external power supply to the semiconductor integrated circuit is required, which causes problems such as an increase in the number of parts used and an increase in the number of external connection terminals. .

Second, in the conventional booster, the charging power source 3
Charge-up capacitor 34 with the voltage of 3 unchanged
, And this is added to the voltage of the reference power supply 36 to generate a boosted voltage. Therefore, the boosted voltage causes a voltage fluctuation twice as large as those two power supply voltages, and the boosted voltage causes the power supply voltage fluctuation. Would be weaker. Therefore, in order to prevent a reduction in the drive capability of the transmission gate irrespective of such power supply voltage fluctuations, it is necessary to design so that the output voltage does not become insufficient irrespective of the fluctuations. It is necessary to secure a large margin, and the problem such as insufficient withstand voltage of the transistor of the transmission gate becomes more severe.

Third, as described above, in the conventional booster, the charge-up capacitor 34 is charged by an external power supply different from the power supply of the semiconductor integrated circuit. It is not possible to specify required specifications such as withstand voltage. Therefore,
In the related art, it is general that the charge-up capacitor 34 used as the charge pump is also externally attached, and further problems such as an increase in the number of components used and an increase in the number of external connection terminals occur. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and can generate a boosted voltage within an appropriate voltage range while being configured using elements in a semiconductor integrated circuit. As a result, an object of the present invention is to provide a booster that reduces the number of external components and the number of external connection terminals and does not cause a problem of insufficient withstand voltage of a transistor in a transmission gate to which an output voltage is supplied.

[0009]

According to the present invention, there is provided a booster for outputting a boosted voltage having a voltage higher than a power supply voltage from an output terminal by using a storage voltage stored in a capacitor. Charging means for connecting and charging the power supply, a discharging means for electrically connecting both terminals of the charged capacitor to discharge, and connecting a low voltage side terminal of the discharged capacitor to the power supply and a high voltage side. Output means for connecting the terminal to the output terminal.

The booster according to the present invention comprises a capacitor, a first transistor connecting one terminal of the capacitor to a high voltage side of a power supply, and a second transistor connecting the other terminal of the capacitor to a low voltage side of the power supply. A third diode connecting one or more series-connected diodes and the anode of the uppermost diode to the high voltage side of the power supply;
A diode unit having a transistor, the cathode of the lowermost diode being connected to the other terminal of the capacitor; a fourth transistor connecting the other terminal of the capacitor to the high voltage side of the power supply; an output terminal; A fifth transistor connecting one terminal of the first transistor to the output terminal; first, the first transistor and the second transistor are turned on, then the first transistor and the third transistor are turned on, and finally, the fourth transistor is turned on. And a control circuit for turning on the fifth transistor.

In the booster according to the present invention, the diode unit includes a sixth transistor for connecting an anode of a diode other than the lowermost diode to a high voltage side of the power supply,
A control circuit selects one of the third transistor and the sixth transistor in accordance with the output voltage and turns on the third transistor.

The booster according to the present invention comprises a first back gate transistor connecting the back gate of the first transistor to the high voltage side of the power supply, and a second back gate connecting the back gate of the fifth transistor to the high voltage side of the power supply. A transistor, and when the control circuit turns on the fourth transistor and the fifth transistor, the control circuit turns off the first back gate transistor and the second back gate transistor.

A booster according to the present invention is provided with a seventh transistor for connecting an output terminal to a high voltage side of a power supply and an eighth transistor for connecting the output terminal to a low voltage side of the power supply. When the transistor is not turned on, the seventh transistor or the eighth transistor is turned on.

The booster according to the present invention includes a third back gate transistor connecting the back gate of the seventh transistor to the high voltage side of the power supply, and the control circuit turns on the fourth transistor and the fifth transistor. Turns off the third back gate transistor.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a circuit diagram showing a configuration of a booster according to Embodiment 1 of the present invention. This circuit is configured as a part of a semiconductor integrated circuit in which MOS transistors are integrated. In the figure, reference numeral 1 denotes a high-voltage power supply line connected to a high-voltage side of a power supply (not shown) of a semiconductor integrated circuit; 2, a ground line connected to a low-voltage side of the power supply; Reference numeral 4 is a capacitor connected to the booster reference voltage line, 4 is a PchMOS transistor (first transistor, charging means, discharging means) connecting one terminal A of the capacitor 4 and the booster reference voltage line 3, and 6 is a capacitor 4 N-channel MOS transistor (second transistor, charging means) for connecting the other terminal B to the low-voltage side power supply line 2; 7, a diode (diode, discharging means) having a cathode connected to the other terminal B of the capacitor 4; Is a diode (diode, discharging means) having a cathode connected to the anode of the diode 7; PchMOS transistor (third connecting the reference voltage line 3
Transistor, discharging means), 10 are PchMOS connecting the anode of the diode 7 and the boosted reference voltage line 3
A transistor (sixth transistor, discharging means), 11 is a PchMOS transistor (fourth transistor, output means) connecting the boosted reference voltage line 3 and the other terminal B of the capacitor 4, 12 is an output terminal, and 13 is a capacitor 4
PchMO connecting one terminal A of the
This is an S transistor (fifth transistor, output means).

Reference numeral 14 denotes an output terminal 12 and a high voltage side power supply line 1.
PchMOS transistor (seventh transistor) connecting the output terminal 12 and an NchMOS transistor (eighth transistor) connecting the output terminal 12 and the ground line 2
It is.

Reference numeral 16 denotes a P disposed between the back gate of the Pch MOS transistor 5 and the boosted reference voltage line 3.
A chMOS transistor (first back gate transistor) 17 is a PchM transistor 17 provided between the back gate of the PchMOS transistor 13 and the high-voltage power supply line 1.
An OS transistor (second back gate transistor),
Reference numeral 18 denotes a PchMOS transistor (third backgate transistor) provided between the back gate of the PchMOS transistor 14 and the high-voltage power supply line 1.

Reference numeral 19 denotes these 11 MOS transistors 5, 6, 9,..., 11, 13,.
Is a control circuit for controlling the gate voltage of the gate.

FIG. 2 is a sectional view showing a structure and an electrical connection relationship of a PchMOS transistor of the semiconductor integrated circuit according to the first embodiment of the present invention. FIG. 1A shows a normal Pch MOS transistor, and FIG. 1B shows the Pch MOS transistor.
MOS transistor 5, PchMOS transistor 13
And a PchMOS transistor 14. In these figures, reference numeral 20 denotes a P (-) semiconductor substrate, and reference numeral 21 denotes this P (-) semiconductor substrate.
(−) N (−) well (back gate) formed in the semiconductor substrate 20 to be a back gate, 22
(−) P (+) semiconductor layer formed in well 21, 2
Reference numeral 3 denotes a P (+) semiconductor layer formed in the N (-) well 21 so as to be separated from the P (+) semiconductor layer 22;
Is a gate insulating layer laminated on the P (-) semiconductor substrate 20 between the P (+) semiconductor layer 22 and the P (+) semiconductor layer 23, and 25 is a gate electrode laminated on the gate insulating layer 24. , 26 are source electrodes laminated on the P (+) semiconductor layer 22, 27 is a drain electrode laminated on the P (+) semiconductor layer 23, 28 is the N (-) well 21 and the high voltage side power supply line 1, Is a back gate transistor. Incidentally, the P (-) semiconductor substrate 20 is grounded to the ground level, and the N (-) well 21 is directly connected to the high voltage side power supply line in a general PchMOS transistor.

In FIG. 2B, if the back gate transistor 28 is in the ON state, the normal PchMO
Since the N (−) well 21 is connected to the high voltage side power supply line 1 like the S transistor, the P (+) semiconductor layer 22 and the P (+) semiconductor layer 23 are connected according to the voltage applied to the gate electrode 25. An inversion region is formed therebetween, and a current flows between the source electrode 26 and the drain electrode 27.

Next, the operation will be described. PchMOS transistor 16, PchMOS transistor 17, and Pc provided as back gate transistor 28
By controlling the hMOS transistor 18 to the on state, Pc
hMOS transistor 5, PchMOS transistor 1
3 and the Pch MOS transistor 14 are replaced with a normal Pch
The control circuit 19 first sets the PchMOS transistor 5 and the NchMOS transistor 6 to the ON state after setting the operation state similar to the MOS transistor. As a result, the voltage of the boost reference voltage line 3 and the voltage of the ground line 2 are applied to both ends of the capacitor 4, and the capacitor 4 is charged up to the voltage difference such that the one terminal A is on the positive side ( This is the charging process).

Next, the control circuit 19 turns off the NchMOS transistor 6 and turns on one of the PchMOS transistor 9 and the PchMOS transistor 10. When the PchMOS transistor 9 is turned on, the boost reference voltage line 3
A connection state in which two diodes 7 and 8 are connected in series is formed between the capacitor 4 and the other terminal B of the capacitor 4, so that the charging voltage of the capacitor 4 is equal to the sum of the threshold values of the two diodes 7 and 8. Voltage. Also, Pch
When the MOS transistor 10 is turned on, a connection state in which one diode 7 is connected in series between the boosted reference voltage line 3 and the other terminal B of the capacitor 4 is formed. The charging voltage decreases to the threshold voltage of the one diode 7 (discharge processing).

Finally, the control circuit 19 includes a PchMOS transistor 5, a PchMOS transistor 9, a PchM
The OS transistor 10 is turned off and the Pch
The MOS transistor 11 and the PchMOS transistor 13 are turned on. As a result, the capacitor 4 charged to an integral multiple (here, 1 or 2 times) of the threshold value of the diodes 7 and 8 has its low-voltage side terminal B connected to the boost reference power supply line 3 and The side terminal A is connected to the output terminal 12 and the boost reference power supply line 3
Is applied to the output terminal 12.

At this time, the control circuit 19 controls the PchMO
The S transistor 16, PchMOS transistor 17, and PchMOS transistor 18 are turned off.
Thereby, the PchMOS transistor 5, the PchMOS
Transistor 13 and PchMOS transistor 14
The voltage of the output terminal 12 is higher than the voltage of the back gate (N (−) well 21).
1) can be in an electrically insulated state. In these transistors 5, 13, and 14, the gate electrode 2
No current flows from the back gate 5 to the back gate (N (−) well 21) (output processing).

The control circuit 19 turns on the PchMOS transistor 14 to output the voltage of the high-voltage power supply line 1 from the output terminal 12, or turns on the NchMOS transistor 15 to turn on the ground line 2 from the output terminal 12. A voltage can be output, and these three types of voltages can be switched to perform various controls connected to the output terminal 12.

FIG. 3 is a circuit diagram showing a configuration of a transmission gate to which such a booster can be suitably applied. In the figure, 29 is an NchMOS transistor, 30 is a PchMOS transistor whose source and drain are connected to the NchMOS transistor 29, 31 is an input / output terminal to which the source is connected, 32
Is an input / output terminal to which the drain is connected.

For example, if a sufficient power supply voltage can be secured, the voltage is switched between the voltage of the high-voltage power supply line 1 and the voltage of the ground line 2 to exchange the gate voltages of these two transistors 29 and 30. Regardless of the voltage of the input / output terminals 31, 32, at least one of the transistors 29, 30 can be completely turned on to transmit the voltage from one to the other.

Further, even in the case where a sufficient voltage cannot be secured, the voltage between the boosted voltage obtained by adding the charging voltage of the capacitor 4 to the voltage of the boosted reference power supply line 2 and the voltage of the ground line 3 is obtained. By switching and exchanging the gate voltages of these two transistors 29 and 30,
Whatever the voltage of the input / output terminals 31, 32, at least one of the transistors 29, 30 can be completely turned on to transmit the voltage from one to the other.

Since the charging voltage of the capacitor 4 is limited to a voltage equal to or less than two diodes, the voltage level at which the transistors 29 and 30 of the transmission gate cause insufficient withstand voltage is much higher than the conventional one. The power supply voltage range can be expanded accordingly, and the allowable power supply voltage range can be expanded accordingly, and a sufficient range can be secured as the allowable power supply voltage range of the semiconductor integrated circuit.

As described above, in a semiconductor integrated circuit that does not use a booster, the minimum power supply voltage can be reduced only within a range in which a voltage necessary for controlling a transmission gate can be secured. According to the first embodiment, it is possible to reduce the minimum power supply voltage without being limited to such a circuit, and to obtain an effect of realizing a semiconductor integrated circuit driven at a lower voltage than ever before.

Moreover, the charging voltage charged in the capacitor 4 is limited to two thresholds of the diodes 7 and 8 regardless of the power supply voltage used for the charging. A stable boosted voltage can be generated despite charging. In addition, since the power supply of the semiconductor integrated circuit can be used, the specifications of the capacitor 4 can be specified.
Arranged in the semiconductor integrated circuit together with 6, 9,..., 11, 13 and the like, the effect of greatly reducing the number of parts used and the number of external connection terminals can be obtained.

Next, since the diodes 7 and 8 are used to keep the charging voltage of the capacitor 4 constant, the boosted voltage is less affected by the voltage fluctuation of the power supply, and the voltage of the output voltage is accordingly reduced. The effect is obtained that the margin can be reduced and the above-mentioned shortage of withstand voltage can be further reduced, and the usable power supply voltage range can be secured.

Further, since the magnitude of the boosted voltage can be switched by switching the number of stages of the diodes 7 and 8, it is possible to suppress the occurrence of insufficient withstand voltage of the transmission gate when the power supply is at a high voltage and to reduce the power supply voltage. It is possible to prevent the drive capability of the transmission gate from being lowered at the time of voltage, and to obtain an effect that the usable power supply voltage range can be further expanded.

Finally, the PchMOS transistors 5, P
A back gate transistor 1 is connected between the back gates of the chMOS transistor 13 and the PchMOS transistor 14 and the boost reference power supply line 3 or the high-voltage power supply line 1.
, 18 are provided, and the control circuit 19 is a PchMO
S transistor 11 and PchMOS transistor 1
3 is turned on, the back gate transistors 16,..., 18 are turned off, so that the boosted voltage is higher than the high voltage side power supply line 1, and the drain-back gate of these transistors 5, 13, 14 Even if the threshold value of the parasitic diode between them exceeds the threshold, it is possible to prevent the current from flowing backward between the drain and the back gate, and thus the amount of charge in such a semiconductor integrated circuit. , The transistors 29,
30 can be supplied with a stable gate voltage.

[0035]

As described above, according to the present invention, in a booster that outputs a boosted voltage having a voltage higher than a power supply voltage from an output terminal by using a stored voltage stored in a capacitor, both terminals of the capacitor are connected. Charging means for charging by connecting to a power supply; discharging means for electrically connecting both terminals of the charged capacitor to discharge; connecting a low-voltage terminal of the discharged capacitor to the power supply; And output means for connecting the output terminal to the output terminal, so that the accumulated voltage of the capacitor can be reduced by discharging, and a boosted voltage can be output using this.

Therefore, even if this boosted voltage is supplied to each transistor of the transmission gate when the power supply voltage is high, the shortage of the withstand voltage does not occur, and when the power supply voltage is low, the shortage is reduced. There is an effect that the drive capability of the transmission gate can be prevented from being reduced by supplementing with the storage voltage of the capacitor.

Further, since the boosted voltage can be set irrespective of the power supply voltage, a desired voltage can be charged to the capacitor while using the IC power supply for the semiconductor integrated circuit as the power supply, and the external power supply can be set. There is an effect that external connection terminals for connection can be reduced. At the same time, if an IC power supply for a semiconductor integrated circuit is used, the basic specifications such as the withstand voltage required for the capacitor can be specified. By forming, the number of external parts and the number of external connection terminals can be further reduced.

According to the present invention, a capacitor, a first transistor for connecting one terminal of the capacitor to the high voltage side of the power supply, and a second transistor for connecting the other terminal of the capacitor to the low voltage side of the power supply, A diode having one or more series-connected diodes and a third transistor connecting the anode of the uppermost diode to the high voltage side of the power supply, the cathode of the lowermost diode being connected to the other terminal of the capacitor; Unit and
A fourth transistor for connecting the other terminal of the capacitor to the high voltage side of the power supply; an output terminal; a fifth transistor for connecting one terminal of the capacitor to the output terminal; And a control circuit for turning on the transistors, then turning on the first and third transistors, and finally turning on the fourth and fifth transistors. It discharges to a certain voltage, and can use this to output a boosted voltage.

Therefore, even if the boosted voltage is supplied to each transistor of the transmission gate when the power supply voltage is high, the shortage of the breakdown voltage does not occur, and when the power supply voltage is low, the shortage is reduced. There is an effect that the drive capability of the transmission gate can be prevented from being reduced by supplementing with the storage voltage of the capacitor.
In particular, since the charging voltage of the capacitor is stabilized by one or a plurality of series-connected diodes, the boosted voltage is hardly affected by the voltage fluctuation of the power supply. This has the effect of lowering the voltage and expanding the allowable range of the power supply.

In addition, since the boosted voltage can be set regardless of the power supply voltage, the capacitor can be charged with a desired voltage while using an IC power supply for a semiconductor integrated circuit as a power supply, and an external power supply can be used. There is an effect that external connection terminals for connection can be reduced. At the same time, if an IC power supply for a semiconductor integrated circuit is used, the basic specifications such as the withstand voltage required for the capacitor can be specified. By forming, the number of external parts and the number of external connection terminals can be further reduced.

According to the present invention, the diode unit includes the sixth transistor for connecting the anodes of the diodes other than the lowermost diode to the high voltage side of the power supply, and the control circuit controls the third transistor and the third transistor in accordance with the output voltage. 6
One of the transistors is selected to be turned on. For example, when the power supply voltage of the semiconductor integrated circuit is high, the sixth transistor is turned on to suppress the boosted voltage, and conversely, when the power supply voltage of the semiconductor integrated circuit is low. In this case, the third transistor is turned on to increase the boosted voltage, thereby preventing shortage of the transistor's withstand voltage at the transmission gate and preventing the drive capability of the transmission gate from decreasing at low voltage. There is an effect that the power supply voltage allowable range can be expanded.

According to the present invention, the first back gate transistor connecting the back gate of the first transistor to the high voltage side of the power supply, and the second back gate transistor connecting the back gate of the fifth transistor to the high voltage side of the power supply And when the control circuit turns on the fourth transistor and the fifth transistor, the first back gate transistor and the second back gate transistor are turned off. Therefore, a voltage higher than the high voltage side of the power supply is applied to the output terminal. Is configured to apply
It is possible to prevent a current from flowing between the drain and the back gate of these transistors. Therefore, even if a capacitor having a small capacity in the semiconductor integrated circuit is used as the capacitor, there is an effect that the output voltage can be stabilized.

According to the present invention, the seventh transistor for connecting the output terminal to the high voltage side of the power supply and the eighth transistor for connecting the output terminal to the low voltage side of the power supply are provided. If you do not want to turn on
Since the seventh transistor or the eighth transistor is turned on, it is possible to output a voltage other than the boosted voltage, whereby the transistor used for the transmission gate can be turned on / off reliably. is there.

According to the present invention, the third back gate transistor that connects the back gate of the seventh transistor to the high voltage side of the power supply is provided, and when the control circuit turns on the fourth transistor and the fifth transistor, the third back gate transistor is turned on. Since the third back gate transistor is turned off, a current flows between the drain and the back gate of these transistors despite the fact that a voltage higher than the high voltage side of the power supply is applied to the output terminal. Can be prevented. Therefore, even if a capacitor with a small capacity in a semiconductor integrated circuit is used as a capacitor,
There is an effect that the output voltage can be stabilized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a booster according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure and an electrical connection relationship of a PchMOS transistor of the semiconductor integrated circuit according to the first embodiment of the present invention;

FIG. 3 is a circuit diagram showing a configuration of a transmission gate to which such a booster can be suitably applied.

FIG. 4 is a circuit diagram showing a configuration of a conventional booster.

[Explanation of symbols]

1 high voltage side power supply line, 2 ground line, 3 boost reference voltage line, 4 capacitor, 5 Pch MOS transistor (first transistor, charging means, discharging means),
6 NchMOS transistor (second transistor, charging means), 7 diode (diode, discharging means), 8
Diode (diode, discharge means), 9 PchM
OS transistor (third transistor, discharging means), 1
0 PchMOS transistor (sixth transistor, discharging means), 11 PchMOS transistor (fourth transistor, output means), 12 output terminals, 13 PchM
OS transistor (fifth transistor, output means), 1
4 PchMOS transistor (seventh transistor),
15 NchMOS transistor (eighth transistor), 16 PchMOS transistor (first backgate transistor), 17 PchMOS transistor (second backgate transistor), 18 PchMOS
Transistor (third back gate transistor), 19
Control circuit, 20 P (-) semiconductor substrate, 21 N
(-) Well (back gate), 22P (+) semiconductor layer, 23P (+) semiconductor layer, 24 gate insulating layer, 2
5 gate electrode, 26 source electrode, 27 drain electrode, 28 back gate transistor, 29 NchM
OS transistor, 30 PchMOS transistor,
31 I / O terminal, 32 I / O terminal.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5H420 NA03 NB02 NB25 NE28 5H730 AS04 BB02 DD04 5J056 AA00 BB46 BB52 CC29 DD13 DD28 DD51 DD55 EE03 EE04 KK02

Claims (6)

[Claims] 1. A booster for outputting a boosted voltage having a voltage higher than a power supply voltage from an output terminal by using a storage voltage stored in a capacitor, charging means for connecting both terminals of the capacitor to a power supply for charging, Discharge means for electrically connecting both terminals of the charged capacitor to discharge, and output means for connecting the low voltage side terminal of the discharged capacitor to the power supply and connecting the high voltage side terminal to the output terminal. Booster. 2. A capacitor, a first transistor for connecting one terminal of the capacitor to the high voltage side of the power supply, a second transistor for connecting the other terminal of the capacitor to the low voltage side of the power supply, A diode unit including a series-connected diode and a third transistor for connecting an anode of the uppermost diode to the high voltage side of the power supply, and a cathode of a lowermost diode connected to the other terminal of the capacitor; A fourth transistor for connecting the other terminal of the capacitor to the high voltage side of the power supply; an output terminal; a fifth transistor for connecting one terminal of the capacitor to the output terminal; first and second transistors first Is turned on, then the first transistor and the third transistor are turned on, and finally 4 transistor and the fifth
And a control circuit for turning on the transistor. 3. The diode unit includes a sixth transistor that connects an anode of a diode other than the lowermost diode to a high voltage side of a power supply, and the control circuit controls the third transistor and the sixth transistor according to an output voltage. 3. The step-up device according to claim 2, wherein one of the two is selected to be turned on. 4. A first back gate transistor for connecting a back gate of the first transistor to a high voltage side of a power supply;
A second back gate transistor for connecting a back gate of the fifth transistor to the high voltage side of the power supply; and a control circuit, when the fourth transistor and the fifth transistor are turned on, the first back gate transistor and the second 4. The step-up device according to claim 2, wherein the back gate transistor is turned off. 5. A seventh terminal for connecting an output terminal to a high voltage side of a power supply.
A transistor and an eighth transistor for connecting the output terminal to the low voltage side of the power supply, wherein the control circuit turns on the seventh or eighth transistor when the fifth transistor is not turned on. The boost device according to claim 2 or 3, wherein 6. A third back gate transistor for connecting a back gate of a seventh transistor to a high voltage side of a power supply, wherein the control circuit is configured to turn on the fourth transistor and the fifth transistor when the third transistor is turned on. The booster according to claim 5, wherein the transistor is turned off.