五、發明説明（） 5-1發明領域 (請先閱讀背面之>±'意事項再填寫本頁) 本發明係有關於一種增益玫大器（gain amplifier) 偏壓電路用之控制電路，特別是有關於一種可程式化 (programmable)增益放大器偏壓電路用之控制電路。 5-2發明背景 在可程式化增益放大器偏壓電路所使用之控制電 路中’ 一般是利用一對差動放大器（differential amplifier) 的輸出電壓’控制 PM〇S(p-type Metal Oxide Semiconductor)電晶體的閘極來調整開關的深淺，進而 達到控制可程式化增益放大器電流源所輸出電流大小的 目的。其中P Μ 0 S電晶體的源極電流之大小，會以等比 例的電壓值回授（feed back)到差動對的一個輸人端，藉此 回授機制調整P Μ 0 S電晶體閘極電壓。 經濟部智慧財產局員工消費合作社印製 上述傳統可程式化增益玫大器，其使用時需要搭配 一個電流源，此電流源即為一控制電路，以提供可程式 化增益放大器使用時所需之偏壓電流。參考圖一，上述 傳統控制電路1 0在使用時’其電性偶合到可程式化增益 放大器12，以提供可程式化增益放大器12之偏壓電路 所需之電流。控制電路10中包含運算放大器（operational am pi if ier)1 4 ’其正輸入端是由數位至類比轉換器的輸出 所提供’而其輸出端連接到電晶體1 6的閘極，在傳統的 控制電路1 0中，所使用的電晶體1 6是Ρ Μ O S電晶體。 本紙浪尺度適用中國國家標準（CNS ) Α4規格（210X 297公嫠） 4 2 3 211 A7 B7 五、發明説明（） 請 先 閲 讀 背 ώ 之 注— 意 事 項- 再 填 本 頁 上述的電晶體16之源極除了透過—電阻接VDD 外，並且電性偶合至上述運算放大器14的負輪入端。而 上述電晶體1 6的汲極被電性偶合到第—雙栽子電晶體 1 8的基極，並接著被電性偶合到第二雙载子電晶體 的集極（collector)，而第二雙載子電晶體的射極 (emitter)透過一電阻被電性偶合到電壓Vee’並且第二雙 載子電晶體20的基極（base)電性偶合到第—雙載子電晶 體1 8的射極之後，再被電性偶合到可程式化增益放大器 1 2内，以提供偏壓電流丨D ™ 訂 上述傳統控制電路10中，是以運算放大器卡的差 動放大器輸出電壓控制PM〇S ’而pM〇s的源極電流大 小會以一個比例之電壓回授到運算放大器的負輪入端。 此種傳統的電流控制方式具有下列缺點。首先，回授電 路穩定性問題，必須特別注意以免造成電路不穩定。其 次，傳統的控制電路中的PM0S(電晶體16)要操作在線 性區域（triode region)，此時其通道等效阻抗是—個非線 性參數，若是在製作過程中的PM0S製程條件有偏移 時，則其誤差變大。另外，此種傳統控制電路的電路架 構較為複雜’導致其佈局（Layout)後電路面積較大。 經濟部智慧財產局員工消費合作社印製 5-3發明目的及概述 鑒於上述之發明背景中’可程式化增益放大器令所 需要用到的偏壓電流，皆是由傳統的控制電路所提供， 因為傳統控制電路採用回授控制方式，以控制p M 〇 s門 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X2.97公釐） ^3 21 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明説明（ 關的深淺，進而控制電流源的電流於一定範圍内。然而 因為回授電路穩定性問題，須加注意以避免電路之不穩 定。又因為傳統控制電路中的P Μ 0 S電晶體要操作在線 性區域（tri od e reg i ο η)，此時其通道等效阻抗是一個非線 性參數，容易隨製程條件的偏移，產生輸出電流的誤差。 另外，此種傳統的控制電路之電路架構較為複雜，導致 其佈局所需空間變大。 所以本發明的目的在於：1 .線性且精確地控制所產 生的電流，以準確控制可程式化增益放大器之增益變 化：2.避免因為利用回授電路設計所導致的穩定性問 題；3.避免電阻的製程條件變動而影響到所產生的電流， 所以本發明使用電阻分壓方式求得電流；4.整個控制電 路的溫偏係數小。 根據以上所述之目的，本發明提供了一種控制電 路，係用於提供可程式化增益放大器操作所需之偏壓電 流，本發明的一較佳實施例所提出的控制電路包含下列 元件：參考電壓產生裝置、第一電流產生裝置以及電流 重複裝置。 上述的參考電壓產生裝置的功用在於產生一參考 電壓，以提供第一電流產生裝置偏壓所需。並使第一電 流產生裝置依據參考電壓而於第一電流產生裝置的集極 與射極之間產生第一電流，此第一電流產生裝置之基極 被電性偶合到參考電壓產生裝置，以將參考電壓偶合到 第一電流產生裝置。第一電流產生裝置之射極經由第一 本紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁)V. Description of the invention (1) 5-1 Field of invention (please read the > ± 'notes on the back before filling this page) The present invention relates to a control circuit for a gain amplifier bias circuit In particular, it relates to a control circuit for a programmable gain amplifier bias circuit. 5-2 Background of the Invention In a control circuit used in a programmable gain amplifier bias circuit, 'the output voltage of a pair of differential amplifiers is generally used to control PMOS (p-type Metal Oxide Semiconductor) The gate of the transistor adjusts the depth of the switch, thereby controlling the output current of the programmable gain amplifier current source. Among them, the source current of the P Μ 0 S transistor will be fed back to an input terminal of the differential pair with an equal proportion of the voltage value, thereby adjusting the P MOS transistor by the feedback mechanism. Pole voltage. The consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs printed the above-mentioned traditional programmable gain amplifier, which needs to be matched with a current source when used. This current source is a control circuit to provide the programmable gain amplifier required for use. Bias current. Referring to FIG. 1, when the conventional control circuit 10 is used, it is electrically coupled to the programmable gain amplifier 12 to provide the current required by the bias circuit of the programmable gain amplifier 12. The control circuit 10 includes an operational amplifier (operational am pi if ier) 1 4 'its positive input is provided by the output of a digital-to-analog converter' and its output is connected to the gate of the transistor 16 in the conventional In the control circuit 10, the transistor 16 used is a PM OS transistor. The scale of this paper is in accordance with Chinese National Standard (CNS) A4 specification (210X 297 cm) 4 2 3 211 A7 B7 V. Description of the invention () Please read the back note-notice-then fill in the transistor above on this page 16 In addition to being connected to VDD through a resistor, the source is electrically coupled to the negative input terminal of the operational amplifier 14. The drain of the above transistor 16 is electrically coupled to the base of the first-battery transistor 18, and then is electrically coupled to the collector of the second double-battery transistor, and the first The emitters of the two double-carrier transistors are electrically coupled to the voltage Vee 'through a resistor and the base of the second double-carrier transistor 20 is electrically coupled to the first double-carrier transistor 1 After the emitter of 8 is electrically coupled to the programmable gain amplifier 12 to provide a bias current. D ™ In the conventional control circuit 10 described above, the differential amplifier output voltage of the op amp card is used to control the PM. 〇S ', and the source current of pM〇s will be fed back to the negative input terminal of the operational amplifier with a proportional voltage. This conventional current control method has the following disadvantages. First, the stability of the feedback circuit must be paid special attention to avoid instability. Secondly, the PM0S (transistor 16) in the traditional control circuit needs to operate in the triode region. At this time, the channel equivalent impedance is a non-linear parameter. If the PM0S process conditions are offset during the manufacturing process, As time goes by, the error becomes larger. In addition, the circuit structure of such a conventional control circuit is more complicated ', resulting in a larger circuit area after layout. Printed by the Consumer Property Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs of the People's Republic of China 5-3 The purpose and summary of the invention In view of the above background of the invention, the bias current required by the "programmable gain amplifier" is provided by the traditional control circuit because The traditional control circuit adopts feedback control method to control p M 〇s. The paper size is applicable to Chinese National Standard (CNS) Α4 specification (210X2.97 mm) ^ 3 21 Printed by the Consumers ’Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 Fifth, the description of the invention (the depth of the switch, so that the current of the current source is controlled within a certain range. However, due to the stability of the feedback circuit, care must be taken to avoid the instability of the circuit. Also because of the P Μ 0 S power in the traditional control circuit The crystal should be operated in the linear region (tri od e reg i ο η). At this time, the channel equivalent impedance is a non-linear parameter, and it is easy to produce the error of the output current with the deviation of the process conditions. In addition, this traditional control The circuit architecture of the circuit is relatively complicated, resulting in a large space required for its layout. Therefore, the purpose of the present invention is to: 1. Control the production linearly and accurately Current to accurately control the gain change of the programmable gain amplifier: 2. Avoid the stability problem caused by the use of feedback circuit design; 3. Avoid the process current of the resistor from affecting the generated current, so the present invention The current is obtained using a resistor divider method; 4. The temperature deviation coefficient of the entire control circuit is small. According to the above-mentioned purpose, the present invention provides a control circuit for providing a bias voltage required for the operation of a programmable gain amplifier Current, a control circuit provided by a preferred embodiment of the present invention includes the following components: a reference voltage generating device, a first current generating device, and a current repeating device. The function of the aforementioned reference voltage generating device is to generate a reference voltage to provide The first current generating device is biased, and the first current generating device generates a first current between the collector and the emitter of the first current generating device according to the reference voltage. The base of the first current generating device is Electrically coupled to the reference voltage generating device to couple the reference voltage to the first current generating device. The emitter of the current generating device passes the first paper size. Applicable to China National Standard (CNS) Α4 specification (210X297 mm) (Please read the precautions on the back before filling this page)
- 3 21 A7 B7 五、發明説明（） (請先閲讀背面之注^^項再填寫本頁) 控制電阻被電性偶合到第一電壓，上述的第一電流產生 裝置係為雙載子接面電晶.體（bipolar junction transistor)。 而電流重複裝置係用於作為第一電流產生裝置的 電流鏡（current mirror) ’並且電流重複裝置的第二控制 極被電性偶合到可程式化增益放大器中的電流複製電晶 體。此第一電流產生裝置的集極與電流重複裝置的集極 分別被電性偶合到一組負載電流鏡，使得此負載電流鏡 產生大小與第一電流相同之電流，並流經上述電流重複 裝置的集極與射極之間而成為第一重製電流，此第一重 製電流流經電流重複裝置的集極與射極之間，使得此可 程式化增益放大器中的電晶體產生第二重製電流，第二 重製電流大小與第一重製電流大小成比例，也與第一電 流成比例。 經濟部智慧財產局員工消費合作社印製 其中上述之電流重複裝置係為與第一電流產生裝 置相同製程條件下所製造的雙載子接面電晶體，此第一 重製電流係為構成此電流重複裝置的電晶體之集極電 流，而負載電流鏡係為一對閘極（g a t e)相連接的場效電晶 體（field effect transistor)，此對閘極相連接的電晶體的 閘極被連接到此第一電流產生裝置的集極，以提供此對 場效電晶體產生之電流與上述第一電流相同，並與第一 重製電流相同1此對場效電晶體的其中之一個電晶體之 汲極（drainΗ皮電性偶合到電流重複裝置的集極，而第一 重製電流係用於提供上述可程式化增益放大器操作所需 冬紙張尺度適用中國國家標準（CNS ) Α4規格（210X297公釐} 423 21 1」岫 A7 B7 五、發明説明（） 之偏壓電流。 (請先閎讀背面之注意事項再填寫本頁) 上述的第一電流產生裝置係由NPN型雙載子電晶 體所構成，而上述之電流重複裝置也是由NPN型雙載子 電晶體所構成。其中上述之可程式化增益放大器中電流 .複製電晶體係作為電流鏡，係與電流重複裝置相同製程 條件下所製造的電晶體，並且上述的電流複製電晶體之 基極被連接到此電流重複裝置的基極。而上述之可程式 化增益放大器中電流複製電晶體為 N P N型雙載子電晶 體。上述之可程式化增益放大器中電流複製電晶體之基 極與電流重複裝置之閘極連接之後，被連接電晶體的射 極所連接，並且此射極連接電晶體的集極電性偶合到第 二電壓，其中的第二電壓亦被連接到上述的場效電晶體 之源極。 5-4圖式簡單說明 將後續的說明配合下列圖式，將可以對於本發明的 特徵有更為清楚之了解，其中： 圖一為傳統的可程式化增益放大器偏壓電路用之 控制電路之電路架構圖； 經濟部智慧財產局員工消費合作社印製 圖二為依據本發明的一較佳實施例中，用以提供可 程式化增益放大器偏壓電流所用之控制電路的電路架構 圖； 圖三為依據本發明的一較佳實施例中，用以提供可 程式化增益放大器偏壓電流所用之控制電路中所使用的 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨Ο X 297公釐） 4^3 21 1 ⑷ A7 B7 五、發明説明（） 可變電阻的架構圖之一個實施例； (請先閲讀背面之注意事，項再填寫本頁) 圖四為依據本發明的一較佳實施例中’用以提供可 程式化增益放大器偏壓電流所用之控制電路中’可變電 阻内所使用的開關之架構圖之一個實施例；以及. 圖五為依據本發明的一較佳實施例中，用以提供可 程式化增益放大器偏壓電流所用之控制電路内，當一個 控制訊號傳送到可變電阻内，其產生第一集極電流的電 晶體所連接的射極電阻等效電路圖° 5-5發明詳細說明 由於上述的傳統可程式化增益放大器偏壓電路所 使用之控制電路因為其電路設計本身複雜性缺點，所以 本發明提供一種可程式化增益放大器偏壓電路所使用之 控制電路，避免使用回授電路，以提高電流控制的準確 度，並避免電路本身不穩定之問題。另外，本發明的電 路結構可以避免因為製程條件偏移所導致的誤差，而且 本發明的電路在製程上較為簡單易製作。此皆是相較於 習知技術的優點。 經濟部智慧財產局員工消費合作社印製 本發明提出可程式化增益放大器偏壓電路所使用 之控制電路，該控制電路的作用是要準確地控制可程式 化增益放大器各級偏壓電流，藉由改變增益放大級的偏 壓電流可以達到控制增益的目的。參考圖二，上述控制 電路 3 0在使用時，其電性偶合到可程式化增益放大器 32，以提供可程式化增益放大器32之偏壓電路所需之電 本紙張尺度適用中國國家標準（CNS ) A4規格（2丨Ο X 297公釐}-3 21 A7 B7 V. Description of the invention () (Please read the note ^^ on the back before filling this page) The control resistor is electrically coupled to the first voltage. The first current generating device is a double-carrier connection. Bipolar junction transistor. The current repeating device is used as a current mirror of the first current generating device, and the second control electrode of the current repeating device is electrically coupled to the current replicating electric crystal in the programmable gain amplifier. The collector of the first current generating device and the collector of the current repeating device are electrically coupled to a set of load current mirrors, respectively, so that the load current mirror generates a current having the same magnitude as the first current and flows through the current repeating device. Between the collector and the emitter of the first repeat current, this first reproduced current flows between the collector and the emitter of the current repeating device, so that the transistor in the programmable gain amplifier produces a second Reproduction current, the second reproduction current is proportional to the first reproduction current, and is also proportional to the first current. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, where the above-mentioned current repeating device is a double-carrier junction transistor manufactured under the same process conditions as the first current generating device, and this first re-current is to constitute this current The collector current of the transistor of the repeating device, and the load current mirror is a field effect transistor connected to a pair of gates, and the gates of the transistors connected to the gates are connected The collector of the first current generating device to provide the current generated by the pair of field effect transistors is the same as the first current described above, and is the same as the first reproduced current. One of the pair of field effect transistors The drain electrode is electrically coupled to the collector of the current repeating device, and the first reproduced current is used to provide the above-mentioned programmable gain amplifier operation. The winter paper size is applicable to the Chinese National Standard (CNS) A4 specification (210X297 Mm} 423 21 1 ″ 岫 A7 B7 V. Bias current of the description of the invention (Please read the precautions on the back before filling this page) The above-mentioned first current generating device is The NPN type bipolar transistor is composed of the above-mentioned current repeating device, which is also composed of the NPN type bipolar transistor. The current in the programmable gain amplifier is described above. The replication transistor system is used as a current mirror, which is related to the current. The repeater device is a transistor manufactured under the same process conditions, and the base of the current replication transistor is connected to the base of the current repeater device. The current replication transistor in the programmable gain amplifier described above is an NPN type dual Carrier transistor. After the base of the current replication transistor in the programmable gain amplifier is connected to the gate of the current repeating device, it is connected to the emitter of the connected transistor, and this emitter is connected to the collector of the transistor. It is electrically coupled to the second voltage, and the second voltage is also connected to the source of the field-effect transistor described above. 5-4 Schematic Description Briefly combining the following description with the following figures will provide the features of the present invention. Have a clearer understanding, of which: Figure 1 is a circuit architecture diagram of a control circuit for a conventional programmable gain amplifier bias circuit; Ministry of Economic Affairs Printed by Intellectual Property Bureau employee consumer cooperative Figure 2 is a circuit architecture diagram of a control circuit used to provide a programmable gain amplifier bias current according to a preferred embodiment of the present invention; Figure 3 is a In a preferred embodiment, the paper size used in the control circuit used to provide the programmable gain amplifier bias current is in accordance with the Chinese National Standard (CNS) A4 specification (2 丨 〇 X 297 mm) 4 ^ 3 21 1 ⑷ A7 B7 V. Description of the invention () An example of the structure diagram of the variable resistor; (Please read the notes on the back, and then fill out this page) Figure 4 shows a preferred embodiment according to the present invention. An embodiment of a structural diagram of a switch used in a 'variable resistor in a control circuit for providing a programmable gain amplifier bias current; and FIG. 5 shows a preferred embodiment according to the present invention. To provide a programmable gain amplifier bias current in the control circuit, when a control signal is transmitted to the variable resistor, it generates the first collector current of the emitter connected to the transistor Resistance equivalent circuit diagram ° 5-5 Detailed description of the invention Because of the control circuit used in the conventional programmable gain amplifier bias circuit described above due to the complexity of its circuit design itself, the present invention provides a programmable gain amplifier bias The control circuit used in the circuit avoids the use of feedback circuit to improve the accuracy of current control and avoid the problem of unstable circuit itself. In addition, the circuit structure of the present invention can avoid errors caused by process condition deviations, and the circuit of the present invention is relatively simple and easy to manufacture in the manufacturing process. These are all advantages over the conventional technology. Printed by the Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economics The present invention proposes a control circuit for a bias circuit of a programmable gain amplifier. The function of the control circuit is to accurately control the bias current of the programmable gain amplifier at various levels. The gain can be controlled by changing the bias current of the gain amplifier stage. Referring to FIG. 2, when the control circuit 30 is used, it is electrically coupled to the programmable gain amplifier 32 to provide the electricity required for the bias circuit of the programmable gain amplifier 32. The paper size is in accordance with Chinese national standards ( CNS) A4 size (2 丨 〇 X 297 mm)
A 4 23 21 1 ^ 五、發明説明（） -- 流，此即可程式化增益放大器32所需之操作電流。本發 明在進行電路的實作時，是以雙載子互補式金氧半導體 (BKMOS)製程來實現電路。其中第—電晶體^的基極 偏壓是由溫偏控制良好的參考電壓產生裝置34所提供。 在本發明的一較佳實施例中，參考電壓產生裝置34 是一個參考電壓源（Bandgap Reference)，用以產生一不 太隨溫度變化而改變的穩定電壓。在本發明的—較佳實 施例中，參考電壓產生裝置34所產生的電壓大約為]2 伏特。而且第一電晶體cm的基極被電性偶合到參考電壓 產生裝置3 4 ’使得第一電晶體〇 1的基_射級接面因順偏 (forward biased)而導通，而第一電晶體Q1的射極 (Emitter)經由第一射極電阻被電性偶合到射極電壓 VEE。第一電晶體Q1的集極（C0||ect〇r)被電性偶合到第 一金氧半電晶體（Metal Oxide Semiconductor : M0S)P1 的汲極（drain)與閘極（gate)，而第一金氧半電晶體ρι的 源極（source)被電性偶合到電壓Vdi^同時第—金氧半電 晶體P1的閘極被電性偶合到第二金氧半電晶體p 2的閘 極而產生其鏡像電流（mf「rorecl current) -另外，第二金 氧半電晶體P 2的源極被電性偶合到電壓v D D，同時第二 金氧半電晶體P 2的；及極被電性偶合到第二電晶體q 2的 集極以及第二電晶體Q3的基極。 其中第三電晶體Q 3的集極被連接到電壓v D D,作用 在於提高緊接可程式化增益放大器内的電流源之電流增 益，而第二電晶體Q2之射極經過第二射極電阻Re2被電 尽紙張尺度適用中國國家標準（CNS ) A4規格（2IOX297公釐） (請先閲讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局負工消貪合作社印製 ^3 21 A7 B7 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 性偶合到電壓 vEE是作為增益放大器内增益級偏壓電流 的鏡相電流源。第三電晶體Q 3的射極被電性偶合到第二 電晶體Q 2的基極，並且也被電性偶合到可程式化增益放 大器32中的第四電晶體Q4的基極，而第四電晶體Q4 的射極經由第三射極電阻Re3被電性偶合到電壓Vee。其 中上述的第四電晶體Q4及第三射極電阻RE3並非本發明 的控制電路之一部份，只是在可程式化增益放大器 32 中，用以配合本發明的一較佳實施例之電路，以取得可 程式化增益放大器32所需之操作電流。在本發明的一較 佳實施例中，所使用的第一射極電阻R E 1特性上類似一 可變電阻。調整第一射極電阻R e !的大小，可以控制第 一電晶體集極電流丨c 1的大小。 而第一電晶體Q1的集極電流丨透過第一金氧半 電晶體 P1及第二金氧半電晶體 P 2所形成的電流鏡 (C u「「e n t M i r ro r)，得到在第二電晶體Q 2上的鏡橡電流， 此鏡像電流值與第一電晶體Q 1的集極電流丨c 1大小相 同。同時第二電晶體Q2與第三電晶體Q3為提供可程式 化增益放大器的偏壓電流所需的鏡像電流源。 經濟部智慧財產局員工消費合作社印製 本發明的控制電路3 0可以提供可程式化增益放大 器所需的偏壓電流，並且藉著精確調整射極電阻R E 1而. 間接控制偏壓電流大小，繼而達到控制可程式化增益放 大器增益的目的。因為本發明的控制電路並不使用回授 電路，而且以電阻分壓的方式控制電流所以可以產生精 確而不受製程影響的電流。 木紙張尺度適用中國國家標準（CNS ) A4規格（2丨Ο X 297公釐） 4 2 3 21 1 經濟部智慧財產局員工消費合作社印製 A7 B7____五、發明説明（） 在本發明的一較佳實施例中，第一金氧半電晶體P 1 與第二金氧半電晶體P2是由P通道金氧半場效電晶體（P channel Metal Oxide Semiconductor transistor ： PMOS) 所構成’而第一電晶體Q1、第二電晶體Q2、第三電晶 體Q3以及第四電晶體Q4都是由雙載子電晶體（bipoiar transistor)所構成的 NPN型電晶體。然而就本發明而 言’所使用的電晶體類型並不限定於上述幾種，只要可 以達成電流鏡的功能，所使用的電晶體種類可以用其他 種類電晶體替代’並且將電晶體連接成電流鏡的方式， 亦不限定於上述實施例所列舉者，只要能將電晶體連接 以造成電流鏡功能者’其連接方式皆可以運用於本發明 中。並且本發明的一較佳實施例中’參考電壓產生裝置 34所產生的電壓雖為彳.2伏特，但是若有需要可以提供 不同的參考電壓。 在本發明的一較佳實施例中’第_射極電阻RE1被 被設計為内含N個電阻器（Rr R2、…Rn)、個開關 (SW!、SW2、... sWu)以及一個解碼器（dec〇de「）40。在 本發明的一較佳實施例中，用以構成此N的電阻者，是 利用製程控制較精確、溫偏係數較小的複晶矽電阻器來 製成，本發明所提出的可以調整電阻值大小之第一射極 電阻Ru之一個較佳實施例的電路圖如圖三所示。其中 第一射極電阻中的N個電阻器是互相串接的，並且每兩 個電阻器之間就有一個開關，開關的方式是將二個電阻 的連接處連接到地或是連接到開路狀態。 10 本紙張尺度適用中國國家標準（CNS ) A4規格（210X 297公釐） —丨1——αΐ (請先閱讀背面之注意事項再填寫本頁) 訂_ 束 4^321 1 A7 _B7__ 五、發明説明（） (請先閲讀背面之注意事項再填寫本頁) 參考圖三，第一電阻器R1第一端連接到第一電晶 體Q1的射級（圖二中），第一電阻器R，其第二端連接到 第二電阻器R2的第一端，並連接到第一開關SWi的第一 端T1。而第一開關SWi的第二端T2是固定接地，並且 第一開關S W1的地三端T 3是電性偶合到解碼器4 0的複 數條控制線的其中之一。同理第二電阻器R2第一端連接 到第一電阻器 Ri的第二端，並且連接到第一開關 SW; 的第一端T1，而第二電阻器 R2其第二端連接到第三電 阻器R3的第一端，並連接到第二開關SW2的第一端T1。 而第二開關SW2的第二端T2是固定接地，並且第二開 關S W 2的第三端T 3是電性偶合到解碼器4 0的複數條控 制線的其中之一。以此類推，第N個電阻器R n第一端連 接到第N -1個電阻器R N -1的第二端，並且連接到第（N -1 ) 個開關S W N _ 1的第一端T1，而第N個電阻器R N其第二 端連接到電壓νΕε (圖二中）。而第（N-1〉個開關SWn — !的 第二端T2是固定接地，並且第（N-1)個開關SWN_i的第 三端T 3是電性偶合到解碼器4 0的複數條控制線的其中 之一，其連接方式如圖三所示。 經濟部智慧財產局員工消費合作社印製A 4 23 21 1 ^ V. Description of the invention ()-current, which can program the operating current required by the gain amplifier 32. When the present invention is implemented in a circuit, the circuit is implemented by a double-carrier complementary metal-oxide-semiconductor (BKMOS) process. The base bias voltage of the first transistor ^ is provided by the reference voltage generating device 34 with good temperature deviation control. In a preferred embodiment of the present invention, the reference voltage generating device 34 is a reference voltage source (Bandgap Reference) for generating a stable voltage that does not change much with temperature. In the preferred embodiment of the present invention, the voltage generated by the reference voltage generating device 34 is approximately 2 volts. Moreover, the base of the first transistor cm is electrically coupled to the reference voltage generating device 3 4 ′, so that the base-emitter junction of the first transistor 01 is turned on due to forward bias, and the first transistor is turned on. The emitter of Q1 is electrically coupled to the emitter voltage VEE via the first emitter resistance. The collector (C0 || ect〇r) of the first transistor Q1 is electrically coupled to the drain and gate of the first Metal Oxide Semiconductor (M0S) P1, and The source of the first metal-oxide semiconductor transistor p1 is electrically coupled to the voltage Vdi ^ and the gate of the first metal-oxide semiconductor transistor P1 is electrically coupled to the gate of the second metal-oxide semiconductor transistor p 2 And its mirror current (mf "rorecl current)-In addition, the source of the second metal-oxide-semiconductor P 2 is electrically coupled to the voltage v DD, while the second metal-oxide-semiconductor P 2; It is electrically coupled to the collector of the second transistor q 2 and the base of the second transistor Q3. The collector of the third transistor Q 3 is connected to the voltage v DD to improve the programmable gain immediately after The current gain of the current source in the amplifier, and the emitter of the second transistor Q2 is exhausted through the second emitter resistor Re2. The paper size applies the Chinese National Standard (CNS) A4 specification (2IOX297 mm) (Please read the back Please fill in this page for the matters needing attention.) Order printed by the Intellectual Property Bureau of the Ministry of Economic Affairs. Explanation () (Please read the precautions on the back before filling this page) The coupling to voltage vEE is a mirror-phase current source as the gain stage bias current in the gain amplifier. The emitter of the third transistor Q 3 is electrically Is coupled to the base of the second transistor Q 2 and is also electrically coupled to the base of the fourth transistor Q4 in the programmable gain amplifier 32, and the emitter of the fourth transistor Q4 is passed through the third emitter The resistor Re3 is electrically coupled to the voltage Vee. The above-mentioned fourth transistor Q4 and the third emitter resistor RE3 are not part of the control circuit of the present invention, but are included in a programmable gain amplifier 32 to cooperate with this A circuit of a preferred embodiment of the invention is used to obtain the operating current required by the programmable gain amplifier 32. In a preferred embodiment of the invention, the first emitter resistor RE 1 used is similar in characteristics to a Variable resistance. Adjusting the size of the first emitter resistor Re! Can control the collector current of the first transistor 丨 c 1. The collector current of the first transistor Q1 passes through the first metal-oxide semiconductor transistor P1. And the second metal-oxide semi-transistor P 2 The current mirror (Cu, "ent Mirr," obtains the mirror current of the second transistor Q2, and the value of the mirror current is the same as the collector current of the first transistor Q1. At the same time, the second transistor Q2 and the third transistor Q3 are the mirror current sources required to provide the bias current of the programmable gain amplifier. The control circuit 3 0 of the present invention printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs can provide The bias current required by the programmable gain amplifier is controlled indirectly by adjusting the emitter resistance RE 1 precisely. Then, the gain of the programmable gain amplifier is controlled. Because the control circuit of the present invention does not use a feedback circuit, and controls the current in the manner of resistance voltage division, it can generate an accurate current that is not affected by the process. The size of the wood paper is applicable to the Chinese National Standard (CNS) A4 specification (2 丨 〇 X 297 mm) 4 2 3 21 1 Printed by the Consumers ’Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs A7 B7 ____ 5. Description of the invention () In a preferred embodiment, the first metal-oxide-semiconductor transistor P 1 and the second metal-oxide-semiconductor transistor P2 are composed of a P-channel metal-oxide-semiconductor field-effect transistor (PMOS). The transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are all NPN-type transistors made of bipoiar transistors. However, according to the present invention, 'the type of transistor used is not limited to the above, as long as the function of the current mirror can be achieved, the type of transistor used can be replaced by other types of transistor' and the transistor is connected to form a current. The mode of the mirror is not limited to those listed in the above embodiments, as long as the transistor can be connected to cause the function of the current mirror, the connection mode can be used in the present invention. And in a preferred embodiment of the present invention, although the voltage generated by the 'reference voltage generating device 34' is 彳. 2 volts, different reference voltages can be provided if necessary. In a preferred embodiment of the present invention, the _th emitter resistor RE1 is designed to include N resistors (Rr R2, ... Rn), switches (SW !, SW2, ... sWu), and a Decoder (decode) 40. In a preferred embodiment of the present invention, the resistor used to form this N is manufactured by using a polycrystalline silicon resistor with more precise process control and a smaller temperature deviation coefficient. Therefore, a circuit diagram of a preferred embodiment of the first emitter resistor Ru that can be adjusted in resistance value according to the present invention is shown in Fig. 3. The N resistors in the first emitter resistor are connected in series with each other. And there is a switch between every two resistors. The way of the switch is to connect the connection of the two resistors to the ground or to the open state. 10 This paper size applies the Chinese National Standard (CNS) A4 specification (210X 297mm) — 丨 1——αΐ (Please read the notes on the back before filling this page) Order _ bundle 4 ^ 321 1 A7 _B7__ 5. Description of the invention () (Please read the notes on the back before filling this page ) Referring to FIG. 3, the first end of the first resistor R1 is connected to the first transistor Q1. Stage (in Figure 2), the first resistor R, the second terminal of which is connected to the first terminal of the second resistor R2, and is connected to the first terminal T1 of the first switch SWi. Terminal T2 is a fixed ground, and the ground terminal T3 of the first switch SW1 is one of a plurality of control lines electrically coupled to the decoder 40. Similarly, the first terminal of the second resistor R2 is connected to the first A second end of a resistor Ri and connected to the first end T1 of the first switch SW; and a second end of the second resistor R2 connected to the first end of the third resistor R3 and connected to the second The first terminal T1 of the switch SW2. The second terminal T2 of the second switch SW2 is fixedly grounded, and the third terminal T3 of the second switch SW2 is one of a plurality of control lines electrically coupled to the decoder 40. And so on, the first end of the Nth resistor R n is connected to the second end of the N -1th resistor RN -1, and the first end of the (N -1) th switch SWN _ 1 One terminal T1, and the second terminal of the Nth resistor RN is connected to the voltage νEε (in Figure 2). The second terminal T2 of the (N-1> th switch SWn —! Is fixedly grounded, and The third terminal T 3 of the (N-1) th switch SWN_i is one of a plurality of control lines electrically coupled to the decoder 40, and its connection method is shown in Figure 3. Employees ’Consumption, Intellectual Property Bureau, Ministry of Economic Affairs Printed by a cooperative
參考圖四，在本發明的一較佳實施例中所使用的開 關，可以有很多種選擇，本發明的一較佳實施例中，所. 使用的開關是由簡單的反相器（i n v e「t e「）和傳輸閘 (transfer gate)所構成，參考圖四，其中每一個開關包含 三端’第一端T1、第二端T2以及第三端T3，並且第一 端T 1電性偶合到傳輸閘T G中的P Μ 0 S的源極和N Μ 0 S 本纸張尺度適用中國國家標準（CNS ) Α4規格（210Χ 297公釐） 4 2 3 211 . μ Α7 Β7 五、發明説明（） (請先閱讀背面之注意事項再填寫本頁) 的汲極。而第二端T2電性偶合到傳輸閘T G中的N Μ〇S 的源極和PIVI0 S的汲極，而第二端Τ2亦電性偶合到接 地。第三端Τ 3被電性偶合到傳輸閘T G的Ν Μ 0 S之閘 極，並且第三端Τ 3被電性偶合到反相器丨Ν V的輸入，然 後反相器丨Ν V的輸出亦被電性偶合到傳輸閘 T G中的 PMOS之閘極。 依據上述本發明所用的開關之結構及連接方式，若 第三端Τ3為高電位，則傳輸閘TG會導通，使得第一端 Τ1與第二端Τ2短路（short circuit)，並且短路到接地， 此時依據本發明的較佳實施利之開關的輸出狀態為短路 到地。另外，當第三端T3為低電位，則傳輸閘TG不會 導通，使得第一端T1與第二端T2開路（open circuit)， 此時依據本發明的較佳實施利之開關的輸出狀態為開 路。 經濟部智慧財產局員工消費合作社印製 在本發明的一較佳實施例中，開關的輸出端只有開 路或短路到地兩種選擇，而且控制訊號是由解碼器40(圖 三）的N-1條連接到所有開關的第三端T3之控制線所輸 出，其中每條控制線皆輸出一電位。在同一時間中只能 有一條控制線是高電位，而其餘皆為低電位，亦即，每 次控制狀態的改變只允許一條控制線輸出呈高電位，其 餘皆為低電位。故假設解碼器4 0經由控制線的輸出訊號 僅讓第丨個開關短路到地，其餘開關呈現開路狀態，此時 電阻R i +1至R N全部短路到地，第一射極電阻R E彳相當於 R!到R i共i個電阻串聯。所以第一電晶體Q1的集極電 本紙張尺度適用中國國家標準（CNS > A4规格（2丨0 X 297公釐） 4 23 21 1 A7 B7五、發明説明（） 流IC1之大小，可以視為等於參考電壓產生裝置3 4 (圖二） 所輸出的電壓 VBG扣除第一電晶體CM的基射級電壓 (V B E 1 )之後再除以R E 1而得到。 而 Re·!可變電阻可以等效於圖五中的電路，其中 Req為R2至Ri的電阻串聯之總電阻值，Vctr|則相當於參 考電壓產生裝置34所輸出的電壓VBG扣.除第一電晶體 Q1的基射電壓（VBei)之後在Req上的分麼，所以改變控 制訊號時’即會改變 Req值，亦即改變 Vctrl值。所以 VctriMVBG-VBEdfReq/iRT+Req)]而因為第一電晶體 Q1 集 極電流I。1為Vctrl除以Req，又因為可程式化增益放大器 所用的偏壓電流均正比於丨c1，所以也就正比於Vctrl，故 本發明的控制電路可以達成線性地控制可程式化增益放 大器增益之目的。 以上所述僅為本發明之較佳實施例而已，並非用以 限定本發明之申請專利範圍；凡其它未脫離本發明所揭 示之精神下所完成之等效改變或修飾，均應包含在下述 之申請專利範圍内。 (請先閱讀背面之，注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 13 本紙張尺度逍用中國國家標準（CNS ) Μ規格（210X297公釐）Referring to FIG. 4, a switch used in a preferred embodiment of the present invention can have many options. In a preferred embodiment of the present invention, the switch used is a simple inverter (inve " te "and a transfer gate, refer to Figure 4, where each switch includes three terminals' first terminal T1, second terminal T2, and third terminal T3, and the first terminal T1 is electrically coupled to Source of P Μ 0 S and N Μ 0 S in the transmission gate TG This paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 × 297 mm) 4 2 3 211. Μ Α7 Β7 V. Description of the invention () (Please read the notes on the back before filling this page). The second terminal T2 is electrically coupled to the source of N MOS in the transmission gate TG and the drain of PIVI0 S, and the second terminal T2 It is also electrically coupled to ground. The third terminal T 3 is electrically coupled to the gate of NM 0 S of the transmission gate TG, and the third terminal T 3 is electrically coupled to the input of the inverter Ν V, and The output of the inverter 丨 N V is also electrically coupled to the gate of the PMOS in the transmission gate TG. According to the above-mentioned switch used in the present invention Structure and connection method. If the third terminal T3 is at a high potential, the transmission gate TG will be turned on, so that the first terminal T1 and the second terminal T2 are short-circuited and short-circuited to ground. The output state of the implemented switch is shorted to ground. In addition, when the third terminal T3 is low, the transmission gate TG will not be turned on, so that the first terminal T1 and the second terminal T2 are open circuit. The preferred embodiment of the invention is that the output state of the switch is open. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs In a preferred embodiment of the present invention, the output of the switch has only two options: open circuit or short circuit to ground. The signal is output by the N-1 control lines of the decoder 40 (Figure 3) connected to the third end T3 of all switches, each of which outputs a potential. There can be only one control line at a time It is high potential, and the rest are low potential, that is, each change of control state allows only one control line output to be high potential, and the rest are low potential. So it is assumed that the decoder 40 outputs through the control line. No. only short-circuited the first switch to ground, and the remaining switches showed an open circuit state. At this time, the resistors R i +1 to RN were all short-circuited to ground. The first emitter resistance RE 彳 was equivalent to a total of i! Therefore, the paper size of the collector of the first transistor Q1 applies the Chinese national standard (CNS > A4 specification (2 丨 0 X 297 mm) 4 23 21 1 A7 B7 V. Description of the invention () The size of the current IC1, It can be regarded as equal to the voltage VBG output from the reference voltage generating device 3 4 (FIG. 2), which is obtained by subtracting the base-emitter stage voltage (VBE 1) of the first transistor CM and then dividing it by RE 1. The Re ·! Variable resistor can be equivalent to the circuit in Figure 5, where Req is the total resistance value of the resistors R2 to Ri in series, and Vctr | is equivalent to the voltage VBG output of the reference voltage generating device 34. What is the point on the Req after the base-emitter voltage (VBei) of a transistor Q1, so when the control signal is changed, the value of Req will change, that is, the value of Vctrl. So VctriMVBG-VBEdfReq / iRT + Req)] and because of the first transistor Q1 collector current I. 1 is Vctrl divided by Req, and because the bias current used by the programmable gain amplifier is proportional to c1, so it is also proportional to Vctrl, so the control circuit of the present invention can achieve linear control of the gain of the programmable gain amplifier. purpose. The above are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention shall be included in the following Within the scope of patent application. (Please read the back of the page first, and pay attention to this page before filling in this page.) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 13 This paper size is in accordance with Chinese National Standards (CNS) M specifications (210X297 mm)