4 23 14 5 - A7 ---- B7_ 五、發明說明（1 ) 〔發明之領域〕 本發明係關於半導體裝置及其製造方法。 〔先前之技術〕 就半導體裝置之習知技術而言，已知者有例如圖1 1 所示之半導體裝置1之構造。 如圖1 1所示，半導體裝置1係於矽基板2上形成元 件分離膜1 0A、閘氧化膜1 1A及閘電極3，構成電晶 體。 又，上述電晶體之上方，形成電容器下部電極8、電 介質膜9、電容器上部電極1 0，於電介質膜9蓄積電荷 。更者，於電容器上部電極1 0之週邊或電晶體之上方， 形成層間絕緣膜4、6、2 1 ，於上部或周圍形成配線5 〇 圖11所示之半導體裝置1，係藉由以下所示之製造 方法形成者。 首先，爲了使各電晶體電氣地絕緣分離，局部地進行 矽基板2之熱氧化，形成元件分離膜1 Ο A。更者，於形 成電晶體之領域，藉由熱氧化法形成閘氧化膜1 1 A，於 其上，使用C V D法及接著的微影（photolithography )技 術形成閘電極3。 · 其次，爲了於矽基板2之內部形成ρ η接合，因此進 行離子注入，形成離子注入層。然後，於閘電極3之上， 以將閘電極3覆蓋之方式，使用C VD法形成層間絕緣膜 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） — — — — — — — — — — — II * I I 1 I I I I — — — — — — {請先閲价背面41·注$項再填窝本I > *1 t 經濟部智慧財產局貝工消費合作社印製 -4 - 經濟部智慧財Α局貝工消費合作社印製 4 23 145 Α7 Β7 五、發明說明（2 ) 4。這時，爲了使層間絕緣膜4之表面盡可能的平滑，利 用回火（anneal)使層間絕緣膜4再熱流（reflow )，或使 層間絕緣膜4厚厚地堆積進行回蝕（etch-back)。 更者，於層間絕緣膜4之上面，使用濺射法及接著的 微影（photolithography)技術形成下層配線層5。於其上 方，形成以矽氮化膜或矽氧化膜爲主要成分之層間絕緣膜 6。又，於其上方，形成電容器之下部電極8，以沿著其 側壁之方式形成電介質膜9。更者，於其上面形成上部電 極1 0。 這些電容器，係使用微影及蝕刻技術，以使表面面積 變大爲目的而成爲複雜形狀所形成者。 更者，於其週邊及上方，使用微影及蝕刻技術，形成 層間絕緣膜或配線，及將配線間以電氣連接之通孔。 又，關於這種技術，例如於日本特開昭5 6 — 147471號公報有記載。 但是，於DRAM等之具有電容器部之半導體裝置， 爲了高集積化而要將記憶體單元尺寸弄小時，如不特別考 量，則電容器部之表面積會變小，蓄積電荷量也減少。 因此，爲了使半導體裝置即是高積集化，也不會招至 電容器部之表面積之大幅減少，所以有對電容器部之形狀 作成葉片狀或王冠狀者。 更者，如圖12所示，於電容器下部電極8處，採用 被稱爲H S G或RU G之半球狀之具有凹凸之粗面化矽膜 1 1 ’藉由其微小之凹凸，使電容器部7表面積增加，此 本紙張尺度適用中國國家標準（CNS>A4規格（210 * 297公爱） -5- II--— — — — — — — i I I I I I I «— — — — It — I <請先83使背面<-注意事項再填寫本頁) 4 23145 、 A7 _ B7 五、發明說明（3 ) 種方式被嘗試使用。關於像這樣的技術之習知技術，有美 國專利之USP5082797。 閲 nr 背. 面 注’ 意 事 項 再 填 寫 本 頁 〔發明所欲解決之問題〕 如上述這樣，具有電容器部7之半導體裝置，隨著其 積集度之增加，爲了確保足夠之蓄積電荷量，不得不成爲 葉片狀或王冠狀、半球狀等之複雜之電容器形狀》 但是，隨著電容器形狀之複雜，電容器之漏電流會增 加，此爲其問題點。 電容器之漏電流之增加，係表示積蓄之電荷隨著時間 之急速之減少，也造成半導體裝置之動作性能及信賴性之 大幅降低。 特別是，將稱爲H S G或R U G之粗面化矽膜當作下 部電極用時，·與平坦化電容器比較，漏電流之增加變大， 而造成問題。 經濟部智慧財產局貝工消费合作社印製 即，於習知技術中，於圖1 2所示之電容器部7之下 部電極8，即使採用粗面化矽膜1 1 ，使蓄積電荷量增加 時，也會使漏電流大幅增加，所以，半導體裝置之動作性 能或信賴性會產生問題。 又，即使是具有葉片狀或王冠狀之形狀之電容器’與 具有平坦之電極構造之電容器比較，由於電容器漏電流增 加，所以，使裝置之動作性能有極限。 本發明之目的，係實現即使於電容器部之下部電極’ 採用粗面化矽膜時，或形成具有葉片狀或王冠狀形狀之電 -6- 本紙張尺度適用中國國家禕準（CNS)A4規格（210 X 297公釐） 423145 A7 B7 經濟部智慧財產局員工消费合作社印製 五、發明說明（4 ) 谷器時’也可以實現電容器漏電流很小之信賴性高之半導 體裝置集其製造方法。 〔解決問題之手段〕 爲了瞭、解上述之電容器洩漏現象，發明者假設電容器 之最小曲率與漏電流之大小有關，在此假定下，使電容器 之最小曲率變化，然後測定電容器之漏電流。 此處’所謂電容器之最小曲率，係指圖1 2所示之下 部電極8與電介質膜9及上部電極1〇與電介質9之界面 中，囲率最小者。 實驗之結果’如圖1 3所示，可看出有明確之相關。 圖1 3中，縱軸表示以平坦之電容器時爲準所格式化之漏 電流之値，橫軸係表示1 /曲率半徑（n m 1 )。 電容器之平坦電極等之最小曲率大時，漏電流很小， 隨著最小曲率變小，漏電流會增加。特別是，增加之程度 於曲率爲1 0 n m以下時很顯著。 其原因，係由於曲率之減少所造成之電界集中的增加 ，使應力之集中影響電介質膜9。 由以上之結果，可明顯看出電容器之曲率大幅下降’ 會導致漏電流之增大。 H S G或R U G等之粗面化矽膜之形狀，係如圖1 4 所示，於膜基部有尖的角部1 3，該腳部1 3之曲率爲5 n m以下左右係相當小。 因此，可認爲該角部1 3係電容器漏電流之大幅增力口 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） ---------ί-^ii--•訂---1--線 4 (請先《^背面項再填寫本頁) 23 14 A7 B7 五、發明說明（5 ) 之原因。但是，由於粗面化矽膜1 1之成膜條件之範圍狹 窄，所以，利用成膜條件控制粗面化矽膜1 1之形狀很困 難，僅只是使粗面化矽本身之形狀變化，增加曲率是困難 的。 又，於形成王冠狀或葉片狀之電容器中，如圖1 1及 圖1 5所示，於其前端部有角部1 7。雖然該角部1 7之 曲率依存於蝕刻裝置之性能，但是，比粗面化矽膜1 1之 角部1 3大，大約爲1 0 n m以下。 因此，於形成爲葉片狀或王冠狀之電容器中，與具有 平坦之電極之電容器相較，漏電流增加係由於該角部1 7 之曲率小的程度所造成者。 因此，爲了解決這些問題，一邊考慮不會導致電容器 部7之表面積之大量之減少，一邊使角部1 3或角部1 7 之曲率變大即可。 即，爲了達成上述之目的，本發明係由以下這樣所構 成者。 經濟部智慧財產局員工消費合作社印製 (1 )該半導體裝置，係至.少具有半導體基板，及於 該半導體基板上所形成之電晶體，及於上述半導體基板上 所形成之電容器部；其特徵爲：上述電容器部，係至少胃 備有粗面化矽膜、及電介質膜、及具有導電性之電極膜， 於.上述粗面化矽膜與電介質膜之間形成導電膜。 (2 )又，該半導體裝置，係至少具有半導體基板， 及於該半導體基板上所形成之電晶體，及於上述半導體基 板上所形成之電容器部；其特徵爲：上述電容器部，係至 本紙满尺度適用中國國家標準（CNS)A4規格（210 X 297公釐) ~ ~ --- 3 145 A7 B7 五、發明說明（6 ) 少具備有粗面化矽膜、及電介質膜、及具有導電性之電極 膜’於上述粗面化矽膜與電介質膜之間，形成有具有導電 性之矽膜。 (3 )更理想者係於上述（1 )中，其中上述導電膜 係含有鎢、鉅、氮化鈦、氮化鎢、氧化鈦、鉛 '釕、銥、 氧化釕中任何一種。 (4 )又，該半導體裝置，係至少具有半導體基板， 及於該半導體基板上所形成之電晶體，及於上述半導體基 板上所形成之電容器部；其特徵爲：上述電容器部，係至 少具備有第1之矽膜、及電介質膜、及具有導電性之電極 膜’於上述電介質膜之下層，存在有第1矽膜，更於第1 矽膜之下層形成有第2矽膜，於第1矽膜與電介質膜之界 面，有◦ n m以上之曲率。 經濟部智慧財產局員工消費合作社印製 (請先閲讀背面之注^^#項再填寫本1 > 線f (5 )又，該半導體裝置，係至少具有半導體基板， 及於該半導體基板上所形成之電晶體，及於上述半導體基 板上所形成之電容器部；其特徵爲：上述電容器部，係至 少具備有矽膜、及電介質膜、及具有導電性之電極膜，上 述電介質膜之下層存在有導電膜，更於上述導電膜之下層 形成有上述矽膜。 (6 )又，該半導體裝置，係至少具有半導體基板， 及於該半導體基板上所形成之電晶體，及於上述半導體基 板上所形成之電容器部；其特徵爲：上述電容器部，係至 少具備有矽膜、‘及電介質膜 '及具有導電性之電極膜，上 述電介質膜之下層存在有導電膜，更於上述導電膜之下層 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） •9- 4 ϋΙ 4 5 ， Α7 --—__Β7___ 五、發明說明（7 ) 形成有上述矽膜，上述導電膜與上述電介質膜之界面，具 有10nm以上之曲率。 (7 )更理想者係於上述（5 )中，其中上述導電膜 係含有鎢、鉅、氮化鈦 '氮化鎢、氧化鈦、鉑、釕、銥' 氧化釕中任何一種.。 (8 )又，該半導體裝置，係至少具有半導體基板， 及於該半導體基板上所形成之電晶體，及於上述半導體基 板上所形成之王冠型電容器部；其特徵爲：上述王冠型電 容器部1係至少具備有下部電極膜、及電介質膜、及上部 電極膜，上述王冠型電容器部之上端部，·係成爲直線狀之 邊，該邊係與上述半導體基板之上述電晶體所形成之面大 約平行。 (9 )又，該半導體裝置，係至少具有半導體基板’ 及於該半導體基板上所形成之電晶體，及於上述半導體基 板上之層間絕緣膜中所形成之地溝型電容器部：其特徵爲 :上述地溝型電容器部，係於含有矽之下部電極與電介質 膜之間，具備有含有鎢、鉬、氮.化鈦、氮化鎢 '氧化鈦、 鉑、釕、銥、氧化钌中任何一種之導電膜。 經濟部智慧財產局員工消费合作社印製 <請先閲圯背面^注意事項再填寫本頁> (1 0 )又，該半導體裝置，係至少具有半導體基板 ，及於該半導體基板上所形成之電晶體，及於上述半導體 基板上所形成之電容器部；其特徵爲：上述電容器部’係 至少具備有粗面化矽膜、及電介質膜、及具有導電性之電 極膜，與上述電介質膜相鄰之電極膜之界面之曲率爲1 〇 n m以上。 本紙張尺度適用t國國家標準（CNS)A4規格（210 X 297公釐） •10- 經濟部智慧財產局貝工消費合作社印製 4 2 3 14 5 at _ B7 五、發明說明（8 ) (1 1 )又，該半導體裝置，係至少具有半導體基板 ，及於該半導體基板上所形成之電晶體，及於上述半導體 基板上所形成之地溝型電容器部；其特徵爲：上述地溝型 電容器部，係至少具備有下部電極膜、及電介質膜、上部 電極膜，上述地溝型電容器部之上端部，係成爲直線狀之 邊，該邊係與上述半導體基板之上述電晶體所形成之面大 約平行。 (1 2 )又，該半導體裝置，係至少具有半導體基板 ，及於該半導體基板上所形成之電晶體，及於上述半導體 基板上所形成之地溝型電容器部或王冠型電容器部；其特 徵爲：上述電容器部，係至少具備有含有粗面化矽膜之下 部電極、及電介質膜、及上部電極膜，上述電容器部之下 部電極上端部，係成爲直線狀之邊，上述上端部係沒有粗 面化矽膜所造成之凹凸。 (1 3 )又，該半導體裝置之製造方法，係該半導體 裝置至少具備有半導體基板’及於該半導體基板上所形成 之電晶體，及於上述半導體基板上所形成之電容器部之； 其特徵爲：形成下部電極之後，於該下部電極之表面形成 粗面化矽膜：於上述粗面化矽膜之上面形成上部砍膜：於 上述上部矽膜之上面形成電介質膜；於上述電介質膜之上 面形成上部電極，然後形成上述電容器部。 (1 4 )又’該半導體裝置之製造方法，係該半導體 裝置至少具備有半導體基板’及於該半導體基板上所形成 之電晶體’及於上述半導體基板上所形成之電容器部之： ---------「政--------訂---------線^ (锖先Mi»'背面注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公») 11 _-____B7___ 五、發明說明（9 ) 其特徵爲：於形成下部電極後’將該下部電極之前端，藉 由CMP技術’以使與上述半導體基板之上述電晶體所形 成之面大約平行之方式予以硏磨；於上述下部電極之上部 ’形成電介質膜：於上述電介質膜之上面形成上部電極， 然後形成上述電容器部。 〔發明之實施型態〕 以下，使用圖面，說明本發明之實施型態。 又，圖1係表示本發明之半導體裝置1之第1之實施 型態之剖面模式圖。圖係圖1之主要部位之槪略剖面模式 圖" 於圖1中，於矽基板2上，形成元件分離膜1 0A、 閘氧化膜1 1 A及閘電極3，構成電晶體。 又，於上述電晶體之上方，形成電容器下部電極8、 粗面化矽膜1 1、上部矽膜1 2、電介質膜9、電容器上 部電極1 0，將電荷蓄積於電介質膜9。更者，於電容器 上部電極1 0之週邊或電晶體之上方，形成層間絕緣膜4 、6、2 1 ，於上部或週邊形成配線5。 經濟部智慧財產局貝工消費合作社印製 下部矽膜8被加工成王冠狀，其表面上形成多數之粗 面化矽膜1 1。又，如圖2所示，於粗面化矽膜1 1之上 形成上部矽膜1 2，形成電介質膜9被夾於上部矽膜1 2 與上部電極1 〇之間之構造。 又，上部矽膜1 2之膜厚，係以不會將粗面化矽膜 1 1之凹凸埋起，且可以使粗面化矽膜1 1之角部1 3之 -12- 本紙張尺度適用中國國家標準（CNS)A4規格（210 * 297公釐） 423145 A7 ____B7_____五、發明說明（10 ) 曲率變大之範圍，即，3〜20nm爲理想者。又，上部 電極1 0最好是矽、鎢、鉅、氮化鈦、氮化鎢、氧化鈦、 舶 '釕、紙、氧化訂等。 電介質膜9理想者爲氧化矽、氮化矽、氧化鉅、4 23 14 5-A7 ---- B7_ V. Description of the Invention (1) [Field of Invention] The present invention relates to a semiconductor device and a manufacturing method thereof. [Previous Technology] As for a conventional technology of a semiconductor device, a structure of the semiconductor device 1 shown in FIG. 11 is known, for example. As shown in FIG. 11, the semiconductor device 1 is formed on the silicon substrate 2 with an element separation film 10A, a gate oxide film 11A, and a gate electrode 3, forming an electric crystal. A capacitor lower electrode 8, a dielectric film 9, and a capacitor upper electrode 10 are formed above the transistor, and charges are accumulated in the dielectric film 9. Further, an interlayer insulating film 4, 6, 2 1 is formed around the upper electrode 10 of the capacitor or above the transistor, and a wiring 5 is formed above or around the semiconductor device 1. The semiconductor device 1 shown in FIG. The manufacturer of the manufacturing method shown. First, in order to electrically isolate and isolate each transistor, the silicon substrate 2 is thermally oxidized locally to form an element separation film 10 A. Further, in the field of forming a transistor, a gate oxide film 1 1 A is formed by a thermal oxidation method, and a gate electrode 3 is formed thereon by using a C V D method and a subsequent photolithography technique. · Next, in order to form a ρ η junction inside the silicon substrate 2, ion implantation is performed to form an ion implantation layer. Then, the gate electrode 3 is covered on top of the gate electrode 3, and an interlayer insulating film is formed by using the C VD method. The paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) — — — — — — — — — — — II * II 1 IIII — — — — — — {Please read the price on the back 41. Note $ item before filling in the book I > * 1 t Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs- 4-Printed by the Shellfish Consumer Cooperative of the Bureau of Intellectual Property A, Ministry of Economic Affairs 4 23 145 Α7 Β7 V. Description of Invention (2) 4. At this time, in order to make the surface of the interlayer insulating film 4 as smooth as possible, the interlayer insulating film 4 is reflowed by annealing, or the interlayer insulating film 4 is thickly stacked for etch-back. Furthermore, a lower wiring layer 5 is formed on the interlayer insulating film 4 by a sputtering method and a subsequent photolithography technique. Above it, an interlayer insulating film 6 mainly composed of a silicon nitride film or a silicon oxide film is formed. A capacitor lower electrode 8 is formed above the capacitor, and a dielectric film 9 is formed along the sidewall thereof. Furthermore, an upper electrode 10 is formed on the upper electrode. These capacitors are formed into complex shapes by using lithography and etching techniques to increase the surface area. Furthermore, lithography and etching techniques are used on the periphery and above to form interlayer insulating films or wirings, and through holes for electrically connecting wiring rooms. Such a technique is described in, for example, Japanese Patent Application Laid-Open No. 5 6-147471. However, in a semiconductor device having a capacitor portion such as a DRAM, the size of a memory cell is made small for high integration. Without special consideration, the surface area of the capacitor portion becomes small, and the amount of accumulated electric charge also decreases. Therefore, in order to increase the accumulation of the semiconductor device without causing a large reduction in the surface area of the capacitor portion, there is a blade-like or crown-like shape of the capacitor portion. Furthermore, as shown in FIG. 12, at the lower electrode 8 of the capacitor, a hemispherical roughened silicon film 1 1 'called a hemispherical shape called HSG or RU G is used to make the capacitor portion 7 with its minute unevenness. Increased surface area, this paper size applies Chinese national standard (CNS > A4 specification (210 * 297 public love) -5- II --- — — — — — — i IIIIII «— — — — It — I < 83 make the back < -notes to fill in this page again) 4 23145 、 A7 _ B7 5. Description of the invention (3) The method is tried to use. As for a conventional technique such as this technique, there is USP5082797 of the U.S. patent. Please read the nr back. Note the matter and fill in this page again [Problems to be Solved by the Invention] As described above, as the accumulation degree of the semiconductor device with the capacitor section 7 increases, in order to ensure a sufficient accumulated charge amount, It has to be a complicated capacitor shape such as a blade shape, a crown shape, a hemisphere shape, etc. However, as the shape of the capacitor is complicated, the leakage current of the capacitor will increase, which is the problem. The increase in the leakage current of a capacitor means that the accumulated charge decreases rapidly with time, which also causes a significant decrease in the operating performance and reliability of the semiconductor device. In particular, when a roughened silicon film called H S G or R U G is used as the lower electrode, compared with a flattened capacitor, the increase in leakage current becomes larger, which causes a problem. Printed by the Shelley Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs, that is, in the conventional technology, even when the roughened silicon film 1 1 is used on the lower electrode 8 of the capacitor section 7 shown in FIG. Also, the leakage current will be greatly increased, so the operation performance or reliability of the semiconductor device will cause problems. Moreover, even if a capacitor having a blade-like shape or a crown-like shape is compared with a capacitor having a flat electrode structure, the capacitor leakage current increases, which limits the operating performance of the device. The purpose of the present invention is to achieve the formation of a blade-like or crown-shaped electric shape even when a roughened silicon film is used on the lower electrode of the capacitor.-This paper is applicable to China National Standards (CNS) A4 Specifications (210 X 297 mm) 423145 A7 B7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the invention (4) The trough device can also realize high reliability semiconductor devices with a small capacitor leakage current. method. [Means for Solving the Problem] In order to solve the above-mentioned capacitor leakage phenomenon, the inventor assumed that the minimum curvature of the capacitor is related to the magnitude of the leakage current. Under this assumption, the minimum curvature of the capacitor is changed, and then the leakage current of the capacitor is measured. Here, the "minimum curvature of the capacitor" refers to the one having the smallest curvature among the interfaces between the lower electrode 8 and the dielectric film 9 and the upper electrode 10 and the dielectric 9 shown in Fig. 12. The result of the experiment 'is shown in Fig. 13 and it can be seen that there is a clear correlation. In Figure 13, the vertical axis represents the magnitude of the leakage current formatted with a flat capacitor, and the horizontal axis represents 1 / curvature radius (n m 1). When the minimum curvature of a flat electrode of a capacitor is large, the leakage current is small. As the minimum curvature becomes smaller, the leakage current increases. In particular, the degree of increase is significant when the curvature is 10 nm or less. The reason is that the concentration of the electric field increases due to the decrease in the curvature, so that the concentration of the stress affects the dielectric film 9. From the above results, it can be clearly seen that a sharp decrease in the curvature of the capacitor 'causes an increase in leakage current. The shape of the roughened silicon film such as H S G or RU G is shown in Fig. 14. The corner 13 of the film has a sharp corner 13 and the curvature of the leg 13 is less than about 5 nm. Therefore, it can be considered that the corner 1 3 series capacitors have a significant increase in leakage current. The paper size is applicable to Chinese national standards (CNS > A4 specifications (210 X 297 mm) --------- ί- ^ ii-- • Order --- 1--Line 4 (please fill in this page with "^" on the back) 23 14 A7 B7 V. Reason for the invention (5). However, because of the roughened silicon film 1 1 The range of film formation conditions is narrow. Therefore, it is difficult to control the shape of the roughened silicon film 11 using the film formation conditions. It is difficult to increase the curvature only by changing the shape of the roughened silicon itself. As shown in FIG. 11 and FIG. 15, a blade-shaped capacitor has a corner portion 17 at the front end portion. Although the curvature of the corner portion 17 depends on the performance of the etching device, the ratio is roughened. The corners 13 of the silicon film 11 are large, about 10 nm or less. Therefore, compared with a capacitor having a flat electrode, the leakage current increases due to the angle compared with a capacitor having a flat electrode. It is caused by the small degree of curvature of the portion 17. Therefore, in order to solve these problems, consider that the surface of the capacitor portion 7 will not be caused. It is sufficient to increase the curvature of the corner portion 13 or the corner portion 17 by a large amount. That is, in order to achieve the above-mentioned object, the present invention is constituted by the following. (1) The semiconductor device includes at least a semiconductor substrate, a transistor formed on the semiconductor substrate, and a capacitor portion formed on the semiconductor substrate; characterized in that the capacitor portion is at least The stomach is provided with a roughened silicon film, a dielectric film, and an electrode film having conductivity, and a conductive film is formed between the roughened silicon film and the dielectric film. (2) The semiconductor device includes at least A semiconductor substrate, a transistor formed on the semiconductor substrate, and a capacitor portion formed on the semiconductor substrate; the feature is that the capacitor portion is to the full scale of this paper and applies the Chinese National Standard (CNS) A4 specification ( 210 X 297 mm) ~ ~ --- 3 145 A7 B7 V. Description of the invention (6) It is less equipped with a roughened silicon film, a dielectric film, and a conductive electrode film. A conductive silicon film is formed between the siliconized film and the dielectric film. (3) More preferably, it is the above (1), wherein the conductive film contains tungsten, giant, titanium nitride, tungsten nitride, Any one of titanium oxide, lead, ruthenium, iridium, and ruthenium oxide. (4) The semiconductor device includes at least a semiconductor substrate, and a transistor formed on the semiconductor substrate, and formed on the semiconductor substrate. The capacitor section is characterized in that the capacitor section is provided with at least a first silicon film, a dielectric film, and an electrode film having conductivity, and a first silicon film is provided below the dielectric film. A second silicon film is formed under the first silicon film, and has a curvature of ◦ nm or more at the interface between the first silicon film and the dielectric film. Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs (please read the note ^^ # on the back before filling in this 1 > line f (5)), and the semiconductor device has at least a semiconductor substrate and is on the semiconductor substrate The formed transistor and the capacitor portion formed on the semiconductor substrate are characterized in that the capacitor portion is provided with at least a silicon film, a dielectric film, and an electrode film having conductivity, and a lower layer of the dielectric film. There is a conductive film, and the silicon film is formed below the conductive film. (6) The semiconductor device includes at least a semiconductor substrate, a transistor formed on the semiconductor substrate, and the semiconductor substrate. The capacitor portion formed above is characterized in that the capacitor portion is provided with at least a silicon film, a 'dielectric film' and an electrode film having conductivity, and a conductive film exists under the dielectric film, and is more than the conductive film. The paper size of the lower layer applies the Chinese National Standard (CNS) A4 specification (210 X 297 mm) • 9- 4 ϋΙ 4 5, Α7 ---__ Β7 ___ V. Invention (7) The above-mentioned silicon film is formed, and the interface between the conductive film and the dielectric film has a curvature of 10 nm or more. (7) More preferably, it is in the above (5), wherein the conductive film contains tungsten, giant, Any one of titanium nitride, tungsten nitride, titanium oxide, platinum, ruthenium, and iridium ruthenium oxide. (8) The semiconductor device includes at least a semiconductor substrate and a transistor formed on the semiconductor substrate. And a crown-shaped capacitor portion formed on the semiconductor substrate; characterized in that the crown-shaped capacitor portion 1 is provided with at least a lower electrode film, a dielectric film, and an upper electrode film; and the upper end portion of the crown-type capacitor portion Is a straight edge, which is approximately parallel to the surface formed by the transistor of the semiconductor substrate. (9) The semiconductor device includes at least a semiconductor substrate and is formed on the semiconductor substrate. A transistor and a trench capacitor portion formed in the interlayer insulation film on the semiconductor substrate, which is characterized in that the trench capacitor portion is formed of silicon Between the lower electrode and the dielectric film, a conductive film containing any one of tungsten, molybdenum, nitrogen, titanium nitride, tungsten nitride 'titanium oxide, platinum, ruthenium, iridium, and ruthenium oxide is provided. Employees' Cooperatives, Intellectual Property Bureau, Ministry of Economic Affairs Printed <Please read the back page ^ Note before filling in this page> (1 0) Also, the semiconductor device has at least a semiconductor substrate, and a transistor formed on the semiconductor substrate, and the above semiconductor The capacitor portion formed on the substrate is characterized in that the capacitor portion 'is provided with at least a roughened silicon film, a dielectric film, and an electrode film having conductivity, and an interface of an electrode film adjacent to the dielectric film. The curvature is above 10nm. This paper size is applicable to the national standard (CNS) A4 specification (210 X 297 mm) • 10- Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 2 3 14 5 at _ B7 5 (8) (1 1) The semiconductor device includes at least a semiconductor substrate, a transistor formed on the semiconductor substrate, and a trench-type transistor formed on the semiconductor substrate. It is characterized in that the above-mentioned trench capacitor unit is provided with at least a lower electrode film, a dielectric film, and an upper electrode film, and the upper end portion of the above-mentioned trench capacitor unit is a straight edge, and this edge is in accordance with the above. The surfaces formed by the transistors of the semiconductor substrate are approximately parallel. (1 2) The semiconductor device includes at least a semiconductor substrate, a transistor formed on the semiconductor substrate, and a trench-type capacitor portion or a crown-type capacitor portion formed on the semiconductor substrate; : The capacitor portion includes at least a lower electrode including a roughened silicon film, a dielectric film, and an upper electrode film. The upper end portion of the lower electrode of the capacitor portion is a straight edge, and the upper end portion is not rough. The unevenness caused by the silicon film. (1 3) Furthermore, the method for manufacturing a semiconductor device is one in which the semiconductor device includes at least a semiconductor substrate, a transistor formed on the semiconductor substrate, and a capacitor portion formed on the semiconductor substrate; After the lower electrode is formed, a roughened silicon film is formed on the surface of the lower electrode: an upper cut film is formed on the roughened silicon film; a dielectric film is formed on the upper silicon film; and a dielectric film is formed on the upper silicon film. An upper electrode is formed thereon, and then the capacitor portion is formed. (1 4) And 'The manufacturing method of the semiconductor device is that the semiconductor device has at least a semiconductor substrate' and a transistor formed on the semiconductor substrate 'and a capacitor portion formed on the semiconductor substrate:- ------- "Administration -------- Order --------- line ^ (锖 Mi» 'Notes on the back before filling out this page) This paper size applies to Chinese national standards (CNS) A4 specification (210 X 297 male ») 11 _-____ B7___ 5. Description of the invention (9) It is characterized in that after forming the lower electrode, the front end of the lower electrode is subjected to CMP technology to communicate with the above semiconductor The surface formed by the above-mentioned transistor of the substrate is honed in a parallel manner; a dielectric film is formed on the upper portion of the lower electrode: an upper electrode is formed on the upper surface of the dielectric film, and then the capacitor portion is formed. ] Hereinafter, an embodiment of the present invention will be described using drawings. FIG. 1 is a schematic cross-sectional view showing a first embodiment of a semiconductor device 1 of the present invention. The diagram is a schematic cross-section of a main part of FIG. 1 The pattern diagram is shown in Figure 1. On the substrate 2, an element separation film 10A, a gate oxide film 1 1 A, and a gate electrode 3 are formed to form a transistor. A capacitor lower electrode 8, a roughened silicon film 11, and an upper portion are formed above the transistor. Silicon film 1, 2, dielectric film 9, capacitor upper electrode 10, accumulate charge on dielectric film 9. Furthermore, an interlayer insulating film 4, 6, 2 1 is formed around the capacitor upper electrode 10 or above the transistor. The wiring 5 is formed on the upper or peripheral side. The lower silicon film 8 printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs is processed into a crown shape, and most of the roughened silicon films 11 are formed on the surface. It is shown that an upper silicon film 12 is formed on the roughened silicon film 11 and a structure in which a dielectric film 9 is sandwiched between the upper silicon film 12 and the upper electrode 120 is formed. Also, a film of the upper silicon film 12 is formed. Thick, because it will not bury the unevenness of the roughened silicon film 11 and can make the corners of the roughened silicon film 11 1-13 of -12- This paper size applies to China National Standard (CNS) A4 (210 * 297 mm) 423145 A7 ____B7_____ V. Description of the invention (10) The range where the curvature becomes larger, That is, 3 to 20 nm is ideal. The upper electrode 10 is preferably silicon, tungsten, giant, titanium nitride, tungsten nitride, titanium oxide, ruthenium, paper, oxide, etc. Dielectric film 9 is ideal For silicon oxide, silicon nitride, oxide giant,
P Z T ( P b C Z T 1 )〇 經濟部智慧財產局貝工消费合作社印製 B S T ( B a i .. X S r X T 1 0 3 )等。特別是，確認氧化 鉬（五氧化鉅）於本發明有很高之有效性。 如以上這樣，本發明之第1實施型態，爲了於粗面化 矽膜1 1之上部，形成上部矽膜1 2，上部矽膜1 2與電 介質膜9成爲相接。於上部矽膜1 2所形成之角部1 4 > 係與粗面化矽膜11之角部13相比，曲率變大，又，於 電介電介質膜9與上部電極1 0之界面所形成之上部角部 1 5，也受到其底子形狀之影響，曲率變大。 依據本發明之第1實施型態，於電容器部7之下部電 極，採用粗面化矽膜1 1 ，使蓄積電荷量增加時，也可以 使電容器之電介質膜9之最小曲率變大，所以可以將電容 器漏電流控制成很小。 所以，即使於電容器部之下部電極採用粗面化矽膜時 ，也可以實現電容器漏電流很小，而信賴性高之半導體裝 置。 又，於上述之第1之實施型態，係使電容器部7之形 狀成爲王冠狀，但是，也可以是葉片狀。又，如圖1 3所 示，當曲率半徑成爲1 0 n m以下時，漏電流會大幅增加 ，所以，以與電介質膜9相接之角部成爲曲率半徑1 0 諳 先 閲 讀* 背. 面 之-注 意 事 項Γ表 頁I w I I I I I I訂 K紙張尺度適用中國困家楳準（CNS>A4規格C210 X 297公；* ) -13- 423145 Α7 Β7 經濟部智慧財產局貝工消费合作社印製 五、發明說明（11) n m以上之方式形成上部矽膜，是最理想者。 更者，於裝置之設計上，由必須要將漏電流値控制於 平坦電容器時之5 0被左右，所以曲率半徑1 〇 n m以上 也是必要者。 其次，於本發明之第1實施型態之半導體裝置之製造 方法，於以下說明。 首先，爲了使各電晶體成爲電氣絕緣分離，局部地進 行矽基板2之熱氧化，形成元件分離膜1 0A。更者，於 形成電晶體之領域，藉由熱氧化法形成閘氧化膜1 1 A， 於其上，使用C V D法及接著的微影技術，形成閘電極3 〇 爲了於矽基板2之內部形成ρ η接合，進行離子注入 ，形成離子注入層。使用C V D法，於閘電極3之上，以 將閘電極3覆蓋之方式，形成層間絕緣膜4。 這時，爲了使層間絕緣膜4之表面盡可能地平坦化， 藉由回火，使層間絕緣膜4再熱流，或使層間絕緣膜厚厚 地堆積，進行回蝕。更者^於層間絕緣膜4之上面，使用濺 射法及接著的微影技術，形成下層配線5。於其上方，以 覆蓋下層配線5之方式形成層間絕緣膜6。之後，形成電 容器部7。 電容器部7，係首先藉由微影及蝕刻之技術，將下部 電極8加工成王冠狀之後，於其表面，形成粗面化矽膜 1 1。更者，於其上面’形成上部矽膜1 2之後進行蝕刻 (請先Μ讀背面之注意事項再瑱寫本頁) _「表· — —訂---------線Λ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 14- 經濟部智慧財產局貝工消费合作社印製 2 3 14 5 A7 ___B7____ _ 五、發明說明（12 ) 於其側壁形成電介質膜9，但是，爲了使電介質膜9 之性質提高，於氧氣中或氧氣電發中進行回火，是很理想 者。更者，上部電極1 0形成，藉由蝕刻除去不要之部位 ，藉此完成電容器部7 «更者，於其周圍或上部，形成層 間絕緣膜4、6 ' 2 1或配線5，成爲半導體裝置1。 藉由本發明之第1實施型態之半導體之製造方法，即 使於電容器部之下部電極，採用粗面化矽膜時，也可以實 現電容器漏電流小，信賴性高之半導體裝置之製造方法。 其次，針對本發明之第2實施型態之半導體裝置，作 一說明。 圖3係本發明之第2實施型態之半導體裝置之主要部 位之槪略剖面模式圖。又，該第2實施型態，除了圖3所 示之部分外，係與第1之實施型態相同之構成，所以，省 略圖示及說明。 該第2實施型態，係於粗面化矽膜1 1之上形成砂膜 以外之具有導電性之膜1 6之例子。 於圖3中，下部電極8被加工成王冠狀，其表面形成 粗面化矽膜1 1。又，於粗面化矽膜1 1之上’形成導電 膜1 6，電介質膜9成爲被夾於導電膜1 6與上部電極 1 0之間之構造。 即使是於上述之本發明之第2實施型態，也可以使角 音P 1 3或上部角部1 5之曲率變大，所以，可以使漏電.流 變小，與第1實’施型態相同地，即使於電容器部之下部電 極，採用粗面化矽膜時，也可以實現電容器漏電流很小’ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -15- it--ml ^ illtln ^-11111111 ^ <請先閲it·背面L注意Ϋ項再瑱寫本頁) 經濟部智慧財產局負工消費合作社印製 2 3 14 5 A7 「 _ B7___五、發明說明（13 ) 而信賴性高之半導體裝置。 更者’依據本發明之第2實施型態，由於電介質膜9 沒有與矽相接’所以進行電介質膜9之回火處理時，於電 介質膜9之界面，形成氧化矽膜，介電常數不會降低。因 此’即使進行以改善電介質膜9之質爲目的之回火，所蓄 積之電荷量也不會降低，此爲其利點》 又’導電膜1 6之膜厚，理想者係與第1實施型態相 同之範圍。又，導電膜較理想者爲鎢、鉅、氮化鈦、氮化 鎢、氧化鈦、鉑、釕、銥、氧化釕。 又’導電膜1 6也可以將上述材質之中2種類以上混 合，或基層膜也可。 又，該第2之實施型態之半導體裝置之製造方法，於 上述第1實施型態之製造方法中，除了形成導電膜1 6代 替上部矽膜1 2之外，幾乎都相同。 圖4係本發明之第3實施型態之半導體裝置之主要部 位之槪略剖面模式圖。又，該第3實施型態，係除了圖4 所示之部位之外，與第1實施型態有相同之構造，所以， 圖示及說明予以省略。又，本發明之第3實施型態係沒有 粗面化矽膜者之例。 於圖4中，半導體電容器部5主要係由下部矽膜8、 上部矽膜1 2、電介質膜9、上部電極1 0所構成。下部 矽膜8被加工成王冠狀，於其表面，形成上矽膜1 2，電 介質膜9成爲被上部矽膜12與上部電極10夾著之構造 -------丨—4.'^.--------訂---------線Λ <請先閱_讀背面L注意事項再填寫本I) 本紙張尺度適用中國國家標準（CNSXA4規格（210 X 297公爱） • 16 - 2 3 14 § 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（14) 下部矽膜8之形狀，除了王冠狀之外，也可以是葉片 狀，於具有複雜形狀’曲率半徑小之角部時很有效。王冠 狀之電容器形狀時’下部矽膜8之最上部成爲曲率半徑最 小之角部1 7。 但是，依據此實施型態，係將上部矽膜1 2形成於其 上部，所以’於上部矽膜1 2與電介質膜9之界面所形成 之角部14，與下部矽膜8之角部17比較，曲率變大， 又’電介質與上部電極1 〇之界面所形成之上部角部i 5 ，也受其底子形狀之影響，曲率變大。 又，圖4之王冠狀電容器部，不只是最上部，最下部 也存在有角部2 0，本發明於該角部2 0也同樣地有使曲 率半徑變大之功效。 因此，依據本發明之第3實施型態，即使將電容器部 之形狀加工成王冠狀或葉片狀，使表面積增加，使蓄積電 荷量增加時’其角部1 7或上部角部1 5、角部2 0，可 以使電容器部之最小曲率變大’所以可以電容器漏電流控 制成最小。 又，該第3實施型態之半導體裝置之製造方法，與上 述第1之實施型態之製造方法’除了沒有形成粗面化細膜 之外，幾乎是相同地。 圖5係本發明之第4實施型態之半導體裝置之主要部 位之槪略剖模式圖。又該第4實施型態，係除了圖5所示 之部分外’與第1實施型態有相同之構成。所以，省略圖 示及說明。又’該第4實施型態’是沒有粗面化細膜者， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公* ) . <|7~ ίι — ί — ! A^· ! — ! 訂--- {請先Μίι·背面I注意ί項再填寫本IK) 。23彳45 A7 ---- B7__ 五、發明說明（15 ) 於下部電極之表面上，不是形成有上部細膜丨2而是形成 有具有導電性之導電膜16之例子。 於該第4之實施型態中，與第3之實施例相同地，可 以使角部1 7或角部2 0之曲率變大，所以，可以使漏電 流變小。藉此，可以獲得與第1實施例相同之效果β 更者，依據第4實施型態，由於電介質膜9沒有與矽 相接，所以於進行電介質膜9之回火處理時，於電介質膜 9之界面，形成氧化矽膜，而不會使介電常數降低。 因此’即使進行以改良電介質膜9之性質爲目的之回 火，也具有不會使蓄積之電荷量下降之優點。 又，該第4實施型態之半導體裝置之製造方法，與上 述第1實施型態之、造方法，除了不形成粗面化矽膜，以 形成導電膜1 6代替矽膜1 2之外，幾乎相同。 圖6是本發明之第5實施型態之半導體裝置之主要部 位之槪略剖面模式圖。又，該第5實施型態，是除 所示之部分外，與第1實施例有相同之構成，所以，省略 圖示極說明。 經濟部智慧財產局員工消費合作社印製 又，該第5實施型態，係被應用於電容器部之形狀爲 所謂王冠狀者。此處，所謂王冠狀係指電容器部爲圓筒形 或圓柱形、或將其壓扁之橢圚之筒狀、柱狀或腳柱、有角 之筒狀者，而其側面及內面成爲主要之電荷之蓄積部。 像這樣之王冠形狀之下部電極8形成時’進行乾蝕刻 ，但是，這時，於下部電極8之王冠上端部形成銳角之角 部1 7 (圖4、圖5所示）。以前’連接於該下部電極8 -18- 本紙張尺度適用中國國家標準<CNS)A4規格（210 * 297公釐） A7 _____B7_ 五、發明說明（16) 之上端部之角部1 7，電介質膜9被形成。更者，上部電 極10被形成，所以，於該銳角之角部1 7，產生於電介 質膜9內顯著之應力集中。 以前，由於該應力集中之原因，使漏電流增加，使更 新時間不充足，所以信賴性有問題。 該第5實施型態，於形成王冠狀之下部電極8時，使 用 C Μ P ( chemical ) mechanical polishing化學機械硏磨 )技術，將藉由乾蝕刻所形.成之上端部之角部1 7，切削 至圖7所示之硏磨面C爲止，使與形成矽基板2之閘氧化 膜1 1之面，幾乎平行之邊2 2，形成於王冠狀之下部電 極8之上端部。 藉此，可以減低王冠狀之上端部之應力集中，所.以， 可以降低上端部之漏電流，可以作成有足夠時間更新之信 賴性高之半導體裝置。 又，該第5實施型態中，於下部電極8沒有形成粗面 化矽膜1 1 ，但是也可以形成粗面化矽膜1 1 ，於形成粗 面化矽膜1 1時，即使於通常之砍膜時，也可以期待有該 第5之實施型態之效果。 又，通常，於半導體記憶體內，由於有多數之王冠狀 電容器這樣之筒狀電容器存在，所以，於圖7所示之 CMP 5硏磨面C，如果硏磨上端部，多數之電容器之上 端部，成爲與形成矽基板2之閘氧化膜1 1之面幾乎平行 之邊。 圖8是本發明之第6之實施型態之半導體裝置之主要 I紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 請 先 讀· 背. 面 之· 注P Z T (P b C Z T 1) 〇 B S T (B a i .. X S r X T 1 0 3) printed by Shelley Consumer Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs. In particular, it has been confirmed that molybdenum oxide (giant pentoxide) is highly effective in the present invention. As described above, in the first embodiment of the present invention, an upper silicon film 12 is formed on the roughened silicon film 11 and the upper silicon film 12 is in contact with the dielectric film 9. The corner portion 1 4 formed on the upper silicon film 12 is larger in curvature than the corner portion 13 of the roughened silicon film 11 and is formed at the interface between the dielectric film 9 and the upper electrode 10. The formation of the upper corners 15 is also affected by the shape of the base, and the curvature becomes large. According to the first embodiment of the present invention, when the roughened silicon film 1 1 is used for the lower electrode of the capacitor section 7 to increase the amount of accumulated charge, the minimum curvature of the dielectric film 9 of the capacitor can also be increased. The capacitor leakage current is controlled to be small. Therefore, even when a roughened silicon film is used for the lower electrode of the capacitor portion, a semiconductor device with high reliability and small leakage current of the capacitor can be realized. In the first embodiment described above, the shape of the capacitor portion 7 is a crown shape, but it may be a blade shape. Also, as shown in Figure 13, when the radius of curvature is less than 10 nm, the leakage current will increase significantly. Therefore, the corner contacting the dielectric film 9 will become the radius of curvature 1 0. 谙 Read first * Back. -Precautions Γ sheet I, III, III, K paper standards are applicable to Chinese families (CNS > A4 size C210 X 297);) -13- 423145 Α7 Β7 Printed by the Shellfish Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs DESCRIPTION OF THE INVENTION Forming an upper silicon film in a manner above (11) nm is the most ideal. Furthermore, in the design of the device, since the leakage current 値 must be controlled to about 50 when the flat capacitor is used, a curvature radius of 100 nm or more is also necessary. Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described below. First, in order to electrically isolate each transistor, the silicon substrate 2 is thermally oxidized locally to form an element isolation film 10A. Furthermore, in the field of forming a transistor, a gate oxide film 1 1 A is formed by a thermal oxidation method, and a gate electrode 3 is formed thereon by using a CVD method and a subsequent lithography technique. In order to form the inside of the silicon substrate 2 ρ η bonding, ion implantation is performed, and an ion implantation layer is formed. Using the C V D method, an interlayer insulating film 4 is formed on the gate electrode 3 so as to cover the gate electrode 3. At this time, in order to flatten the surface of the interlayer insulating film 4 as much as possible, the interlayer insulating film 4 is reheated by tempering, or the interlayer insulating film is deposited thickly and etched back. Furthermore, a lower layer wiring 5 is formed on the interlayer insulating film 4 by a sputtering method and a subsequent lithography technique. Above this, an interlayer insulating film 6 is formed so as to cover the lower-layer wiring 5. Thereafter, the capacitor portion 7 is formed. The capacitor portion 7 is formed by first processing a lower electrode 8 into a crown shape by a technique of lithography and etching, and then forming a roughened silicon film 11 on the surface. Furthermore, after the upper silicon film 12 is formed thereon, etching is performed (please read the precautions on the back side before writing this page) _ 「表 · — — 订 --------- 线 Λ 本Paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 14- Printed by Shelley Consumer Cooperative, Intellectual Property Bureau, Ministry of Economic Affairs 2 3 14 5 A7 ___B7____ _ V. Description of the invention (12) A dielectric is formed on the side wall Film 9, however, in order to improve the properties of the dielectric film 9, it is ideal to perform tempering in oxygen or in the electrical generation of oxygen. In addition, the upper electrode 10 is formed, and unnecessary portions are removed by etching, whereby The capacitor section 7 is completed. Further, an interlayer insulating film 4, 6 '2 1 or a wiring 5 is formed around or above the capacitor section 7 to become a semiconductor device 1. With the semiconductor manufacturing method according to the first embodiment of the present invention, When a roughened silicon film is used for the lower electrode of the capacitor portion, a semiconductor device manufacturing method with small capacitor leakage current and high reliability can be realized. Next, a description will be given of a semiconductor device according to the second embodiment of the present invention. Figure 3 is the present invention A schematic cross-sectional schematic view of the main parts of the semiconductor device of the second embodiment. The second embodiment has the same structure as the first embodiment except for the part shown in FIG. 3, so, The second embodiment is an example in which a conductive film 16 other than a sand film is formed on the roughened silicon film 11. In FIG. 3, the lower electrode 8 is processed into The crown-like shape has a roughened silicon film 11 on its surface. A conductive film 16 is formed on the roughened silicon film 11 and the dielectric film 9 is sandwiched between the conductive film 16 and the upper electrode 10. Even in the above-mentioned second embodiment of the present invention, the curvature of the corner sound P 1 3 or the upper corner portion 15 can be increased, so that the leakage current can be reduced and the first current can be reduced. In the same way, even with the roughened silicon film on the lower electrode of the capacitor, the capacitor leakage current can be very small. ”This paper size applies to China National Standard (CNS) A4 (210 X 297 mm). ^) -15- it--ml ^ illtln ^ -11111111 ^ < Please read it · Notes on the back L before writing Page) Printed by the Consumer Goods Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 2 3 14 5 A7 "_ B7___ V. Invention Description (13) Semiconductor device with high reliability. Furthermore, according to the second embodiment of the present invention, Since the dielectric film 9 is not connected to silicon ', when the tempering process of the dielectric film 9 is performed, a silicon oxide film is formed at the interface of the dielectric film 9 and the dielectric constant will not decrease. Therefore,' even if it is performed to improve the dielectric film 9 ' Tempering for the purpose of quality will not reduce the amount of accumulated electric charge, which is its advantage. The thickness of the conductive film 16 is preferably the same as that of the first embodiment. The conductive film is preferably tungsten, giant, titanium nitride, tungsten nitride, titanium oxide, platinum, ruthenium, iridium, or ruthenium oxide. The 'conductive film 16 may be a mixture of two or more of the above materials, or a base film may be used. The manufacturing method of the semiconductor device of the second embodiment is almost the same as the manufacturing method of the first embodiment except that the conductive film 16 is formed instead of the upper silicon film 12. Fig. 4 is a schematic cross-sectional view of a main part of a semiconductor device according to a third embodiment of the present invention. In addition, the third embodiment has the same structure as the first embodiment except for the portion shown in FIG. 4, so the illustration and description are omitted. The third embodiment of the present invention is not an example in which the silicon film is roughened. In FIG. 4, the semiconductor capacitor section 5 is mainly composed of a lower silicon film 8, an upper silicon film 1 2, a dielectric film 9, and an upper electrode 10. The lower silicon film 8 is processed into a crown shape, and on its surface, an upper silicon film 12 is formed, and the dielectric film 9 is a structure sandwiched between the upper silicon film 12 and the upper electrode 10 ----- 丨 -4. ' ^ .-------- Order --------- Line Λ < Please read _Read the Cautions on the back before filling in this I) This paper size applies to Chinese National Standard (CNSXA4 Specification (210 X 297 public love) • 16-2 3 14 § A7 B7 printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (14) The shape of the lower silicon film 8 can be leaf-shaped in addition to the crown-like shape. It is effective when corners with a complex shape 'small curvature radius. In the case of a crown-shaped capacitor shape, the uppermost part of the lower silicon film 8 becomes a corner 17 with the smallest curvature radius. However, according to this embodiment, the system will The upper silicon film 12 is formed on the upper part, so that the corner 14 formed at the interface between the upper silicon film 12 and the dielectric film 9 has a larger curvature than the corner 17 of the lower silicon film 8, and the dielectric and The upper corner i 5 formed by the interface of the upper electrode 10 is also affected by the shape of its base, and the curvature becomes larger. Also, the king of FIG. 4 The capacitor part is not only the uppermost part, but also the corner part 20 at the lowermost part. The corner part 20 of the present invention also has the effect of increasing the radius of curvature. Therefore, according to the third embodiment of the present invention, Even if the shape of the capacitor part is processed into a crown shape or a blade shape, the surface area is increased, and the accumulated charge amount is increased. 'The corner portion 17 or the upper corner portion 15 and the corner portion 20 can make the minimum curvature of the capacitor portion. It becomes larger, so that the capacitor leakage current can be controlled to a minimum. In addition, the manufacturing method of the semiconductor device of the third embodiment and the manufacturing method of the first embodiment described above except that a roughened fine film is not formed. It is almost the same. FIG. 5 is a schematic sectional view of a main part of a semiconductor device according to a fourth embodiment of the present invention. The fourth embodiment is similar to the first embodiment except for the portion shown in FIG. 5. The implementation type has the same structure. Therefore, illustrations and explanations are omitted. Also, the “fourth implementation type” is a person without a roughened thin film. This paper size applies the Chinese National Standard (CNS) A4 specification (210 X 297). Public *). ≪ | 7 ~ ίι ί -! A ^ · -!! Order --- {please Μίι · back I note ί items to fill out this IK). 23 彳 45 A7 ---- B7__ 5. Description of the invention (15) An example in which a conductive film 16 having conductivity is formed instead of the upper thin film 2 on the surface of the lower electrode. In the fourth embodiment, as in the third embodiment, the curvature of the corner portion 17 or the corner portion 20 can be made larger, so that the leakage current can be made smaller. Thereby, the same effect β as that of the first embodiment can be obtained. Furthermore, according to the fourth embodiment, since the dielectric film 9 is not connected to the silicon, the dielectric film 9 is subjected to the tempering treatment of the dielectric film 9 when the tempering process is performed. Interface, a silicon oxide film is formed without lowering the dielectric constant. Therefore, even if tempering is performed for the purpose of improving the properties of the dielectric film 9, there is an advantage that the amount of accumulated charges does not decrease. In addition, the manufacturing method of the fourth embodiment of the semiconductor device and the manufacturing method of the first embodiment described above, except that a roughened silicon film is not formed, and a conductive film 16 is formed instead of the silicon film 12. almost the same. Fig. 6 is a schematic cross-sectional view of a main part of a semiconductor device according to a fifth embodiment of the present invention. The fifth embodiment has the same structure as the first embodiment except for the parts shown in the figure. Therefore, the description of the poles is omitted. Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. This fifth implementation type is applied to the capacitor department in a so-called crown shape. Here, the so-called crown shape refers to a cylindrical, cylindrical, or elliptical cylindrical, columnar, or toe-shaped, or angular cylindrical shape in which the capacitor portion is flattened, and its side and inner surfaces become The main charge accumulation part. When the crown-shaped lower electrode 8 is formed in this way, dry etching is performed. However, at this time, an acute-angled corner portion 17 is formed at the upper end of the crown of the lower electrode 8 (shown in Figs. 4 and 5). Previously 'connected to the lower electrode 8 -18- This paper size applies to the Chinese national standard < CNS) A4 specification (210 * 297 mm) A7 _____B7_ V. Description of the invention (16) The corner of the upper end 1 7, dielectric The film 9 is formed. Furthermore, since the upper electrode 10 is formed, a significant stress concentration in the dielectric film 9 occurs at the corner portion 17 of the acute angle. Previously, due to the stress concentration, the leakage current was increased and the update time was insufficient. Therefore, reliability was problematic. In the fifth embodiment, when the crown-shaped lower electrode 8 is formed, the CMP (chemical) mechanical polishing technique is used to form the corner of the upper end by dry etching. 1 7 After cutting to the honing surface C shown in FIG. 7, the side that is almost parallel to the surface forming the gate oxide film 11 of the silicon substrate 2 is formed at the upper end of the crown-like lower electrode 8. This can reduce the stress concentration at the upper end portion of the crown, so that the leakage current at the upper end portion can be reduced, and a highly reliable semiconductor device with sufficient time to update can be made. In this fifth embodiment, the roughened silicon film 1 1 is not formed on the lower electrode 8, but the roughened silicon film 1 1 may be formed. When the roughened silicon film 11 is formed, When cutting the film, the effect of the fifth embodiment can also be expected. Also, most semiconductor capacitors have cylindrical capacitors such as crown-shaped capacitors. Therefore, if the upper end portion is honed on the CMP 5 shown in FIG. 7, the upper end portion of most capacitors is honed. It becomes a side almost parallel to the surface on which the gate oxide film 11 of the silicon substrate 2 is formed. Fig. 8 is the main semiconductor device of the sixth embodiment of the present invention. I Paper size is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm). Please read it first. Back.
項 再 填二 I ^ I I w I I I I I 訂 經濟部智慧財產局員工消费合作社印製 19- 經濟部智慧財產局員工消费合作社印製 ^ 23 1dS A7 B7 五、發明說明（17 ) 部位之槪略剖面模式圖。該第6之實施型態係被應用於電 容器形狀爲所謂之溝渠狀者。 此處，所謂之溝渠狀係指，電容器爲圓筒狀或圓柱狀 或將其壓扁之橢圓狀之筒狀、柱狀或有角柱、角之筒狀之 形狀之孔的內面，作爲主要電荷之蓄積部。 像這樣之溝渠狀之下部電極8形成時，藉由乾蝕刻進 行孔之形成，但是，這時，於孔底部形成銳角之角部2 0 。又，下部電極8，由蝕刻的容易度來看，以矽被用的最 多，角部20最容易成爲銳角。 於該銳角之角部2 0中，由於電介質膜9內產生顯著 之應力集中，所以，習知之方法，有漏電流增加，更新時 間不足之問題。 · 即，像圖9所不之於層間絕緣膜2 1之一部份成爲下 部電極8之膜被埋入之狀態，所以，藉由蝕刻形成孔（溝 渠），藉由於其內面形成電介質膜9之方法，形成電容器 時，漏電流變多，信賴性降低。 於該第6實施型態，如圖8.所示，於下部電極8與電 介質膜9之間，形成由矽、鎢、鉅 '氮化鈦、氮化鎢、氧 化鈦、鉑、釕、銥、氧化釕等所形成之導電膜1 6。 藉此，與第4實施型態同樣地，藉由形成矽膜，可以 使底部之邊緣之曲率變大，可以防止角部之角之應力集中 〇 所以，可以減低電容器之漏電流，可以成爲具有足夠 更新時間之有高度信賴性之半導體裝置。 ! —(^iill· — — —^· — — — — ！-線^' (請先閲'讀"面^注意事項再填寫本買> 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） -20· 423145 Α7 Β7 經濟部智慧財產局員工消費合作社印製 五、發明說明（18) 又，於該第6之實施型態中’於下部電極8沒有形成 粗面化矽膜1 1 ，但是也可以形成粗面化矽膜1 1 ，於形 成粗面化矽膜1 1時*即使於通常之矽膜時，也可以期待 該第6實施型態之效果。 圖10係本發明之第7之實施型態之半導體裝置之主 要部位之槪略剖面模式圖。該第7之實施型態，係藉由 C Μ P技術硏磨溝渠型之電容器之下部電極8之上端部之 例子。 如第5實施型態所述者，藉由乾蝕刻形成下部電極8 時，有前端部很尖之問題。形成粗面化矽膜1 1之後，於 蝕刻時，由於受到附著於上端部之粗面化矽膜1 1被蝕刻 之影響，成爲上端部之曲率更小之複雜之形狀。 因此，於使用習知之蝕刻之方法，會有漏電流增加之 問題。 此處，於該第7之實施型態中，係以C Μ Ρ技術，於 C Μ Ρ之硏磨面C，硏磨下部電極8，所以，可以使上端 部之曲率變大，可以使漏電流控制成很低。 又，於下部電極8形成粗面化矽膜1 1時，也藉由 C Μ Ρ技術，使附著於上端部之粗面化矽膜1 1被切削， 成爲平坦。 所以，將粗面化矽膜1 1使用於下部電極8時，可 以使上端部之曲率變大，因此，可以使漏電流降低，可以 有具有足夠之更’新時間之高信賴性之半導體裝置β 本紙張尺度適用中固a家標準（CNS)A4規格（210 X 297公爱） -21 - -----!「^il·-----訂---------線-S (請先Μηί背面t注意事項再填窝本頁) 4 2 3 1 4 5 A7 B7 五、發明說明（2〇 ) 又’藉由CMP技術，使下部電極之前端，與半導體 基板之上述電晶體所形成之面幾乎平行之方式，予以硏磨 ，構成電容器部時，也可以使電容器之最小曲率變大，可 以將電容器漏電流控制成很小，可以實現信賴性高之半導 體裝置及其製造方法。 〔圖示簡單說明〕 圖1係表示本發明之第1實施型態之半導體裝置之剖 面模式圖。 圖2係圖1之主要部位之槪略剖面模式圖。 圖3係本發明之第2之實施型態之半導體裝置之主要 部位之槪略剖面模式圖。 + 圖4係本發明之第3實施型態之半導體裝置之主要部 位之槪略剀面模式圖。 圖5係本發明之第4實施型態之半導體裝置之主要部 位之槪略剖面模式圖。 請 先 I 背· 面 之· 注Fill in the second item I ^ II w IIIII Order printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 19- Printed by the employee's consumer cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs ^ 23 1dS A7 B7 V. Summary profile pattern of the description of the invention (17) Illustration. This sixth embodiment is applied to a capacitor having a so-called trench shape. Here, the so-called ditch shape refers to the inner surface of the hole in which the capacitor is cylindrical or cylindrical, or an elliptical cylindrical, columnar, or angular column, or angular cylindrical shape that is flattened. Charge accumulation section. When the trench-like lower electrode 8 is formed in this manner, the hole is formed by dry etching, but at this time, an acute corner portion 20 is formed at the bottom of the hole. In view of the ease of etching, the lower electrode 8 is most often used with silicon, and the corner portion 20 is most likely to become an acute angle. In this acute-angled corner portion 20, since a significant stress concentration occurs in the dielectric film 9, the conventional method has problems of increased leakage current and insufficient update time. · That is, a part of the interlayer insulating film 21 as shown in FIG. 9 is in a state where the film of the lower electrode 8 is buried. Therefore, a hole (ditch) is formed by etching, and a dielectric film is formed on the inner surface thereof. In the 9 method, when a capacitor is formed, the leakage current increases and the reliability decreases. In this sixth embodiment, as shown in FIG. 8, between the lower electrode 8 and the dielectric film 9, silicon, tungsten, giant titanium nitride, tungsten nitride, titanium oxide, platinum, ruthenium, and iridium are formed. 16 and ruthenium oxide. Thus, similar to the fourth embodiment, by forming a silicon film, the curvature of the bottom edge can be increased, and the stress concentration at the corners can be prevented. Therefore, the leakage current of the capacitor can be reduced, and Highly reliable semiconductor device with sufficient update time. ! — (^ Iill · — — — ^ · — — — —！-线 ^ '(Please read' Read " face ^ Note before filling in this purchase > This paper size applies to China National Standard (CNS) A4 specifications (210 X 297 public love) -20 · 423145 Α7 Β7 Printed by the Consumers' Cooperative of Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (18) In the sixth implementation form, no rough surface is formed on the lower electrode 8. The silicon film 11 is formed, but a roughened silicon film 11 can also be formed. When the roughened silicon film 11 is formed *, even in the case of a normal silicon film, the effect of the sixth embodiment can be expected. 10 is a schematic cross-sectional schematic view of a main part of a semiconductor device according to a seventh embodiment of the present invention. The seventh embodiment is a method of honing the lower electrode 8 of a trench-type capacitor by CMP technology. Example of the upper end portion. As described in the fifth embodiment, when the lower electrode 8 is formed by dry etching, there is a problem that the front end portion is sharp. After the roughened silicon film 11 is formed, it is subject to adhesion during etching. The roughened silicon film 11 at the upper end is affected by the etching, and the curvature of the upper end becomes smaller. Therefore, in the conventional etching method, there is a problem that the leakage current increases. Here, in the seventh implementation mode, the CMP technology is used to polish the CMP surface. C, honing the lower electrode 8, so that the curvature of the upper end portion can be increased, and the leakage current can be controlled to be very low. In addition, when the roughened silicon film 11 is formed on the lower electrode 8, the CMP is also used. Technology, the roughened silicon film 11 attached to the upper end portion is cut and flattened. Therefore, when the roughened silicon film 11 is used for the lower electrode 8, the curvature of the upper end portion can be increased, so that The leakage current can be reduced, and a semiconductor device with high reliability and new time can be provided. Β This paper size is applicable to China Solid Standard (CNS) A4 specification (210 X 297 public love) -21----- -! 「^ Il · ----- Order --------- line-S (please note on the back of the η and fill in this page) 4 2 3 1 4 5 A7 B7 V. Description of the invention (20) Also, by CMP technology, the front end of the lower electrode is honed so that it is almost parallel to the surface formed by the transistor of the semiconductor substrate. When the capacitor section is configured, the minimum curvature of the capacitor can be increased, the capacitor leakage current can be controlled to be small, and a highly reliable semiconductor device and a method of manufacturing the same can be realized. A schematic cross-sectional view of a semiconductor device according to a first embodiment of the invention. Fig. 2 is a schematic cross-sectional view of a main portion of Fig. 1. Fig. 3 is a schematic view of a main portion of a semiconductor device according to a second embodiment of the invention. Figure 4 is a schematic cross-sectional view of a main part of a semiconductor device according to a third embodiment of the present invention. Fig. 5 is a schematic cross-sectional view of a main part of a semiconductor device according to a fourth embodiment of the present invention. Please I back · front · note
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I I 訂 I I I I I I I 線 經濟部智慧財產局員工消費合作杜印製 要 主 之 置 裝 澧 SH 導 半 之 態 型 施 實 之 5 。 第圖 之式 明模 發面 本剖 係略 6 槪 圖之 位 β. 0 部 要 主 之 。 置. 圖裝 明體 說導 之半 術之 技態 Ρ 型 Μ 施 C« 之 6 子第。 例之圖 之明式 6 發模 圖本面 係係剖 7 8 略 圖圖槪 之 位 之 要 置 主 裝 之 體 置 導 裝 半 體 之 導 狀 半 渠 之 溝 態 之 型 謂 施 所 實 爲 7 成 第 狀 之 形 明 器 發 容。本 電圖係 係明 ο 9 說 1 圖之圖 造 製 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） -23- 經濟部智慧財產局員工消f合作社印製 A7 ______B7__ 五、發明說明（21 ) 部位之模式圖。 圖1 1係習知之半導體裝置之一例子之槪略剖面模式 圖。 圖1 2係表示習知之半導體裝置之其他之例子之槪略 面模式圖。 圖13係表示電容器部之曲率與漏電流之關係之圖。 圖14係漏電流之發生部分之說明圖。 圖15係習知之半導體裝置之葉片形狀之電容器部之 剖面模式圖。 [符號說明〕. 1 半導體裝置 2 矽膜基板 3 閘電極 4 層間絕緣膜 5 下層配線 6 層間絕緣膜 7 電容器部 8 下部矽膜 9 電介質膜 10 上部電極 1 0 A 元件分離膜 11 粗面化矽膜 12 上部矽膜 - ---i».^. i ! I 訂-----·5^'-Ν (靖先Μ讀背面t注$項再填寫本頁) 本紙張尺度適用中國國家標準（CNS>A4規格（210 X 297公釐） -24- A7 423145 B7 五、發明說明（22 ) 13 角部 14 角部 1 δ 上部角部 16 導電膜 17 角部 18 上部配線 19 層間絕緣膜 2 0 角部 2 1 層間絕緣膜 2 2 邊 經濟部智慧財產局員工消费合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -25-I I order I I I I I I I Line I Consumers ’cooperation with the Intellectual Property Bureau of the Ministry of Economic Affairs to print the main installation and installation of SH-guided half-state implementation 5. The formula in the figure is the surface of the exposed model. This section is a bit 6. The position of the figure β. 0 is the main part. Figure. The state of the art semi-speaking technique P type Μ The 6th subsection of C «. The figure of the example is the clear formula 6 The model of the hair is cut 7 7 The outline of the figure 槪 The position of the main device is to be installed The guide device is half of the channel and the shape of the groove is called 7 The shape of the shape of the device is made. This electrograph is clearly ο 9 said. 1 The drawings are made according to the Chinese standard (CNS > A4 size (210 X 297 mm). -23- Printed by the staff of the Intellectual Property Bureau of the Ministry of Economic Affairs. F7 printed by a cooperative. ______B7__ 5 Schematic diagram of part (21) of the invention description. Fig. 1 1 is a schematic cross-sectional schematic diagram of an example of a conventional semiconductor device. Fig. 12 is a schematic schematic diagram showing other examples of a conventional semiconductor device. 13 is a graph showing the relationship between the curvature and leakage current of the capacitor portion. Fig. 14 is an explanatory diagram of the leakage current occurrence portion. Fig. 15 is a schematic sectional view of the capacitor portion of the conventional semiconductor device blade shape. [Symbol Description]. 1 Semiconductor device 2 Silicon film substrate 3 Gate electrode 4 Interlayer insulating film 5 Lower wiring 6 Interlayer insulating film 7 Capacitor section 8 Lower silicon film 9 Dielectric film 10 Upper electrode 1 0 A Element separation film 11 Roughened silicon film 12 Upper silicon film ---- i ». ^. i! I order ----- · 5 ^ '-N (Jingxian M read the t note on the back and fill in this page) This paper size applies to Chinese national standards (CNS > A4 Specifications (210 X 297 mm) -24- A7 4 23145 B7 V. Description of the invention (22) 13 Corner 14 Corner 1 δ Upper corner 16 Conductive film 17 Corner 18 Upper wiring 19 Interlayer insulating film 2 0 Corner 2 1 Interlayer insulating film 2 2 Intellectual Property Office of the Ministry of Economic Affairs The paper size printed by the employee consumer cooperative is applicable to Chinese National Standard (CNS) A4 (210 X 297 mm) -25-