TW421985B - Substrate of semiconductor package - Google Patents

Substrate of semiconductor package Download PDF

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Publication number
TW421985B
TW421985B TW88100086A TW88100086A TW421985B TW 421985 B TW421985 B TW 421985B TW 88100086 A TW88100086 A TW 88100086A TW 88100086 A TW88100086 A TW 88100086A TW 421985 B TW421985 B TW 421985B
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TW
Taiwan
Prior art keywords
substrate
film
injection
glue injection
glue
Prior art date
Application number
TW88100086A
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Chinese (zh)
Inventor
Kun-Ching Chen
Wu-Chang Wang
Shyh-Ing Wu
Yung-I Yeh
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Advanced Semiconductor Eng
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Priority to TW88100086A priority Critical patent/TW421985B/en
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Publication of TW421985B publication Critical patent/TW421985B/en

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Abstract

The present invention relates to a substrate of a semiconductor package, in which an encapsulation region is provided on a substrate. The encapsulation region is placed with a film. The substrate underneath the film is provided with a circuit layout. The circuit layout is deposited with a layer of a soldering mask. When an encapsulant is injected into the encapsulation region, the encapsulant is isolated by the film and does not come into direct contact with the soldering mask, in which the adhesion capability between the film and the encapsulant is greater than the adhesion capability between the film and the soldering mask. When the encapsulant on the encapsulation passage is peeled off after encapsulation, the film can be peeled off along with the encapsulant of the encapsulation passage. Therefore, no film or encapsulant will remain on the substrate.

Description

42 1 98 5 五、發明說明(l) 發明領域: 本發明係有關於一種半導體封裝之基板,特別是有關於 製造球格陣列積體電路之基板時,在封裝電子元件之注膠 位置與基板之間’用以隔絕封膠與基板表面在注膠位置上 發生直接接觸的可剝離隔絕墊層之構造。 先前技術: 隨著積體電路的功能越來越形複雜,以電晶體為單位的 電路數量之集積度(Integration)越來越高,故傳統的四 角平板包裝(Quad Flat Pack ; QFP)或接腳晶格陣列 (Pin_Grid Array ; PGA)已逐漸不符合實際應用的要求。 球格障列積體電路(BGA 1C) ’是為一種新—代的高接腳數 積體電路封裝(IC Package),其係適用於今日以次微米解 析度所製造出來的超大規模集積(ultra_Large Seale42 1 98 5 V. Description of the invention (l) Field of the invention: The present invention relates to a substrate for a semiconductor package, and more particularly to a substrate for manufacturing a ball grid array integrated circuit. Between 'is a structure of a peelable insulation pad that isolates the sealant from direct contact with the surface of the substrate at the position of the injection. Prior technology: As the functions of integrated circuits become more and more complex, the integration degree of the number of circuits in units of transistors is getting higher and higher, so the traditional Quad Flat Pack (QFP) or Pin grid array (PGA) has gradually failed to meet the requirements of practical applications. Ball grid barrier integrated circuit (BGA 1C) is a new-generation high-pin integrated circuit package (IC Package), which is suitable for ultra-large-scale integrated circuits manufactured today with sub-micron resolution ( ultra_Large Seale

Integration ;ULSI)的積體電路之封裝使用。此球格陣列 $體電路封裝即為一種可以符合此種高接腳數要求的 在球格陣列積體電路之中,較常見的是塑膠球袼陣列 (Plastic BGA)封裝,其係在製作封裝本體時利用模且進 行注膠,將熔融的液態膠質材料,經由模具的注入口'灌入 ,凡^地包封住突出於基板表面上的整個積體電 ==電,)晶片提供完全氣密的密封環 r;二:=離=形:;::=電路 膠質封裝本趙的模具注膠口附近區域,必須進行修整= 趣 C:\Program Files\Patents\PK6441. ptd 第 五、發明說明(2) 作’以將因為模具的注膠通道所殘留的塑膠邛於 習=中’製作球袼陣列積體電:(=二=方 :裝=鑛有金之金屬片,其成形於球格陣 封裝的基板上,當掇t 體電路 .± ^ ^ θ 畜模具覆盍於基板的定位上時,佞$仿趴 注膠模具的注膠注入通道之下方。 使之位於 之金屬片,作為掇且黹&匕 進仃,主膠時,此鍍金 之間的隔絕層:以"!注穆注入通道與基板 =動作’如第—,圖所示之習用封裝習電用子二 二ΓΓ E1rtronic Device)10進行注膠作動時,在基 =LI : 示之注膠作動完畢時再進行脫模作 二圖,此時,位於注勝口之鍍金面的二 i IίI 入通道内所殘留的封膠易於與基板^ 1脫Integration; ULSI). This ball grid array package is a type of ball grid array integrated circuit that can meet such high pin count requirements. The most common is the plastic ball grid array (Plastic BGA) package, which is used to make the package. When the body is used, the mold is used for injection, and the molten liquid colloidal material is injected through the injection port of the mold, and the entire integrated body protruding on the surface of the substrate is encapsulated. The chip provides complete gas. Dense sealing ring r; 2 :: away = shape:; :: = Circuit adhesive package The area near the mold injection port of Ben Zhao must be trimmed = Fun C: \ Program Files \ Patents \ PK6441. Ptd Fifth, invention Explanation (2) Make 'to remove the plastic left over from the injection channel of the mold in the middle of the mold' to make a ball array array: (==== square: equipment = metal sheet with gold, which is formed on On the substrate of the ball grid package, when 掇 t body circuit. ± ^ ^ θ The animal mold is overlaid on the positioning of the substrate, the injection molding channel of the imitation injection molding mold is placed below the metal sheet. , As 掇 and 黹 & dagger into 仃, when the main glue, the isolation layer between the gold plating: with "! Mu injection channel and substrate = action 'as shown in the first —, the conventional package shown in the figure is used to perform the glue injection operation. When the glue injection operation is performed at the base = LI: The mold is shown in the second figure. At this time, the remaining sealant in the second channel of the gold-plated surface of the injection gate is easy to be removed from the substrate.

離’而不致於如同封裝的本體一樣,與基极】】的表面 地黏附在一起,因而利於修整封裝本體外形上的突出 餘0 上述習用之鍍金面金屬片13的存在,會估用了基板丨丨之 電路佈局的空間,使基板丨丨可製造電路佈局的空間減少。 另一方面,金的成本高,且由於此脫模用的鍍金金屬片 ,相對於整體基板而言乃是佔有相當的面積,成本耗費太 大。此外,當金屬片13熱膨脹時’該金屬片13對兩側之焊 接罩15產生水平擠壓,因此,該焊接罩15内之電路佈局 亦受擠壓’進而降低基板11之製造良率。 有趨於此,本發明改良上述之諸缺點,藉以—薄膜置於It is not separated from the surface of the package body like the body of the package], which is conducive to trimming the protruding shape of the package body. The existence of the conventional gold-plated metal sheet 13 above will estimate the substrate. The space of the circuit layout reduces the space that the substrate can manufacture the circuit layout. On the other hand, the cost of gold is high, and because the gold-plated metal sheet for demolding occupies a considerable area relative to the overall substrate, the cost is too large. In addition, when the metal sheet 13 thermally expands, 'the metal sheet 13 horizontally squeezes the welding cover 15 on both sides, so the circuit layout inside the welding cover 15 is also squeezed', thereby reducing the manufacturing yield of the substrate 11. To this end, the present invention improves the above disadvantages, whereby the film is placed

涑膠位置上形成一可隨注膠通道剝離之剝離層,當注膠通 道進行剝離時,在基板上不致殘留薄膜或注膠,該可剝離 廣之,計不但可增加電路佈局面積且不使用金或其它金屬 基板製作成本’並可避免擠迫基板的電路佈局, 增加製造良率’又可維持在注膠後注膠位置與注膠通道剝 離的功效。 發明概要: 本,明之主要目的係提供一種半導體封裝之基板,其可 去除習用基板上注膠口。本發明以一薄膜置於注膠位置上 形成一可隨注膠通道剝離之剝離層,當注膠通道進行剝離 時’在基板上不致殘留薄膜或注膠,此種可剝離層之設計 不但可增加電路佈局面積且不使用金,可節省基板製作成 本’並可避免擠迫基板的電路佈局,增加製造良率, 維持在注膠後注膠位置與注膠剝離的功效。 根據本發明,在一基板注膠位置上設一層薄膜,該薄胰 係具黏附力可黏附於注膠位置上,而該薄膜底下之基板設 有電路佈局’該電路佈局上沉積一層焊接罩〔s〇lder mask〕’當注膠由注膠位置注入時,注膠受薄膜隔離而不 直接與焊接罩接觸·»此時,注膠通道之注膠與薄膜產生一 黏附力’使薄膜黏附於注膠通道之注膠,其中該薄膜與注: 膠黏附力大於該薄膜與焊接罩之黏附力,因而當注膠過後 注膠通道進行剝離時’由於該薄膜可隨注膠通道之注膠剝 離’因此’在基板上不致殘留薄膜或注膠。A peeling layer is formed on the glue position, which can be peeled off along with the glue injection channel. When the glue injection channel is peeled off, no film or glue is left on the substrate. The peelability can be broadened. It can increase the circuit layout area and not use it. The production cost of gold or other metal substrates can prevent the circuit layout of the substrate from being squeezed, increase the manufacturing yield, and can maintain the effectiveness of the injection position and the peeling of the injection channel after the injection. SUMMARY OF THE INVENTION The main purpose of the present invention is to provide a substrate for a semiconductor package, which can remove a glue injection port on a conventional substrate. In the present invention, a film is placed on the glue injection position to form a peeling layer that can be peeled off along with the glue injection channel. When the glue injection channel is peeled off, 'the film or glue does not remain on the substrate. The design of this peelable layer is not only Increasing the area of the circuit layout without using gold can save the substrate manufacturing cost, and can avoid squeezing the circuit layout of the substrate, increase the manufacturing yield, and maintain the effectiveness of the injection position and the peeling after the injection. According to the present invention, a thin film is provided on a substrate injection position. The thin pancreas can be adhered to the injection position with adhesive force, and the substrate under the film is provided with a circuit layout. A solder mask is deposited on the circuit layout. s〇lder mask] 'When the injection is injected from the injection position, the injection is isolated by the film and does not directly contact the welding cover. »At this time, the injection of the injection channel and the film create an adhesion force' to make the film adhere to Glue injection of the injection channel, where the film and note: The adhesive force is greater than the adhesion of the film and the welding cover, so when the injection channel is peeled off after the injection, because the film can be peeled off with the injection of the injection channel 'Therefore', no film or glue remains on the substrate.

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五、發明說明(4) 圖式說明: 特徵、和優點能更明顯| 例’並配合所附圓式, 為讓本發明之上述和其他目的、 易懂’下文特舉本發明之較佳實施 作詳細說明如下: 第1A圖:習用封裝電子元件注膠動作示意圖; 第1B圖習用封裝雷子元株沐麻 打扳电十兀仵/主膠凡畢進行脫模動作示 意圖; 第2圖.習用封裝電子元件 』衣电于兀忏之汪膠口局部剖面示意圖; 第3圖·本發明較佳實施例之整塊基板上視圖; 第4圖·本發明第3圖沿4 - 4線剖面圖;及 第5圖·本發明第4圖注耀狀態之剖面圖。 圖號說明: 10 封裝電子元件 11 基板 12 Μ 0-: 13 金屬片 14 電路佈局 15 焊接罩 20 基板 21 薄膜 22 電路佈局 23 焊接罩 24 注膠 25 注膠區域 發明說明: 請參照第三圖,本發明較佳實施例係主要包含一基板2〇 | 及一薄膜21。基板20設有球格陣列積體電路,該基板2〇設1 一注膠區域25 ’該注膠區域25下方仍可設電路佈局22,而 該基板20之注勝區域25則位於注膠周圍。薄膜21係採用非 金屬材料或金屬材料如膠帶〔tape〕或高分子化合物,由V. Description of the invention (4) Schematic description: Features and advantages can be more obvious | Examples' and the accompanying round form, in order to make the above and other purposes of the present invention easy to understand, hereinafter, the preferred implementation of the present invention is enumerated. The detailed description is as follows: Figure 1A: Schematic diagram of glue injection of conventional packaged electronic components; Figure 1B: Schematic diagram of demographic action of conventional packaged Lei Ziyuan Zhuma Muma to trigger ten vultures / main glue Fanbi; Figure 2. Partial cross-sectional schematic diagram of the conventional plastic electronic component "on the vulture's rubber mouth; Figure 3 · Top view of the entire substrate of the preferred embodiment of the present invention; Figure 4 · Section 3 of the present invention along the line 4-4 FIG. 5 and FIG. 5 are cross-sectional views of a gleaming state of FIG. 4 of the present invention. Description of drawing number: 10 packaged electronic components 11 substrate 12 Μ 0-: 13 metal sheet 14 circuit layout 15 solder cover 20 substrate 21 film 22 circuit layout 23 solder cover 24 glue 25 glue area Description of the invention: Please refer to the third figure, The preferred embodiment of the present invention mainly includes a substrate 20 | and a thin film 21. The substrate 20 is provided with a ball grid array integrated circuit. The substrate 20 is provided with a glue injection area 25. The circuit layout 22 can still be provided below the glue injection area 25, and the injection area 25 of the substrate 20 is located around the glue injection. . The film 21 is made of a non-metal material or a metal material such as a tape or a polymer compound.

C:\PiOgramFiles\Patents\PK6441.ptd 第 7 頁C: \ PiOgramFiles \ Patents \ PK6441.ptd page 7

於本發明薄膜21並非採用鍍金金屬片 之功效。 而具有節省製造成本 凊再參照第四圖,一基板2〇之注膠區域25上置一薄膜2 i 由^薄膜21係較佳與注膠區域25之形狀相同並具有黏附力 使&潯膜21黏附於注膠區域25,而該薄膜21底下之基板2〇 設有電路佈局22,該電路佈局22上覆蓋一層焊接罩23 〔solder mask〕’而薄膜21則黏附於該焊接罩23上。由 於該薄膜21黏附於該烊接罩23上,因此,在薄膜以底下之 基板20可空出電路佈局面積,本發明具有增加電路佈局面 積且不使用金或其它金屬片,可節省基板製作成本,並可:, 避免金屬片膨脹撥迫基板2〇兩侧的電路佈局,而增加製造 良率。 請再參照第五圖’當注膠由注膠區域25注入時,注 受薄膜21隔離覆蓋於注膠區域25上而使該注膠24不直接與 焊接罩23接觸,由於模具(未繪示]使注膠24位於薄膜21 上而不超出薄膜21兩側,進而使注膠24不會殘留於該薄膜 21兩側’此時,注膠通道之注膠24與薄膜21產生一黏附力 ’使薄膜21黏附於注膠通道之注膠24,其中該薄膜2〗與注 膠24黏附力大於該薄膜21與焊接罩23之黏附力,當注膠過 後注膠通道進行剝離時,由於該薄膜21可隨注膠通道之注 膠24剝離’因此’在基板20之焊接草23上不致殘留薄臈21 或注膠24。本發明基板20封裝時,其可剝離層在注膠製程 完成之後,即可以利用適當的方式予以剝離β此時由於模 具的注膠24注入通道内所殘留的封膠殘體皆是附著在本發The film 21 of the present invention does not use the effect of a gold-plated metal sheet. It has the advantages of saving manufacturing cost. Referring to the fourth figure again, a film 2 i is placed on the glue injection area 25 of a substrate 20. The film 21 is preferably the same shape as the glue injection area 25 and has an adhesive force. The film 21 is adhered to the glue injection area 25, and the substrate 20 under the film 21 is provided with a circuit layout 22. The circuit layout 22 is covered with a solder mask 23 [solder mask] 'and the film 21 is adhered to the solder mask 23. . Since the film 21 is adhered to the junction cover 23, the circuit layout area can be vacated on the substrate 20 under the film. The present invention has an increased circuit layout area and does not use gold or other metal pieces, which can save substrate manufacturing costs. And: It can avoid the expansion of the metal sheet and force the circuit layout on both sides of the substrate 20 to increase the manufacturing yield. Please refer to the fifth figure again. When the injection is injected from the injection area 25, the injection and receiving film 21 is isolated and covered on the injection area 25 so that the injection 24 does not directly contact the welding cover 23. Because the mold (not shown) ] Make the glue injection 24 on the film 21 without exceeding the two sides of the film 21, so that the glue injection 24 will not remain on both sides of the film 21 'At this time, the glue injection 24 of the glue injection channel and the film 21 generate an adhesion force' The film 21 is adhered to the glue injection channel 24 of the glue injection channel, wherein the adhesion force of the film 2 and the glue injection 24 is greater than the adhesion force of the film 21 and the welding cover 23. When the glue injection channel is peeled off after the glue injection, because of the film 21 can be peeled off with the glue injection 24 of the glue injection channel 'so' there will be no thin film 21 or glue injection 24 on the welding grass 23 of the substrate 20. When the substrate 20 of the present invention is packaged, the peelable layer thereof after the injection process That is, it can be peeled off in a proper way. At this time, the remaining sealant residues in the injection channel of the mold injection 24 are all attached to the hair.

C:\Program F i1es\Patents\PK6441. ptd 第 8 頁 98 5 . 五、發明說明(6) 明的可剝離 離時,該注 23上脫離, 面'本發明 屬片唐,而 使用鍍金不 省了金本身 雖然本發 發明,任何 内,當可作 視後附之申 層薄膜21的 膠24的殘留 該焊接罩23 採用基板2 0 祇在基板20 但省卻了鍍 的南成本。 明已以較佳 熟習此技藝 各種之更動 請專利範圍 表面上, 物亦可以 亦不致因 在形成電 之注膠位 金的相對 實施例揭 者,在不 與修改, 所界定者 故當可剝離層薄膜2 2被剝 同時地由基板20之焊接罩 剝離作動而受損》另一方 路佈局22時不需要形成金 置上覆蓋一層薄膜21。不 複雜程序,更重要的是節 :離:ί並非用以限定本 發明之精神和範圍 為準。 保護範圍當C: \ Program F i1es \ Patents \ PK6441. Ptd page 8 98 5. V. Description of the invention (6) When the peelable separation is clear, the note 23 is separated, and it says' The present invention belongs to the film Tang, but the use of gold plating does not Although the invention itself saves gold, although the adhesive 24 of the attached film 21 can be regarded as the residue of the adhesive 24, the welding cover 23 uses the substrate 20 only on the substrate 20, but the cost of plating is saved. Ming has better familiarized himself with this technique. Various modifications are patented. On the surface, the material may or may not be caused by the relative embodiment of the formation of the glue injection bit of electricity. Without the modification, the defined ones should be stripped. The layer film 22 is peeled and damaged by the peeling of the welding cover of the substrate 20 at the same time. The other way layout 22 does not need to form a gold layer to cover the film 21. The procedure is not complicated, the more important is the section: Li: It is not used to limit the spirit and scope of the present invention. When the scope of protection

Claims (1)

42 1 SQ 案號 88100086 啊· 修正 六、申請專利範圍 1. 一種半導體封裝之基板,其包含: 一基板,其表面上設有焊接罩,具有一注膠區域供注 膠注入;及 一薄膜,其黏貼於該基板之注膠區域上; 其中該薄膜與注膠黏附力大於該薄膜與焊接罩之黏附 力,當注膠過後注膠通道進行剝離時,該薄膜可隨注膠通 道之注膠剝離。 2 .如申請專利範圍第1項所述之半導體封裝之基板,其中 該基板係用以形成一球格陣列封裝構造。 3, 如申請專利範圍第1項所述之半導體封裝之基板,其中 該基板之注膠位置位於注膠周圍。 4. 如申請專利範圍第1項所述之半導體封裝之基板,其中 該薄膜係以非金屬材料製成。 5 .如申請專利範圍第4項所述之半導體封裝之基板,其中 該薄膜係為一膠帶。 6 .如申請專利範圍第1項所述之半導體封裝之基板,其中 該薄膜係以金屬材料製成。42 1 SQ Case No. 88100086 Amendment 6. Scope of Patent Application 1. A substrate for a semiconductor package, comprising: a substrate with a solder mask on its surface, with a glue injection area for glue injection; and a thin film, It adheres to the glue injection area of the substrate; wherein the adhesive force between the film and the glue is greater than the adhesive force between the film and the welding cover. When the glue injection channel is peeled off after the glue is injected, the film can follow the glue injection channel. Peel off. 2. The substrate of the semiconductor package according to item 1 of the scope of patent application, wherein the substrate is used to form a ball grid array package structure. 3. The substrate of the semiconductor package according to item 1 of the scope of the patent application, wherein the glue injection position of the substrate is located around the glue injection. 4. The substrate of the semiconductor package according to item 1 of the scope of patent application, wherein the thin film is made of a non-metal material. 5. The substrate of the semiconductor package according to item 4 of the scope of patent application, wherein the film is an adhesive tape. 6. The substrate of the semiconductor package according to item 1 of the scope of patent application, wherein the thin film is made of a metal material. POO-069-TW.ptc 第10頁 2000. 08. 22.010POO-069-TW.ptc Page 10 2000. 08. 22.010
TW88100086A 1999-01-04 1999-01-04 Substrate of semiconductor package TW421985B (en)

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